Method of forming a flash memory structure
By forming discrete word line gates and source/drain openings within the memory gate material layer and forming the memory gate structure in the same etching process, the performance problem caused by overlay errors is solved, the stability and programming efficiency of the flash memory structure are improved, and the photomask processing cost is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2022-10-14
- Publication Date
- 2026-07-10
AI Technical Summary
The performance of existing NOR flash memory structures needs further improvement, especially as the size of memory cells shrinks, the differences in memory gate structure caused by overlay errors affect the stability of device performance and programming efficiency.
By performing a first patterning process on the memory gate material layer, mutually independent word line gate openings and source/drain openings are formed within the memory gate material layer, and the memory gate structure is formed in the same etching process to avoid overlay errors; a second patterning process is performed on the initial word line gate structure, and a photomask with ordinary precision requirements is used to form the word line gate structure.
It improves the performance stability and programming efficiency of flash memory structure, avoids differences in memory gate structure caused by overlay errors, and reduces photomask processing costs.
Smart Images
Figure CN115425027B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a flash memory structure. Background Technology
[0002] Flash memory is a type of non-volatile memory that retains data for an extended period even without a power supply, meaning data is not lost when power is off. Based on its structure, flash memory can be divided into two types: NOR flash memory and NAND flash memory. NOR flash memory, due to its characteristics such as direct code execution, high reliability, and fast read speed, has become the mainstream non-volatile memory technology and is widely used in fields such as mobile phones and motherboards that require recording system code.
[0003] With the continuous development of semiconductor technology, shrinking the size of NOR flash memory cells is imperative. However, the problems that NOR flash memory may bring, such as reliability failures and low programming efficiency, will become increasingly significant as size reduction progresses.
[0004] Therefore, the performance of existing NOR flash memory structures needs further improvement. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a flash memory structure to improve the performance of the formed flash memory structure.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a flash memory structure, comprising: providing a substrate; forming a memory gate material layer on the surface of the substrate; performing a first patterning process on the memory gate material layer to form a word line gate opening and two source drain openings that are mutually discrete and expose the substrate within the memory gate material layer, wherein the two source drain openings are respectively located on both sides of the word line gate opening, and forming a memory gate structure with the memory gate material layer between the word line gate opening and the source drain opening; forming an initial word line gate structure within the word line gate opening and the source drain opening; and performing a second patterning process on the initial word line gate structure to remove the initial word line gate structure within the source drain opening, thereby forming a word line gate structure within the word line gate opening.
[0007] Optionally, the memory gate material layer includes a floating gate material layer and a control gate material layer located on the floating gate material layer; the memory gate structure includes a floating gate and a control gate located on the floating gate, wherein the floating gate is formed by the floating gate material layer and the control gate is formed by the control gate material layer.
[0008] Optionally, the method for performing a first patterning process on the memory gate material layer includes: forming a first patterned layer on the surface of the memory gate material layer, the first patterned layer exposing a portion of the memory gate material layer; using the first patterned layer as a mask, etching the control gate material layer to form an initial word line gate opening and two initial source / drain openings within the control gate material layer, the two initial source / drain openings being located on opposite sides of the initial word line gate opening; forming a control gate using the control gate material layer between the initial word line gate opening and the initial source / drain openings; forming a sidewall on the control gate sidewall; using the sidewall as a mask, etching the floating gate material layer to form the floating gate, forming the word line gate opening using the initial word line gate opening, and forming the source / drain opening using the initial source / drain opening.
[0009] Optionally, the top surface of the memory gate structure further has a first hard mask layer; the method further includes: forming a hard mask material layer on the surface of the memory gate material layer before performing the first patterning process; the hard mask material layer is etched to form the first hard mask layer.
[0010] Optionally, the memory gate material layer further includes a control gate dielectric material layer, the control gate dielectric material layer being located between the floating gate material layer and the control gate material layer; the method includes: etching the control gate dielectric material layer to form a control gate dielectric layer, the memory gate structure further including the control gate dielectric layer, the control gate dielectric layer being located between the floating gate and the control gate.
[0011] Optionally, the sidewall is formed after the control gate is formed and before the control gate dielectric layer is formed; the method of forming the sidewall includes: forming a sidewall material layer on the control gate sidewall and the surface of the control gate dielectric material layer; etching back the sidewall material layer until the control gate dielectric material layer is exposed, thereby forming the sidewall.
[0012] Optionally, the memory gate material layer further includes a floating gate dielectric material layer, the floating gate dielectric material layer being located between the substrate and the floating gate material layer; the method includes: etching the floating gate dielectric material layer to form the floating gate dielectric layer, the memory structure further including the floating gate dielectric layer, the floating gate dielectric layer being located between the floating gate and the substrate.
[0013] Optionally, the sidewall material includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride.
[0014] Optionally, performing a second patterning process on the initial word line gate structure includes: forming a second patterning layer on the surface of the initial word line gate structure, the second patterning layer exposing the initial word line gate structure within the source / drain opening; using the second patterning layer as a mask, etching the initial word line gate structure within the source / drain opening to remove the initial word line gate structure within the source / drain opening.
[0015] Optionally, the initial word line grid structure includes an initial word line grid; a word line grid is formed using the initial word line grid, and the word line grid structure includes the word line grid.
[0016] Optionally, the method for forming the initial word line gate structure includes: forming a word line gate material layer on the substrate surface, the sidewalls of the memory gate structure, and the surface, wherein the top surface of the word line gate material layer is higher than the top surface of the memory gate structure; planarizing the word line gate material layer until the top surface of the memory gate structure is exposed, thereby forming the initial word line gate with the word line gate material layer.
[0017] Optionally, the word line grid structure further includes a word line grid dielectric layer located between the word line grid opening and the word line grid.
[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0019] In a flash memory structure formation method provided by the present invention, the memory gate material layer is subjected to a first patterning process to form a word line gate opening and two source / drain openings that are mutually discrete and expose the substrate within the memory gate material layer. The two source / drain openings are respectively located on both sides of the word line gate opening. A memory gate structure is formed by the memory gate material layer between the word line gate opening and the source / drain opening. Since the two memory gate structures are formed by etching with the same photomask in the same etching process, the difference between the two memory gate structures caused by overlay errors is avoided, thereby improving the performance stability of the flash memory structure. In addition, the initial word line gate structure is subjected to a second patterning process to remove the initial word line gate structure within the source / drain opening and form a word line gate structure in the word line gate opening. The second patterning process can be formed using a photomask with ordinary precision requirements, without increasing the processing cost of the photomask due to the precision requirements of the photomask. Attached Figure Description
[0020] Figures 1 to 2 This is a schematic diagram illustrating the formation process of a flash memory structure.
[0021] Figures 3 to 9 This is a schematic diagram of the steps in the method for forming a flash memory structure according to an embodiment of the present invention. Detailed Implementation
[0022] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0023] As described in the background section, the performance of non-linear flash memory structures formed using existing technologies needs further improvement. The formation process of a flash memory structure will now be explained and analyzed.
[0024] Figures 1 to 2 This is a schematic diagram of the formation process of a flash memory structure.
[0025] Please refer to Figure 1 A substrate 100 is provided; two mutually discrete initial memory gate structures and an opening (not shown) between the two initial memory gate structures are formed on the surface of the substrate 100. Each initial memory gate structure includes an initial floating gate oxide layer 101, an initial floating gate 102 located on the initial floating gate oxide layer 101, an initial control gate dielectric layer 103 located on the initial floating gate 102, and an initial control gate structure located on the initial control gate dielectric layer 103. The initial control gate structure includes an initial control gate 104, an initial hard mask layer 105 located on the initial control gate, and sidewalls 106 located on the sidewalls of the initial control gate 104 and the initial hard mask layer 105. The opening exposes the sidewalls 106. A word line gate structure is formed within the opening. The word line gate structure includes a word line gate dielectric layer 107 and a word line gate 108 located on the word line gate dielectric layer 107.
[0026] Please refer to Figure 2 A patterned layer (not shown in the figure) is formed on the top surface of the two initial memory gate structures and the word line gate structure, the patterned layer exposing a portion of the initial memory gate structures; using the patterned layer as a mask, the two initial memory gate structures are etched to form two memory gate structures on the sidewall of the word line gate structure. Each memory gate structure includes a floating gate oxide layer 109, a floating gate 110 on the floating gate oxide layer 109, a control gate dielectric layer 111 on the floating gate 110, a control gate 112 on the control gate dielectric layer 111, and a hard mask layer 113 on the control gate 112. The floating gate oxide layer 109 is formed with the initial floating gate oxide layer 101, the floating gate 110 is formed with the initial floating gate 102, the control gate dielectric layer 111 is formed with the initial control gate dielectric layer 103, the control gate 112 is formed with the initial control gate 104, and the hard mask layer 113 is formed with the initial hard mask layer 105.
[0027] The above method is used to form a NOR flash memory structure. Ideally, two memory gate structures are formed on the sidewalls of the word line gate structure, and the two memory gate structures are mirror-symmetrical about the central axis of the word line gate structure. However, as the size of the memory cell shrinks, the overlay accuracy has an increasingly greater impact on device performance. In the photolithography process of etching the two initial memory gate structures, unavoidable overlay errors cause the memory gate structures A and B on both sides of the word line gate structure (e.g., ...) to become mirror-symmetrical. Figure 2 The dimensions (shown by the dashed line) vary. Since a longer floating gate results in stronger coupling between the floating gate and the control gate, and higher programming efficiency, memory gate structures B with shorter floating gates may experience problems such as low programming efficiency, affecting device performance.
[0028] To address the aforementioned issues, this invention provides a method for forming a flash memory structure. A first patterning process is performed on the memory gate material layer to form a word line gate opening and two source / drain openings that are mutually discrete and expose the substrate within the memory gate material layer. The two source / drain openings are located on opposite sides of the word line gate opening. A memory gate structure is formed using the memory gate material layer between the word line gate opening and the source / drain opening. Since the two memory gate structures are formed using the same photomask in the same etching process, differences between the two memory gate structures caused by overlay errors are avoided, thereby improving the performance stability of the flash memory structure. Furthermore, a second patterning process is performed on the initial word line gate structure to remove the initial word line gate structure within the source / drain opening, forming the word line gate structure within the word line gate opening. This second patterning process can be performed using a photomask with ordinary precision requirements, eliminating the need to increase the processing cost of the photomask due to precision requirements.
[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Figures 3 to 9 This is a schematic diagram of the steps in the method for forming a flash memory structure according to an embodiment of the present invention.
[0031] Please refer to Figure 3 Substrate 200 is provided.
[0032] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0033] Please continue to refer to this. Figure 3A storage gate material layer is formed on the surface of the substrate 200.
[0034] In this embodiment, the storage gate material layer includes a floating gate material layer 201 and a control gate material layer 202 located on the floating gate material layer 201.
[0035] In this embodiment, the floating gate material layer 201 is made of polysilicon; the control gate material layer 202 is made of polysilicon.
[0036] In this embodiment, the storage gate material layer further includes a floating gate dielectric material layer 203, which is located between the substrate 200 and the floating gate material layer 201.
[0037] In this embodiment, the material of the floating gate dielectric material layer 203 is silicon oxide.
[0038] In this embodiment, the storage gate material layer further includes a control gate dielectric material layer 204, which is located between the floating gate material layer 201 and the control gate material layer 202.
[0039] In this embodiment, the control gate dielectric material layer 204 includes a first gate dielectric material layer (not shown in the figure), a second gate dielectric material layer (not shown in the figure) located on the first gate dielectric material layer, and a third gate dielectric material layer (not shown in the figure) located on the second gate dielectric material layer. Specifically, the material of the first gate dielectric material layer is silicon oxide, the material of the second gate dielectric material layer is silicon nitride, and the material of the third gate dielectric material layer is silicon oxide.
[0040] Subsequently, the memory gate material layer is subjected to a first patterning process to form a word line gate opening and two source / drain openings that are mutually discrete and expose the substrate 200 within the memory gate material layer. The two source / drain openings are located on both sides of the word line gate opening, and a memory gate structure is formed by the memory gate material layer between the word line gate opening and the source / drain opening.
[0041] In this embodiment, before performing the first patterning process, a hard mask material layer 205 is also formed on the surface of the storage gate material layer.
[0042] In this embodiment, the memory gate structure includes a floating gate and a control gate located on the floating gate, wherein the floating gate is formed with the floating gate material layer and the control gate is formed with the control gate material layer.
[0043] For a specific method of performing the first patterning processing on the storage gate material layer, please refer to [reference needed]. Figures 4 to 6 .
[0044] Please refer to Figure 4A first patterned layer (not shown in the figure) is formed on the surface of the memory gate material layer, exposing a portion of the memory gate material layer. Using the first patterned layer as a mask, the control gate material layer 202 is etched to form an initial word line gate opening 205 and two initial source / drain openings 206 within the control gate material layer 202. The two initial source / drain openings 206 are located on both sides of the initial word line gate opening 205. A control gate 207 is formed in the control gate material layer 202 between the initial word line gate opening 205 and the initial source / drain openings 206.
[0045] In this embodiment, the material of the first patterning layer includes photoresist.
[0046] In this embodiment, the formation process of the first patterned layer is a photolithography process. The photolithography process includes deep ultraviolet lithography or extreme ultraviolet lithography.
[0047] In this embodiment, the hard mask material layer 205 is etched to form a first hard mask layer 208. The first hard mask layer 208 is used to protect the control gate 207 during subsequent etching processes.
[0048] Please refer to Figure 5 A sidewall 209 is formed on the sidewall of the control gate 207.
[0049] Subsequently, the control gate dielectric material layer 204 is etched to form the control gate dielectric layer.
[0050] Specifically, the sidewall 209 is formed after the control gate 207 is formed and before the control gate dielectric layer is formed.
[0051] The material of the sidewall 209 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
[0052] In this embodiment, the sidewall 209 has a double-layer structure. Specifically, the sidewall 209 includes a first sidewall (not shown in the figure) and a second sidewall (not shown in the figure) located on the sidewall of the first sidewall. More specifically, the first sidewall is made of silicon oxide, and the second sidewall is made of silicon nitride. In other embodiments, the sidewall can be a single-layer or multi-layer structure.
[0053] The method of forming the sidewall 209 includes: forming a sidewall material layer (not shown in the figure) on the sidewall of the control gate 207 and the surface of the control gate dielectric material layer 204; etching back the sidewall material layer until the control gate dielectric material layer 204 is exposed to form the sidewall 209.
[0054] In this embodiment, the sidewall 209 is also located on the sidewall of the first hard mask layer 208. The sidewall 209 is used to isolate the control gate 207 from the subsequently formed word line gate structure.
[0055] Please refer to Figure 6 Using the sidewall 209 as a mask, the floating grid material layer 201 is etched to form the floating grid 210, the initial word grid opening 205 is used to form the word grid opening 211, and the initial source drain opening 206 is used to form the source drain opening 212.
[0056] In this embodiment, the storage gate structure includes a floating gate 210 and a control gate 207 located on the floating gate 210. The word line gate opening 211 is used to form a word line gate structure, and the word line gate structure and the storage gate structures on both sides constitute a storage cell.
[0057] Since the two memory gate structures are formed using the same photomask in the same etching process, the differences between the two memory gate structures caused by overlay errors are avoided, thereby improving the performance stability of the flash memory structure.
[0058] In this embodiment, the top surface of the storage gate structure also has a first hard mask layer 208.
[0059] In this embodiment, the floating gate dielectric material layer 203 is etched to form a floating gate dielectric layer 213, and the memory structure further includes the floating gate dielectric layer 213, which is located between the floating gate 210 and the substrate 200.
[0060] In this embodiment, the control gate dielectric material layer 204 is etched to form a control gate dielectric layer 214, and the storage gate structure further includes the control gate dielectric layer 214, which is located between the floating gate 210 and the control gate 207.
[0061] Specifically, the control gate dielectric layer 214 includes a first gate dielectric layer (not shown in the figure), a second gate dielectric layer (not shown in the figure) located on the first gate dielectric layer, and a third gate dielectric layer (not shown in the figure) located on the second gate dielectric layer. Specifically, the first gate dielectric layer is formed with a first gate dielectric material layer, the second gate dielectric layer is formed with a second gate dielectric material layer, and the third gate dielectric layer is formed with a third gate dielectric material layer.
[0062] Subsequently, an initial word line grid structure is formed within the word line grid opening 211 and the source / drain opening 212. In this embodiment, the method for forming the initial word line grid structure is described in reference [reference needed]. Figures 7 to 9 .
[0063] Please refer to Figure 7A word line gate material layer 215 is formed on the surface of the substrate 200, the sidewalls of the memory gate structure, and the surface thereon, with the top surface of the word line gate material layer 215 being higher than the top surface of the memory gate structure.
[0064] In this embodiment, the word line gate material layer 215 is made of polycrystalline silicon.
[0065] In this embodiment, before forming the word line gate material layer 215, a word line gate dielectric material layer 216 is also formed on the surface of the substrate 200, the sidewall of the storage gate structure, and the surface.
[0066] In this embodiment, the material of the word line gate dielectric material layer 216 is silicon oxide.
[0067] Please refer to Figure 8 The word line grid material layer 215 is planarized until the top surface of the memory gate structure is exposed, thereby forming the initial word line grid 217 with the word line grid material layer 215.
[0068] In this embodiment, the initial word line grid structure includes the initial word line grid 217.
[0069] The process of planarizing the word line grid material layer 215 includes a mechanical-chemical polishing process.
[0070] Please refer to Figure 9 The initial word line grid structure is subjected to a second patterning process to remove the initial word line grid structure within the source drain opening 212 and form a word line grid structure within the word line grid opening 211.
[0071] The second patterning process can be performed using a photomask with a standard precision level, without increasing the processing cost of the photomask due to the precision requirements.
[0072] Specifically, the initial word line grid 217 within the source drain opening 212 is removed.
[0073] In this embodiment, the process of removing the initial word line gate 217 within the source / drain opening 212 includes a dry etching process.
[0074] In this embodiment, the second patterning process of the initial word line gate structure includes: forming a second patterning layer (not shown in the figure) on the surface of the initial word line gate structure, the second patterning layer exposing the initial word line gate structure within the source-drain opening 212; using the second patterning layer as a mask, etching the initial word line gate structure within the source-drain opening 212 to remove the initial word line gate structure within the source-drain opening 212.
[0075] In this embodiment, the material of the second patterning layer includes photoresist.
[0076] In this embodiment, the word line grid structure further includes a word line grid dielectric layer 218 located between the word line grid opening 211 and the word line grid.
[0077] In this embodiment, the method for forming the word line gate dielectric layer includes: forming the word line gate dielectric layer 218 with the word line gate dielectric material layer 216.
[0078] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a flash memory structure, characterized in that, include: Provide substrate; A storage gate material layer is formed on the surface of the substrate; The memory gate material layer is subjected to a first patterning process to form a word line gate opening and two source drain openings that are mutually discrete and expose the substrate within the memory gate material layer. The two source drain openings are respectively located on both sides of the word line gate opening, and a memory gate structure is formed by the memory gate material layer between the word line gate opening and the source drain opening. An initial word line grid structure is formed within the word line grid opening and the source / drain opening; The initial word line grid structure is subjected to a second patterning process to remove the initial word line grid structure within the source-drain opening, and to form a word line grid structure within the word line grid opening.
2. The method for forming a flash memory structure as described in claim 1, characterized in that, The storage gate material layer includes a floating gate material layer and a control gate material layer located on the floating gate material layer; the storage gate structure includes a floating gate and a control gate located on the floating gate, wherein the floating gate is formed by the floating gate material layer and the control gate is formed by the control gate material layer.
3. The method for forming a flash memory structure as described in claim 2, characterized in that, A method for performing a first patterning process on the memory gate material layer includes: forming a first patterned layer on the surface of the memory gate material layer, the first patterned layer exposing a portion of the memory gate material layer; using the first patterned layer as a mask, etching the control gate material layer to form an initial word line gate opening and two initial source / drain openings within the control gate material layer, the two initial source / drain openings being located on opposite sides of the initial word line gate opening; forming a control gate using the control gate material layer between the initial word line gate opening and the initial source / drain openings; forming a sidewall on the control gate sidewall; using the sidewall as a mask, etching the floating gate material layer to form the floating gate, forming the word line gate opening using the initial word line gate opening, and forming the source / drain opening using the initial source / drain opening.
4. The method for forming a flash memory structure as described in claim 3, characterized in that, The top surface of the memory gate structure also has a first hard mask layer; the method further includes: forming a hard mask material layer on the surface of the memory gate material layer before performing a first patterning process; the hard mask material layer is etched to form the first hard mask layer.
5. The method for forming a flash memory structure as described in claim 3, characterized in that, The storage gate material layer further includes a control gate dielectric material layer, which is located between the floating gate material layer and the control gate material layer; the method includes: etching the control gate dielectric material layer to form a control gate dielectric layer, the storage gate structure further including the control gate dielectric layer, which is located between the floating gate and the control gate.
6. The method for forming a flash memory structure as described in claim 5, characterized in that, The sidewall is formed after the control gate is formed and before the control gate dielectric layer is formed; the method of forming the sidewall includes: forming a sidewall material layer on the control gate sidewall and the surface of the control gate dielectric material layer; etching back the sidewall material layer until the control gate dielectric material layer is exposed, thereby forming the sidewall.
7. The method for forming a flash memory structure as described in claim 3, characterized in that, The memory gate material layer further includes a floating gate dielectric material layer, which is located between the substrate and the floating gate material layer; the method includes: etching the floating gate dielectric material layer to form a floating gate dielectric layer, the memory gate structure further including the floating gate dielectric layer, which is located between the floating gate and the substrate.
8. The method for forming a flash memory structure as described in claim 3, characterized in that, The sidewall material includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
9. The method for forming a flash memory structure as described in claim 1, characterized in that, The second patterning process for the initial word line gate structure includes: forming a second patterning layer on the surface of the initial word line gate structure, the second patterning layer exposing the initial word line gate structure within the source-drain opening; using the second patterning layer as a mask, etching the initial word line gate structure within the source-drain opening to remove the initial word line gate structure within the source-drain opening.
10. The method for forming a flash memory structure as described in claim 9, characterized in that, The initial word line grid structure includes an initial word line grid; a word line grid is formed from the initial word line grid, and the word line grid structure includes the word line grid.
11. The method for forming a flash memory structure as described in claim 10, characterized in that, The method for forming the initial word line gate structure includes: forming a word line gate material layer on the substrate surface, the sidewalls and surface of the memory gate structure, wherein the top surface of the word line gate material layer is higher than the top surface of the memory gate structure; planarizing the word line gate material layer until the top surface of the memory gate structure is exposed, thereby forming the initial word line gate with the word line gate material layer.
12. The method for forming a flash memory structure as described in claim 10, characterized in that, The word line grid structure also includes a word line grid dielectric layer located between the word line grid opening and the word line grid.