Display panel, manufacturing method thereof, and display device

Abstract

A display panel, a manufacturing method thereof, and a display device are provided. The display area of the display panel includes a plurality of pixel areas and a plurality of gate driving circuit areas. The gate driving circuit areas are located between two adjacent pixel areas. The display panel includes: a substrate; a backplane circuit layer located on the substrate, and in the gate driving circuit areas, the backplane circuit layer has a plurality of thin film transistors; a plurality of light emitting elements located on a side of the backplane circuit layer away from the substrate and within the areas where the pixel areas are located. The display panel has light shielding holes filled with a metal layer, and the positions of the light shielding holes and the metal layer in the orthographic projection on the substrate are configured to block the light irradiating the active layers of the thin film transistors.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing the same, and a display device. Background Art

[0002] In the field of displays, especially in display devices based on organic light-emitting diodes (OLEDs), the gate driving circuit is an important component in the display device. The gate driving circuit may include a plurality of cascaded shift registers. The shift registers generate scan signals to scan each row of sub-pixels in the display device, thereby realizing the display of images. With the prevalence of large-size and narrow-bezel display devices, more and more display devices adopt the strategy of arranging the gate driving circuit on the display panel to narrow the bezel of the display device.

[0003] Therefore, the current display panel, the method for manufacturing the same, and the display device still need to be improved. Summary of the Invention

[0004] The present application aims to alleviate or solve at least one of the above-mentioned problems to at least a certain extent.

[0005] The inventors found that in some display devices, especially in large-size OLED displays, the gate driving circuit is usually arranged on both sides of the display panel, making it difficult to achieve an ultra-narrow bezel or even a borderless design. Moreover, many current display panels are designed in non-rectangular shapes, making it difficult to achieve a narrow bezel with traditional design methods. In particular, when thin-film transistors (TFTs) in the gate driving circuit are designed in the active area (AA area) of the display, they are affected by the light emitted from the adjacent pixel light-emitting areas, resulting in a negative drift of the TFTs and affecting the panel lifespan.

[0006] In view of this, in one aspect of the present application, a display panel is proposed. The display area of the display panel includes a plurality of pixel areas and a plurality of gate driving circuit areas. The gate driving circuit areas are located between two adjacent pixel areas. The display panel includes: a substrate; a backplane circuit layer, which is located on the substrate, and in the gate driving circuit areas, the backplane circuit layer has a plurality of thin-film transistors; a plurality of light-emitting elements, which are located on the side of the backplane circuit layer away from the substrate and in the areas where the pixel areas are located. The display panel has light-shielding holes filled with a metal layer, and the positions of the light-shielding holes and the metal layer in the orthographic projection on the substrate are configured to block the light irradiating the active layer of the thin-film transistors. Thus, the light-shielding holes and the metal layer of the display panel can alleviate or even avoid the influence of the light emission of the light-emitting elements on the TFTs in the gate driving circuit areas, and further improve the service life of the display panel on the premise of achieving a narrow bezel.

[0007] In some examples of the present application, the light-shielding holes and the metal layer are located on the side of the backplane circuit layer away from the substrate. Thus, the active layer of the thin-film transistor can be better protected to prevent negative drift.

[0008] In some examples of the present application, the pixel region and the gate driving circuit region are arranged adjacent to each other. The light-emitting element is located within the pixel region, and there is a pixel definition structure between adjacent light-emitting elements. The light-shielding holes are formed on the pixel definition structure. Thus, the light-shielding holes and the metal layer can be simply arranged.

[0009] In some examples of the present application, the metal layer includes a cathode metal. Thus, the light-shielding holes and the metal layer can be simply arranged.

[0010] In some examples of the present application, there are multiple light-shielding holes, and there is a light-shielding hole between each pixel region and the thin-film transistors within the gate driving circuit region. Thus, the protection of the light-shielding holes for the active layer of the thin-film transistor can be further improved.

[0011] In some examples of the present application, the thin-film transistors within the gate driving circuit region include: an active layer; a gate and a gate insulating layer, the gate and the gate insulating layer are located on the side of the active layer away from the substrate; source and drain electrodes, the source and drain electrodes are located on the side of the active layer away from the substrate, there is an interlayer dielectric layer between the source and drain electrodes and the gate, and the source and drain electrodes are connected to the active layer through vias penetrating the interlayer dielectric layer. There is no overlapping area between the orthographic projection of the light-shielding hole on the substrate and the orthographic projection of the via of the interlayer dielectric layer on the substrate. Thus, the protection of the light-shielding holes for the active layer of the thin-film transistor can be further improved.

[0012] In some examples of the present application, the pixel region further includes a pixel light-emitting sub-region and a pixel circuit sub-region. The light-emitting element is located within the pixel light-emitting region. The pixel light-emitting sub-region and the pixel circuit sub-region are arranged along a first direction, and the light-shielding holes extend along the first direction. Thus, the protection of the light-shielding holes for the active layer of the thin-film transistor can be further improved.

[0013] In some examples of the present application, there are two light-shielding holes between two adjacent pixel regions. The length of the light-shielding holes along the first direction is consistent with the length of the transistor group, and multiple thin-film transistors within the transistor group are arranged between the two light-shielding holes along the first direction. The protection of the light-shielding holes for the active layer of the thin-film transistor can be further improved.

[0014] In some examples of the present application, the pixel regions are arranged in an array on the substrate. Each pixel region includes at least two sub-pixels. Each row of pixel regions corresponds to at least two gate driving circuit regions. Each gate driving circuit region is located between two adjacent pixel regions. The gate driving circuit includes a plurality of cascaded shift registers. Each shift register is electrically connected to a row of sub-pixels. Each shift register includes a plurality of transistor groups. Each transistor group includes at least one thin film transistor.

[0015] In some examples of the present application, the depth of the light-shielding hole is 1-3 micrometers, and the width of the light-shielding hole is 3-10 micrometers. Thus, the protection of the active layer of the thin film transistor by the light-shielding hole can be further improved.

[0016] In another aspect of the present application, a method for manufacturing the aforementioned display panel is proposed. The method includes: forming a backplane circuit layer on a substrate, and forming a plurality of thin film transistors in the gate driving circuit regions in the display panel; forming a plurality of light-emitting elements on a side of the backplane circuit layer away from the substrate, and positioning the light-emitting elements in the pixel regions; and the method includes operations of forming a light-shielding hole and a metal layer, and filling the metal layer into the light-shielding hole. The positions of the projections of the light-shielding hole and the metal layer on the substrate are configured to block the light of the light-emitting elements from irradiating the active layer of the thin film transistor. Thus, the aforementioned display panel can be simply obtained.

[0017] In some examples of the present application, forming the light-shielding hole and the metal layer includes: before forming the light-emitting elements, forming a pixel defining structure in advance between the plurality of light-emitting elements, and forming the light-shielding hole on the pixel defining structure; when forming the light-emitting elements, forming the metal layer using a cathode metal. Thus, the light-shielding hole and the metal layer can be simply formed.

[0018] In yet another aspect of the present application, a display device is proposed. The display device includes the aforementioned display panel. Thus, the display device has at least one of the advantages such as a narrow border and a long service life. Description of the Drawings

[0019] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0020] Figure 1 shows a schematic structural diagram of a display panel according to an example of the present application;

[0021] Figure 2 shows Figure 1 a schematic cross-sectional structural diagram of the display panel along the A-A' direction in

[0022] Figure 3 shows a schematic structural diagram of a display panel according to an example of the present application;

[0023] Figure 4 shows a schematic circuit diagram of a pixel circuit according to an example of the present application;

[0024] Figure 5 shows a schematic circuit diagram of a gate driving circuit according to an example of the present application;

[0025] Figure 6 shows a schematic circuit diagram of a gate driving circuit according to another example of the present application;

[0026] Figure 7 shows a schematic circuit diagram of a gate driving circuit according to still another example of the present application;

[0027] Figure 8 shows a schematic circuit diagram of a gate driving circuit according to still another example of the present application;

[0028] Figure 9 shows a flowchart of a method for manufacturing a display panel according to an example of the present application. Detailed Description of the Embodiments

[0029] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0030] In one aspect of the present application, the present application provides a display panel. Referring to Figure 1 and Figure 2 , the display area of the display panel 1000 includes a plurality of pixel areas 1100 and a plurality of gate driving circuit areas 1200. The gate driving circuit areas 1200 are located between two adjacent pixel areas 1100. The substrate 100 has a backplane circuit layer, and the backplane circuit layer has a plurality of thin film transistors in the gate driving circuit areas. A plurality of light emitting elements ( Figure 2 only one is shown) 800 are located on the side of the backplane circuit layer away from the substrate 100 and within the area where the pixel areas are located. Light shielding holes (see Figure 1The interior of (1220) is filled with a metal layer 50, and the positions of the light-shielding holes and the orthographic projection of the metal layer on the substrate are configured to block the light irradiated onto the active layer of the thin-film transistor. Thus, the light-shielding holes and the metal layer of the display panel can alleviate or even avoid the influence of the light emission of light-emitting elements, etc. on the TFTs in the gate drive circuit region. Furthermore, on the premise of achieving a narrow border, the service life of the display panel can be further extended.

[0031] For the convenience of understanding, the principle by which the display panel can achieve the above beneficial effects will be briefly described below:

[0032] According to some examples of the present application, in order to narrow the border of the display panel, the gate drive circuit can be arranged between two adjacent pixel regions in the display area. However, since the gate drive circuit has a relatively complex structure, in order to reduce its occupied area, multiple thin-film transistors in the gate drive circuit are concentrated and arranged to form a transistor group 1210, which is adjacent to the pixel region. This design can better achieve the effect of narrowing the border. However, at the same time, if no light-shielding holes and metal layer are provided, the light emitted by the pixel light-emitting sub-region 1110 in the pixel region will easily irradiate onto the active layer of the transistor group, causing negative drift of the thin-film transistor. By providing the light-shielding holes and the metal layer, the light emitted by the pixel light-emitting sub-region can be better blocked, preventing it from irradiating onto the active layer, and thus the negative drift caused by light irradiation can be alleviated or even avoided, thereby achieving the effect of extending the service life of the display panel.

[0033] In some examples of the present application, the specific positions of the light-shielding holes and the metal layer in the cross-sectional direction (i.e., the direction perpendicular to the plane where the substrate 100 is located) of the display panel are not particularly limited as long as light shielding can be achieved. For example, referring to Figure 2 , the light-shielding holes and the metal layer 50 can be located on the side of the backplane circuit layer away from the substrate, that is, on the side of the thin-film transistor away from the substrate 100. Thus, the active layer of the thin-film transistor can be better protected from negative drift.

[0034] Specifically, as Figure 2As shown, there is a pixel defining structure 600 between adjacent light-emitting elements 800, and a light-shielding hole may be formed on the pixel defining structure. The metal layer 50 includes a cathode metal. Thus, the light-shielding hole and the metal layer can be simply arranged. On the one hand, the arrangement of the light-shielding hole and the metal layer 50 here does not affect the change of the etching patterns of the respective stacked structures and metals in the backplane circuit layer. On the other hand, since the pixel defining structure needs to isolate the light-emitting layers and other structures of two adjacent light-emitting elements, it has a relatively large thickness, which is convenient for the preparation of the light-shielding hole. Moreover, the pixel defining structure 600 itself has an opening for accommodating the light-emitting element 800, so the light-shielding hole can be formed synchronously with the opening. The metal layer 50 filled in the light-shielding hole can be formed by using the cathode metal of the light-emitting element 800.

[0035] In some examples of the present application, the display panel may include a plurality of the light-shielding holes. Refer to Figure 1 , there may be the light-shielding holes between each pixel region and the thin-film transistors in the gate driving circuit region. For example, when the gate driving circuit includes a transistor group 1210, each gate driving circuit region may have two light-shielding holes 1220 to isolate the light emission of two adjacent pixel regions 1100. Thus, the protection of the light-shielding hole for the active layer of the thin-film transistor can be further improved.

[0036] In some examples of the present application, the specific number and structure of the thin-film transistors in the gate driving circuit region are not particularly limited, and those skilled in the art can design according to actual needs. For example, in some examples of the present application, the thin-film transistor may include an active layer 10, a gate 21, and a gate insulating layer 700. The gate and the gate insulating layer are located on the side of the active layer 10 away from the substrate 100; the source-drain electrodes (source electrode 31 and drain electrode 32) may be located on the side of the active layer 10 away from the substrate 100. There is an interlayer dielectric layer 300 between the source-drain electrodes and the gate, and the source-drain electrodes are connected to the active layer 10 through vias penetrating the interlayer dielectric layer 300.

[0037] It should be particularly noted here that the foregoing thin-film transistor is only an example of the present invention and should not be construed as a limitation on the specific structure of the thin-film transistor. For example, the backplane circuit layer may include a buffer layer 200 on the substrate 100, the respective hierarchical structures of the foregoing thin-film transistor, and structures such as a passivation layer 400 and a planarization layer 500.

[0038] According to some examples of the present application, there may be no overlapping area between the orthographic projection of the light-shielding hole on the substrate and the orthographic projection of the through hole penetrating the interlayer dielectric layer 300 on the substrate. That is to say, the position of the light-shielding hole can be set as close to the pixel area as possible. Thus, the protection of the active layer of the thin-film transistor by the light-shielding hole can be further improved: at this time, the light-shielding hole and the metal layer 50 filled therein can better protect the channel region between the source and drain electrodes. The light emitted by the light-emitting element 800 and the like can be better blocked by the metal layer 50 (refer to Figure 2 the direction indicated by the arrow in

[0039] In some examples of the present application, referring to Figure 1 and Figure 3 , the pixel area further includes a pixel light-emitting sub-region 1110 and a pixel circuit sub-region 1120. The light-emitting element is located in the pixel light-emitting area. The pixel light-emitting sub-region and the pixel circuit sub-region are arranged along a first direction, and the light-shielding hole 1220 extends along the first direction. Thus, the protection of the active layer of the thin-film transistor by the light-shielding hole can be further improved: as described above, in order to save the occupied area of the gate driving circuit, many of the thin-film transistors in the transistor group 1210 are arranged in sequence, such as also arranged along the first direction. At this time, arranging the light-shielding hole 1220 along the first direction can save the occupied area on the one hand and better block the transistor group on the other hand. The pixel circuit in the pixel light-emitting sub-region may also have a plurality of thin-film transistors and capacitor structures. The active layers 10 of the plurality of thin-film transistors can be formed by patterning a whole layer of semiconductor material. Similarly, the gate layer 20 can be formed by patterning a whole layer of metal material into a plurality of metal blocks and metal traces to act as the gates of the thin-film transistors, as well as traces such as gate lines, and form a capacitor structure with other metal layers. The source-drain layer 30 can also be used to form source-drain electrodes and data traces. The plurality of signal lines 40 can be formed by patterning the gate metal or the source-drain metal. The metal traces that need to be electrically connected, and the source-drain electrodes and the active layers of the thin-film transistors can be connected by means of vias.

[0040] In some examples of the present application, there are two light-shielding holes between two adjacent pixel areas 1100. The length of the light-shielding hole along the first direction is consistent with the length of the transistor group 1210. That is to say, the protection of the active layer of the thin-film transistor by the light-shielding hole can be further improved. According to some examples of the present application, the depth and width of the light-shielding hole are not particularly limited. For example, in some examples, the depth of the light-shielding hole can be 1-3 microns, and the width of the light-shielding hole is 3-10 microns. Among them, the depth of the light-shielding hole is the extension depth along the direction perpendicular to the plane of the substrate 100, and the width is the dimension of the light-shielding hole perpendicular to the first direction on the plane of the substrate 100.

[0041] In the present application, the specific shape and size of the light-shielding holes are not particularly limited, and those skilled in the art can select according to the actual situation. For example, the light-shielding holes can be through holes penetrating the pixel defining structure, or can be blind holes that do not completely penetrate the pixel defining structure. The orthographic projection of the light-shielding holes on the substrate 100 can be strip-shaped, circular or other shapes, as long as the metal layer filled in the light-shielding holes can block the light irradiated onto the active layer.

[0042] Similarly, the specific structure of the metal layer 50 is not particularly limited either. For example, when the metal layer 50 is formed of the cathode metal, the metal layer 50 can be connected to the cathode 830 of the light-emitting element 80 (this structure is not shown in the figure), or can have the structure as Figure 2 shown, that is, the metal layer 50 is not connected to the cathode 830. Those skilled in the art can understand that only one situation of the light-emitting element 800 is shown here, that is, the light-emitting element 800 includes an anode 810, a cathode 830, and a light-emitting layer 820 sandwiched therebetween. In some other examples of the present application, the structure of the light-emitting element 800 is not limited thereto, and can also have structures including but not limited to an electron transport layer, an electron blocking layer, a hole transport layer, and a hole blocking layer, etc.

[0043] It should be particularly noted here that the length of the light-shielding holes along the first direction is consistent with the length of the transistor group 1210, which means that their lengths are approximately the same, rather than exactly equal. That is, the length of the light-shielding holes can be approximately the same as the length of the extension of the transistor group, so as to achieve a better shielding effect. The length of the light-shielding holes can be slightly shorter than the length of the transistor group, or can be longer than the length of the transistor group. Those skilled in the art can adjust the setting position and length of the light-shielding holes according to the specific positions of the multiple active layers in the transistor group.

[0044] In some examples of the present application, the pixel regions are arranged in an array on the substrate, each pixel region includes at least two sub-pixels, each row of pixel regions corresponds to at least two gate driving circuit regions, each gate driving circuit region is located between two adjacent pixel regions, the gate driving circuit includes a plurality of cascaded shift registers, each shift register is electrically connected to a row of sub-pixels; each shift register includes a plurality of transistor groups, and each transistor group includes at least one thin film transistor.

[0045] The following briefly describes the specific structure and working principle of the gate driving circuit in combination with some examples of the present application:

[0046] Refer to Figure 1 and Figure 3 and Figure 4, a pixel circuit may be provided in the pixel circuit sub-region 1100. Each sub-pixel corresponds to one pixel circuit, and the structure of the pixel circuit is not particularly limited. The pixel circuit is used to control the light emission of the light-emitting element in the pixel light-emitting sub-region, such as controlling its turn-on and turn-off and adjusting the light emission brightness. The specific pixel circuit structure can be selected and set according to actual needs. For example, the structure of the pixel circuit may include structures such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C", where "T" is a thin-film transistor, and the number in front of "T" represents the number of thin-film transistors, and "C" is a storage capacitor, and the number in front of "C" represents the number of storage capacitors. Usually, the pixel circuit may include a switching transistor and a driving transistor. In an example of the present application, the pixel circuit may have a structure as shown in Figure 4 shown.

[0047] During the use of the display panel, the stability of the thin-film transistors and light-emitting devices (OLEDs) in the pixel circuit may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel. Therefore, it is necessary to compensate the pixel circuits of the sub-pixels. The compensation method may include various types and can be selected and set according to actual needs. For example, a pixel compensation circuit may be provided in the sub-pixel to perform internal compensation on the sub-pixel using the pixel compensation circuit. Another example is that the driving transistor or the light-emitting device can be measured through the thin-film transistor inside the sub-pixel, and the measured data is transmitted to an external sensing circuit to calculate the driving voltage value that needs to be compensated and perform external compensation using the external sensing circuit.

[0048] Taking the case of adopting an external compensation method and the pixel circuit having a 3T1C structure (including a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst) as an example, in some examples, the control electrode (gate) of the switching transistor T1 is electrically connected to the first gate signal terminal G1, one of the first electrodes (one of the source-drain electrodes) of the switching transistor T1 is electrically connected to the data signal terminal Data, and the second electrode (the other of the source-drain electrodes) of the switching transistor T1 is electrically connected to the first node G. At this time, the switching transistor T1 can respond to the first gate signal received at the first gate signal terminal G1, that is, when the switching transistor T1 is turned on, the data signal received at the data signal terminal Data is transmitted to the first node G. The data signal may specifically include a detection data signal and a display data signal. The control electrode of the driving transistor T2 is electrically connected to the first node G, the first electrode of the driving transistor T2 is electrically connected to the fourth voltage signal terminal ELVDD, and the second electrode of the driving transistor T2 is electrically connected to the second node S. Further, the driving transistor T2 is turned on under the control of the voltage at the node G, and the fourth voltage signal received at the fourth voltage signal terminal ELVDD can be transmitted to the second node S. The first end of the storage capacitor Cst is electrically connected to the first node G, and the second end is electrically connected to the second node S. Thus, when the switching transistor T1 charges the first node G, the storage capacitor Cst can be charged simultaneously. The anode of the light-emitting device (OLED) is electrically connected to the second node S, and the cathode is electrically connected to the fifth voltage signal terminal ELVSS, so that light emission can be performed under the mutual cooperation of the fourth voltage signal from the second node S and the fifth voltage signal transmitted by the fifth voltage signal terminal ELVSS.

[0049] The control electrode of the sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first electrode is electrically connected to the second node S, and the second electrode is electrically connected to the sensing signal terminal Sense. The sensing transistor T3 can respond to the second gate signal received at the second gate signal terminal G2 to detect the electrical characteristics of the driving transistor T2 to achieve external compensation. According to some examples of the present application, the electrical characteristics may include one or both of the threshold voltage and the carrier mobility of the driving transistor T2. The sensing signal terminal Sense can provide a reset signal or obtain a sensing signal, where the reset signal is used to reset the second node S, and the obtained sensing signal is used to obtain the threshold voltage of the driving transistor T2.

[0050] In some examples, the first gate signal received by each sub-pixel at the first gate signal terminal G1 and the second gate signal received at the second gate signal terminal G2 may be the same. Specifically, multiple pixel circuits in the same row of sub-pixels may be electrically connected to two gate lines (such as Figure 3 formed by the gate layer 20 shown), and the electrical signals transmitted by the two gate lines are the same. Alternatively, multiple pixel circuits in the same row of sub-pixels may be electrically connected to one gate line.

[0051] In some examples of the present application, the display phase of a frame may include a display period and a blanking period that are sequentially performed. Specifically, during the display period in the display phase of a frame, the working process of the sub-pixels may include, for example, a reset phase, a data writing phase, and a light emitting phase. Hereinafter, taking the thin film transistors all being N-type transistors as an example for illustration:

[0052] During the reset phase, referring to Figure 4 , the level of the second gate signal provided by the second gate signal terminal G2 is a high level, and the sense signal terminal Sense provides a reset signal (the level of this reset signal is, for example, a low level). The sense transistor T3 is turned on under the control of the second gate signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S. During the data writing phase, the level of the first gate signal provided by the first gate signal terminal G1 is a high level, and the level of the display data signal provided by the data signal terminal Data is a high level. The switching transistor T1 is turned on under the control of the first gate signal, receives the display data signal, and transmits the display data signal to the first node G, and at the same time charges the storage capacitor Cst. During the light emitting phase, the level of the first gate signal provided by the first gate signal terminal G1 is a low level, the level of the second gate signal provided by the second gate signal terminal G2 is a low level, and the level of the fourth voltage signal provided by the fourth voltage signal terminal ELVDD is a high level. The switching transistor T1 is turned off under the control of the first gate signal, and the sense transistor T3 is turned off under the control of the second gate signal. The storage capacitor Cst starts to discharge, so that the voltage of the first node G remains at a high level. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal, and transmits the fourth voltage signal to the second node S, so that the light emitting device emits light in cooperation with the fourth voltage signal and the fifth voltage signal transmitted by the fifth voltage signal terminal ELVSS.

[0053] The working process of the blanking period sub-pixels in a frame display stage may include: a first stage and a second stage. In the first stage, the levels of the first gate signal provided by the first gate signal terminal G1 and the second gate signal provided by the second gate signal terminal G2 are both high levels, and the level of the detection data signal provided by the data signal terminal Data is a high level. The switching transistor T1 is turned on under the control of the first gate signal, receives the detection data signal, and transmits the detection data signal to the first node G to charge the first node G. The sensing transistor T3 is turned on under the control of the second gate signal, receives the reset signal provided by the sensing signal terminal Sense, and transmits the reset signal to the second node S. In the second stage, the sensing signal terminal Sense is in a floating state. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal provided by the fourth voltage signal terminal ELVDD, and transmits the fourth voltage signal to the second node S to charge the second node S, causing the voltage of the second node S to rise until the driving transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2. Since the sensing transistor T3 is in the on state and the sensing signal terminal Sense is in the floating state, during the process of the driving transistor T2 charging the second node S, the sensing signal terminal Sense will also be charged simultaneously. By sampling the voltage of the sensing signal terminal Sense (i.e., obtaining the sensing signal), the threshold voltage Vth of the driving transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal. After calculating the threshold voltage Vth of the driving transistor T2, the threshold voltage Vth can be compensated into the display data signal in the display period of the next frame display stage to complete the external compensation of the sub-pixels.

[0054] In some examples, referring to Figure 5 and Figure 6 , the gate driving circuit may include a multi-stage cascaded shift register 1230, and one stage of the shift register may be electrically connected to a plurality of pixel circuits in one row of sub-pixels. In the display stage of a frame, the first gate signal transmitted by the first gate signal terminal G1 and the second gate signal transmitted by the second gate signal terminal G2 may both be provided by the gate driving circuit. Each stage of the shift register 1230 in the gate driving circuit may be electrically connected to the first gate signal terminal G1 through the first gate line, transmit the first gate signal to the first gate signal terminal G1 through the first gate line, and be electrically connected to the second gate signal terminal G2 through the second gate line, and transmit the second gate signal to the second gate signal terminal G2 through the second gate line.

[0055] The structure of the above-mentioned shift register 1230 is not particularly limited and can be selected and set according to actual needs. The structures of two types of shift registers are schematically described below, but it should not be construed as a limitation on the shift register 1230:

[0056] In some examples, such as Figure 5 and Figure 6 shown, the shift register 1230 may include: a first input circuit 3101, a leakage prevention circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108, and a fifth reset circuit 3109.

[0057] Exemplarily, such as Figure 5 and Figure 6 shown, the first input circuit 3101 is connected to the input signal terminal (abbreviated as Iput in the drawings and the following text), the pull-up node Q <n>and the anti-electric leakage node is OFF <n>Electric connection. During the display period in a frame display stage, the first input circuit 3101 can transmit the input signal to the pull-up node Q based on the input signal received at the input signal terminal Iput. <n>Here, N is a positive integer representing the number of rows of sub-pixels. More specifically, when the level of the input signal is high, the first input circuit 3101 can be turned on under the action of the input signal and transmit the input signal to the pull-up node Q <n>, for the pull-up node Q <n>is charged so that the pull-up node Q <n>The voltage increases. The first input circuit 3101 may specifically include a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, the first electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the second transistor M2 and the first anti-leakage node OFF1. The control electrode of the second transistor M2 is electrically connected to the input signal terminal Iput, and the second electrode of the second transistor M2 is electrically connected to the first pull-up node Q1.

[0058] Thus, when the level of the input signal transmitted by the input signal terminal Iput is high, the first transistor M1 and the second transistor M2 can be simultaneously turned on under the action of the input signal. The first transistor M1 can receive the input signal transmitted by the input signal terminal Iput and transmit the received input signal to the first electrode of the second transistor M2 and the anti-leakage node OFF <n>The second transistor M2 can transmit the received input signal to the pull-up node Q <n>, for the pull-up node Q <n>is charged so that the pull-up node Q <n>The voltage rises.

[0059] According to some examples of the present application, the anti-electric leakage circuit 3102 can be connected to the pull-up node Q <n>, the first voltage signal terminal VDD and the anti-leakage node OFF <n>Electric connection. The anti-electric leakage circuit 3102 can be at the pull-up node Q <n>Under the control of the voltage, the first voltage signal transmitted by the first voltage signal terminal VDD is transmitted to the anti-leakage node OFF <n>, to prevent the pull-up node Q <n>Leakage: Specifically, it is possible to avoid the pull-up node Q <n>Leakage occurs through the first input circuit 3101, causing the pull-up node Q <n>It is possible to maintain a relatively high and stable voltage. The first voltage signal can be a constant high voltage signal.

[0060] For example, at the pull-up node Q <n>When the voltage is at a high level, the anti-leakage circuit 3102 can be at the pull-up node Q <n>conducts under the control of the voltage, receives and transmits the first voltage signal to the anti-electric leakage node OFF <n>, causing the anti-electric leakage node to be OFF <n>The voltage rises. The anti-electric leakage circuit 3102 may specifically include a third transistor M3, and the control electrode of the third transistor M3 is connected to the pull-up node Q <n>electrically connected, the first pole of the third transistor M3 is electrically connected to the first voltage signal terminal VDD, and the second pole of the third transistor M3 is connected to the anti-leakage node OFF <n>Electric connection. Thus, at the pull-up node Q <n>When the voltage of [is] high level, the third transistor M3 can pull up the node Q <n>conducts under the control of the voltage and transmits the first voltage signal to the anti-electric leakage node OFF <n>, causing the anti-electric leakage node to be OFF <n>The voltage increases, and the voltage difference between the control electrode and the first electrode of the second transistor M2 becomes less than zero, ensuring that the second transistor M2 is completely or relatively completely cut off.

[0061] Exemplarily, such as Figure 5 and Figure 6 As shown, the output circuit 3103 is connected to the pull-up node Q <n>, the first clock signal terminal CLKE_1 and the first output signal terminal Output1 <n>(The attached drawings and the following text are abbreviated as Oput1 <n>) Electrical connection. Among them, the output circuit 3103 can be at the pull-up node Q during the display period in a frame display stage <n>Under the control of the voltage, the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 <n>。

[0062] Of course, as Figure 5 shown, the output circuit 3103 may also be connected to, for example, a third clock signal terminal CLKD_1 and a shift signal terminal CR <n>Electrical connection. Among them, the output circuit 3103 can also be at the pull-up node Q during the display period in a frame display stage <n>Under the control of the voltage, the third clock signal received at the third clock signal terminal CLKD_1 is transmitted to the shift signal terminal CR <n>。

[0063] Of course, the exemplary output circuit 3103 may also be connected to the fourth clock signal terminal CLKF_1 and the second output signal terminal Output2 <n>(The accompanying drawings and the following text are both abbreviated as Oput2 <n>) Electrical connection. During the blanking period in a frame display stage, the output circuit 3103 is at the pull-up node Q <n>Under the control of the voltage, the fourth clock signal received at the fourth clock signal terminal CLKF_1 can be transmitted to the second output signal terminal Oput2 <n>Specifically, at the pull-up node Q <n>In the case of an increase in voltage, the output circuit 3103 can be at the pull-up node Q <n>conducts under the control of the voltage, takes the third clock signal received at the third clock signal terminal CLKD_1 as a shift signal, and from the shift signal terminal CR <n>Output; Use the first clock signal received at the first clock signal terminal CLKE_1 as the first output signal, from the first output signal terminal Oput1 <n>Output. During the blanking period in a frame display stage, at the pull-up node Q <n>In the case of an increase in voltage, the output circuit 3103 can be at the pull-up node Q <n>conducts under the control of the voltage, takes the fourth clock signal received at the fourth clock signal terminal CLKF_1 as the second output signal, and outputs from the second output signal terminal Oput2 <n>Output. More specifically, the first output signal terminal Oput1 <n>Can be electrically connected to the first gate line, the first output signal terminal Oput1 <n>The first output signal output can be used as the first gate signal and is sequentially transmitted to the pixel circuit 12 via the first gate line and the first gate signal terminal G1. The second output signal terminal Oput2 <n>can be electrically connected to the second gate line, the second output signal terminal Oput2 <n>The second output signal output can be used as a second gate signal and is sequentially transmitted to the pixel circuit via the second gate line and the second gate signal terminal G2.

[0064] According to some examples of the present application, referring to Figure 6 , the output circuit 3103 may include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2. The control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>electrically connected, the first pole of the fourth transistor M4 is electrically connected to the third clock signal terminal CLKD_1, and the second pole of the fourth transistor M4 is electrically connected to the shift signal terminal CR <n>Electrical connection.

[0065] During the display period in a frame display stage, when the first input circuit 3101 is turned on, the pull-up node Q <n>When the voltage increases, the fourth transistor M4 can pull up the node Q <n>conducts under the control of a high voltage and transmits a third clock signal to the shift signal terminal CR <n>, and use the third clock signal as a shift signal from the shift signal terminal CR <n>Output. The control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>Electrically connected, the first pole of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE_1, and the second pole of the fifth transistor M5 is connected to the first output signal terminal Oput1 <n>Electric connection. The first end of the first capacitor C1 is connected to the pull-up node Q <n>Electrically connected, the second terminal of the first capacitor C1 is connected to the first output signal terminal Oput1 <n>Electrical connection.

[0066] During the display period in a frame display phase, when the first input circuit 3101 is turned on, causing the pull-up node Q <n>While the voltage is rising, the first capacitor C1 is charged. When the first input circuit 3101 is turned off, the first capacitor C1 can discharge, causing the pull-up node Q <n>Remain at a high level, so that the fifth transistor M5 can remain in the conducting state and transmit the first clock signal to the first output signal terminal Oput1 <n>, and use the first clock signal as the first output signal from the first output terminal Oput1 <n>Output

[0067] Exemplarily, the control electrode of the sixth transistor M6 is connected to the pull-up node Q <n>Electrically connected, the first pole of the sixth transistor M6 is electrically connected to the fourth clock signal terminal CLKF_1, and the second pole of the sixth transistor M6 is electrically connected to the second output signal terminal Oput2 <n>Electrically connected. The first end of the second capacitor C2 is connected to the pull-up node Q <n>Electrically connected, the second terminal of the second capacitor C2 is connected to the second output signal terminal Oput2 <n>Electrical connection. During the blanking period in a frame display stage, at the pull-up node Q <n>While the voltage rises, the second capacitor C2 is charged. In the corresponding stage, the second capacitor C2 can be discharged, causing the pull-up node Q <n>Remain at a high level, so that the sixth transistor M6 can remain in a conducting state and transmit the fourth clock signal to the second output terminal Oput2 <n>, and use the fourth clock signal as the second output signal from the second output terminal Oput2 <n>Output

[0068] According to some examples of the present application, after cascading the multi-stage shift register 1230 to form a gate driving circuit, the shift signal terminal CR in the Nth stage shift register <n>For example, it can be electrically connected to the input signal terminal Iput in the (N + 1)-th stage shift register, and further, the shift signal terminal CR of the N-th stage shift register <n>The output shift signal serves as the input signal in the (N + 1)-th stage shift register 21. Of course, the cascading relationship of the multi-stage shift registers is not limited to this, and those skilled in the art can design according to actual situations.

[0069] According to some other examples of the present application, the input signal terminal Iput of a part of the shift register 1230 can also be electrically connected to the start signal terminal STU, that is, receive the start signal transmitted by the start signal terminal STU as the input signal. Specifically, this part of the shift register can be the first-stage shift register in the gate driving circuit, or can be the first-stage shift register and the second-stage shift register, etc. The number of shift registers electrically connected to the start signal terminal STU is not limited, and those skilled in the art can select and set according to actual needs.

[0070] Exemplarily, as Figure 5 and Figure 6 shown, the control circuit 3104 is connected to the pull-up node Q <n>, the sixth voltage signal terminal VDD_A, the pull-down node QB_A, and the second voltage signal terminal VGL1 are electrically connected. Among them, the control circuit 3104 is configured to, at the pull-up node Q <n>Under the control of the voltage of [voltage name] and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A, the voltage of the pull-down node QB_A is controlled. The level of the sixth voltage signal can remain unchanged, for example, during the display period of one frame. The second voltage signal terminal VGL1 can be configured to transmit a DC low-level signal (e.g., lower than or equal to the low-level portion of the clock signal). The second voltage signal terminal VGL1 can be grounded, for example.

[0071] Specifically, at the pull-up node Q <n>When the voltage rises, the control circuit 3104 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, pulling down the voltage of the pull-down node QB_A to a low voltage. At the pull-up node Q <n>When the voltage is a low voltage, the control circuit 3104 can transmit the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A to the pull-down node QB_A, and pull up the voltage of the pull-down node QB_A to a high level. The control circuit 3104 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The control electrode of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD_A, the first electrode of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD_A, and the second electrode of the seventh transistor M7 is electrically connected to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The first electrode of the eighth transistor M8 is electrically connected to the sixth voltage signal terminal VDD_A, and the second electrode of the eighth transistor M8 is electrically connected to the pull-down node QB_A and the first electrode of the tenth transistor M10. The control electrode of the ninth transistor M9 is connected to the pull-up node Q <n>electrically connected, the second pole of the ninth transistor M9 is electrically connected to the second voltage signal terminal VGL1. The control pole of the tenth transistor M10 is connected to the pull-up node Q <n>Electrically connected, the second pole of the tenth transistor M10 is electrically connected to the second voltage signal terminal VGL1.

[0072] Thus, when the level of the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A is high, the seventh transistor M7 can be turned on under the action of the sixth voltage signal, receive and transmit the sixth voltage signal to the control pole of the eighth transistor M8 and the first pole of the ninth transistor M9. The eighth transistor M8 can be turned on under the action of the sixth voltage signal, receive and transmit the sixth voltage signal to the pull-down node QB_A and the first pole of the tenth transistor M10.

[0073] At the pull-up node Q <n>When the voltage is at a high level, the ninth transistor M9 and the tenth transistor M10 can pull up the node Q <n>When turned on under the control of the voltage, the ninth transistor M9 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the control electrode of the eighth transistor M8, so that the eighth transistor M8 is turned off. The tenth transistor M10 can transmit the second voltage signal to the pull-down node QB_A, pulling the voltage of the pull-down node QB_A down to a low level.

[0074] At the pull-up node Q <n>When the voltage is at a low level, the ninth transistor M9 and the tenth transistor M10 can pull up the node Q <n>Under the control of the voltage, the eighth transistor M8 can transmit the received sixth voltage signal to the pull-down node QB_A, raising the voltage of the pull-down node QB_A to a high level.

[0075] According to some examples of the present application, the first reset circuit 3105 is connected to the pull-down node QB_A and the pull-up node Q <n>, the second voltage signal terminal VGL1 and the anti-leakage node OFF <n>Electric connection. Among them, the first reset circuit 3105 can, under the control of the voltage of the pull-down node QB_A, pull up the node Q <n>Perform reset:

[0076] When the voltage of the pull-down node QB_A is high, the first reset circuit 3105 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q <n>, for the pull-up node Q <n>Perform a pull-down reset. Specifically, the first reset circuit 3105 may include: an eleventh transistor M11 and a twelfth transistor M12. The control electrode of the eleventh transistor M11 is electrically connected to the pull-down node QB_A, and the first electrode of the eleventh transistor M11 is connected to the pull-up node Q <n>Electrically connected, the second pole of the eleventh transistor M11 is connected to the first pole of the twelfth transistor M12 and the anti-leakage node OFF <n>Electrically connected. The control electrode of the twelfth transistor M12 is electrically connected to the pull-down node QB_A, and the second electrode of the twelfth transistor M12 is electrically connected to the second voltage signal terminal VGL1.

[0077] When the voltage at the pull-down node QB_A is at a high level, the eleventh transistor M11 and the twelfth transistor M12 can be simultaneously turned on under the action of the voltage at the pull-down node QB_A, and the twelfth transistor M12 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the eleventh transistor M11 can receive from the anti-leakage node OFF <n>The second voltage signal is transmitted to the pull-up node Q <n>, for the pull-up node Q <n>Perform reset.

[0078] At the pull-up node Q <n>When the potential of <n>conduct under the control of the voltage, and transmit the first voltage signal to the anti-leakage node OFF <n>, making the anti-electric leakage node OFF <n>The voltage increases, thereby causing the voltage difference between the control electrode and the second electrode of the eleventh transistor M11 to be less than zero, ensuring that the eleventh transistor M11 is completely or relatively completely cut off. Thus, the pull-up node Q can be avoided <n>Leakage occurs through the first reset circuit 3105, causing the pull-up node Q <n>It is able to maintain a relatively high and stable voltage.

[0079] Such as Figure 5 and Figure 6 As shown, the second reset circuit 3106 can be connected to the display reset signal terminal STD and the pull-up node Q <n>, the second voltage signal terminal VGL1 and the anti-leakage node OFF <n>Electric connection. Thus, the second reset circuit 3106 can, under the control of the display reset signal transmitted by the display reset signal terminal STD, pull up the node Q <n>Perform reset:

[0080] When the level of the display reset signal is high, the second reset circuit 3106 can be turned on under the action of the display reset signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q <n>, for the pull-up node Q <n>Perform a pull-down reset. The second reset circuit 3106 may include a thirteenth transistor M13 and a fourteenth transistor M14. The control electrode of the thirteenth transistor M13 is electrically connected to the display reset signal terminal STD, and the first electrode of the thirteenth transistor M13 is connected to the pull-up node Q <n>Electrically connected, the second pole of the thirteenth transistor M13 is connected to the first pole of the fourteenth transistor M14 and the anti-leakage node OFF <n>Electrically connected. The control electrode of the fourteenth transistor M14 is electrically connected to the display reset signal terminal STD, and the second electrode of the fourteenth transistor M14 is electrically connected to the second voltage signal terminal VGL1.

[0081] When the voltage of the display reset signal is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 can be simultaneously turned on under the action of the display reset signal, and the fourteenth transistor M14 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the thirteenth transistor M13 can receive from the anti-leakage node OFF <n>The second voltage signal is transmitted to the pull-up node Q <n>, for the pull-up node Q <n>Perform a reset.

[0082] Specifically, at the pull-up node Q <n>When the potential of <n>conducts under the control of the voltage and transmits the first voltage signal to the anti-leakage node OFF <n>, making the anti-electric leakage node OFF <n>The voltage rises, and further makes the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 less than zero, ensuring that the thirteenth transistor M13 is completely or relatively completely cut off. This can avoid the pull-up node Q <n>Leakage occurs through the second reset circuit 3106, causing the pull-up node Q <n>It is able to maintain a relatively high and stable voltage.

[0083] Similarly, after cascading multiple-stage shift registers to form a gate driving circuit, the display reset signal terminal STD of the Nth-stage shift register 1230 can be connected to, for example, the shift signal terminal CR of the (N + 4)th-stage shift register. <n>electrically connected, and then the shift signal terminal CR of the (N + 4)-th stage shift register <n>The output shift signal serves as the display reset signal for the Nth-stage shift register.

[0084] Exemplarily, as Figure 5 and Figure 6 shown, the third reset circuit 3107 can be connected to the global reset signal terminal TRST and the pull-up node Q <n>, the second voltage signal terminal VGL1 and the anti-leakage node OFF <n>Electric connection. Thus, the third reset circuit 3107 can, under the control of the global reset signal transmitted by the global reset signal terminal TRST, pull up the node Q <n>Perform a reset:

[0085] For example, when the level of the global reset signal is high, the third reset circuit 3107 can be turned on under the action of the global reset signal to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q <n>, for the pull-up node Q <n>Perform a pull-down reset. Specifically, the third reset circuit 3107 may include: a fifteenth transistor M15 and a sixteenth transistor M16. The control electrode of the fifteenth transistor M15 is electrically connected to the global reset signal terminal TRST, and the first electrode of the fifteenth transistor M15 is connected to the pull-up node Q <n>Electrically connected, the second pole of the fifteenth transistor M15, the first pole of the sixteenth transistor M16, and the anti-leakage node OFF <n>Electrically connected. The control electrode of the sixteenth transistor M16 is electrically connected to the global reset signal terminal TRST, and the second electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal VGL1.

[0086] When the voltage of the global reset signal is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 can be simultaneously turned on under the action of the global reset signal, and the sixteenth transistor M16 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the fifteenth transistor M15 can receive from the anti-leakage node OFF <n>The fifth voltage signal is transmitted to the pull-up node Q <n>, for the pull-up node Q <n>Reset.

[0087] Here, at the pull-up node Q <n>When the potential of <n>conducts under the control of the voltage and transmits the first voltage signal to the anti-leakage node OFF <n>, causing the anti-electric leakage node to be OFF <n>The voltage increases, further causing the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 to be less than zero, ensuring that the fifteenth transistor M15 is completely or relatively completely cut off. This can avoid the pull-up node Q <n>Leakage occurs through the third reset circuit 3107, causing the pull-up node Q <n>It can maintain a relatively high and stable voltage.

[0088] Exemplarily, such as Figure 6 As shown, the fourth reset circuit 3108 can be connected to the pull-down node QB_A and the shift signal terminal CR <n>, First output signal terminal Oput1 <n>, Second output signal terminal Oput2 <n>, is electrically connected to the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2. The fourth reset circuit 3108 can, under the control of the voltage at the pull-down node QB_A, reset the shift signal terminal CR <n>, First output signal terminal Oput1 <n>and a second output signal terminal Oput2 <n>Perform a reset.

[0089] In some examples of the present application, the third voltage signal terminal VGL2 is configured to transmit a DC low-level signal (e.g., lower than or equal to the low-level portion of the clock signal). The third voltage signal terminal VGL2 can be grounded, for example. The low-level signals transmitted by the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 can be equal or unequal.

[0090] Specifically, when the voltage of the pull-down node QB_A is high, the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Perform a pull-down reset to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, to the first output signal terminal Oput1 <n>Perform a pull-down reset to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second output signal terminal Oput2 <n>, for the second output signal terminal Oput2 <n>Perform a pull-down reset.

[0091] More specifically, the fourth reset circuit 3108 may include: a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19. The control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A, and the first electrode of the seventeenth transistor M17 is connected to the shift signal terminal CR <n>Electrically connected, the second pole of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal VGL1.

[0092] When the voltage at the pull - down node QB_A is at a high level, the seventeenth transistor M17 can be turned on under the action of the voltage at the pull - down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR. <n>, to the shift signal terminal CR <n>Perform a pull-down reset. The control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A, and the first electrode of the eighteenth transistor M18 is connected to the first output signal terminal Oput1 <n>Electrically connected, the second pole of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL2. When the voltage at the pull-down node QB_A is at a high level, the eighteenth transistor M18 can be turned on under the action of the voltage at the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Perform a pull-down reset. The control electrode of the nineteenth transistor M19 is electrically connected to the pull-down node QB_A, and the first electrode of the nineteenth transistor M19 is connected to the second output signal terminal Oput2 <n>Electrically connected, the second pole of the nineteenth transistor M19 is electrically connected to the third voltage signal terminal VGL2. When the voltage at the pull-down node QB_A is high, the nineteenth transistor M19 can be turned on under the action of the voltage at the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second output signal terminal Oput2 <n>, to the second output signal terminal Oput2 <n>Perform a pull - down reset.

[0093] Exemplarily, as Figure 5 and Figure 6 shown, the fifth reset circuit 3109 is electrically connected to the input signal terminal Iput, the pull - down node QB_A, and the second voltage signal terminal VGL1. The fifth reset circuit 3109 can reset the pull - down node QB_A under the control of the input signal transmitted by the input signal terminal Iput:

[0094] For example, when the level of the input signal is high, the fifth reset circuit 3109 can be turned on under the action of the input signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull - down node QB_A to perform a pull - down reset on the pull - down node QB_A. Specifically, the fifth reset circuit 3109 may include: the twentieth transistor M20.

[0095] The control electrode of the twentieth transistor M20 is electrically connected to the input signal terminal Iput, the first electrode of the twentieth transistor M20 is electrically connected to the pull - down node QB_A, and the second electrode of the twentieth transistor M20 is electrically connected to the second voltage signal terminal VGL1. When the level of the input signal is high, the twentieth transistor M20 can be turned on under the action of the input signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull - down node QB_A to perform a pull - down reset on the pull - down node QB_A.

[0096] In some examples of the present application, referring to Figure 6 , the gate driving circuit may further include a plurality of blanking input circuits 3200. One blanking input circuit can be electrically connected to at least two adjacent stages of shift registers. In other words, at least two stages of shift registers can share one blanking input circuit. The blanking input circuit can control the corresponding shift register to input a blanking control signal to the pixel circuit of the corresponding row during the blanking period of a frame display stage, so that the pixel circuit obtains a sensing signal:

[0097] Specifically, as Figure 6 shown, the blanking input circuit 3200 may, for example, include a selection control circuit 3201, a second input circuit 3202, and at least two transmission circuits 3203. The selection control circuit 3201 is connected to the selection control signal terminal OE, the shift signal terminal CR <n>, is electrically connected to the second voltage signal terminal VGL1 and the first blanking node H, and under the control of the selection control signal transmitted by the selection control signal terminal OE, will be at the shift signal terminal CR <n>The received shift signal is transmitted to the first blanking node H.

[0098] Specifically, when the level of the selection control signal is high, the selection control circuit 3201 can be turned on under the control of the selection control signal, and transmit the received shift signal to the first blanking node H to charge the first blanking node H, causing the voltage of the first blanking node H to increase. During the blanking period of a frame display stage, when it is necessary to obtain a sensing signal, the waveform timing of the selection control signal can be made the same as the waveform timing of the input signal, thereby causing the selection control circuit 3201 to turn on. Specifically, the selection control circuit 3201 may include: a twenty-first transistor M21, a twenty-second transistor M22, and a third capacitor C3. The control electrode of the twenty-first transistor M21 is electrically connected to the selection control signal terminal OE, and the first electrode of the twenty-first transistor M21 is connected to the shift signal terminal CR <n>Electrically connect, the second pole of the twenty-first transistor M21 is electrically connected to the first pole of the twenty-second transistor M22. The control pole of the twenty-second transistor M22 is electrically connected to the selection control signal terminal OE, and the second pole of the twenty-second transistor M22 is electrically connected to the first blanking node H.

[0099] When the level of the selection control signal transmitted by the selection control signal terminal OE is high, the twenty-first transistor M21 and the twenty-second transistor M22 can be simultaneously turned on under the action of the selection control signal, and the twenty-first transistor M21 can transfer the shift signal terminal CR <n>The transmitted shift signal is transmitted to the first pole of the twenty-second transistor M22. The twenty-second transistor M22 can receive and transmit the shift signal to the first blanking node H to charge the first blanking node H. The first end of the third capacitor C3 is electrically connected to the first blanking node H, and the second end of the third capacitor C3 is electrically connected to the second voltage signal terminal VGL1. During the process of the selection control circuit 3201 charging the first blanking node H, the third capacitor C3 is also charged. In this way, when the selection control circuit 3201 is turned off, the third capacitor C3 can discharge to keep the first blanking node H at a high level.

[0100] Specifically, the selection control circuit 3201 may further include, for example: a twenty-third transistor M23. The control pole of the twenty-third transistor M23 is electrically connected to the first blanking node H, the first pole of the twenty-third transistor M23 is electrically connected to the first voltage signal terminal VDD, and the second pole of the twenty-third transistor M23 is electrically connected to the first pole of the twenty-second transistor M22. Thus, when the voltage of the first blanking node H is high and the twenty-first transistor M21 and the twenty-second transistor M22 are not working, the twenty-third transistor M23 can be turned on under the control of the voltage of the first blanking node H to transmit the first voltage signal transmitted by the first voltage signal terminal VDD to the first pole of the twenty-second transistor M22, increasing the voltage of the first pole of the twenty-second transistor M22, and further making the voltage difference between the control pole and the first pole of the twenty-second transistor M22 less than zero, ensuring that the twenty-second transistor M22 is completely or relatively completely cut off. This can prevent the first blanking node H from leaking electricity through the twenty-second transistor M22, enabling the first blanking node H to maintain a relatively high and stable voltage.

[0101] According to some examples of the present invention, the second input circuit 3202 is electrically connected to the first blanking node H, the second blanking node N, and the second clock signal terminal CLKA or the first voltage signal terminal VDD to transmit the second clock signal received at the second clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N under the control of the voltage of the first blanking node H.

[0102] For example, when the selection control circuit 3201 is turned on to increase the voltage of the first blanking node H, the second input circuit 3202 can be turned on under the control of the voltage of the first blanking node H, receive the second clock signal transmitted by the second clock signal terminal CLKA, and transmit the second clock signal to the second blanking node N. Specifically, the second input circuit 3202 may include: a twenty-fourth transistor M24. The control electrode of the twenty-fourth transistor M24 is electrically connected to the first blanking node H, the first electrode of the twenty-fourth transistor M24 is electrically connected to the second clock signal terminal CLKA or the first voltage signal terminal VDD, and the second electrode of the twenty-fourth transistor M24 is electrically connected to the second blanking node N.

[0103] When the voltage of the first blanking node H is at a high level, the twenty-fourth transistor M24 can be turned on under the control of the voltage of the first blanking node H, and transmit the fourth clock signal received at the fourth clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N.

[0104] Exemplarily, the above at least two transmission circuits 3203 may be electrically connected to at least two shift registers in a one-to-one correspondence. One transmission circuit 3203 is connected to the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q of the first-stage shift register <n>Electrically connected. Among them, the transmission circuit 3202 is configured to transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q under the control of the second clock signal transmitted by the second clock signal terminal CLKA. <n>。

[0105] For example, when the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the transmission circuit 3202 can be turned on under the control of the second clock signal, receive the second clock signal or the first voltage signal from the second blanking node N, and transmit the received second clock signal or the first voltage signal to the pull-up node Q <n>, so that the pull-up node Q <n>The voltage rises, which can then cause the output circuit 3103 to conduct, enabling the second output signal terminal Oput2 of the output circuit 3103 <n>Output a second output signal. Specifically, the transmission circuit 3203 may include: a twenty-fifth transistor M25 and a twenty-sixth transistor M26. The control electrode of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, the first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and the second electrode of the twenty-fifth transistor M25 is electrically connected to the first electrode of the twenty-sixth transistor M26. The control electrode of the twenty-sixth transistor M26 is electrically connected to the second clock signal terminal CLKA, and the second electrode of the twenty-sixth transistor M26 is electrically connected to the pull-up node Q <n>Electrical connection.

[0106] Thus, when the level of the second clock signal transmitted on the second clock signal terminal CLKA is high, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 can be simultaneously turned on under the action of the second clock signal. The twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the first pole of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 can receive and transmit the second clock signal or the first voltage signal to the pull-up node Q. <n>, for the pull-up node Q <n>Charge. The sixth transistor M6 in the output circuit 3103 can be at the pull-up node Q <n>conducts under the control of the voltage, receives the fourth clock signal, and uses the fourth clock signal as the second output signal to output from the second output signal terminal Oput2 <n>Output

[0107] The transmission circuit 3203 is also connected to the anti-electric leakage node OFF <n>In the case of electrical connection, the first pole of the twenty-sixth transistor M26 can be connected to the anti-leakage node OFF <n>and is electrically connected to the second pole of the twenty-fifth transistor M25. At this time, at the pull-up node Q <n>When the potential of <n>conducts under the control of the voltage and transmits the first voltage signal to the anti-electric leakage node OFF <n>, causing the anti-electric leakage node to be OFF <n>The voltage increases, thereby causing the voltage difference between the control electrode and the first electrode of the twenty-sixth transistor M26 to be less than zero, ensuring that the twenty-sixth transistor M26 is completely or relatively completely cut off. This can avoid the pull-up node Q <n>Leakage occurs through the transmission circuit 3203, causing the pull-up node Q <n>It is possible to maintain a relatively high and stable voltage.

[0108] According to some examples of the present application, when the gate driving circuit further includes a blanking input circuit, the shift register may further include a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A, and the second voltage signal terminal VGL1, and thus can reset the pull-down node QB_A under the common control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H during the blanking period of one frame display stage.

[0109] For example, during the blanking period of one frame display stage, when the level of the second clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 3110 can be turned on under the common control of the second clock signal and the voltage of the first blanking node H, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A to perform a pull-down reset on the pull-down node QB_A. Specifically, the sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33. The control electrode of the thirty-second transistor M32 is electrically connected to the second clock signal terminal CLKA, the first electrode of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A, and the second electrode of the thirty-second transistor M32 is electrically connected to the first electrode of the thirty-third transistor M33. The control electrode of the thirty-third transistor M33 is electrically connected to the first blanking node H, and the second electrode of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL1.

[0110] When the level of the second clock signal is high and the voltage of the first blanking node H is high, the thirty-third transistor M33 can be turned on under the control of the voltage of the first blanking node H to transmit the second voltage signal to the first electrode of the thirty-third transistor M33, and the thirty-second transistor M32 can be turned on under the control of the second clock signal to transmit the second voltage signal from the first electrode of the thirty-third transistor M33 to the pull-down node QB_A to perform a pull-down reset on the pull-down node QB_A.

[0111] Next, taking the example that two adjacent stages of shift registers share a blanking input circuit 3200, the structure of the gate driving circuit will be schematically described: In the following description, N represents a positive odd number.

[0112] As Figure 6 shown, in two adjacent stages of shift registers, the fourth transistor M4 may not be provided in the output circuit 3103 of the latter-stage shift register and is not electrically connected to the third clock signal terminal CLKD_1. At this time, the shift signal terminal CR in the Nth-stage shift register <n>It can be electrically connected to the input signal terminal Iput in the (N + 2)-th stage and the (N + 3)-th stage shift registers, and further connect the shift signal terminal CR of the N-th stage shift register <n>The output shift signal serves as the input signal in the (N + 2)-th stage and the (N + 3)-th stage shift registers. For example, the display reset signal terminals STD of the N-th stage and the (N + 1)-th stage shift registers can be electrically connected to the shift signal terminal CR<N+4> of the (N + 4)-th stage shift register, so that the shift signal output from the shift signal terminal CR<N+4> of the (N + 4)-th stage shift register serves as the display reset signal for the N-th stage and the (N + 1)-th stage shift registers.

[0113] For example, the shift signal terminal CR in the first stage shift register <n>It can be electrically connected to the input signal terminal Iput in the third-level and fourth-level shift registers. The shift signal terminal CR in the fifth-level shift register <n>It can be electrically connected to the display reset signal terminal STD in the first-stage and second-stage shift registers. Thereby, it is beneficial to simplify the structure of the gate driving circuit and reduce the space occupation ratio of the gate driving circuit in the display panel. Of course, the cascading relationship of the multi-stage shift registers is not limited to the foregoing description, and those skilled in the art can make changes according to the situation.

[0114] In some examples of the present application, referring to Figure 6 , among two adjacent stages of shift registers, the previous stage (i.e., the Nth stage) shift register 1230a can be referred to as the first scanning unit, and the next stage (i.e., the N+1th stage) shift register 1230b can be referred to as the second scanning unit 21b. The pull-up node Q in the first scanning unit 21a <n>Can be referred to as the first pull-up node Q <n>, the pull-up node Q in the second scan unit 21b <n>is called the second pull-up node Q<N+1>. Similarly, the pull-down node QB_A in the first scan unit 21a is called the first pull-down node QB_A, and the pull-down node QB_A in the second scan unit 21b is called the second pull-down node QB_B; the anti-leakage node OFF in the first scan unit 21a <n>Called the first anti-electric leakage node OFF <n>, turn off the anti-leakage node in the second scanning unit 21b <n>It is called the second anti-electric leakage node OFF<N+1>; the first clock signal CLKE_1 in the second scanning unit 21b is called the fifth clock signal CLKE_2, and the fourth clock signal CLKF_1 in the second scanning unit 21b is called the sixth clock signal CLKF_2; the first output signal terminal Oput1 in the first scanning unit 21a <n>Called the first sub-output signal terminal Oput1 <n>, the second output signal terminal Oput2 in the first scanning unit 21a <n>Called the second sub-output signal terminal Oput2 <n>, the first output signal terminal Oput1 in the second scanning unit 21b <n>It is called the third sub-output signal terminal Oput1<N+1>, and the second output signal terminal Oput2 in the second scanning unit 21b <n>It is called the fourth sub-output signal terminal Oput2<N+1>.

[0115] Reference Figure 6 , the control circuit 3104 in the second scanning unit 21b can be electrically connected to the seventh voltage signal terminal VDD_B, and the seventh voltage signal terminal VDD_B is used to replace the sixth voltage signal terminal VDD_A. Among them, during the display stage of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are inverse-phase signals to each other.

[0116] According to some examples of the present application, reference Figure 6 , the first reset circuit 3105 in the first scanning unit 21a can also be electrically connected to the second pull-down node QB_B. The first reset circuit 3105 can, under the control of the voltage of the second pull-down node QB_B, reset the first pull-up node Q <n>Perform reset:

[0117] Specifically, when the voltage at the second pull-down node QB_B is high, the first reset circuit 3105 can be turned on under the action of the voltage at the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the first pull-up node Q <n>, to the first pull-up node Q <n>Perform a pull-down reset. The first reset circuit 3105 in the first scanning unit 21a may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0118] More specifically, in the first scanning unit 21a, the control electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-seventh transistor M27 is connected to the first pull-up node Q <n>Electrically connected, the second pole of the twenty-seventh transistor M27 is connected to the first pole of the twenty-eighth transistor M28 and the first anti-leakage node OFF <n>Electrically connected. The control electrode of the twenty-eighth transistor M28 is electrically connected to the second pull-down node QB_B, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL1.

[0119] When the voltage of the second pull-down node QB_B is at a high level, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 can be simultaneously turned on under the action of the voltage of the second pull-down node QB_B, and the twenty-eighth transistor M28 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the first anti-leakage node OFF <n>, the twenty-seventh transistor M27 can receive from the first anti-leakage node OFF <n>The second voltage signal is transmitted to the first pull-up node Q <n>, to the first pull-up node Q <n>Perform a reset.

[0120] In some examples of the present application, with reference to Figure 6 , the first reset circuit 3105 in the second scanning unit 21b can also be electrically connected to the first pull-down node QB_A. Among them, the first reset circuit 3105 is further configured to reset the second pull-up node Q<N+1> under the control of the voltage of the first pull-down node QB_A. Specifically, when the voltage of the first pull-down node QB_A is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the second pull-up node Q<N+1>, and perform a pull-down reset on the second pull-up node Q<N+1>. More specifically, the first reset circuit 3105 in the second scanning unit 21b may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0121] That is to say, at this time in the second scanning unit 21b, the control electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB_A, the first electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-up node Q<N+1>, and the second electrode of the twenty-seventh transistor M27 is electrically connected to the first electrode of the twenty-eighth transistor M28 and the second anti-leakage node OFF<N+1>. The control electrode of the twenty-eighth transistor M28 is electrically connected to the first pull-down node QB_A, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL1.

[0122] When the voltage of the first pull-down node QB_A is at a high level, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 can be turned on simultaneously under the action of the voltage of the first pull-down node QB_A. The twenty-eighth transistor M28 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the second anti-leakage node OFF<N+1>, and the twenty-seventh transistor M27 can transmit the second voltage signal from the second anti-leakage node OFF<N+1> to the second pull-up node Q<N+1> to reset the second pull-up node Q<N+1>.

[0123] In some other examples of the present application, the fourth reset circuit 3108 in the first scanning unit 21a can also be electrically connected to the second pull-down node QB_B. Thus, the fourth reset circuit 3108 can reset the shift signal terminal CR under the control of the voltage of the second pull-down node QB_B. <n>, the first sub-output signal terminal Oput1 <n>and a second sub-output signal terminal Oput2 <n>Reset: When the voltage at the second pull-down node QB_B is high, the fourth reset circuit 3108 can be turned on under the action of the voltage at the second pull-down node QB_B to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, to the shift signal terminal CR <n>Perform a pull-down reset and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1 <n>and the second sub-output signal terminal Oput2 <n>, for the first sub-output signal terminal Oput1 <n>and the second sub-output signal terminal Oput2 <n>Perform a pull-down reset.

[0124] Specifically, the fourth reset circuit 3108 in the first scanning unit 21a may further include: a twenty-ninth transistor M29, a thirtieth transistor M30, and a thirty-first transistor M31. The control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-ninth transistor M29 is connected to the shift signal terminal CR <n>Electrically connected, the second pole of the twenty-ninth transistor M29 is electrically connected to the second voltage signal terminal VGL1. Thus, when the voltage at the second pull-down node QB_B is at a high level, the twenty-ninth transistor M29 can be turned on under the action of the voltage at the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Perform a pull-down reset.

[0125] The control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirtieth transistor M30 is connected to the first sub-output signal terminal Oput1 <n>Electrically connected, the second pole of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2. When the voltage at the second pull-down node QB_B is at a high level, the thirtieth transistor M30 can be turned on under the action of the voltage at the second pull-down node QB_B, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Perform a pull-down reset.

[0126] The control electrode of the thirty-first transistor M31 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-first transistor M31 is connected to the second sub-output signal terminal Oput2 <n>Electrically connected, the second pole of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL2. When the voltage at the second pull-down node QB_B is at a high level, the thirty-first transistor M31 can be turned on under the action of the voltage at the second pull-down node QB_B, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput2 <n>, for the second sub-output signal terminal Oput2 <n>Perform a pull-down reset.

[0127] According to some examples of the present application, the fourth reset circuit 3108 in the second scanning unit 21b can also be electrically connected to the first pull-down node QB_A. That is, the fourth reset circuit 3108 can reset the third sub-output signal terminal Oput1<N + 1> and the fourth sub-output signal terminal Oput2<N + 1> under the control of the voltage of the first pull-down node QB_A:

[0128] When the voltage of the first pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1<N + 1>, perform a pull-down reset on the third sub-output signal terminal Oput1<N + 1>, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2<N + 1>, and perform a pull-down reset on the fourth sub-output signal terminal Oput2<N + 1>. Specifically, the fourth reset circuit 3108 may further include: a thirtieth transistor M30 and a thirty-first transistor M31.

[0129] At this time, the control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A, the first electrode of the thirtieth transistor M30 is electrically connected to the third sub-output signal terminal Oput1<N + 1>, and the second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2. When the voltage of the first pull-down node QB_A is at a high level, the thirtieth transistor M30 can be turned on under the action of the voltage of the first pull-down node QB_A, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1<N + 1>, and perform a pull-down reset on the third sub-output signal terminal Oput1<N + 1>.

[0130] The control electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB_A, the first electrode of the thirty-first transistor M31 is electrically connected to the fourth sub-output signal terminal Oput2<N + 1>, and the second electrode of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL2. When the voltage of the first pull-down node QB_A is at a high level, the thirty-first transistor M31 can be turned on under the action of the voltage of the first pull-down node QB_A, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2<N + 1>, and perform a pull-down reset on the fourth sub-output signal terminal Oput2<N + 1>.

[0131] In other examples, such as Figure 5 and Figure 8 As shown, the shift register 1230 may include: a first input circuit 3101, a leakage prevention circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108, and a fifth reset circuit 3109. Specifically, here Figure 8 The structures of the first input circuit 3101, the leakage prevention circuit 3102, the output circuit 3103, the control circuit 3104, the first reset circuit 3105, the second reset circuit 3106, the third reset circuit 3107, the fourth reset circuit 3108, and the fifth reset circuit 3109 shown in Figure 6 may be the same as the corresponding circuit structures shown in

[0132] Different from the foregoing examples, as Figure 8 shown, the output circuit 3103 is connected to the pull-up node Q <n>, the first clock signal terminal CLKE_1 and the first output signal terminal Oput1 <n>Electrically connected, during the display period in a frame display stage, at the pull-up node Q <n>Under the control of the voltage, the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 <n>; During the blanking period in a frame display stage, at the pull-up node Q <n>Under the control of the voltage, the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 <n>。

[0133] Alternatively, the output circuit 3103 may also be connected to, for example, a third clock signal terminal CLKD_1 and a shift signal terminal CR <n>Electrically connected. Thus, during the display period in a frame display stage, at the pull-up node Q <n>Under the control of the voltage, the third clock signal received at the third clock signal terminal CLKD_1 is transmitted to the shift signal terminal CR <n>Specifically, during the display period in a frame display stage, at the pull-up node Q <n>When the voltage rises, the output circuit 3103 can pull up the node Q <n>conducts under the control of the voltage, uses the third clock signal received at the third clock signal terminal CLKD_1 as a shift signal, and outputs from the shift signal terminal CR <n>Output; using the first clock signal received at the first clock signal terminal CLKE_1 as the output signal (i.e., the first gate signal received by the pixel circuit), from the first output signal terminal Oput1 <n>Output. During the blanking period in a frame display phase, at the pull-up node Q <n>In the case of an increase in voltage, the output circuit 3103 can be at the pull-up node Q <n>conducts under the control of the voltage, takes the first clock signal received at the first clock signal terminal CLKE_1 as the output signal (i.e., the second gate signal received by the pixel circuit), and outputs from the first output signal terminal Oput1 <n>Output

[0134] In this example, the first output signal terminal Oput1 of the shift register 1230 <n>Can be electrically connected to both the first gate line and the second gate line, so that during the display period in a frame display stage, the first output signal terminal Oput1 of the shift register <n>The first gate signal can be sequentially transmitted to the pixel circuit via the first gate line and the first gate signal terminal G1, and the first output signal terminal Oput1 during the blanking period in a frame display period <n>The second gate signal can be sequentially transmitted to the pixel circuit via the second gate line and the second gate signal terminal G2. In some other examples, the first output signal terminal Oput1 of the shift register <n>It can be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 respectively through a gate line, so as to facilitate the first output signal terminal Oput1 during the display period in one frame display period <n>The first gate signal can be sequentially transmitted to the pixel circuit 12 through the gate line and the first gate signal terminal G1, and during the blanking period in one frame display period, the first output signal terminal Oput1 of the shift register <n>The second gate signal can be sequentially transmitted to the pixel circuit via the gate line and the second gate signal terminal G2.

[0135] Specifically, the output circuit 3103 may include a fourth transistor M4, a fifth transistor M5, and a first capacitor C1. The control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>electrically connected, a first pole of the fourth transistor M4 is electrically connected to the third clock signal terminal CLKD_1, and a second pole of the fourth transistor M4 is electrically connected to the shift signal terminal CR <n>Electrical connection. Thus, during the display period in a frame display stage, when the first input circuit 3101 is turned on, the pull-up node Q <n>When the voltage rises, the fourth transistor M4 can pull up the node Q <n>conducts under the control of a high voltage and transmits the third clock signal to the shift signal terminal CR <n>, and use the third clock signal as a shift signal from the shift signal terminal CR <n>Output. The control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>electrically connected, a first pole of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE_1, and a second pole of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 <n>Electrically connected. The first end of the first capacitor C1 is connected to the pull-up node Q <n>Electrically connected, the second terminal of the first capacitor C1 and the first output signal terminal Oput1 <n>Electric connection.

[0136] During the display period in a frame display stage, when the first input circuit 3101 is turned on, the pull-up node Q <n>While the voltage is rising, the first capacitor C1 is charged. When the first input circuit 3101 is turned off, the first capacitor C1 can discharge, causing the pull-up node Q <n>Remain at a high level, so that the fifth transistor M5 can remain in a conducting state and transmit the first clock signal to the first output terminal Oput1 <n>, and use the first clock signal as an output signal (i.e., the first gate signal received by the pixel circuit) from the first output signal terminal Oput1 <n>Output

[0137] During the blanking period in a frame display stage, at the pull-up node Q <n>While the voltage rises, the first capacitor C1 is charged. During the corresponding phase, the first capacitor C1 can be discharged so that the pull-up node Q <n>Remain at a high level, so that the fifth transistor M6 can remain in the conducting state and transmit the first clock signal to the first output signal terminal Oput1 <n>, and use the first clock signal as an output signal (i.e., the second gate signal received by the pixel circuit) from the first output signal terminal Oput1 <n>Output

[0138] Reference Figure 8 , the fourth reset circuit 3108 and the pull-down node QB_A, the shift signal terminal CR <n>, First output signal terminal Oput1 <n>is electrically connected to the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2. Among them, the fourth reset circuit 3108 is configured to, under the control of the voltage of the pull-down node QB_A, for the shift signal terminal CR <n>and a first output signal terminal Oput1 <n>Perform a reset. Specifically, when the voltage of the pull-down node QB_A is high, the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, to the shift signal terminal CR <n>Perform a pull-down reset to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Perform a pull-down reset.

[0139] For example, the fourth reset circuit 3108 may include: a seventeenth transistor M17 and an eighteenth transistor M18. The control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A, and the first electrode of the seventeenth transistor M17 is connected to the shift signal terminal CR <n>Electrically connected, the second pole of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal VGL1. When the voltage at the pull-down node QB_A is at a high level, the seventeenth transistor M17 can be turned on under the action of the voltage at the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, to the shift signal terminal CR <n>Perform a pull-down reset. The control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A, and the first electrode of the eighteenth transistor M18 is connected to the first output signal terminal Oput1 <n>Electrically connected, the second pole of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL2. When the voltage at the pull-down node QB_A is at a high level, the eighteenth transistor M18 can be turned on under the action of the voltage at the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, to the first output signal terminal Oput1 <n>Perform a pull-down reset.

[0140] Similarly, as Figure 8 shown, the gate driving circuit may further include a plurality of blanking input circuits 3200. Among them, one blanking input circuit may be electrically connected to at least two adjacent stages of shift registers. The blanking input circuit 3200 can control the corresponding shift register to input a blanking control signal to the pixel circuit of the corresponding row during the blanking period of a frame display stage, so that the pixel circuit 12 obtains a sensing signal. Specifically, the blanking input circuit 3200 may include, for example: a selection control circuit 3201, a second input circuit 3202, and at least two transmission circuits 3203. Similarly, Figure 8 the selection control circuit 3201, the second input circuit 3202, and at least two transmission circuits 3203 used in Figure 6 may have structures and functions consistent with the corresponding structures shown in

[0141] Specifically, in the structure shown in Figure 8 the above at least two transmission circuits 3203 may be electrically connected to at least two shift registers in a one-to-one correspondence. One transmission circuit 3203 is connected to the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q of one stage of the shift register <n>Electrically connect, during the blanking period in a frame display stage, under the control of the second clock signal transmitted at the second clock signal terminal CLKA, transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q <n>。

[0142] For example, during the blanking period in a frame display stage, when the level of the second clock signal transmitted at the second clock signal terminal CLKA is high, the transmission circuit 3202 can be turned on under the control of the second clock signal, receive the second clock signal or the first voltage signal from the second blanking node N, and transmit the received second clock signal or first voltage signal to the pull-up node Q <n>, such that the pull-up node Q <n>The voltage rises, which can then cause the output circuit 3103 to conduct, enabling the output signal terminal of the output circuit 3103 to output Oput <n>Output signal. The transmission circuit 3203 may include: a twenty-fifth transistor M25, a control electrode of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, a first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and a second electrode of the twenty-fifth transistor M25 is electrically connected to the pull-up node Q <n>Electrical connection. During the blanking period in a frame display stage, when the level of the second clock signal transmitted at the second clock signal terminal CLKA is high, the twenty-fifth transistor M25 can be turned on under the action of the second clock signal, and the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the pull-up node Q <n>, for the pull-up node Q <n>Charge. The fifth transistor M5 in the output circuit 3103 can be at the pull-up node Q <n>conducts under the control of the voltage, receives the first clock signal, and uses the first clock signal as the output signal from the first output terminal Oput1 <n>Output

[0143] Similarly, when the gate driving circuit further includes a blanking input circuit, the shift register may further include a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A, and the second voltage signal terminal VGL1. During the blanking period of a frame display stage, under the common control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H, the pull-down node QB_A is reset. Specifically, during the blanking period of a frame display stage, when the level of the second clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 3110 can be turned on under the common control of the second clock signal and the voltage of the first blanking node H, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A to perform a pull-down reset on the pull-down node QB_A. The sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33.

[0144] Specifically, the control electrode of the thirty-second transistor M32 is electrically connected to the first blanking node H, the first electrode of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A, and the second electrode of the thirty-second transistor M32 is electrically connected to the first electrode of the thirty-third transistor M33. The control electrode of the thirty-third transistor M33 is electrically connected to the second clock signal terminal CLKA, and the second electrode of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL1. When the level of the second clock signal is high and the voltage of the first blanking node H is high, the thirty-third transistor M33 can be turned on under the control of the second clock signal to transmit the second voltage signal to the first electrode of the thirty-third transistor M33, and the thirty-second transistor M32 can be turned on under the control of the voltage of the first blanking node H to transmit the second voltage signal from the first electrode of the thirty-third transistor M33 to the pull-down node QB_A to perform a pull-down reset on the pull-down node QB_A.

[0145] Next, taking the example that two adjacent stages of shift registers share a blanking input circuit, the structure of the gate driving circuit will be schematically described. In the following description, N represents a positive odd number.

[0146] As Figure 8 shown, in two adjacent stages of shift registers, the fourth transistor M4 may not be provided in the output circuit 3103 of the subsequent stage shift register and is not electrically connected to the third clock signal terminal CLKD_1. At this time, the cascading relationship of the multi-stage shift register may be the same as that of the multi-stage shift register in some of the above examples, which will not be elaborated here.

[0147] For example, in two adjacent shift registers, the previous stage (i.e., the Nth stage) shift register can be referred to as the first scan unit 21a, and the subsequent stage (i.e., the N+1th stage) shift register can be referred to as the second scan unit 21b. Similarly, the pull-up node Q in the first scan unit 21a <n>Called the first pull-up node Q <n>, the pull-up node Q in the second scanning unit 21b <n>is called the second pull-up node Q<N+1>. The pull-down node QB_A in the first scan unit 21a can be called the first pull-down node QB_A, and the pull-down node QB_A in the second scan unit 21b can be called the second pull-down node QB_B. The anti-leakage node OFF in the first scan unit 21a <n>Called the first anti-electric leakage node OFF <n>, turn off the anti-leakage node in the second scanning unit 21b <n>It is called the second anti-electric leakage node OFF<N+1>. The first clock signal CLKE_1 in the second scanning unit 21b can be called the fifth clock signal CLKE_2. The first output signal terminal Oput1 in the first scanning unit 21a <n>Called the first sub-output signal terminal Oput1 <n>, the first output signal terminal Oput1 in the second scanning unit 21b <n>It is called the second sub-output signal terminal Oput1<N+1>.

[0148] Reference Figure 8 , the control circuit 3104 in the second scanning unit 21b can be electrically connected to the seventh voltage signal terminal VDD_B, and the seventh voltage signal terminal VDD_B is used to replace the sixth voltage signal terminal VDD_A. During the display phase of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are anti-phase signals to each other. In this example, the structure and function of the first reset circuit 3105 in the first scanning unit 21a can be the same as those of the first reset circuit 3105 in the first scanning unit 21a in the above some examples, and the structure and function of the first reset circuit 3105 in the second scanning unit 21b in this example can be the same as those of the first reset circuit 3105 in the second scanning unit 21b in the above some examples. For the structure and function of the same circuit, they will not be elaborated here.

[0149] Specifically, the fourth reset circuit 3108 in the first scanning unit 21a can also be electrically connected to the second pull-down node QB_B. Among them, the fourth reset circuit 3108 is further configured to, under the control of the voltage of the second pull-down node QB_B, perform operations on the shift signal terminal CR <n>and the first sub-output signal terminal Oput1 <n>Perform reset. When the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, to the shift signal terminal CR <n>Perform a pull-down reset and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Perform a pull-down reset. The fourth reset circuit 3108 in the first scan unit 21a may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30. The control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-ninth transistor M29 is connected to the shift signal terminal CR <n>Electrically connected, the second pole of the twenty-ninth transistor M29 is electrically connected to the second voltage signal terminal VGL1. When the voltage at the second pull-down node QB_B is at a high level, the twenty-ninth transistor M29 can be turned on under the action of the voltage at the second pull-down node QB_B, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, to the shift signal terminal CR <n>Perform a pull-down reset. The control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirtieth transistor M30 is connected to the first sub-output signal terminal Oput1 <n>Electrically connected, the second pole of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2. When the voltage at the second pull-down node QB_B is at a high level, the thirtieth transistor M30 can be turned on under the action of the voltage at the second pull-down node QB_B, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Perform a pull-down reset.

[0150] For example, the fourth reset circuit 3108 in the second scan unit 21b can also be electrically connected to the first pull-down node QB_A, and under the control of the voltage of the first pull-down node QB_A, reset the second sub-output signal terminal Oput1<N + 1>.

[0151] Specifically, when the voltage of the first pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1<N + 1> to perform a pull-down reset on the second sub-output signal terminal Oput1<N + 1>. The fourth reset circuit 3108 in the second scan unit 21b can also include: the thirtieth transistor M30. The control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A, the first electrode of the thirtieth transistor M30 is electrically connected to the second sub-output signal terminal Oput2<N + 1>, and the second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2. When the voltage of the first pull-down node QB_A is at a high level, the thirtieth transistor M30 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1<N + 1> to perform a pull-down reset on the second sub-output signal terminal Oput1<N + 1>.

[0152] Next, taking the structure of the shift register shown in the first example (as Figure 6 shown in) as an example, the structure of the gate driving circuit will be further described:

[0153] Refer to Figure 7 , the gate driving circuit can also include a plurality of control signal lines 33 extending along the second direction (perpendicular to Figure 1 and Figure 3 the light-shielding hole extension direction shown in). Among them, the first-stage shift register is electrically connected to at least a part of the plurality of control signal lines 33, and under the control of at least a part of the control signal lines 33 connected thereto, provides output signals to the pixel circuits of multiple pixels in the corresponding row.

[0154] Specifically, refer to Figure 7 , where RS1, RS2, RS3... RS6 shown therein respectively represent the first-stage shift register, the second-stage shift register, the third-stage shift register... the sixth-stage shift register, and are respectively electrically connected to the pixel circuits of the first-row sub-pixels, the second-row sub-pixels, the third-row sub-pixels... the sixth-row sub-pixels in the display panel.

[0155] Among them, RS1, RS3, and RS5 can respectively pass through the first sub-output signal terminal Oput1 <n>electrically connected to the first gate signal terminal G1 in the corresponding row pixel circuit, through the second sub-output signal terminal Oput2 <n>It is electrically connected to the second gate signal terminal G2 in the corresponding row pixel circuit. RS2, RS4, and RS6 can be respectively electrically connected to the first gate signal terminal G1 in the corresponding row pixel circuit through the third sub-output signal terminal Oput1<N+1>, and electrically connected to the second gate signal terminal G2 in the corresponding row pixel circuit through the fourth sub-output signal terminal Oput2<N+1>. In other words, RS1, RS3, and RS5 can be respectively referred to as the first scanning unit 21a, and RS2, RS4, and RS6 can be respectively referred to as the second scanning unit 21b.

[0156] In some examples, the above-mentioned multiple control signal lines 33 may include a first clock signal line CLK_1, a second clock signal line CLK_2, and a third clock signal line CLK_3. The third clock signal terminal CLKD_1 in the first-stage shift register is electrically connected to the first clock signal line CLK_1 to receive the third clock signal. The third clock signal terminal CLKD_1 in the third-stage shift register is electrically connected to the second clock signal line CLK_2 to receive the third clock signal. The third clock signal terminal CLKD_1 in the fifth-stage shift register is electrically connected to the third clock signal line CLK_3 to receive the third clock signal.

[0157] The above-mentioned multiple control signal lines 33 may further include a fourth clock signal line CLK_4, a fifth clock signal line CLK_5, a sixth clock signal line CLK_6, a seventh clock signal line CLK_7, an eighth clock signal line CLK_8, a ninth clock signal line CLK_9, a tenth clock signal line CLK_10, an eleventh clock signal line CLK_11, a twelfth clock signal line CLK_12, a thirteenth clock signal line CLK_13, a fourteenth clock signal line CLK_14, and a fifteenth clock signal line CLK_15.

[0158] Specifically, the first clock signal terminal CLKE_1 in the first-stage shift register is electrically connected to the fourth clock signal line CLK_4 to receive the first clock signal, and the fourth clock signal terminal CLKF_1 is electrically connected to the fifth clock signal line CLK_5 to receive the fourth clock signal. The fifth clock signal terminal CLKE_2 in the second-stage shift register is electrically connected to the sixth clock signal line CLK_6 to receive the fifth clock signal, and the sixth clock signal terminal CLKE_2 is electrically connected to the seventh clock signal line CLK_7 to receive the sixth clock signal. The first clock signal terminal CLKE_1 in the third-stage shift register is electrically connected to the eighth clock signal line CLK_8 to receive the first clock signal, and the fourth clock signal terminal CLKF_1 is electrically connected to the ninth clock signal line CLK_9 to receive the fourth clock signal. The fifth clock signal terminal CLKE_2 in the fourth-stage shift register is electrically connected to the tenth clock signal line CLK_10 to receive the fifth clock signal, and the sixth clock signal terminal CLKE_2 is electrically connected to the eleventh clock signal line CLK_11 to receive the sixth clock signal. The first clock signal terminal CLKE_1 in the fifth-stage shift register is electrically connected to the twelfth clock signal line CLK_12 to receive the first clock signal, and the fourth clock signal terminal CLKF_1 is electrically connected to the thirteenth clock signal line CLK_13 to receive the fourth clock signal. The fifth clock signal terminal CLKE_2 in the sixth-stage shift register is electrically connected to the fourteenth clock signal line CLK_14 to receive the fifth clock signal, and the sixth clock signal terminal CLKE_2 is electrically connected to the fifteenth clock signal line CLK_15 to receive the sixth clock signal.

[0159] In some other examples, the above-mentioned multiple control signal lines 33 may further include a sixteenth clock signal line CLK_16. The global reset signal terminal TRST in each stage of the shift register is electrically connected to the sixteenth clock signal line CLK_16 to receive the global reset signal.

[0160] In some other examples, the above-mentioned multiple control signal lines 33 may further include a seventeenth clock signal line CLK_17 and an eighteenth clock signal line CLK_18. The selection control signal terminal OE of each blanking input circuit is electrically connected to the seventeenth clock signal line CLK_17 to receive the selection control signal. The second clock signal terminal CLKA of each blanking input unit is electrically connected to the eighteenth clock signal line CLK_18 to receive the second clock signal.

[0161] In some examples, the above-mentioned multiple control signal lines 33 may further include a nineteenth clock signal line CLK_19 and a twentieth clock signal line CLK_20. The sixth voltage signal terminal VDD_A in the first-stage shift register, the sixth voltage signal terminal VDD_A in the third-stage shift register 21, and the sixth voltage signal terminal VDD_A in the fifth-stage shift register are all electrically connected to the nineteenth clock signal line CLK_19 to receive the sixth voltage signal. The seventh voltage signal terminal VDD_B in the second-stage shift register, the seventh voltage signal terminal VDD_B in the fourth-stage shift register, and the seventh voltage signal terminal VDD_B in the sixth-stage shift register are all electrically connected to the twentieth clock signal line CLK_20 to receive the seventh voltage signal.

[0162] In some examples, the above-mentioned multiple control signal lines 33 may further include a twenty-first clock signal line CLK_21. The input signal terminal Iput in the first-stage shift register and the input signal terminal Iput in the second-stage shift register may be both electrically connected to the twenty-first clock signal line CLK_21 to receive a start signal as an input signal.

[0163] The above-mentioned multiple control signal lines 33 may further include a twenty-second clock signal line CLK_22. The display reset signal terminals STD of the last four-stage shift registers in the gate driving circuit may be all electrically connected to the twenty-second clock signal line CLK_22 to receive a display reset signal.

[0164] Exemplarily, in the gate driving circuit, in the shift registers of other stages except the first-stage shift register and the second-stage shift register, the shift signal terminal CR in the Nth-stage shift register <n>It can be electrically connected to the input signal terminal Iput in the (N + 2)-th and (N + 3)-th stage shift registers, and further connect the shift signal terminal CR of the N-th stage shift register <n>The output shift signal serves as the input signal in the (N + 2)-th and (N + 3)-th stage shift registers. In the shift registers of other stages except the last four stages, the display reset signal terminals STD of the N-th and (N + 1)-th stage shift registers can be electrically connected to the shift signal terminal CR<N+4> of the (N + 4)-th stage shift register 21, so that the shift signal output from the shift signal terminal CR<N+4> of the (N + 4)-th stage shift register serves as the display reset signal for the N-th and (N + 1)-th stage shift registers.

[0165] It should be particularly noted here that in this application, terms such as the first pull-up node, the second pull-up node, the first pull-down node, and the second pull-down node do not represent actually existing components, but represent the convergence points of relevant electrical connections in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram. The term "pull-up" means charging a node or an electrode of a transistor to increase the absolute value of the level of the node or the electrode, so as to realize the operation of the corresponding transistor (such as turning on). The term "pull-down" means discharging a node or an electrode of a transistor to reduce the absolute value of the level of the node or the electrode, so as to realize the operation of the corresponding transistor (such as turning off).

[0166] In another aspect of this application, this application proposes a method for manufacturing the aforementioned display panel. Refer to Figure 9 , this method includes:

[0167] S100: Form a backplane circuit layer on the substrate, and form a plurality of thin film transistors in the gate driving circuit area in the display panel

[0168] According to the example of this application, the operation of forming the backplane circuit on the substrate can be performed in this step. Regarding the structure of the backplane circuit, the pixel circuit, and the structure of the gate driving circuit, detailed descriptions have been made above and will not be repeated here.

[0169] Generally speaking, this step may include operations of depositing materials and performing a patterning process to form structures constituting transistors, capacitors, and signal lines.

[0170] S200: Form a plurality of light-emitting elements on the side of the backplane circuit layer away from the substrate, and make the light-emitting elements located in the pixel area

[0171] According to the example of this application, a plurality of light-emitting elements are arranged in this step. The plurality of light-emitting elements can be OLEDs.

[0172] The method further includes operations of forming a light-shielding hole and a metal layer, and filling the metal layer into the light-shielding hole. The positions of the light-shielding hole and the metal layer in the orthographic projection on the substrate are configured to block the light of the light-emitting element from irradiating the active layer of the thin-film transistor. Thus, the foregoing display panel can be simply obtained.

[0173] In some examples of the present application, taking the light-shielding hole formed on the pixel defining structure as an example, the forming of the light-shielding hole and the metal layer may include: before forming the light-emitting element, forming a pixel defining structure in advance between a plurality of the light-emitting elements, and forming the light-shielding hole on the pixel defining structure; when forming the light-emitting element, forming the metal layer by using a cathode metal. Thus, the light-shielding hole and the metal layer can be simply formed.

[0174] In yet another aspect of the present application, the present application provides a display device. The display device includes the foregoing display panel. Thus, the display device has at least one of the advantages such as a narrow border and a long service life.

[0175] In the description of this specification, the descriptions referring to terms such as "one embodiment", "another embodiment", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment are included in at least one embodiment of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without conflict, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0176] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, wherein a display area of the display panel includes a plurality of pixel areas and a plurality of gate driving circuit areas, the gate driving circuit areas are located between two adjacent pixel areas, and the display panel includes: a substrate; a backplane circuit layer, the backplane circuit layer is located on the substrate, and in the gate driving circuit areas, the backplane circuit layer has a plurality of thin film transistors; a plurality of light emitting elements, the plurality of light emitting elements are located on a side of the backplane circuit layer away from the substrate and within the area where the pixel areas are located, the display panel has a light shielding hole filled with a metal layer, and positions of the light shielding hole and the metal layer in a positive projection on the substrate are configured to block light irradiated to an active layer of the thin film transistor; the thin film transistors in the gate driving circuit areas include: an active layer; a gate and a gate insulating layer, the gate and the gate insulating layer are located on a side of the active layer away from the substrate; source-drain electrodes, the source-drain electrodes are located on a side of the active layer away from the substrate, there is an interlayer dielectric layer between the source-drain electrodes and the gate, and the source-drain electrodes are connected to the active layer through vias penetrating the interlayer dielectric layer; there is no overlapping area between a positive projection of the light shielding hole on the substrate and a positive projection of a via of the interlayer dielectric layer on the substrate; the pixel area further includes a pixel light emitting sub-area and a pixel circuit sub-area, the light emitting elements are located in the pixel light emitting area, the pixel light emitting sub-area and the pixel circuit sub-area are arranged along a first direction, and the light shielding hole extends along the first direction; there are two light shielding holes between two adjacent pixel areas, the gate driving circuit includes a transistor group, a length of the light shielding hole along the first direction is consistent with a length of the transistor group, and a plurality of thin film transistors in the transistor group are arranged along the first direction between the two light shielding holes.

2. The display panel according to claim 1, wherein the light shielding hole and the metal layer are located on a side of the backplane circuit layer away from the substrate.

3. The display panel according to claim 2, wherein the pixel area and the gate driving circuit area are adjacent to each other, the light emitting elements are located in the pixel area, and there is a pixel defining structure between adjacent light emitting elements, and the light shielding hole is formed on the pixel defining structure.

4. The display panel according to claim 3, wherein the metal layer includes a cathode metal.

5. The display panel according to claim 1, including a plurality of the light shielding holes, and there is a light shielding hole between the thin film transistors in each pixel area and the gate driving circuit area.

6. The display panel according to any one of claims 1-5, wherein the pixel regions are arranged in an array on the substrate, each pixel region includes at least two sub-pixels, each row of pixel regions corresponds to at least two gate driving circuit regions, each gate driving circuit region is located between two adjacent pixel regions, the gate driving circuit includes a plurality of cascaded shift registers, each shift register is electrically connected to a row of sub-pixels; each shift register includes a plurality of transistor groups, and each transistor group includes at least one thin film transistor.

7. The display panel according to any one of claims 1-5, wherein the depth of the light shielding hole is 1-3 micrometers, and the width of the light shielding hole is 3-10 micrometers.

8. A method for manufacturing the display panel according to any one of claims 1-7, comprising: forming a backplane circuit layer on the substrate, and forming a plurality of thin film transistors in the gate driving circuit regions in the display panel; forming a plurality of light emitting elements on a side of the backplane circuit layer away from the substrate, and positioning the light emitting elements in the pixel regions; and the method includes operations of forming a light shielding hole and a metal layer, and filling the metal layer into the light shielding hole, and positions of the light shielding hole and the metal layer in a front projection on the substrate are configured to block light of the light emitting elements from irradiating an active layer of the thin film transistors.

9. According to the method of claim 8, forming the light shielding hole and the metal layer includes: before forming the light emitting elements, forming a pixel defining structure in advance between the plurality of light emitting elements, and forming the light shielding hole on the pixel defining structure; when forming the light emitting elements, forming the metal layer by using a cathode metal.

10. A display device, characterized in that, including the display panel according to any one of claims 1-7.

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