A control method and circuit

Abstract

The circuit of the present invention is applied to a thyristor LED driver, comprising a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a discharge current threshold adjustment module and a constant current module; the voltage conversion, zero-crossing detection and abnormal state detection modules are connected to the bus voltage divider after rectification; the voltage conversion module is connected to the abnormal state detection module and outputs a differential and integral voltage; the zero-crossing detection module is connected to the abnormal state detection module and the timing module and outputs a zero-crossing signal; the timing module is connected to the abnormal state detection module and outputs a timing signal; the abnormal state detection module is connected to the discharge current threshold adjustment module and outputs a discharge current adjustment signal; the discharge current threshold adjustment module outputs a reference voltage Vref1 to the constant current module; the constant current module is connected to a resistor Rb; and the present invention also provides a corresponding control method, which can realize real-time automatic adjustment of the discharge current according to the detected abnormal state of the dimmer and is compatible with various models of dimmers.

Description

Technical Field

[0001] The present invention relates to the field of LED dimming power supplies, and in particular to an adaptive control circuit and a control method thereof. Background Art

[0002] Early lighting generally used incandescent lamps, which generate light by heating a resistor wire. In order to meet the lighting brightness adjustment needs in different applications, the thyristor dimmer was invented. By adjusting the conduction angle of the thyristor, the effective value of the input voltage is adjusted to adjust the brightness of the incandescent lamp. This dimmer is not only widely used in public places, but also commonly used in homes.

[0003] With the development of the times, light-emitting diodes (LEDs) have become widely used as a new light source due to their advantages of color tunability, high luminous efficiency, low power consumption, high reliability, and long life. There are various dimming methods for LED light sources, such as thyristor dimming, analog dimming, PWM dimming, and switch dimming. However, since many buildings were equipped with thyristor dimmers in the early days, thyristor-dimmable LED lamps have a very large market share. Among them, linear drive thyristor dimming has a simple circuit structure and does not require magnetic components. Therefore, it is low cost, has good EMI, and is compact, making it widely used.

[0004] Existing linear drive thyristor dimming LED drive circuit is as follows Figure 1 As shown, this solution has two current-limiting units. Current-limiting unit 1 is used to set a fixed discharge current to maintain the normal operation of the thyristor, and current-limiting unit 2 is used to set a fixed maximum LED current. Since the holding current specifications of thyristors vary, and because the thyristor is inside the dimmer box and has long been fixed to the wall, a linear driver with a larger discharge current must be used to be compatible with different dimmer models. Therefore, traditional solutions often cause the discharge current to be much larger than the actual required holding current. This excess discharge current has no effect and is wasted, resulting in high power consumption, severe heat generation and other problems. Summary of the Invention

[0005] In view of this, the technical problem to be solved by the present invention is to provide a controller and control method for a dimming power supply, which can enable the linear thyristor LED driver of the present invention to detect abnormal conditions of the dimmer and automatically adjust the discharge current in real time according to the abnormal conditions, thereby achieving self-use discharge current regulation and being compatible with various models of dimmers.

[0006] The technical solutions to the above problems to be solved by the present invention are as follows:

[0007] A control circuit, applied to an LED driver, comprises a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a discharge current threshold adjustment module and a constant current module; the voltage conversion module, the zero-crossing detection module and the abnormal state detection module are used to input the bus voltage divided voltage after rectification of the LED driver; the voltage conversion module is connected to the abnormal state detection module and outputs a differential voltage V1 and an integral voltage V2 thereto; the zero-crossing detection module is connected to the abnormal state detection module and the timing module and outputs a zero-crossing signal Vz thereto; the timing module is connected to the abnormal state detection module and outputs a timing signal Vm thereto; the abnormal state detection module is connected to the discharge current threshold adjustment module and outputs a discharge current adjustment signal Vt thereto; the discharge current threshold adjustment module outputs a reference voltage Vref1 to the constant current module; one end of the constant current module is connected to one end of a resistor Rb of the LED driver; the other end of the resistor Rb of the LED driver is connected to the bus voltage after rectification of the LED driver; and the other end of the constant current module is connected to a reference ground GND.

[0008] As one of the methods for obtaining bus voltage division, one end of the upper voltage divider resistor RH is connected to the rectified bus voltage VBUS, the other end of the upper voltage divider resistor RH is connected to one end of the lower voltage divider resistor RL, the voltage conversion module, the zero-crossing detection module and the abnormal state detection module, and the other end of the lower voltage divider resistor RL is connected to the reference ground GND.

[0009] As a specific embodiment of the voltage conversion module, it includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3; one end of the resistor R5 is connected to one end of the capacitor C2, and this connection point is used to access the bus voltage divided by the rectification of the LED driver; the other end of the capacitor C2 is connected to one end of the resistor R2, one end of the resistor R3 and one end of the resistor R4, and this connection point is used to output the differential voltage V1; the other end of the resistor R2 is used to connect to the reference voltage Vref; the other end of the resistor R5 is connected to one end of the capacitor C3, and is used to output the integral voltage V2; the other end of the resistor R3, the other end of the resistor R4 and the other end of the capacitor C3 are connected to the reference ground GND.

[0010] As a specific embodiment of the zero-crossing detection module, it includes a comparator 1, a comparator 2, a capacitor C4, a resistor R6, a diode D2 and a diode D3; the negative input end of the comparator 1 is used to connect to the bus voltage divider after rectification of the LED driver, the positive input end of the comparator 1 is used to connect to the reference voltage Vref0, the output end of the comparator 1 is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to the cathode of the diode D2 and the anode of the diode D3, the cathode of the diode D3 is connected to one end of the resistor R6 and the negative input end of the comparator 2, the positive input end of the comparator 2 is used to connect to the reference voltage Vref2, the output end of the comparator 2 is connected to one end of the timing module for outputting the zero-crossing signal Vz, the other end of the timing module is connected to the abnormal state detection module for outputting the timing signal Vm, and the anode of the diode D2 and the other end of the resistor R6 are connected to the reference ground GND.

[0011] As a specific implementation of the abnormal state detection module, it includes comparator 3, comparator 4, comparator 5, comparator 6, D flip-flop 1, D flip-flop 2, counter 1 and OR gate 1; the positive input terminal of comparator 3 is used to input the integral voltage V2, the negative input terminal of comparator 3 is used to connect the reference voltage Vref3, the output terminal of comparator 3 is connected to the data input terminal D of D flip-flop 1, the output terminal Q of D flip-flop 1 is connected to the first input terminal of OR gate 1, the reset terminal R of D flip-flop 1 is used to input the zero-crossing signal Vz, the positive input terminal of comparator 4 is used to connect the reference voltage Vref4, the negative input terminal of comparator 4 is used to input the differential voltage V1, the output terminal of comparator 4 is connected to the second input terminal of OR gate 1, the positive input terminal of comparator 5 is used to input the differential voltage V1, and the comparator 4 is used to connect the reference voltage Vref4. The negative input terminal of comparator 5 is used to connect to the reference voltage Vref5, the output of comparator 5 is connected to the edge signal input terminal CP of D flip-flop 1, and is also connected to the clock signal input terminal CLK of counter 1. The reset terminal RST of counter 1 is used to input the zero-crossing signal Vz, the output terminal Q1 of counter 1 is connected to the third input terminal of OR gate 1, the positive input terminal of comparator 6 is used to connect to the reference voltage Vref6, the negative input terminal of comparator 6 is used to input the bus voltage divided by the rectification of the thyristor LED driver, the output terminal of comparator 6 is connected to the data input terminal D of D flip-flop 2, the output terminal Q of D flip-flop 2 is connected to the fourth input terminal of OR gate 1, the edge signal input terminal CP of D flip-flop 2 is used to input the timing signal Vm, and the output terminal of OR gate 1 is used to output the discharge current adjustment signal Vt.

[0012] As a specific implementation of the discharge current threshold adjustment module, it includes a counter 2, a resistor R7, a voltage-controlled current source 1, a voltage-controlled current source 2, a voltage-controlled current source 3 and a voltage-controlled current source 4; the clock signal input terminal CLK of the counter 2 is used to input the discharge current adjustment signal Vt, the output terminal Q0 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 1, the output terminal Q1 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 2, the output terminal Q2 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 3, and the output terminal Q3 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 4. The power supply terminals of the four voltage-controlled current sources are all connected to VCC, the reference terminals of the four voltage-controlled current sources are all connected to the reference ground GND, the current output terminals of the four voltage-controlled current sources are all connected to one end of the resistor R7 for outputting the reference voltage Vref1, and the other end of the resistor R7 is connected to the reference ground GND.

[0013] As a specific implementation of the constant current module, it includes an operational amplifier 1, a MOS transistor S1 and a resistor R8; the positive input terminal of the operational amplifier 1 is used to input a reference voltage Vref1, the negative input terminal of the operational amplifier 1 is connected to one end of the resistor R8 and is also connected to the source of the switch tube S1, the gate of the MOS transistor S1 is connected to the output terminal of the operational amplifier 1, the drain of the MOS transistor S1 is used to connect to one end of the resistor Rb of the thyristor LED driver, and the other end of the resistor R8 is connected to the reference ground GND.

[0014] Preferably, the control circuit further includes a thyristor access identification module, and the thyristor access identification module is connected to the abnormal state detection module and the constant current module.

[0015] As a specific implementation of the thyristor access identification module, it includes a D trigger 3 and a diode D4; the edge signal input terminal CP of the D trigger 3 is connected to the abnormal state detection module, the data input terminal D of the D trigger 3 is used to connect to the voltage VCC, the output terminal Q of the D trigger 3 is connected to the cathode of the diode D4, and the anode of the diode D4 is connected to the constant current module.

[0016] The present invention also provides a control method applied to an LED driver, characterized by comprising the following steps:

[0017] The voltage conversion step converts the input bus voltage into differential voltage V1 and integral voltage V2 and then outputs them;

[0018] a zero-crossing detection step, detecting the bus voltage divided voltage, and outputting a zero-crossing signal Vz after detecting that the bus voltage divided voltage drops from a high voltage to a low voltage;

[0019] a timing step, using the input zero-crossing signal Vz as a period reset signal for abnormal state recognition, starting timing after receiving the zero-crossing signal Vz, the timing time being a first timing time, and outputting a timing signal Vm after the first timing time expires;

[0020] an abnormal state detection step, identifying whether the dimmer is operating normally based on the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz, or based on the timing signal Vm and the bus voltage divider, and outputting a discharge current adjustment signal Vt when an abnormal state occurs, wherein the discharge current adjustment signal Vt is a pulse signal;

[0021] a discharge current threshold adjustment step of increasing the reference voltage Vref1 according to the discharge current adjustment signal Vt until the discharge current affected by the reference voltage Vref1 is just greater than the holding current of the dimmer in the LED driver, wherein the reference voltage Vref1 is increased by a small amount each time so as to better match the discharge current with the holding current of the dimmer in the LED driver;

[0022] In the constant current step, the magnitude of the discharge current is adjusted according to the change of the reference voltage Vref1.

[0023] "Identify whether the dimmer is operating normally based on the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz, or based on the timing signal Vm and the bus voltage divider" specifically means:

[0024] The differential voltage V1 is compared with a first set threshold value inside the abnormal state detection module. When the differential voltage V1 is higher than the first set threshold value, a first counting signal is output. When the first counting signal exceeds 1, it is determined that the working state of the dimmer is abnormal;

[0025] The differential voltage V1 is also compared with the second set threshold value inside the abnormal state detection module. When it is lower than the second set threshold value, it is determined that the working state of the dimmer is abnormal.

[0026] The integrated voltage V2 is compared with the third threshold value inside the abnormal state detection module at the moment when the first counting signal is first generated. If the integrated voltage V2 is higher than the third threshold value, it is determined that the working state of the dimmer is abnormal.

[0027] When the abnormal state detection module receives the timing signal Vm, the bus voltage divided voltage VB is compared with the fourth threshold value inside the abnormal state detection module. If the bus voltage divided voltage VB is lower than the fourth threshold value, it is determined that the working state of the dimmer is abnormal.

[0028] The beneficial effects of the present invention are:

[0029] 1. Adaptive regulation of discharge current is achieved through abnormal state detection of thyristor;

[0030] 2. Improve dimmer compatibility of the driver circuit solution through adaptive bleeder current regulation;

[0031] 3. Adaptive discharge current regulation is used to achieve optimal matching between discharge current and holding current, thus reducing power consumption and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is the existing linear drive thyristor dimming LED drive circuit diagram;

[0033] Figure 2 This is a circuit principle block diagram of the present invention;

[0034] Figure 3 This is a schematic diagram of the first part of the module of Example 1 of the present invention;

[0035] Figure 4 This is a schematic diagram of the second part of the module of Example 1 of the present invention;

[0036] Figure 5 This is a waveform diagram of the abnormal state of the first type of thyristor dimmer identified in the first embodiment of the present invention;

[0037] Figure 6 This is a waveform diagram of an abnormal state of a second type of thyristor dimmer identified in the first embodiment of the present invention;

[0038] Figure 7 This is a waveform diagram of the abnormal state of the third type of thyristor dimmer identified in the first embodiment of the present invention;

[0039] Figure 8 This is a waveform diagram of the abnormal state of the fourth type of thyristor dimmer identified in the first embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the first module of the second embodiment of the present invention;

[0041] Figure 10 This is a schematic diagram of the second part module of Example 2 of the present invention. DETAILED DESCRIPTION

[0042] The present invention is described in detail below in conjunction with the embodiments and the accompanying drawings to help those skilled in the art better understand the inventive concept of the present invention. However, the scope of protection of the claims of the present invention is not limited to the following embodiments. For those skilled in the art, all other embodiments obtained without creative work without departing from the inventive concept of the present invention shall fall within the scope of protection of the present invention.

[0043] The technical solution of the present invention is as follows Figure 2 As shown, combined Figure 1The linear LED driver includes a thyristor dimmer, a rectifier bridge, an upper voltage divider resistor RH, a lower voltage divider resistor RL, a control circuit, a resistor Rb, a diode D1, a load LED, a current limiting unit and a capacitor C1. The control circuit includes a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a discharge current threshold adjustment module and a constant current module. The rectified bus voltage VBUS is connected to one end of the upper voltage divider resistor RH, and the other end of the upper voltage divider resistor RH is connected to one end of the lower voltage divider resistor RL. The voltage conversion module, the zero-crossing detection module and the abnormal state detection module are connected at the same time. The other end of the lower voltage divider resistor RL is connected to the reference ground GND. The voltage conversion module outputs a differential voltage V1 and an integral voltage V2, both of which are connected to the abnormal state detection module. The zero-crossing detection module outputs a zero-crossing signal Vz to the abnormal state detection module and the timing module. The timing module outputs a timing signal Vm to the abnormal state detection module. The abnormal state detection module The block outputs a discharge current adjustment signal Vt to the discharge current threshold adjustment module, and the discharge current threshold adjustment module outputs a reference voltage Vref1 to the constant current module. One end of the constant current module is connected to one end of the resistor Rb, and the other end of the resistor Rb is connected to the bus voltage VBUS. The bus voltage VBUS is also connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the anode of the load LED and the positive electrode of the capacitor C1. The cathode of the load LED and the negative electrode of the capacitor C1 are connected and connected together to one end of the current limiting unit. The other end of the constant current module and the other end of the current limiting unit are connected to the reference ground GND.

[0044] The circuit working principle of the present invention is:

[0045] When the thyristor dimmer is connected to the power grid, the internal capacitor of the thyristor dimmer is charged, and the bus voltage VBUS begins to rise. When the internal capacitor of the thyristor dimmer is charged enough to break down the bidirectional voltage regulator diode, the thyristor dimmer will be triggered to turn on. In the initial state, the discharge current is minimum. The bus voltage VBUS is divided by the upper voltage divider resistor RH and the lower voltage divider resistor RL to obtain the bus voltage divided voltage VB. The bus voltage divided voltage VB is input to the voltage conversion module, the abnormal state detection module and the zero-crossing detection module. The voltage conversion module will convert the bus voltage divided voltage VB into a differential voltage V1 and an integral voltage V2.

[0046] When the zero-crossing detection module detects that the bus voltage divided voltage VB drops from a high voltage to a low voltage, it outputs a zero-crossing signal Vz to the abnormal state detection module. The zero-crossing signal serves as a periodic reset signal for abnormal state identification. The timing module starts timing after receiving the zero-crossing signal Vz. The timing time is the first timing time. When the first timing time is up, the timing module outputs a timing signal Vm.

[0047] The differential voltage V1 is compared with a first set threshold within the abnormal state detection module. When it exceeds the first threshold, a first count signal is output. When the first count signal exceeds one, abnormal condition 1 is determined to be met. The differential voltage V1 is also compared with a second set threshold within the abnormal state detection module. When it falls below the second threshold, abnormal condition 2 is determined to be met. The integrated voltage V2 is compared with a third threshold within the abnormal state detection module at the moment the first count signal is first generated. If the integrated voltage V2 is higher than the third threshold, abnormal condition 3 is determined to be met. When the abnormal state detection module receives the timing signal Vm, the bus voltage divided voltage VB is compared with a fourth threshold within the abnormal state detection module. If the bus voltage divided voltage VB is lower than the fourth threshold, abnormal condition 4 is determined to be met.

[0048] If any of the above abnormal conditions is met, the abnormal state detection module outputs a discharge current adjustment signal Vt. After receiving the discharge current adjustment signal Vt, the discharge current threshold adjustment module adjusts the constant current reference voltage Vref1 of the constant current module to increase by one gear, and the discharge current is increased by one gear from the minimum value. If no abnormal condition is met, it means that the thyristor dimmer is working normally. The same operation is performed in the next cycle to identify the state of the thyristor dimmer. If the discharge current is less than the holding current of the thyristor dimmer, the abnormal state will be identified, and the reference voltage Vref1 of the constant current module will be increased by one gear again. The next cycle will be detected in the same way until the discharge current is just greater than the holding current. Since the increase of one gear is small, the discharge current can be better matched with the holding current of the thyristor dimmer.

[0049] When introducing the embodiments, only the key modules of the present invention, that is, the principles of the control circuit, are described in detail, and the rest are conventional known technical modules and are not described.

[0050] Example 1

[0051] Figure 3 This is the schematic diagram of the module circuit of the first part of this embodiment. Figure 4 This is a schematic diagram of the module circuit of the second part of this embodiment. This embodiment includes a voltage conversion module, a zero-crossing detection module, a timing module, an abnormal state detection module, a discharge current threshold adjustment module and a constant current module.

[0052] The voltage conversion module is composed of resistors R2, R3, R4, R5 and capacitors C2 and C3. The zero-crossing detection module is composed of comparator 1, comparator 2, capacitor C4, resistor R6 and diodes D2 and D3. The abnormal state detection module is composed of comparator 3, comparator 4, comparator 5, comparator 6, D flip-flop 1, D flip-flop 2, counter 1 and OR gate 1. The discharge current threshold adjustment module includes counter 2, resistor R7 and voltage-controlled current sources 1, 2, 3 and 4. The constant current module includes op amp 1, MOS tube S1 and resistor R8. The specific connection relationship is as follows:

[0053] One end of resistor R5 and one end of capacitor C2 are connected to the busbar voltage divider point. The other end of capacitor C2 is connected to one end of resistor R2, one end of resistor R3, and one end of resistor R4. This connection point is the differential signal output end. The other end of resistor R3 and the other end of resistor R4 are connected to the reference ground GND. The other end of resistor R2 is connected to the reference voltage Vref. The other end of resistor R5 is the integral voltage output end, which is connected to one end of capacitor C3. The other end of capacitor C3 is connected to the reference ground GND.

[0054] The negative input terminal of the comparator 1 of the zero-crossing detection module is connected to the bus voltage divider point, the positive input terminal of the comparator 1 is connected to the reference voltage Vref0, the output terminal of the comparator 1 is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to the cathode of the diode D2 and the anode of the diode D3, the anode of the diode D2 is connected to the reference ground GND, the cathode of the diode D3 is connected to one end of the resistor R6 and the negative input terminal of the comparator 2, the other end of the resistor R6 is connected to the reference ground GND, the positive input terminal of the comparator 2 is connected to the reference voltage Vref2, the output terminal of the comparator 2 is the zero-crossing signal output point, the zero-crossing signal output point is connected to one end of the timing module, and the other end of the timing module is the timing signal output terminal;

[0055] In the abnormal state detection module, the positive input terminal of comparator 3 is connected to the integral voltage output terminal, the negative input terminal of comparator 3 is connected to the reference voltage Vref3, the output terminal of comparator 3 is connected to the data input terminal D of D flip-flop 1, the output terminal Q of D flip-flop 1 is connected to the first input terminal of OR gate 1, the reset terminal R of D flip-flop 1 is connected to the zero-crossing signal output terminal, the positive input terminal of comparator 4 is connected to the reference voltage Vref4, the negative input terminal of comparator 4 is connected to the differential signal output terminal, the output terminal of comparator 4 is connected to the second input terminal of OR gate 1, the positive input terminal of comparator 5 is connected to the differential signal output terminal, and the negative input terminal of comparator 5 is connected to the reference voltage Vref5 The output of comparator 5 is connected to the edge signal input terminal CP of D flip-flop 1 and the clock signal input terminal CLK of counter 1. The reset terminal RST of counter 1 is connected to the zero-crossing signal output terminal. The output terminal Q1 of counter 1 is connected to the third input terminal of OR gate 1. The positive input terminal of comparator 6 is connected to the reference voltage Vref6. The negative input terminal of comparator 6 is connected to the bus voltage divider point. The output terminal of comparator 6 is connected to the data input terminal D of D flip-flop 2. The output terminal Q of D flip-flop 2 is connected to the fourth input terminal of OR gate 1. The edge signal input terminal CP of D flip-flop 2 is connected to the timing signal output terminal of the timing module. The output terminal of OR gate 1 is the adjustment signal output terminal.

[0056] The clock signal input terminal CLK of the counter 2 in the discharge current threshold adjustment module is connected to the output terminal of the OR gate 1, the output terminal Q0 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 1, the output terminal Q1 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 2, the output terminal Q2 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 3, and the output terminal Q3 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 4. The power supply terminals of the four voltage-controlled current sources are all connected to VCC, the reference terminals of the four voltage-controlled current sources are all connected to GND, and the current output terminals of the four voltage-controlled current sources are all connected to one end of the resistor R7, which is the reference output terminal of the threshold adjustment module. The other end of the resistor R7 is connected to the reference ground GND.

[0057] The positive input of op amp 1 in the constant current module is connected to the reference output, the negative input of op amp 1 is connected to one end of resistor R8 and also to the source of MOS transistor S1, the other end of resistor R8 is connected to the reference ground GND, the gate of MOS transistor S1 is connected to the output of op amp 1, and the drain of MOS transistor S1 is connected to one end of the bleeder current branch resistor Rb;

[0058] The bus voltage dividing point outputs the bus voltage divided voltage VB, the integral voltage output terminal outputs the integral voltage V2, the differential signal output terminal outputs the differential voltage V1, the zero-crossing signal output terminal outputs the zero-crossing signal Vz, the timing signal output terminal outputs the timing signal Vm, the adjustment signal output terminal outputs the discharge current adjustment signal Vt, and the reference output terminal outputs the reference voltage Vref1.

[0059] Its working process is:

[0060] Case 1: When the discharge current is slightly smaller than the holding current and the thyristor dimmer is at the brightest position (RC is minimum), Figure 5 In the abnormal state shown, the thyristor dimmer is turned on and off many times. The specific abnormal identification principle is that before the bus voltage VBUS is phase-cut for the first time, it is close to zero, the differential voltage V1 maintains the voltage of the reference voltage Vref divided by the resistors R2 and R4, and the comparator 5 does not flip. When the bus voltage VBUS is phase-cut for the first time, the differential voltage V1 generates a higher voltage spike, which is higher than the reference voltage Vref5. The comparator 5 flips, and the output terminal Q0 is set to 1 after the counter 1 receives a rising edge signal. After the phase is cut, due to insufficient discharge current, the thyristor dimmer is turned off after a period of time, the bus voltage VBUS decreases, and then the capacitor inside the thyristor dimmer is recharged. When the voltage of the internal capacitor is charged to the voltage that can trigger the thyristor dimmer to turn on, the thyristor dimmer is turned on again, the bus voltage VBUS is phase-cut again, the voltage rises rapidly, and the differential voltage V1 generates a higher voltage spike again, which is higher than the reference voltage Vref5, comparator 5 flips, and after counter 1 receives a rising edge signal again, output terminal Q0 is set to 0, output terminal Q1 is set to 1, and the third input terminal of OR gate 1 is high, causing the bleeder current adjustment signal Vt to become high, generating a rising edge. This signal is input to the clock signal input terminal CLK of counter 2, and output terminal Q0 of counter 2 is set to 1. Voltage-controlled current source 1 outputs 1 unit current. Counter 2 counts the number of times the bleeder current adjustment signal Vt is actually received, and eventually causes the four voltage-controlled current sources to output the same number of unit currents as the number of times the adjustment signal appears. The current generates a bleeder current reference on resistor R7. Generally, the output current of voltage-controlled current source 1 is set to 1 times the unit current, the output current of voltage-controlled current source 2 is set to 2 times the unit current, the output current of voltage-controlled current source 3 is set to 4 times the unit current, and the output current of voltage-controlled current source 4 is set to 8 times the unit current. Operational amplifier 1 adjusts the gate voltage of MOS tube S1 according to the size of reference voltage Vref1 and the voltage on resistor R8, so that the bleeder current is constant at the desired value;

[0061] Case 2: When the discharge current is slightly smaller than the holding current and the thyristor dimmer is in the middle (RC is medium to large), Figure 6In the abnormal state shown, the thyristor dimmer shuts down prematurely. The specific abnormal identification principle is that before the bus voltage VBUS is first phase-cut, it is close to zero, the differential voltage V1 maintains the voltage of the reference voltage Vref divided by resistors R2 and R4, and the comparator 5 does not flip. When the bus voltage VBUS is first phase-cut, the differential voltage V1 generates a higher voltage spike, which is higher than the reference voltage Vref5. The comparator 5 flips, and the output terminal Q0 is set to 1 after the counter 1 receives a rising edge signal. Because the phase-cut position is late, the grid voltage is higher than the voltage drop of the load LED when the phase is cut, so the bus voltage VBUS provides current to the load LED. Therefore, although the discharge current is not large, the load LED current can maintain the normal operation of the thyristor dimmer. When the grid voltage is lower than the forward voltage drop of the load LED, the discharge current is insufficient, the thyristor dimmer is turned off, the bus voltage VBUS drops rapidly, and the differential voltage V1 generates a negative The voltage spike in the direction of the output voltage is lower than the reference voltage Vref4, the comparator 4 flips, the second input terminal of the OR gate 1 is high, the bleeder current adjustment signal Vt becomes high, and a rising edge is generated. The signal is input to the clock signal input terminal CLK of the counter 2, the output terminal Q0 of the counter 2 is set to 1, the voltage-controlled current source 1 outputs 1 unit of current, the counter 2 counts according to the number of times the bleeder current adjustment signal Vt is actually received, and eventually the four voltage-controlled current sources output the same number of unit currents as the number of times the adjustment signal appears. The current generates a bleeder current reference on the resistor R7. Generally, the output current of the voltage-controlled current source 1 is set to 1 times the unit current, the output current of the voltage-controlled current source 2 is set to 2 times the unit current, the output current of the voltage-controlled current source 3 is set to 4 times the unit current, and the output current of the voltage-controlled current source 4 is set to 8 times the unit current. The operational amplifier 1 adjusts the gate voltage of the MOS tube S1 according to the size of the reference voltage Vref1 and the voltage on the resistor R8, so that the bleeder current is constant at the desired value;

[0062] Case 3: When the discharge current is very small and the position of the thyristor dimmer is near the brightest (RC minimum), Figure 7In the abnormal state shown, the thyristor dimmer has a voltage platform phenomenon. The specific abnormal identification principle is that the bus voltage VBUS will slowly increase with the grid voltage, but the thyristor dimmer cannot be turned on. When the bus voltage VBUS rises to the voltage of the load LED parallel capacitor, the bus voltage VBUS will not continue to rise and maintain the voltage unchanged. Because there is no voltage mutation in this process, the comparators will not flip. After the platform voltage is maintained for a period of time, the capacitor inside the thyristor dimmer is charged to a voltage that can turn on the thyristor dimmer, and the thyristor dimmer is turned on. The bus voltage VBUS has the first phase cut in the cycle, and the differential voltage V1 generates a higher voltage spike. The spike voltage will be higher than the reference voltage Vref5. The comparator 5 flips and gives a rising edge to the edge signal input terminal CP of the D trigger 1. At this time, the integral voltage V2 is the divided voltage value of the platform voltage before the bus voltage mutation, which will be higher than the reference voltage Vr When ef3 is high, comparator 3 flips, and the output terminal Q of D flip-flop 1 is high. This high level enters the first input terminal of OR gate 1, causing the bleeder current adjustment signal Vt to become high, generating a rising edge. This signal is input to the clock signal input terminal CLK of counter 2, and the output terminal Q0 of counter 2 is set to 1. Voltage-controlled current source 1 outputs 1 unit current. Counter 2 counts the number of times the bleeder current adjustment signal Vt is actually received, and eventually causes the four voltage-controlled current sources to output the same number of unit currents as the number of times the adjustment signal appears. The current generates a bleeder current reference on resistor R7. Generally, the output current of voltage-controlled current source 1 is set to 1 times the unit current, the output current of voltage-controlled current source 2 is set to 2 times the unit current, the output current of voltage-controlled current source 3 is set to 4 times the unit current, and the output current of voltage-controlled current source 4 is set to 8 times the unit current. Operational amplifier 1 adjusts the gate voltage of MOS tube S1 according to the size of reference voltage Vref1 and the voltage on resistor R8, so that the bleeder current is constant at the desired value.

[0063] Case 4: When the discharge current is very small and the dimmer position is near the darkest (RC is maximum), Figure 8In the abnormal state shown, the thyristor dimmer does not turn on at all. The specific abnormal identification principle is that the bus voltage VBUS will slowly increase with the grid voltage. Because the discharge current is small, the internal capacitor of the dimmer charges very slowly and cannot reach the turn-on point of the thyristor dimmer, so the thyristor dimmer cannot turn on. When the bus voltage VBUS rises to the voltage of the load LED parallel capacitor, the bus voltage VBUS will not continue to rise and maintain the voltage unchanged. Because there is no voltage mutation in this process, the comparators will not flip because the discharge current is small. The discharge current is very small, so the capacitor voltage inside the dimmer cannot be charged to the voltage that turns on the thyristor dimmer, so the bus voltage VBUS always keeps the voltage value of the capacitor in parallel with the load LED unchanged. When the timing module reaches the timing time, the timing module outputs the timing signal Vm, which is input to the edge signal input terminal CP of the D trigger 2. The output result of the comparator 6 will be output to the output terminal Q of the D trigger 2. The negative input of the comparator 6 is the bus voltage divided voltage VB, which is basically the same as the grid voltage under normal circumstances. However, in the current abnormal situation, In the normal state, the voltage is clamped by the voltage of the parallel capacitor of the load LED. Therefore, the value of the bus voltage divider VB is less than the value of the reference voltage Vref6. The voltage output by the comparator 6 is high, and the level of the output terminal Q of the D flip-flop 2 is high. It is input to the fourth input terminal of the OR gate 1, so that the discharge current adjustment signal Vt becomes high, generating a rising edge. This signal is input to the clock signal input terminal CLK of the counter 2. The output terminal Q0 of the counter 2 is set to 1, and the voltage-controlled current source 1 outputs 1 unit of current. The counter 2 will adjust the discharge current signal V according to the actual received signal. The number of times t is counted, and finally the four voltage-controlled current sources output unit currents with the same number of unit currents as the number of times the adjustment signal appears. The current generates a discharge current reference on the resistor R7. Generally, the output current of the voltage-controlled current source 1 is set to 1 times the unit current, the output current of the voltage-controlled current source 2 is set to 2 times the unit current, the output current of the voltage-controlled current source 3 is set to 4 times the unit current, and the output current of the voltage-controlled current source 4 is set to 8 times the unit current. The operational amplifier 1 adjusts the gate voltage of the MOS tube S1 according to the size of the reference voltage Vref1 and the voltage on the resistor R8, so that the discharge current is constant at the desired value.

[0064] Figure 3 、 Figure 4 Shown only Figure 2 However, the protection scope of the claims of the present invention is not limited to the above specific implementation manner.

[0065] Example 2

[0066] The specific circuit of the second embodiment of the present invention is as follows Figure 9 and Figure 10As shown, embodiment 2 adds a thyristor access identification module on the basis of embodiment 1. The thyristor access identification module is connected to the abnormal state detection module and the constant current module. The thyristor access identification module is composed of a D trigger 3 and a diode D4. The connection relationship is as follows: the edge signal input terminal CP of the D trigger 3 is connected to the output terminal Q0 of the counter 1, the data input terminal D of the D trigger 3 is connected to the voltage VCC, the output terminal Q of the D trigger 3 is connected to the cathode of the diode D4, and the anode of the diode D4 is connected to the gate VG of the MOS tube S1 in the constant current module.

[0067] Example 2 adds a working state, which can identify whether a thyristor dimmer is connected to the circuit. The specific identification principle is that when the thyristor dimmer is connected, when it is just turned on, although the system has not yet provided a discharge current, the voltage of the load LED parallel capacitor is zero, so the capacitor charging current will charge the capacitor inside the thyristor dimmer. Therefore, when the thyristor dimmer is connected, the thyristor dimmer will be turned on at least once. After the thyristor dimmer is turned on, the bus voltage VBUS will suddenly change, and the differential voltage V1 will generate a voltage spike. The spike voltage will be higher than the reference voltage Vref5, and the comparator 5 will flip. After the counter 1 receives a rising edge signal, the output terminal Q0 is set to 1, and the edge signal input terminal CP of the D flip-flop 3 generates a rising edge, which turns the VCC high level signal of the input terminal D of the D flip-flop 3 to 1. The signal is output to the output terminal Q of the D flip-flop 3. Diode D4 is reverse-blocked and does not affect the normal discharge current control of the constant current module. This voltage value is less than the gate-source voltage threshold for turning on MOS tube S1, so the current is discharged. When the thyristor dimmer is not connected and just turned on, the bus voltage VBUS is directly equal to the grid voltage. Therefore, the bus voltage divider VB does not produce a sudden voltage change but only changes slowly. Therefore, none of the comparators will flip. Therefore, the output terminal Q0 of the counter 1 will remain low, and the D flip-flop 3 will not transmit the data from the input terminal D to the output terminal Q. The output terminal Q of the D flip-flop 3 remains low. The anode of diode D4 is clamped at approximately 0.7V, which is less than the gate-source turn-on threshold of MOS tube S1. Therefore, MOS tube S1 will not turn on, the constant current module will not generate discharge current, and power consumption is not wasted. The specific principles of the remaining working states are similar to those of Example 1 and will not be repeated here.

[0068] The above are only preferred embodiments of the present invention. It should be pointed out that the above preferred embodiments should not be regarded as limiting the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the spirit and scope of the present invention. Improvements and modifications to the triangular wave generating module, the duty cycle generating module and the logic processing module should also be regarded as within the scope of protection of the present invention. No further examples will be used here. The scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A control circuit for an LED driver, characterized in that: It includes a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a discharge current threshold adjustment module and a constant current module; The voltage conversion module, the zero-crossing detection module, and the abnormal state detection module are used to input the bus voltage divided voltage after rectification by the LED driver. The voltage conversion module is connected to the abnormal state detection module and outputs the differential voltage V1 and the integral voltage V2 to it. The zero-crossing detection module is connected to the abnormal state detection module and the timing module and outputs the zero-crossing signal Vz to it. The timing module is connected to the abnormal state detection module and outputs the timing signal Vm to it. The abnormal state detection module is connected to the discharge current threshold adjustment module and outputs the discharge current adjustment signal Vt to it. The discharge current threshold adjustment module outputs the reference voltage Vref1 to the constant current module. One end of the constant current module is connected to one end of the resistor Rb of the LED driver, and the other end of the resistor Rb of the LED driver is connected to the bus voltage after rectification by the LED driver. The other end of the constant current module is connected to the reference ground GND. The discharge current threshold adjustment module includes a counter 2, a resistor R7, a voltage-controlled current source 1, a voltage-controlled current source 2, a voltage-controlled current source 3 and a voltage-controlled current source 4; the clock signal input terminal CLK of the counter 2 is used to input the discharge current adjustment signal Vt, the output terminal Q0 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 1, the output terminal Q1 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 2, the output terminal Q2 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 3, and the output terminal Q3 of the counter 2 is connected to the voltage control terminal of the voltage-controlled current source 4. The power supply terminals of the four voltage-controlled current sources are all connected to VCC, the reference terminals of the four voltage-controlled current sources are all connected to the reference ground GND, the current output terminals of the four voltage-controlled current sources are all connected to one end of the resistor R7 for outputting the reference voltage Vref1, and the other end of the resistor R7 is connected to the reference ground GND.

2. The control circuit according to claim 1, wherein: The bus voltage division is obtained in the following manner: one end of the upper voltage divider resistor RH is connected to the rectified bus voltage VBUS, the other end of the upper voltage divider resistor RH is connected to one end of the lower voltage divider resistor RL, the voltage conversion module, the zero crossing detection module and the abnormal state detection module, and the other end of the lower voltage divider resistor RL is connected to the reference ground GND.

3. The control circuit according to claim 1, wherein: The voltage conversion module comprises resistors R2, R3, R4, R5, capacitors C2 and C3; one end of the resistor R5 is connected to one end of the capacitor C2, and the connection point is used to access the bus voltage divided by the rectification of the LED driver; the other end of the capacitor C2 is connected to one end of the resistor R2, one end of the resistor R3 and one end of the resistor R4, and the connection point is used to output the differential voltage V1; the other end of the resistor R2 is used to connect to the reference voltage Vref; the other end of the resistor R5 is connected to one end of the capacitor C3, and is used to output the integral voltage V2; the other end of the resistor R3, the other end of the resistor R4 and the other end of the capacitor C3 are connected to the reference ground GND.

4. The control circuit according to claim 1, wherein: The zero-crossing detection module includes a comparator 1, a comparator 2, a capacitor C4, a resistor R6, a diode D2 and a diode D3; the negative input end of the comparator 1 is used to connect to the bus voltage divider after rectification of the LED driver, the positive input end of the comparator 1 is used to connect to the reference voltage Vref0, the output end of the comparator 1 is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to the cathode of the diode D2 and the anode of the diode D3, the cathode of the diode D3 is connected to one end of the resistor R6 and the negative input end of the comparator 2, the positive input end of the comparator 2 is used to connect to the reference voltage Vref2, the output end of the comparator 2 is connected to one end of the timing module for outputting the zero-crossing signal Vz, the other end of the timing module is connected to the abnormal state detection module for outputting the timing signal Vm, and the anode of the diode D2 and the other end of the resistor R6 are connected to the reference ground GND.

5. The control circuit according to claim 1, wherein: The abnormal state detection module includes comparator 3, comparator 4, comparator 5, comparator 6, D flip-flop 1, D flip-flop 2, counter 1 and OR gate 1; the positive input terminal of comparator 3 is used to input the integral voltage V2, the negative input terminal of comparator 3 is used to connect the reference voltage Vref3, the output terminal of comparator 3 is connected to the data input terminal D of D flip-flop 1, the output terminal Q of D flip-flop 1 is connected to the first input terminal of OR gate 1, the reset terminal R of D flip-flop 1 is used to input the zero-crossing signal Vz, the positive input terminal of comparator 4 is used to connect the reference voltage Vref4, the negative input terminal of comparator 4 is used to input the differential voltage V1, the output terminal of comparator 4 is connected to the second input terminal of OR gate 1, the positive input terminal of comparator 5 is used to input the differential voltage V1, the negative input terminal of comparator 5 is used to input the differential voltage V1, and the negative input terminal of comparator 5 is used to input the zero-crossing signal Vz. The input terminal is used to connect the reference voltage Vref5, the output of the comparator 5 is connected to the edge signal input terminal CP of the D flip-flop 1, and is also connected to the clock signal input terminal CLK of the counter 1. The reset terminal RST of the counter 1 is used to input the zero-crossing signal Vz, the output terminal Q1 of the counter 1 is connected to the third input terminal of the OR gate 1, the positive input terminal of the comparator 6 is used to connect the reference voltage Vref6, the negative input terminal of the comparator 6 is used to input the bus voltage divided by the rectification of the thyristor LED driver, the output terminal of the comparator 6 is connected to the data input terminal D of the D flip-flop 2, the output terminal Q of the D flip-flop 2 is connected to the fourth input terminal of the OR gate 1, the edge signal input terminal CP of the D flip-flop 2 is used to input the timing signal Vm, and the output terminal of the OR gate 1 is used to output the discharge current adjustment signal Vt.

6. The control circuit according to claim 1, wherein: The constant current module includes an op amp 1, a MOS transistor S1, and a resistor R8; the positive input terminal of the op amp 1 is used to input a reference voltage Vref1, the negative input terminal of the op amp 1 is connected to one end of the resistor R8 and is also connected to the source of the switch tube S1, the gate of the MOS transistor S1 is connected to the output terminal of the op amp 1, the drain of the MOS transistor S1 is used to connect to one end of the resistor Rb of the thyristor LED driver, and the other end of the resistor R8 is connected to the reference ground GND.

7. The control circuit according to claim 1, wherein: It also includes a thyristor access identification module, which is connected to the abnormal state detection module and the constant current module.

8. The control circuit according to claim 7, wherein: The thyristor access identification module includes a D trigger 3 and a diode D4; the edge signal input terminal CP of the D trigger 3 is connected to the abnormal state detection module, the data input terminal D of the D trigger 3 is used to connect to the voltage VCC, the output terminal Q of the D trigger 3 is connected to the cathode of the diode D4, and the anode of the diode D4 is connected to the constant current module.

9. A control method, applied to an LED driver, characterized in that: The steps include: The voltage conversion step converts the input bus voltage into differential voltage V1 and integral voltage V2 and then outputs them; a zero-crossing detection step, detecting the bus voltage divided voltage, and outputting a zero-crossing signal Vz after detecting that the bus voltage divided voltage drops from a high voltage to a low voltage; a timing step, using the input zero-crossing signal Vz as a period reset signal for abnormal state recognition, starting timing after receiving the zero-crossing signal Vz, the timing time being a first timing time, and outputting a timing signal Vm after the first timing time expires; an abnormal state detection step, identifying whether the dimmer is operating normally based on the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz, or based on the timing signal Vm and the bus voltage divider, and outputting a discharge current adjustment signal Vt when an abnormal state occurs, wherein the discharge current adjustment signal Vt is a pulse signal; a discharge current threshold adjustment step of increasing the reference voltage Vref1 according to the discharge current adjustment signal Vt until the discharge current affected by the reference voltage Vref1 is just greater than the holding current of the dimmer in the LED driver, wherein the reference voltage Vref1 is increased each time by an amount such that the discharge current matches the holding current of the dimmer in the LED driver; In the constant current step, the magnitude of the discharge current is adjusted according to the change of the reference voltage Vref1.

10. The control method according to claim 9, characterized in that: The identification of whether the working state of the dimmer is normal based on the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz, or based on the timing signal Vm and the bus voltage division, is specifically as follows: The differential voltage V1 is compared with a first set threshold value inside the abnormal state detection module. When the differential voltage V1 is higher than the first set threshold value, a first counting signal is output. When the first counting signal exceeds 1, it is determined that the working state of the dimmer is abnormal; The differential voltage V1 is also compared with the second set threshold value inside the abnormal state detection module. When it is lower than the second set threshold value, it is determined that the working state of the dimmer is abnormal. The integrated voltage V2 is compared with the third threshold value inside the abnormal state detection module at the moment when the first counting signal is first generated. If the integrated voltage V2 is higher than the third threshold value, it is determined that the working state of the dimmer is abnormal. When the abnormal state detection module receives the timing signal Vm, the bus voltage divided voltage VB is compared with the fourth threshold value inside the abnormal state detection module. If the bus voltage divided voltage VB is lower than the fourth threshold value, it is determined that the working state of the dimmer is abnormal.

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