Data driver and control method

Abstract

The present disclosure document provides a data driver. The data driver includes a shift register, a logic circuit, and a data latch. The shift register is used to output a first output signal. The logic circuit is used to output a second output signal according to the first output signal output by the shift register and a reset control signal. The switch of the data latch is used to transmit a data signal to an internal node according to the second output signal. During the data setting period, when the logic circuit outputs a second output signal with a first logic level according to a first output signal with an enable level, the switch is turned on. During the reset period, the logic circuit outputs a second output signal with a first logic level according to a reset control signal with an enable level, so that the switch is turned on to transmit the data signal to the internal node.

Description

Technical Field

[0001] The present invention relates to a data driver, and more particularly to a data driver and a control method thereof. Background Art

[0002] In current display technology, if the data driver fails to reset during the reset operation of the display during power-on / power-off, it will cause problems such as uneven grayscale of the display screen. Therefore, how to improve the reset operation of the data driver is an important issue in this field. Summary of the invention

[0003] The present disclosure document provides a data driver. The data driver includes a shift register, a first logic circuit, and a data latch. The shift register is used to output a first output signal. The first logic circuit is used to output a second output signal according to the first output signal output by the shift register and a reset control signal, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs a second output signal having a first logic level. The data latch includes a switch. The switch is used to transmit a data signal to an internal node according to the second output signal. During the data setting period, when the first logic circuit outputs a second output signal having a first logic level according to the first output signal having an enable level, the switch is turned on. During the reset period, the first logic circuit outputs a second output signal having a first logic level according to the reset control signal having an enable level, so that the switch is turned on to transmit the data signal to the internal node.

[0004] The present disclosure provides a control method. The control method comprises the following steps. A shift register outputs a first output signal. A first logic circuit outputs a second output signal according to the first output signal output by the shift register and a reset control signal, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs a second output signal having a first logic level. During a reset period, the first logic circuit outputs a second output signal having a first logic level according to the reset control signal having an enable level. During a reset period, a circuit path between an internal node of a data latch and an output end of the register is turned on according to the second output signal having the first logic level, so as to transmit the output of the register to the internal node of the data latch.

[0005] In summary, the present disclosure utilizes a logic circuit to generate a second output signal based on a reset control signal and a first output signal, and during a reset period, a circuit path between an internal node of a data latch and an output end of a register is turned on based on the second output signal, thereby transmitting the reset data signal of the register to the internal node of the data latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

[0007] Figure 1 Schematic diagram of a display device according to an embodiment of the present disclosure.

[0008] Figure 2 Schematic diagram of a data latch according to an embodiment of the present disclosure.

[0009] Figure 3 Schematic diagram of a register for generating a data signal according to an embodiment of the present disclosure.

[0010] Figure 4 Schematic diagram of a logic circuit according to an embodiment of the present disclosure.

[0011] Figure 5 Schematic diagram of the timing of control signals according to an embodiment of the present disclosure.

[0012] Figure 6 Schematic diagram of a data latch according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The following is a detailed description of the embodiments and the accompanying drawings to better understand the aspects of the present invention. However, the embodiments provided are not intended to limit the scope of the present invention, and the description of the structural operation is not intended to limit the order of its execution. Any device with equal functions produced by the re-combination of components is within the scope of the present invention. In addition, according to the standards and common practices of the industry, the drawings are only for the purpose of auxiliary explanation and are not drawn according to the original size. In fact, the sizes of various features can be arbitrarily increased or reduced for the convenience of explanation. In the following description, the same components will be described with the same symbols for easy understanding.

[0014] The indexes 1 to n in the component numbers and signal numbers used in the present specification and drawings are only for the convenience of referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In the present specification and drawings, if a component number or signal number is used without specifying the index of the component number or signal number, it means that the component number or signal number refers to any unspecified component or signal in the component group or signal group to which it belongs.

[0015] In addition, the words "include", "including", "have", "contain", etc. used in this article are open terms, that is, they mean "including but not limited to". In addition, "and / or" used in this article includes any one or more items in the relevant enumerated items and all combinations thereof.

[0016] In this document, when an element is referred to as being "connected" or "coupled", it may refer to being "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish elements or operations described with the same technical terms.

[0017] Please refer to FIG. 1 , which is a schematic diagram of a display device 100 according to an embodiment of the present disclosure. As shown in FIG. 1 , the display device 100 includes a gate driver 110 , a data driver 120 , and a pixel array 130 .

[0018] In some embodiments, the gate driver 110 includes decoders GDEC[1]-GDEC[z]. Each of the decoders GDEC[1]-GDEC[z] is electrically coupled to the pixels PIX of the same pixel line of the pixel array 130 to control whether the data setting path of the pixels PIX of the pixel line is turned on, so that the corresponding pixel data is transmitted to the corresponding pixel PIX in the pixel line via the aforementioned path. In some embodiments, the pixel PIX can be implemented by a pixel embedded memory (Memory InPixel), and during the power-on / power-off period of the display device 100, the gate driver 110 can turn on the paths of all pixels to the corresponding data lines DY[1] to DT[y] to reset all the pixels PIX. In this case, if the potential reset of the data line fails, the pixel embedded memory will retain the original potential, resulting in uneven grayscale of the displayed image.

[0019] Therefore, in order to improve the uniformity of the display image when performing a reset operation during the power-on / power-off period, the present disclosure utilizes the data driver 120 to reset the potential of the data lines DY[1]-DY[y], so that each pixel in the pixel array 130 can complete the reset operation via the data lines DY[1]-DY[y], thereby improving the grayscale uniformity of the display image during the reset period. How to control the data driver 120 to perform the reset operation will be described in detail in subsequent embodiments.

[0020] The data driver 120 includes a shift register circuit 122, a data latch circuit 124, and logic circuits 126[1]-126[x]. The shift register circuit 122 includes shift registers HSR[1]-HSR[x], where "x" can be any positive integer. In some embodiments, "x" can be implemented by 26. However, in other embodiments, "x" can be implemented by 48, 52, or other positive integers. Therefore, the present invention is not limited to this.

[0021] The shift registers HSR[1]-HSR[x] are electrically coupled to the logic circuits 126[1]-126[x], respectively, and generate and transmit the first output signals OUT[1]-OUT[x] to the logic circuits 126[1]-126[x], so that the logic circuits 126[1]-126[x] generate the second output signals HSR_out[1]-HSR_out[x] and the third output signals HSR_out[1]-HSR_out[x] according to the first output signals OUT[1]-OUT[x].

[0022] The logic circuits 126[1]-126[x] are electrically coupled to the data latch circuit 124 to transmit the second output signals HSR_out[1]-HSR_out[x] to the data latch circuit 124. The data latch circuit 124 includes data latches 128[1]-128[y].

[0023] The data latches 128[1] to 128[y] are respectively connected to the data lines DY[1] to DY[y-1] to provide pixel data to the corresponding pixels PIX in the pixel column through the data lines DY[1] to DY[y-1] according to the pixel column scanned by the gate driver 110, wherein the "y" can be any positive integer. In some embodiments, the "y" can be implemented by 208, however, in other embodiments, "y" can be implemented by 312, 416, or other positive integers. Therefore, the present invention is not limited thereto.

[0024] It should be noted that the product of the number of a group of data latches (e.g., data latches 128[1] to 128[a], where data latch 128[a] is not shown in the figure) and the number of shift registers is equal to the total number of data latches. In other words, the number of data latches "a" in the aforementioned group multiplied by the total number of shift registers "x" equals the total number of data latches "y". For example, the data latches 128[1] to 128[a] in the same group are all used to receive the second output signal HSR_out[1] and the third output signal To provide pixel voltages to data lines DY[1] to DY[a] simultaneously. In some embodiments, "a" can be implemented by 8. However, in other embodiments, "a" can be implemented by 4, 16, or 24 or other positive integers. Therefore, the present invention is not limited thereto.

[0025] Similarly, another set of data latches 128[a+1]-128[2a] are all used to receive the second output signal HSR_out[2] and the third output signal To simultaneously provide pixel voltages to the data lines DY[a+1] to DY[2a].

[0026] Please refer to FIG. 2, which is a schematic diagram of a data latch 228[n] according to an embodiment of the present disclosure. Each of the data latches 128[1]-128[y] shown in FIG. 1 can be implemented by the data latch 228[n] shown in FIG. 2, where n can be any positive integer. Accordingly, the data line [n] connected to the data latch 228[n] corresponds to one of the data lines DY[1]-DY[y] shown in FIG. 1.

[0027] As shown in FIG. 2 , the data latch 228[n] includes a switch 230 and a feedback circuit 240. The switch 230 in the present disclosure is implemented as a transmission gate. In other embodiments, those skilled in the art may replace the transmission gate in the present disclosure with a P-type metal oxide field effect transistor switch or an N-type metal oxide field effect transistor switch and adjust the control signal accordingly, and the same function as the embodiment of the present disclosure can be achieved.

[0028] Specifically, the switch 230 includes a transistor 232 and a transistor 234. The first terminals of the transistor 232 and the transistor 234 are used to receive the data signal SI_D[p], and the gate terminals of the transistor 232 and the transistor 234 are used to receive the third output signal and the second output signal HSR_out[m]. The third output signal It is the inverted signal of the second output signal HSR_out[m].

[0029] The transistor 232 is implemented as a P-type transistor, and the transistor 234 is implemented as an N-type transistor. The transistor 232 and the transistor 234 are configured according to the third output signal. And the logic level of the second output signal HSR_out[m] is turned on or off at the same time.

[0030] Thus, when the second output signal HSR_out[m] has a high logic level, the switch 230 is turned on to transmit the data signal SI_D[p] to the internal node N1 via the transistors 232 and 234 .

[0031] In the embodiment of FIG. 2 , the feedback circuit 240 is implemented by a clocked-CMOS logic gate and includes transistors 242 , 244 , 246 , and 248 .

[0032] In terms of architecture, transistors 242, 244, 246, and 248 are electrically connected in series between the system high voltage terminal VDD and the ground terminal. Specifically, transistors 242 and 244 are electrically connected in series between the system high voltage terminal VDD and the internal node N1. A first terminal of transistor 242 is electrically coupled to the system high voltage terminal VDD, a second terminal of transistor 242 is electrically coupled to a first terminal of transistor 244, and a gate terminal of transistor 242 is used to receive the second output signal HSR_out[m]. Furthermore, transistors 242 and 244 may be implemented by P-type transistors.

[0033] The transistors 246 and 248 are electrically connected in series between the ground terminal and the internal node N1. The second terminal of the transistor 248 is grounded, the first terminal of the transistor 248 is electrically coupled to the second terminal of the transistor 246, and the gate terminal of the transistor 248 is used to receive the third output signal Furthermore, the transistors 246 and 248 may be implemented by N-type transistors.

[0034] Since the transistor 242 can be implemented by a P-type transistor and the transistor 248 can be implemented by an N-type transistor, when the second output signal HSR_out[m] has a low logic level, the transistor 242 conducts a circuit path from the system high voltage terminal VDD to the first terminal of the transistor 244, and the third output signal HSR_out[m] is inverse to the second output signal HSR_out[m]. With a high logic level, transistor 248 will complete a circuit path from the ground terminal to the second terminal of transistor 246 .

[0035] The second terminal of the transistor 244 and the first terminal of the transistor 246 are both electrically coupled to the internal node N1, and the gate terminals of the transistors 244 and 246 are both electrically coupled to the node N2. If the second output signal HSR_out[m] has a low logic level, the switch 230 is turned off and the transistors 242 and 248 are turned on. At this time, the level of the node N2 turns on one of the transistors 244 and 246 and turns off the other of the transistors 244 and 246, so that the potential of the system high voltage VDD is transmitted to the internal node N1 through the transistors 242 and 244 or the potential of the ground terminal is transmitted to the internal node N1 through the transistors 246 and 248 according to the level of the node N2.

[0036] Thus, when the second output signal HSR_out[m] has a low logic level, the feedback circuit 240 is used to latch the potential of the internal node N1 .

[0037] Please refer to FIG. 3, which is a schematic diagram of a register RES[p] for generating a data signal SI_D[p] according to an embodiment of the present disclosure. The register RES[p] includes pins "D", "C" and "R", which are respectively used to receive input data Input, a clock signal CLK and a reset signal which is inverse to the enable signal SCS. In some embodiments, the inverter INV is electrically coupled to the pin “R” of the register RES[p] to convert the enable signal SCS into a reset signal. And input reset signal To pin “R” of register RES[p].

[0038] Please refer to FIG. 4, which is a schematic diagram of a logic circuit 426[m] according to an embodiment of the present disclosure. As shown in FIG. 4, the logic circuit 426[m] includes logic circuits 428 and 434. Each of the logic circuits 126[1]-126[x] shown in FIG. 1 can be implemented by the logic circuit 426[m] shown in FIG. 4, where "m" can be any positive integer.

[0039] Functionally, the logic circuits 428 and 434 are used to receive and output the second output signal HSR_out[m] and the third output signal HSR_out[m] according to the first output signal OUT[m] and the reset control signal ALLCLEAR. The first output signal OUT[m] corresponds to one of the first output signals OUT[1] to OUT[x] in FIG. 1 .

[0040] Specifically, the logic circuit 428 includes a NOR gate 430 and an inverter 432. The NOR gate 430 is used to receive the first output signal OUT[m] and the reset control signal ALLCLEAR. If at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has an enable level (e.g., a high logic level), the output of the NOR gate 430 is at a low logic level, and the inverter INV electrically coupled to the output end of the NOR gate 430 generates a second output signal HSR_out[m] having a high logic level. On the other hand, if at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR both have a low logic level, the output of the NOR gate 430 is at a high logic level, and the inverter INV generates a second output signal HSR_out[m] having a low logic level.

[0041] The logic circuit 434 includes a NOR gate 436. The NOR gate 436 is used to receive the first output signal OUT[m] and the reset control signal ALLCLEAR, and if at least one of the first output signal OUT[m] and the reset control signal ALLCLEAR has a high logic level, the NOR gate 436 generates a third output signal having a low logic level. On the other hand, if the first output signal OUT[m] has a low logic level, the NOR gate 436 generates a third output signal OUT[m] having a high logic level.

[0042]

[0043] Please refer to Figures 1 to 5. Figure 5 is a schematic diagram of the timing of the control signal of the embodiment of the present disclosure. As shown in Figure 5, an operation cycle of the display device 100 from power on to power off is generally divided into four periods, namely, an initialization period T1, a maintenance period T2, a data setting period T3, a reserved period T4, and a reset period T5. It should be particularly noted that the time lengths of the periods in Figure 5 are only used for example and are not used to limit the present disclosure.

[0044] During the initialization period T1, the enable signal SCS has a second logic level (eg, a low logic level) so that the enable signal The RES[p] register has a first logic level (eg, a high logic level), thereby performing a reset operation on the register RES[p].

[0045] During the maintenance period T2, the enable signal SCS has a high logic level, so that the enable signal Has a low logic level, thereby stopping the reset operation on register RES[p].

[0046] During the data setting period T3, the register RES[p] generates and outputs the data signal SI_D[p] to the data latch 128[n] according to the input data Input and the clock signal CLK. At this time, if the third output signal HRS_out[m] has a high logic level, the switch 230 of the data latch 128[n] is turned on and transmits the data signal SI_D[p] to the internal node N1 of the data latch 128[n]. On the other hand, if the third output signal HRS_out[m] has a low logic level, the switch 230 of the data latch 128[n] is turned off, and the feedback circuit 240 of the data latch 128[n] is activated accordingly, thereby latching the potential of the internal node N1.

[0047] For example, during the period when the data signal SI_D[p] has the data voltage D(1), when the first output signal OUT[m] generated by the shift register HSR[1] has a high logic level, the second output signal HSR_out[m] generated by the logic circuit 426[m] according to the first output signal OUT[m] will have a high logic level. Accordingly, the third output signal HSR_out[m] which is inverse to the second output signal HSR_out[m] Has a low logic level.

[0048] At this time, the second output signal HSR_out[m] having a high logic level and the third output signal HSR_out[m] having a low logic level The transistors 232 and 234 in the switch 230 of the data latch 128[n] are turned on respectively, thereby transmitting the data voltage D(1) of the data signal SI_D[p] to the internal node N1 of the data latch 128[n], and the data voltage D(1) is converted into the data voltage DV(1) transmitted to the data line DY[n] via the reverse amplifiers 252, 254, 256 and 258 electrically connected in series with the internal node N1.

[0049] After the potential of the internal node N1 of the data latch 128[n] is set to the data voltage D(1), the first output signal OUT[m] generated by the shift register HSR[m] is pulled down to a low logic level, and the logic circuit 426[m] accordingly generates a second output signal HSR_out[m] having a low logic level and a third output signal HSR_out[m] having a high logic level. The data latch 128[n] is configured to receive the second output signal HSR_out[m] and the third output signal HSR_out[m]. The data voltage D(1) is latched. The operation of the feedback circuit 240 has been described in the above embodiment, so it will not be repeated here.

[0050] For another example, in the data setting period T3, if the data signal SI_D[p] has the data voltage D(q), and when the first output signal OUT[m] generated by the shift register HSR[1] has a high logic level, the second output signal HSR_out[m] generated by the logic circuit 426[m] according to the first output signal OUT[m] has a high logic level. Accordingly, the third output signal HSR_out[m] which is inverse to the second output signal HSR_out[m] is Has a low logic level.

[0051] At this time, the second output signal HSR_out[m] having a high logic level and the third output signal HSR_out[m] having a low logic level The transistors 232 and 234 in the switch 230 of the data latch 128[n] are turned on respectively, so that the data voltage D(q) of the data signal SI_D[p] is transmitted to the internal node N1 of the data latch 128[n], and the data voltage D(q) is converted into the data voltage DV(q) transmitted to the data line DY[n] via the reverse amplifiers 252, 254, 256 and 258 electrically connected in series with the internal node N1.

[0052] After the potential of the internal node N1 of the data latch 128[n] is set to the data voltage D(q), the first output signal OUT[m] generated by the shift register HSR[m] is pulled down to a low logic level, and the logic circuit 426[m] accordingly generates a second output signal HSR_out[m] having a low logic level and a third output signal HSR_out[m] having a high logic level. The data latch 128[n] is configured to receive the second output signal HSR_out[m] and the third output signal HSR_out[m]. The data voltage D(q) is latched. The operation of the feedback circuit 240 has been described in the above embodiment, so it will not be repeated here.

[0053] During the reserved period T4, since the first output signal OUT[m] and the reset control signal ALLCLEAR both have a low logic level, the logic circuit 426[m] generates a second output signal HSR_out[m] having a low logic level, and the latch operation is maintained, so that the data line DY[n] still has the data voltage DV(q). On the other hand, during the reserved period T4, since the enable signal SCS has a low logic level, the register RES[p] will be reset according to the reset signal which is opposite to the enable signal SCS. Resetting is performed to output the data signal SI_D[p] having a low logic level.

[0054] During the reset period T5, since the enable signal SCS is still maintained at a low logic level, the data signal SI_D[p] has a low logic level. Furthermore, since the reset control signal ALLCLEAR has a high logic level, the logic circuit 426[m] generates a second output signal HSR_out[m] with a high logic level to turn on the switch 230 in the data latch 228[n], thereby transmitting the data signal SI_D[p] with a low logic level to the internal node N1, thereby resetting the potential of the internal node N1 and the data line DY[n].

[0055] In other words, during the reset period T5, the switch 230 is turned on according to the second output signal HSR_out[m] having a high logic level to turn on the circuit path between the internal node N1 of the data latch 228[n] and the output end of the register RES[p], and transmits the data signal SI_D[p] having a low logic level after the register RES[p] is reset to the internal node N1 of the data latch 228[n], thereby resetting the potential of the data line DY[n] to a low logic level.

[0056] At this time, since the third output signal With a low logic level, the transistor 248 in the feedback circuit 240 is turned off, thereby cutting off the circuit path from the ground terminal to the second terminal of the transistor 246. Thus, at the beginning of the reset period T5, no matter whether the transistor 246 is turned on or not, the potential of the ground terminal is not transmitted to the internal node N1 via the transistor 248.

[0057] Furthermore, since the second output signal HSR_out[m] has a high logic level, the transistor 242 in the feedback circuit 240 is turned off, thereby cutting off the circuit path from the system high voltage terminal VDD to the first terminal of the transistor 244. Thus, at the beginning of the reset period T5, regardless of whether the transistor 244 is turned on or not, the potential of the system high voltage terminal VDD will not be transmitted to the internal node N1 via the transistor 242, resulting in a reset operation failure.

[0058] In some embodiments, the gate driver 110 turns on the circuit paths of all pixels PIX to the corresponding data lines DY[1]-DY[n] during the reset period T5. The data lines DY[1]-DY[n] simultaneously transmit the potential of the low logic level as the data voltage to all pixels PIX. Therefore, all pixels PIX of the display device 100 are reset during the reset period T5, thereby improving the uniformity of the picture of the display device 100.

[0059] Please refer to FIG. 6, which is a schematic diagram of a data latch 628[n] according to an embodiment of the present disclosure. As shown in FIG. 6, the data latch 628[n] includes a switch 630 and a feedback circuit 640. Each of the data latches 128[1] to 128[y] shown in FIG. 1 can be implemented by the data latch 628[n] shown in FIG. 6, where n can be any positive integer.

[0060] The switch 630 includes a transistor 232 and a transistor 234. The connection relationship and operation method of the switch 630 shown in FIG6 are similar to those of the switch 230 in FIG2, and thus will not be described again.

[0061] In the embodiment of FIG. 6 , the feedback circuit 640 is implemented by a transmission gate. Specifically, the feedback circuit 640 includes a transistor 642 and a transistor 644. The transistor 642 is implemented by a P-type transistor, and the transistor 644 is implemented by an N-type transistor. In terms of architecture, the transistors 642 and 644 are connected in parallel between the internal node N1 and the node N2.

[0062] Functionally, the gate terminal of the transistor 642 is used to receive the second output signal HSR_out[m], and the gate terminal of the transistor 644 is used to receive the third output signal HSR_out[m] which is opposite to the third output signal HSR_out[m]. The transistors 642 and 644 are turned on or off simultaneously according to the logic level of the second output signal HSR_out[m].

[0063] Specifically, if the second output signal HSR_out[m] has a high logic level, the switch 630 is turned on and the feedback circuit 640 is turned off. On the other hand, if the second output signal HSR_out[m] has a low logic level, the switch 630 is turned off and the feedback circuit 640 is turned on to latch the potential of the internal node N1 and transmit the potential of the internal node N1 to the data line DY[n] via the reverse amplifiers 622 and 624.

[0064] The remaining operation modes and functions of data latch 628[n] are substantially similar to those of data latch 228[n], and thus will not be described in detail here.

[0065] In summary, the present disclosure utilizes the logic circuit 426[m] to generate the second output signal HSR_out[m] according to the reset control signal ALL and the first output signal OUT[m], and in the reset period T5, the circuit path between the internal node N1 of the data latch 228[n] and the output end of the register RES[p] is turned on according to the second output signal HSR_out[m], so that the reset data signal SI_D[p] of the register RES[p] is transmitted to the internal node N1 of the data latch 228[n], thereby resetting the data latch 228[n]. In this way, the potential of the data line DY[n] can be reset.

[0066] Although the present invention has been disclosed in the implementation mode as above, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the patent application attached hereto.

[0067] Explanation of symbols

[0068] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the attached symbols are explained as follows:

[0069] 100: Display device

[0070] 110: Gate Driver

[0071] 120: Data drive

[0072] 122: Shift register circuit

[0073] 124: Data latch circuit

[0074] 126[1]~126[x],426[m]: logic circuit

[0075] 128[1]~128[y],228[n],628[n]:Data latch

[0076] 130: Pixel Array

[0077] 230,630: switch

[0078] 232,234,242,244,246,248,632,634,642,644 transistors

[0079] 240,640: Feedback circuit

[0080] 252,254,256,258,652,654: Reverse amplifier

[0081] 430,436: NOR gate

[0082] 432: Reverse

[0083] N1: Internal node

[0084] N2: Node

[0085] OUT[1]~OUT[x],OUT[m]: first output signal

[0086] HSR_out[1]~HSR_out[x],HSR_out[m]: second output signal

[0087] The third output signal

[0088] ALLCLEAR: Reset control signal

[0089] HSR[1]~HSR[x]:Shift register

[0090] DY[1]~DY[y]:Data line

[0091] D(1)~D(q),DV(1)~DV(q): data voltage

[0092] GDEC[1]~GDEC[z]: decoder

[0093] RES[p]: Register

[0094] SI_D[p]: data signal

[0095] Input: Input signal

[0096] CLK: Clock signal

[0097] SCS: Enable signal

[0098] Reset signal

[0099] INV: Inverter

[0100] T1: Initialization period

[0101] T2: Maintenance period

[0102] T3: Data setting period

[0103] T4: Reserved period

[0104] T5: Reset period

Claims

1. A data driver comprising: A shift register, used to output a first output signal; a first logic circuit, configured to output a second output signal according to the first output signal output by the shift register and a reset control signal, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs the second output signal having a first logic level; and Data latch, including: A switch, configured to transmit a data signal to an internal node according to the second output signal, wherein: During the data setting period, when the first logic circuit outputs the second output signal having the first logic level according to the first output signal having the enable level, the switch is turned on; as well as During a reset period, the first logic circuit outputs the second output signal having the first logic level according to the reset control signal having the enable level, turning on the switch to transmit the reset data signal of the second logic level to the internal node.

2. The data driver according to claim 1, comprising: A register is used to generate the data signal according to input data, a clock signal and a reset signal, wherein during a reset period, the register outputs the data signal with the second logic level according to the reset signal with the enable level, and the switch of the data latch is turned on according to the second output signal to transmit the data signal with the second logic level to the internal node.

3. The data driver according to claim 1, wherein the data latch further comprises: A feedback circuit is used to latch the potential of the internal node according to the second output signal, wherein: During the reset period, the first logic circuit outputs the second output signal having the first logic level according to the reset control signal having the enable level to turn off the feedback circuit.

4. The data driver according to claim 3, wherein during the data setting: When the first logic circuit outputs the second output signal having the first logic level according to the first output signal having the enable level, the feedback circuit is turned off; and When the first logic circuit outputs the second output signal having a second logic level according to the first output signal having a disable level and the reset control signal, the feedback circuit is turned on.

5. The data driver according to claim 3, wherein the feedback circuit is electrically coupled between the internal node and an output terminal of the data latch.

6. The data driver according to claim 3, wherein the feedback circuit is implemented by a transmission gate or a timing control-complementary metal oxide semiconductor logic circuit.

7. The data driver of claim 1, wherein the open relationship is implemented by a transmission gate.

8. The data driver according to claim 1, further comprising: The second logic circuit is used to output a third output signal according to the first output signal and the reset control signal output by the shift register, and when one of the first output signal and the reset control signal has an enable level, the second logic circuit outputs the third output signal with a second logic level.

9. The data driver according to claim 8, wherein the switch is used to transmit the data signal to the internal node according to the third output signal, wherein: During the data setting period, when the second logic circuit outputs the third output signal having the second logic level according to the first output signal having the enable level, the switch is turned on; as well as During the reset period, the second logic circuit outputs the third output signal having the second logic level to turn on the switch according to the reset control signal having the enable level.

10. A control method, comprising: Outputting a first output signal by the shift register; A first logic circuit outputs a second output signal according to the first output signal output by the shift register and a reset control signal, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs the second output signal having a first logic level; During a reset period, the first logic circuit outputs the second output signal having the first logic level according to the reset control signal having the enable level; and During the reset period, a circuit path between an internal node of the data latch and an output terminal of a register is turned on according to the second output signal having the first logic level, so as to transmit the output of the register having the reset second logic level to the internal node of the data latch.

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