pixel array substrate

Abstract

A pixel array substrate includes a substrate, a plurality of pixels, a plurality of pads, a plurality of buses, a multiplexer, a plurality of gate lines, and a plurality of transmission lines. The plurality of pixels are disposed in an active area of ​​the substrate. The plurality of pads are disposed in a first peripheral area of ​​the substrate. The plurality of buses are disposed in a second peripheral area of ​​the substrate. The multiplexer is disposed in a third peripheral area of ​​the substrate. The plurality of gate lines are electrically connected to the multiplexer and arranged in a first direction. The plurality of transmission lines are arranged in a second direction. The plurality of transmission lines include a plurality of first transmission lines. The first end and the second end of each first transmission line are electrically connected to a corresponding pad and a corresponding bus, respectively.

Description

Technical Field

[0001] The invention relates to a pixel array substrate. Background Art

[0002] With the advancement of display technology, people's demands for display devices are no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect display devices to have narrow borders or even no borders.

[0003] Generally speaking, a display device includes a pixel array arranged in an active area, a plurality of pads arranged on the upper side of the active area, an external drive unit electrically connected to the pads, and a gate drive circuit. In order to reduce the width of the left and right sides of the frame of the display device, the first part of the gate drive circuit can be arranged on the left side, right side, or both sides of the frame, and the second part of the gate drive circuit can be dispersed in the active area. In order for the first part of the gate drive circuit and the second part of the gate drive circuit to cooperate with each other and thus display the image, the external drive unit must be electrically connected to the second part of the gate drive circuit dispersed in the active area through a plurality of pads arranged on the upper side of the active area and a plurality of fan-out trace segments. However, the provision of a plurality of fan-out trace segments causes the upper side width of the frame of the active area to become larger. Summary of the Invention

[0004] The present invention provides a pixel array substrate with excellent performance.

[0005] The pixel array substrate of the present invention comprises a substrate, a plurality of pixels, a plurality of pads, a plurality of buses, a multiplexer, a plurality of data lines, a plurality of gate lines, a plurality of switching transistors, and a plurality of transmission lines. The substrate comprises an active area, a first peripheral area, a second peripheral area, and a third peripheral area. The first peripheral area, the active area, and the second peripheral area are arranged sequentially in a first direction, and the third peripheral area and the active area are arranged sequentially in a second direction, with the first direction interleaving the second direction. A plurality of pixels are disposed in the active area of ​​the substrate, each pixel comprising a pixel transistor and a pixel electrode. The pixel transistor has a first terminal, a second terminal, and a control terminal, and the pixel electrode is electrically connected to the second terminal of the pixel transistor. A plurality of pads are disposed in the first peripheral area of ​​the substrate. A plurality of buses are disposed in the second peripheral area of ​​the substrate and arranged in the first direction. The multiplexer is disposed in the third peripheral area of ​​the substrate. A plurality of data lines are disposed on the substrate and arranged in the second direction, wherein the plurality of data lines are electrically connected to the plurality of first terminals of the plurality of pixel transistors in the plurality of pixels. A plurality of gate lines are disposed on the substrate and arranged in the first direction, wherein the plurality of gate lines are electrically connected to the multiplexer. A plurality of switching transistors are disposed in an active region of a substrate, wherein a plurality of pixels are arranged in a plurality of pixel rows, wherein the plurality of pixels in each pixel row are arranged in a second direction, each switching transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of each switching transistor is electrically connected to a corresponding gate line, and the second terminal of each switching transistor is electrically connected to the plurality of control terminals of the plurality of pixel transistors in the plurality of pixels in the corresponding pixel row. A plurality of transmission lines are disposed on the substrate and arranged in the second direction, wherein each transmission line is electrically connected to the first terminal of a corresponding switching transistor, and the plurality of transmission lines include a plurality of first transmission lines, wherein the first terminal and the second terminal of each first transmission line are electrically connected to a corresponding pad and a corresponding bus, respectively.

[0006] In one embodiment of the present invention, the plurality of transmission lines further include a plurality of second transmission lines, wherein a first end of each second transmission line is structurally separated from the plurality of pads, and a second end of each second transmission line is electrically connected to a corresponding bus.

[0007] In one embodiment of the present invention, the plurality of pads described above include a plurality of pads electrically connected to the same chip-on-film package pad group, the pad group including a plurality of first pads and a plurality of second pads, the plurality of first pads being the plurality of pads in the pad group farthest from the third peripheral region, the plurality of second pads being the plurality of pads in the pad group closest to the third peripheral region, and the plurality of first ends of the plurality of first transmission lines being electrically connected to the plurality of first pads in the pad group. The plurality of transmission lines also include a plurality of third transmission lines, wherein the plurality of first ends of the plurality of third transmission lines are electrically connected to the plurality of second pads in the pad group, and the plurality of second ends of the plurality of third transmission lines are electrically connected to the plurality of bus lines. In a top view of the pixel array substrate, the plurality of second transmission lines are located between the plurality of first transmission lines and the plurality of third transmission lines.

[0008] In one embodiment of the present invention, the plurality of bus lines and the plurality of second transmission lines belong to the first conductive layer and the second conductive layer, respectively. An insulating layer is disposed between the first conductive layer and the second conductive layer. The plurality of second ends of the plurality of second transmission lines are electrically connected to the plurality of bus lines through a plurality of contact windows of the insulating layer, respectively. The plurality of pads and the plurality of contact windows are disposed in the first peripheral region and the second peripheral region, respectively.

[0009] In one embodiment of the present invention, each of the first transmission lines includes a fan-out routing segment, the plurality of bus lines and the plurality of first transmission lines belong to the first conductive layer and the second conductive layer, respectively, an insulating layer is disposed between the first conductive layer and the second conductive layer, the plurality of second ends of the plurality of first transmission lines are electrically connected to the plurality of bus lines via a plurality of contact windows of the insulating layer, and the plurality of fan-out routing segments and the plurality of contact windows of the plurality of first transmission lines are disposed in the first peripheral region and the second peripheral region, respectively.

[0010] In one embodiment of the present invention, in the top view of the pixel array substrate, the plurality of pixels are located between the plurality of pads and the plurality of bus lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

[0012] Figure 2 FIG. 1 is a partial schematic diagram of a pixel array substrate according to an embodiment of the present invention.

[0013] Figure 3 FIG. 1 is a circuit diagram of a multiplexer according to an embodiment of the present invention.

[0014] Figure 4 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate according to an embodiment of the present invention.

[0015] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate according to an embodiment of the present invention.

[0016]

Explanation of symbols

[0017] 100: Pixel array substrate

[0018] 110: Base

[0019] 110a: Active area

[0020] 110b-1: First Peripheral Area

[0021] 110b-2: Second Peripheral Area

[0022] 110b-3: The third peripheral area

[0023] 110b-4: Fourth Peripheral Area

[0024] 120: pad

[0025] 121: First pad

[0026] 122: Second pad

[0027] 130: driving element

[0028] 140: Insulation layer

[0029] 142, 144: contact window

[0030] 150: Chip-on-film packaging

[0031] A21: Switching transistor

[0032] A21a, A32a, Ta: first end

[0033] A21b, A32b, Tb: Second end

[0034] A21c, A32c, Tc: control terminal

[0035] A32: Voltage Regulator Transistor

[0036] BL, BL1, BL2, BL8: bus

[0037] DL: data line

[0038] d1: first direction

[0039] d2: second direction

[0040] G-MUX: Multiplexer

[0041] GL, GL1, GL2, GL8, GL9, GL10, GL16, GL17, GL18, GL24, GL25, GL32: Gate lines

[0042] GP, GP1, GP2, GP3, GP4: gate line group

[0043] G120: pad group

[0044] HC, HC1, HC2, HC8, HC9, HC10, HC16, HC17, HC18, HC24, HC25, HC26, HC32: Transmission lines

[0045] HCA: First Transmission Line

[0046] HCAa, HCBa, HCCa: First End

[0047] HCAb, HCBb, HCCb: second end

[0048] HCA-F, HCC-F: Fan-out trace segments

[0049] HCB: Second Transmission Line

[0050] HCC: The Third Transmission Line

[0051] M1: first conductive layer

[0052] M2: second conductive layer

[0053] PE: pixel electrode

[0054] R: Local

[0055] Rspx: pixel column

[0056] SPX: Pixel

[0057] T: Pixel transistor

[0058] W1, W2: width

[0059] I-I', II-II': section line DETAILED DESCRIPTION

[0060] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0061] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or an intermediate element can also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connected" can refer to physical and / or electrical connections. Furthermore, "electrically connected" or "coupled" can mean that there are other elements between two elements.

[0062] As used herein, "about," "approximately," or "substantially" includes the stated value and an average value that is within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" can be selected based on the optical property, etching property, or other property, and may not apply to all properties with a single standard deviation.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0064] Figure 1 FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

[0065] Please refer to Figure 1 The pixel array substrate 100 includes a substrate 110. The substrate 110 is used to support the components of the pixel array substrate 100. For example, in this embodiment, the substrate 110 may be made of glass, quartz, an organic polymer, or an opaque / reflective material (e.g., a wafer, ceramic, or other applicable materials), or other applicable materials.

[0066] The substrate 110 includes an active region 110a, a first peripheral region 110b-1, a second peripheral region 110b-2, and a third peripheral region 110b-3. The first peripheral region 110b-1, the active region 110a, and the second peripheral region 110b-2 are sequentially arranged in a first direction d1, and the third peripheral region 110b-3 and the active region 110a are sequentially arranged in a second direction d2. The first direction d1 and the second direction d2 intersect. In this embodiment, the first direction d1 and the second direction d2 are, for example, perpendicular to each other, but the present invention is not limited thereto.

[0067] In this embodiment, the substrate 110 further includes a fourth peripheral region 110b-4, wherein the third peripheral region 110b-3, the active region 110a, and the fourth peripheral region 110b-4 are sequentially arranged along the second direction d2. For example, in this embodiment, the first peripheral region 110b-1, the second peripheral region 110b-2, the third peripheral region 110b-3, and the fourth peripheral region 110b-4 may respectively constitute the upper, lower, left, and right border regions of the pixel array substrate 100.

[0068] Figure 2 FIG. 1 is a partial schematic diagram of a pixel array substrate according to an embodiment of the present invention. Figure 2 correspond Figure 1 The local R. Figure 1 Omit Figure 2 The switching transistor A21, the voltage-stabilizing transistor A32, the pixel SPX and the data line DL.

[0069] Please refer to Figure 1 and Figure 2The pixel array substrate 100 further includes a plurality of pixels SPX, which are disposed in the active region 110a of the substrate 110, wherein each pixel SPX includes a pixel transistor T and a pixel electrode PE, the pixel transistor T having a first end Ta, a second end Tb and a control end Tc, and the pixel electrode PE is electrically connected to the second end Tb of the pixel transistor T.

[0070] Please refer to Figure 1 , the pixel array substrate 100 further includes a plurality of pads 120, which are arranged in the first peripheral area 110b-1 of the substrate 110. The pads 120 are used to electrically connect to the chip-on-film package 150. The first peripheral area 110b-1 where the pads 120 are located is the signal input side of the pixel array substrate 100. The driving element film 150 further includes a driving element 130, which is electrically connected to a plurality of data lines DL. For example, in this embodiment, the driving element 130 may include a chip, and the chip may be selectively bonded to the pads 120 by a chip-on-film package (Chip On Film; COF). However, the present invention is not limited thereto. According to other embodiments, the chip may also be bonded to the pads 120 by a chip-on-glass package (Chip On Glass; COG), tape automated bonding (Tape Automated Bonding; TAB) or other methods.

[0071] The pixel array substrate 100 also includes a plurality of bus lines BL disposed in the second peripheral region 110b-2 of the substrate 110 and arranged in a first direction d1. The bus lines BL are disposed opposite the signal input side of the pixel array substrate 100 (i.e., the first peripheral region 110b-1), rather than on the signal input side of the pixel array substrate 100. In a top view of the pixel array substrate 100, the plurality of pixels SPX are located between the plurality of pads 120 and the plurality of bus lines BL.

[0072] Figure 3 This is a circuit diagram of a multiplexer according to an embodiment of the present invention. Figure 1 and Figure 3 The pixel array substrate 100 further includes a multiplexer G-MUX disposed in the third peripheral region 110 b - 3 of the substrate 110 . In this embodiment, the pixel array substrate 100 may further optionally include another multiplexer G-MUX disposed in the fourth peripheral region 110 b - 4 of the substrate 110 . Figure 3 The circuit of the multiplexer G-MUX shown is only an exemplary embodiment and is not intended to limit the present invention. In other embodiments, the circuit of the multiplexer G-MUX may also be of other types.

[0073] Please refer to Figure 1 and Figure 2The pixel array substrate 100 further includes a plurality of data lines DL disposed on the substrate 110 and arranged in the second direction d2, wherein the plurality of data lines DL are electrically connected to the plurality of first ends Ta of the plurality of pixel transistors T of the plurality of pixels SPX. The pixel array substrate 100 further includes a plurality of gate lines GL disposed on the substrate 110 and arranged in the first direction d1, wherein the plurality of gate lines GL are electrically connected to at least one multiplexer G-MUX disposed in the third peripheral region 110b-3. In this embodiment, both ends of each gate line GL may be electrically connected to two multiplexers G-MUX located in the third peripheral region 110b-3 and the fourth peripheral region 110b-4, respectively, but the present invention is not limited thereto.

[0074] Please refer to Figure 1 and Figure 2 The pixel array substrate 100 further includes a plurality of switching transistors A21 disposed in the active region 110a of the substrate 110, wherein the plurality of pixels SPX are arranged into a plurality of pixel columns Rspx, and the plurality of pixels SPX in each pixel column Rspx are arranged in the second direction d2. Each switching transistor A21 has a first end A21a, a second end A21b, and a control end A21c. The control end A21c of each switching transistor A21 is electrically connected to a corresponding gate line GL, and the second end A21b of each switching transistor A21 is electrically connected to a plurality of control ends Tc of a plurality of pixel transistors T in a corresponding pixel column Rspx.

[0075] The pixel array substrate 100 further includes a plurality of transmission lines HC disposed on the substrate 110 and arranged in the second direction d2, wherein each transmission line HC is electrically connected to the first end A21a of a corresponding switching transistor A21. In this embodiment, the pixel array substrate 100 may further optionally include a plurality of voltage-stabilizing transistors A32 disposed corresponding to the plurality of switching transistors A21, wherein the first end A32a of each voltage-stabilizing transistor A32 is electrically connected to the control end A21c of a corresponding switching transistor A21, and the control end A32c and the second end A32b of each voltage-stabilizing transistor A32 are electrically connected to each other and to the control ends Tc of the plurality of pixel transistors T of a corresponding pixel column Rspx.

[0076] Please refer to Figure 1 、 Figure 2 and Figure 3In this embodiment, the plurality of gate lines GL can be divided into a plurality of gate line groups GP. The plurality of gate line groups GP are sequentially arranged in a first direction d1. Each gate line group GP includes a plurality of gate lines GL. The plurality of gate lines GL in each gate line group GP synchronously receive gate-on signals from the multiplexer G-MUX, thereby simultaneously turning on the corresponding plurality of switching transistors A21. Furthermore, the plurality of gate line groups GP receive gate-on signals from the multiplexer G-MUX at different time intervals in a time sequence, thereby sequentially turning on the plurality of switching transistors A21 corresponding to the plurality of gate line groups GP at different time intervals.

[0077] For example, in this embodiment, the plurality of gate lines GL may be divided into a plurality of gate line groups GP1, GP2, GP3, and GP4. The plurality of gate line groups GP1, GP2, GP3, and GP4 are sequentially arranged in a first direction d1. Each gate line group GP1, GP2, GP3, and GP4 includes eight gate lines GL1 to GL8, GL9 to GL16, GL17 to GL24, and GL25 to GL32. The eight gate lines GL1 to GL8, GL9 to GL16, GL17 to GL24, and GL25 to GL32 of each gate line group GP1, GP2, GP3, and GP4 synchronously receive gate-on signals from the multiplexer G-MUX, causing the corresponding plurality of switch transistors A21 to be turned on simultaneously. On the other hand, the plurality of gate line groups GP1, GP2, GP3, GP4 receive gate-on signals from the multiplexer G-MUX at different time intervals in sequence, so that the plurality of switch transistors A21 corresponding to the plurality of gate line groups GP1, GP2, GP3, GP4 are turned on in sequence at different time intervals.

[0078] In this embodiment, each transmission line HC corresponds to a gate line GL. For example, in this embodiment, a plurality of transmission lines HC1-HC8, HC9-HC16, HC17-HC24, HC25-HC32 correspond to a plurality of gate lines GL1-GL8, GL9-GL16, GL17-GL24, GL25-GL32, respectively.

[0079] When the multiple gate lines GL of a certain gate line group GP synchronously receive the gate-on signal from the multiplexer G-MUX in a time interval, the multiple switching transistors A21 corresponding to the multiple gate lines GL of the certain gate line group GP are simultaneously turned on; within this time interval, the external driving unit will provide the pixel gate-on signal to the multiple transmission lines HC corresponding to the multiple gate lines GL of the said gate line group GP through the thin film flip chip package 150 in a time sequence, so that the multiple pixel transistors T of the multiple pixel columns Rspx of the multiple gate lines GL corresponding to the same gate line group GP are turned on in a time sequence, thereby causing the multiple pixel electrodes PE of the multiple pixel columns Rspx of the multiple gate lines GL corresponding to the same gate line group GP to be charged to a specified potential.

[0080] For example, the multiple gate lines GL1~GL8 of the gate line group GP1 synchronously receive the gate start signal from the multiplexer G-MUX in a time interval, so that the multiple switching transistors A21 corresponding to the multiple gate lines GL1~GL8 of the gate line group GP1 are turned on at the same time; during this time interval, the external driving unit will provide the pixel gate start signal to the multiple transmission lines HC1~HC8 corresponding to the multiple gate lines GL1~GL8 through the thin film flip chip package 150 in a timing sequence, so that the multiple pixel transistors T of the multiple pixel columns Rspx of the multiple gate lines GL1~GL8 corresponding to the same gate line group GP1 are turned on in a timing sequence, and then the multiple pixel electrodes PE of the multiple pixel columns Rspx of the multiple gate lines GL1~GL8 corresponding to the same gate line group GP1 are charged to a specified potential.

[0081] The plurality of transmission lines HC of the pixel array substrate 100 include a plurality of first transmission lines HCA, wherein the first end HCAa and the second end HCAb of each first transmission line HCA are electrically connected to a corresponding pad 120 and a corresponding bus line BL, respectively. The plurality of transmission lines HC of the pixel array substrate 100 also include a plurality of second transmission lines HCB, wherein the first end HCBa of each second transmission line HCB is structurally separated from the plurality of pads 120, and the second end HCBb of each second transmission line HCB is electrically connected to a corresponding bus line BL.

[0082] It's worth noting that the multiple bus lines BL are located in the second peripheral area 110b-2, which has a relatively ample layout area. The multiple second transmission lines HCB utilize the existing multiple first transmission lines HCA and the multiple bus lines BL located in the second peripheral area 110b-2 to receive pixel gate-on signals from the chip-on-film package 150. The second transmission lines HCB themselves do not necessarily have fan-out routing segments located in the first peripheral area 110b-1. Consequently, the width W1 (i.e., the width of the upper border area) of the first peripheral area 110b-1 of the pixel array substrate 110 in the first direction d1 is reduced without excessively affecting the width W2 (i.e., the width of the lower border area) of the second peripheral area 110b-2 in the first direction d1.

[0083] For example, in this embodiment, the plurality of bus lines BL include a plurality of bus lines BL1 to BL8 arranged in sequence in the first direction d1, the plurality of first transmission lines HCA include transmission lines HC1 to HC8, and the plurality of second transmission lines HCB include transmission lines HC17 to HC24, wherein the transmission line HC17 receives the pixel gate-on signal from the chip-on-film package 150 by utilizing the existing transmission line HC1 and the bus line BL1 disposed in the second peripheral area 110b-2, the transmission line HC18 receives the pixel gate-on signal from the chip-on-film package 150 by utilizing the existing transmission line HC2 and the bus line BL2 disposed in the second peripheral area 110b-2, ..., the transmission line HC24 receives the pixel gate-on signal from the chip-on-film package 150 by utilizing the existing transmission line HC8 and the bus line BL8 disposed in the second peripheral area 110b-2, but the present invention is not limited thereto.

[0084] Please refer to Figure 1 The plurality of pads 120 of the pixel array substrate 100 include a pad group G120 electrically connected to the same chip-on-film package 150. The pad group G120 includes a plurality of first pads 121 and a plurality of second pads 122. The plurality of first pads 121 are the plurality of pads 120 in the pad group G120 farthest from the third peripheral region 110b-3, while the plurality of second pads 122 are the plurality of pads 120 in the pad group G120 closest to the third peripheral region 110b-3. In this embodiment, the plurality of first ends HCAa of the plurality of first transmission lines HCA are electrically connected to the plurality of first pads 121 of the pad group G120.

[0085] In this embodiment, the plurality of transmission lines HC also includes a plurality of third transmission lines HCC, wherein the plurality of first ends HCCa of the plurality of third transmission lines HCC are respectively electrically connected to the plurality of second pads 122 of the pad group G120, and the plurality of second ends HCCb of the plurality of third transmission lines HCC are respectively electrically connected to the plurality of bus lines BL. In a top view of the pixel array substrate 100, the plurality of second transmission lines HCB are located between the plurality of first transmission lines HCA and the plurality of third transmission lines HCC. In other words, between the plurality of groups of transmission lines HC having fan-out routing segments HCA-F and HCC-F and electrically connected to the left and right outermost pads 120, at least another group of transmission lines HC is located, and this other group of transmission lines HC does not have a fan-out routing segment in the first peripheral area 110b-1.

[0086] For example, in this embodiment, the plurality of first transmission lines HCA include transmission lines HC1 to HC8, the plurality of second transmission lines HCB include transmission lines HC17 to HC24 and HC25 to HC32, and the plurality of third transmission lines HCC include transmission lines HC9 to HC16. In a top view of the pixel array substrate 100, the transmission lines HC17 to HC24 and HC25 to HC32 without fan-out routing segments in the first peripheral area 110b-1 are located between the plurality of transmission lines HC1 to HC8 and the plurality of transmission lines HC9 to HC16 with fan-out routing segments HCA-F and HCC-F, but the present invention is not limited to this.

[0087] Figure 4 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate according to an embodiment of the present invention. Figure 4 correspond Figure 1 Section line I-I'. Figure 5 FIG. 1 is a cross-sectional schematic diagram of a pixel array substrate according to an embodiment of the present invention. Figure 5 correspond Figure 1 Section line II-II'.

[0088] Please refer to Figure 1 and Figure 4 In this embodiment, each first transmission line HCA includes a fan-out trace segment HCA-F. The multiple bus lines BL and the multiple first transmission lines HCA are located in the first conductive layer M1 and the second conductive layer M2, respectively. The insulating layer 140 is disposed between the first conductive layer M1 and the second conductive layer M2. The multiple second ends HCAb of the multiple first transmission lines HCA are electrically connected to the multiple bus lines BL via multiple contact windows 142 of the insulating layer 140. In particular, the multiple fan-out trace segments HCA-F and the multiple contact windows 142 of the multiple first transmission lines HCA are disposed in the first peripheral area 110b-1 and the second peripheral area 110b-2, respectively. In other words, the fan-out trace segments HCA-F of the first transmission lines HCA and the connection points between the first transmission lines HCA and the bus lines BL are located in the upper and lower border areas, respectively, rather than both being located in the upper border area.

[0089] Please refer to Figure 1 and Figure 5 In this embodiment, the plurality of bus lines BL and the plurality of second transmission lines HCB are located in the first conductive layer M1 and the second conductive layer M2, respectively. An insulating layer 140 is disposed between the first conductive layer M1 and the second conductive layer M2. The plurality of second ends HCBb of the plurality of second transmission lines HCB are electrically connected to the plurality of bus lines BL via a plurality of contact windows 144 in the insulating layer 140. Furthermore, the plurality of pads 120 and the plurality of contact windows 144 are disposed in the first peripheral region 110b-1 and the second peripheral region 110b-2, respectively. In other words, the pads 120 for bonding to the chip-on-film package 150 and the connection points between the second transmission lines HCB and the bus lines BL are located in the upper and lower frame regions, respectively, rather than both being located in the upper frame region.

Claims

1. A pixel array substrate, comprising: A substrate having an active region, a first peripheral region, a second peripheral region, and a third peripheral region, wherein the first peripheral region, the active region, and the second peripheral region are sequentially arranged in a first direction, the third peripheral region and the active region are sequentially arranged in a second direction, and the first direction and the second direction are staggered; A plurality of pixels are disposed in the active area of ​​the substrate, wherein each pixel includes a pixel transistor and a pixel electrode, the pixel transistor having a first terminal, a second terminal, and a control terminal, and the pixel electrode is electrically connected to the second terminal of the pixel transistor; A plurality of pads are disposed in the first peripheral region of the substrate; A plurality of bus lines are disposed in the second peripheral region of the substrate and arranged in the first direction; a multiplexer disposed in the third peripheral region of the substrate; a plurality of data lines disposed on the substrate and arranged in the second direction, wherein the data lines are electrically connected to a plurality of first terminals of a plurality of pixel transistors of the pixels; a plurality of gate lines disposed on the substrate and arranged in the first direction, wherein the gate lines are electrically connected to the multiplexer; a plurality of switch transistors disposed in the active region of the substrate, wherein the pixels are arranged in a plurality of pixel rows, a plurality of pixels in each pixel row are arranged in the second direction, each switch transistor having a first end, a second end, and a control end, the control end of each switch transistor being electrically connected to a corresponding gate line, and the second end of each switch transistor being electrically connected to a plurality of control ends of a plurality of pixel transistors of a plurality of pixels in a corresponding pixel row; as well as A plurality of transmission lines are disposed on the substrate and arranged in the second direction, wherein each transmission line is electrically connected to the first end of a corresponding switching transistor, the transmission lines including a plurality of first transmission lines and a plurality of second transmission lines, and the first end and the second end of each first transmission line are electrically connected to a corresponding pad and a corresponding bus, respectively. Each of the first transmission lines includes a fan-out routing segment disposed in the first peripheral region. The second transmission line does not have a fan-out routing segment disposed in the first peripheral region, and utilizes the existing first transmission line and a bus disposed in the second peripheral region to receive a gate-on signal. 2 . The pixel array substrate as claimed in claim 1 , wherein a first end of each second transmission line is structurally separated from the pads, and a second end of each second transmission line is electrically connected to a corresponding bus line.

3. The pixel array substrate of claim 2 , wherein the pads comprise a pad group electrically connected to a same chip-on-film package, the pad group comprising a plurality of first pads and a plurality of second pads, the first pads being pads farthest from the third peripheral region in the pad group, and the second pads being pads closest to the third peripheral region in the pad group, the first ends of the first transmission lines being electrically connected to the first pads of the pad group, and the transmission lines further comprising: a plurality of third transmission lines, wherein a plurality of first ends of the third transmission lines are respectively electrically connected to the second pads of the pad group, and a plurality of second ends of the third transmission lines are respectively electrically connected to the busses; In a top view of the pixel array substrate, the second transmission lines are located between the first transmission lines and the third transmission lines.

4. The pixel array substrate as described in claim 2, wherein the bus lines and the second transmission lines belong to the first conductive layer and the second conductive layer respectively, an insulating layer is arranged between the first conductive layer and the second conductive layer, the second ends of the second transmission lines are electrically connected to the bus lines through the contact windows of the insulating layer, and the pads and the contact windows are respectively arranged in the first peripheral area and the second peripheral area.

5. The pixel array substrate as described in claim 1, wherein the bus lines and the first transmission lines belong to a first conductive layer and a second conductive layer, respectively, an insulating layer is disposed between the first conductive layer and the second conductive layer, the second ends of the first transmission lines are electrically connected to the bus lines through a plurality of contact windows of the insulating layer, and the fan-out routing segments of the first transmission lines and the contact windows are disposed in the first peripheral area and the second peripheral area, respectively. 6 . The pixel array substrate as claimed in claim 1 , wherein in a top view of the pixel array substrate, the pixels are located between the pads and the bus bars.

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