Testing equipment and its usage

Abstract

This invention relates to a testing device and its method of use. A testing device for a semiconductor package includes a circuit board, multiple test patterns, and a socket. The circuit board has a test area and includes multiple test contacts and multiple signal contacts distributed within the test area. The multiple test patterns are embedded in the circuit board and electrically connected to the multiple test contacts. Each of the multiple test patterns includes a first wire and a second wire, the second wire including a main body and a branch connected to the main body, wherein the first wire is connected to the main body. The socket is located on the circuit board and includes multiple connectors electrically connected to the circuit board, wherein the multiple connectors are configured to transmit electrical signals from the testing device for testing the semiconductor package.

Description

Technical Field

[0001] This invention relates to a testing device and its usage method. Background Technology

[0002] Semiconductor devices and integrated circuits (ICs) are typically manufactured on a single semiconductor wafer. Wafer-level dies can be processed and packaged together with other semiconductor devices or dies at the wafer level, and various wafer-level packaging technologies have been developed. Semiconductor processing for manufacturing semiconductor devices and ICs continues to evolve towards increased device density and an increasing number of active devices (primarily transistors) with shrinking device sizes. With the continuous miniaturization of electronic products, warpage caused by temperature rise has become a significant challenge for packaging technology. Summary of the Invention

[0003] This invention provides a testing device for semiconductor packages, including a circuit board, multiple test patterns, and a socket. The circuit board has a test area and includes multiple test contacts and multiple signal contacts distributed within the test area. The multiple test patterns are embedded in the circuit board and electrically connected to the multiple test contacts. Each of the multiple test patterns includes a first wire and a second wire, the second wire including a main body and a branch connected to the main body, wherein the first wire is connected to the main body. The socket is located on the circuit board and includes multiple connectors electrically connected to the circuit board, wherein the multiple connectors are configured to transmit electrical signals for testing the semiconductor package from the testing device. Attached Figure Description

[0004] A thorough understanding of all aspects of this disclosure is best achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0005] Figure 1 This is a flowchart of a method for using a test device according to some embodiments of the present disclosure.

[0006] Figure 2 This is a schematic exploded view of a test apparatus according to some embodiments of the present disclosure.

[0007] Figure 3 yes Figure 2 A schematic cross-sectional view of the test equipment depicted in the figure.

[0008] Figure 4A yes Figure 2A schematic plan view of the relative positions of a portion of the components of the circuit board structure included in the test equipment depicted.

[0009] Figure 4B yes Figure 4A A schematic perspective view of the component indicated by the dashed frame X depicted in the figure.

[0010] Figure 5 This is a schematic exploded view of a test apparatus and semiconductor package assembly according to some embodiments of the present disclosure.

[0011] Figure 6 yes Figure 5 A schematic cross-sectional view of the assembly depicted in the figure.

[0012] Figure 7 yes Figure 5 The diagram depicts a schematic plan view showing the relative positions of the components of the circuit board structure of the test equipment included in the assembly.

[0013] Figures 8 to 13 These are schematic enlarged top views of various configurations of test channels and test points in a circuit board structure included in an assembly according to some embodiments of the present disclosure.

[0014] Figure 14A This is an exemplary equivalent circuit diagram of an assembly according to some embodiments.

[0015] Figure 14B yes Figure 14A An enlarged view of a portion of the assembly depicted in the image.

[0016] Figure 15A This is an exemplary equivalent circuit diagram of an assembly according to some embodiments.

[0017] Figure 15B yes Figure 15A An enlarged view of a portion of the assembly depicted in the image.

[0018] Figure 16A This is an exemplary equivalent circuit diagram of an assembly according to some embodiments.

[0019] Figure 16B yes Figure 16A An enlarged view of a portion of the assembly depicted in the image.

[0020] Figure 17A and Figure 17B This is an exemplary equivalent circuit diagram of a test method using an assembly according to some embodiments.

[0021] [Explanation of Symbols]

[0022] 10: Assembly

[0023] 100: Test Module

[0024] 1000: Test equipment

[0025] 110: Main Body

[0026] 110t, 314b, 314t, S222b, S222t: Surface

[0027] 120: Conductive contact

[0028] 200: Circuit Board Structure

[0029] 210: Fixture

[0030] 220: Circuit board

[0031] 222, 222a, 222b, 222c, 222d: Dielectric layers

[0032] 224, 224a, 224b, 224c, 224d: Metallic through holes

[0033] 226, 226a, 226b, 226c, 226d: Metallic traces

[0034] 230: Connector

[0035] 300: Socket

[0036] 310: Base

[0037] 312: Flange portion

[0038] 312i: Inner surface

[0039] 314: Central Section

[0040] 320, 322, 324: Conductive connectors

[0041] 322a, 322b, 324a, 324b: End portion

[0042] 322c, 324c: Main body

[0043] 330: Cover

[0044] 400: Semiconductor package

[0045] 410: Semiconductor die

[0046] 412, 422: Through holes

[0047] 420: I / O interface die

[0048] 430: Insulating Encapsulation

[0049] 440: Re-layout circuit structure

[0050] 440A: Fine Feature Section

[0051] 440B: Thick and coarse characteristic portion

[0052] 442A, 442B: Dielectric structure

[0053] 444A, 444B: Metallized patterns

[0054] 450, 452, 454: Conductive elements

[0055] 500: Clamping device

[0056] 510: Bolt

[0057] 530: Fasteners

[0058] CL1, CL2: Midline

[0059] CP: Contact Point

[0060] CR: Chip Area

[0061] D1, D2: Width

[0062] DL1, DL2: Diagonal

[0063] DUT: Object to be tested

[0064] I1, I2: Current

[0065] L1, L2: Wires

[0066] L2b: Branch Office

[0067] L2m: Main body

[0068] ME: Merge Edge / Merge Section

[0069] O1: Space

[0070] R, R L1 R L2b :resistance

[0071] R1, R2: Depression

[0072] S1: Top surface shown

[0073] S110, S120, S130: Steps

[0074] S2: Bottom surface shown

[0075] SP1, SP2, SP3: Distance

[0076] TP: Test pattern

[0077] TPP: Test Point

[0078] V1, V2, V3, V4: Voltage

[0079] X: dashed border Detailed Implementation

[0080] The following disclosure provides numerous different embodiments or examples to implement various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are also contemplated. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, an indication of the relationship between the various embodiments and / or configurations discussed.

[0081] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" are used herein to describe the relationship between one element or feature illustrated in the figures and another element or feature. In addition to the orientations shown in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0082] In addition, for ease of explanation, terms such as "first," "second," "third," and "fourth" may be used in this document to describe similar or different elements or features shown in the figures, and these terms may be used interchangeably depending on the order of their existence or the context of the description.

[0083] Figure 1 This is a flowchart of a method for using a test device according to some embodiments of the present disclosure. Figure 2 This is a schematic exploded view of a test apparatus 1000 according to some embodiments of the present disclosure. Figure 3 yes Figure 2 A schematic cross-sectional view of the test equipment 1000 depicted in the figure. Figure 4A yes Figure 2 A schematic plan view depicting the relative positions of components of a circuit board structure included in the test equipment 1000, wherein... Figure 3 Show along Figure 4A An enlarged cross-sectional view taken from the dashed lines (diagonal DL1 or diagonal DL2) depicted in the figure. Figure 4B yes Figure 4A A schematic perspective view of the component indicated by the dashed frame X depicted in the figure. Figure 4A and Figure 4B Omitted Figure 2 and Figure 3 Some of the components shown are illustrated in concise schematic top views and schematic perspective views. These embodiments are intended to provide further explanation but are not intended to limit the scope of this disclosure.

[0084] In some embodiments, according to Figure 1 Step S110 involves providing testing apparatus. For example, refer to... Figure 2 , Figure 3 and Figure 4A In some embodiments, the test device 1000 includes a testing module 100, a circuit board structure 200, a socket 300, and a holding device 500. In some embodiments, the circuit board structure 200 is located on and electrically connected to the test module 100, the socket 300 is located on and electrically connected to the circuit board structure 200, and the holding device 500 extends through the circuit board structure 200 and the socket 300 to lock the socket 300 onto the circuit board structure 200. The socket 300 may have accommodating space for an object to be tested or a device under test (DUT) (e.g., in...). Figure 2 and Figure 3 The recess R1 described in the document refers to the test object or device, such as a semiconductor package 400 (described later). Figures 5 to 7 (As described in the text).

[0085] In some embodiments, the test module 100 includes a body 110, a plurality of conductive contacts 120 exposed from the body 110 (e.g., its surface 110t) for external connections (e.g., to circuit board structure 200), and a controller (not shown) embedded within the body 110 and electrically connected to the conductive contacts 120. For example, the body 110 is made of a material with sufficient rigidity (quantifiable by its Young's modulus) to protect the controller and conductive contacts 120 formed therein, wherein the body 110 is electrically isolated from the controller and conductive contacts 120. The material of the body 110 may include a dielectric material or a combination of dielectric and conductive materials (e.g., a metal or metal alloy).

[0086] In some embodiments, such as Figures 2 to 4A As shown, conductive contacts 120 are distributed on the surface 110t of the body 110. In one embodiment, the conductive contacts 120 are partially electrically isolated from each other. In an alternative embodiment, the conductive contacts 120 are electrically isolated from each other. The material of the conductive contacts 120 may include aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, and may be formed by electroplating or deposition. This disclosure is not limited thereto. The conductive contacts 120 may also be patterned by photolithography and etching processes. Throughout the description, the term "copper" is intended to include copper as a substantially pure element, copper containing unavoidable impurities, and copper alloys containing trace elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium. Figures 2 to 4A The number of conductive contacts 120 shown is for illustrative purposes only, and this disclosure is not limited thereto. The number of conductive contacts 120 can be selected and specified according to requirements and design layout. Due to the conductive contacts 120, external connection to a controller embedded in the body 110 of the test module 100 is feasible (available).

[0087] The controller may or may not have a built-in memory device (e.g., for storing test settings or test results). The controller may include analog and digital circuitry, a processor, or a combination thereof. The controller may be implemented by a circuit system, including but not limited to: analog circuitry; digital circuitry; semiconductor integrated circuits, such as at least one processor (e.g., a central processing unit (CPU)), at least one application-specific integrated circuit (ASIC), and / or at least one field-programmable gate array (FPGA); or combinations thereof. At least one processor can be configured or programmed to perform the functions of the controller further described below by reading one or more instructions from at least one machine-readable tangible medium. For example, there may be one or more controllers. In some embodiments, the test module 100 includes automatic (or automated) testing equipment (ATE) that performs measurements and evaluates test results (e.g., analysis of the response signals) by generating and transmitting test electric signals (e.g., current) and receiving responsive electric signals (e.g., voltage) for testing the integrated circuits and internal circuitry of the object under test (DUT).

[0088] It should be understood that the device under test (DUT) has electrical characteristics (e.g., voltage or current characteristics) that need to be measured and / or tested at various locations, wherein the test module 100 with an embedded controller helps to effectively identify internal wiring faults within the DUT and physical connection faults between the DUT and the socket 300. In this disclosure, the state of the connection between the DUT and the socket 300 represents the warping state of the DUT, which will be discussed later in conjunction with... Figures 5 to 7 , Figures 14A to 14B , Figures 15A to 15B and Figures 16A to 16B Please provide an explanation.

[0089] In some embodiments, the circuit board structure 200 includes a holder 210, a circuit board 220, and a plurality of connectors 230. For example, the circuit board 220 is located (received) within the holder 210, wherein the connectors 230 are located on and electrically connected to the circuit board 220, and the connectors 230 are located within the holder 210. In some embodiments, the holder 210 is used to hold the circuit board 220 in place above the test module 100. For example, the holder 210 may be a frame holder surrounding the periphery of the circuit board 220 to hold the circuit board 220 in position above the test module, such as... Figure 3 As shown. However, alternatively, the retainer 210 can be a housing having various accommodating spaces for the circuit board 220 and the connector 230. The material of the retainer 210 may include stainless steel, polyester, polyimide (PI), glass, epoxy resin, or the like. For example, the retainer 210 is electrically isolated from the test module 100 and the circuit board 220.

[0090] In some embodiments, the circuit board 220 is located on and electrically connected to the test module 100 via the connector 230, such as Figure 3As shown, the connector 230 is located in the space O1 defined by the retainer 210, the circuit board 220, and the test module 100. In some embodiments, the circuit board 220 includes a plurality of build-up layers (not labeled), each build-up layer including a metal trace 226 (e.g., metal trace 226a, metal trace 226b, metal trace 226c, or metal trace 226d), a metal via 224 connected to the metal trace 226 (e.g., metal via 224a, metal via 224b, metal via 224c, or metal via 224d), and a dielectric layer 222 (e.g., dielectric layer 222a, dielectric layer 222b, dielectric layer 222c, or dielectric layer 222d) surrounding the metal trace 226 and the metal via 224. Metal trace 226a, via 224a, and dielectric layer 222a together constitute a first stacked layer; metal trace 226b, via 224b, and dielectric layer 222b together constitute a second stacked layer; metal trace 226c, via 224c, and dielectric layer 222c together constitute a third stacked layer; and metal trace 226d, via 224d, and dielectric layer 222d together constitute a fourth stacked layer. For example, via 224a connects the overlying metal trace 226a and the underlying metal trace 226b, and the metal traces 226a and 226b are electrically connected to each other. Via 224b connects the overlying metal trace 226b and the underlying metal trace 226c, and the metal traces 226b and 226c are electrically connected to each other. Metal via 224c connects its overlying metal trace 226c and its underlying metal trace 226d, and the metal traces 226c and 226d are electrically connected to each other. Metal via 224d connects its overlying metal trace 226d and a corresponding connector 230 among its underlying connectors 230, and the metal trace 226d and connector 230 are electrically connected to each other. That is, multiple electrical connection paths are established between metal trace 226a and metal via 224d. Due to this configuration, metal trace 226a and metal via 224d together constitute a routing structure, thereby enabling circuit board 220 to provide routing functionality. Only four stacked layers are shown in this disclosure for illustrative purposes, and this disclosure is not limited thereto. The number of stacked layers can be selected and specified according to requirements and design layout. The number of stacked layers can exceed 40 layers. Alternatively, the number of stacked layers can exceed 70 layers. This disclosure is not limited thereto.

[0091] The dielectric layer 222 may be made of polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer dielectric material, and may be formed by deposition, lamination, or spin coating. The metal via 224 and metal trace 226 may be made of aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, and may be formed by electroplating or deposition. This disclosure is not limited thereto. The dielectric layer 222, metal via 224, and metal trace 226 may also be patterned independently by photolithography and etching processes. In one embodiment, a metal via 224 and a corresponding metal trace 226 thereon may be formed together by a dual damascene process. In an alternative embodiment, a metal via 224 and a corresponding metal trace 226 thereon may be formed separately by a single damascene process.

[0092] In some embodiments, the connector 230 is distributed on the surface S222b of the circuit board 220 and located within the space O1. The material of the connector 230 may include aluminum, titanium, copper, nickel, tungsten and / or alloys thereof, and may be formed by electroplating or deposition. This disclosure is not limited thereto. The connector 230 may also be patterned by photolithography and etching processes. Figure 3 The number of connectors 230 shown is for illustrative purposes only, and this disclosure is not limited thereto. The number of connectors 230 can be selected and specified according to requirements and design layout. The circuit board 220 (e.g., metal trace 226) is electrically connected to the test module 100 via the connectors 230. In some embodiments, the positions of the connectors 230 correspond to the positions of the conductive contacts 120 to ensure proper electrical connection between them.

[0093] In other words, for the device under test (DUT), the electrical signal generated from the test module 100 can be rerouted to the socket 300 via the circuit board structure 200, and / or the received response electrical signal fed back from the DUT can be rerouted to the test module 100 via the circuit board structure 200 and the socket 300 for further processing by the test module 100. In a particular embodiment, the circuit board 220 serves as the load board of the test module 100, in which various electronic components / devices (e.g., integrated circuits, resistors, capacitors, inductors, relays, etc.) are used to form the test circuit of the load board. However, this disclosure is not limited thereto; in an alternative embodiment, the circuit board 220 serves as the load board of the test module 100 without any additional electronic components / devices. This disclosure is not limited thereto.

[0094] like Figures 4A to 4B As shown and combined Figure 3For example, circuit board 220 includes a plurality of testing patterns TP embedded therein, wherein each testing pattern TP is electrically connected to a corresponding metal trace 226a for electrically connecting the testing pattern TP to a socket 300. In this disclosure, a metal trace 226a connected to a testing pattern TP is referred to as a testing point TPP. For example, as... Figures 4A to 4B As shown and combined Figures 17A to 17B The test pattern TP independently includes conductive line L1 and conductive line L2, wherein conductive line L2 includes a main portion L2m and a branch portion L2b, and conductive line L1 is connected to conductive line L2 at the merged edge (or merged portion) ME. In other words, the branch portion L2b and the main portion L2m of conductive line L2 merge at the merged edge ME where they connect to conductive line L1. In a particular embodiment, the test module 100 provides current through conductive line L1 to the respective metal traces 226a connected to the test pattern TP and measures the voltage at the merged edge ME of conductive line L2. In other words, no current flows through the branch portion L2b of conductive line L2, and the current provided from conductive line L1 is further provided to the socket 300 through the main portion L2m of conductive line L2 to flow to the object under test (DUT). In some embodiments, the metal trace 226a connected to the test pattern TP is called a testing contact, and the metal trace 226a not connected to the test pattern TP is called a signal contact.

[0095] In some embodiments, the state of each of the multiple connections between the device under test (DUT) and the socket 300 is reflected by the resistance R at the contact point between the DUT and the socket 300. For example, the contact point CP (at...) Figure 14B , Figure 15B and Figure 16B (in the middle) refers to the conductive terminals of the semiconductor package 400 (e.g., Figures 5 to 7 , Figure 14B , Figure 15B and Figure 16B The conductive terminal 452 in the middle) and the connector of the socket 300 (e.g., Figures 5 to 7 , Figure 14B , Figure 15B and Figure 16B The connector 322) is in contact with the test point TPP, which is electrically connected to the test pattern TP. Figure 4A and Figure 4B As shown. In a particular embodiment, the resistance R at the contact point CP between the object under test (DUT) (e.g., semiconductor package 400) and the socket 300 is calculated by the following formula (I):

[0096]

[0097] In formula (I), if the resistance R is less than or equal to 10.0 ohms (Ω), the connection between the device under test (DUT) and the socket 300 is considered a good contact. Conversely, if the resistance R reaches the maximum measurable resistance of the test module 100, the connection between the DUT and the socket 300 is considered a no-contact, such as an open circuit. For example, if the maximum measurable resistance of the test module 100 is 1.0 kΩ, and there is no contact between the DUT and the socket 300 at the contact point, the resistance R at the contact point (between the DUT and the socket 300) will be 1.0 kΩ. Furthermore, if the resistance R is greater than 10.0 ohms (Ω) but less than the maximum measurable resistance of the test module 100, the connection between the DUT and the socket 300 is considered a bad contact or oxidation (e.g., the conductive terminals of the semiconductor package 400 are oxidized).

[0098] Based on the above, the connection between the device under test (DUT) and the socket 300 can be easily verified. Therefore, the warpage of the DUT is verified using multiple test points (TPPs), each TPP connected to a test pattern (TP), and each TPP is distributed at a different location in the chip region (CR) on the circuit board 220. The chip region (CR) may correspond to the location of the DUT housed in the socket 300. For example, the chip region (CR) may be referred to as a test area. In some embodiments, in Figure 4A In the top view shown, the chip area CR is square in shape. Alternatively, in the top view, the chip area CR can be rectangular or circular. If the shape of the chip area CR is considered to be circular, then the chip area CR should be located at the center of the socket 300, and the diagonal line or central line used to locate the test point can be the diagonal line or central line of the socket 300; however, this disclosure is not limited thereto.

[0099] In some embodiments, at least the metal traces 226a within the chip region CR are arranged in a matrix, such as an N×N array or an N×M array (N, M>0, N may be equal to or may not be equal to M), on the surface S222t of the circuit board 220 (facing the socket 300), for electrical connection to the connectors of the socket 300. For example, along the stacking direction of the test module 100 and the circuit board structure 200, the surface S222t of the circuit board 220 is opposite to the surface S222b of the circuit board 220. For example, some of the metal traces 226a within the chip region CR are used as test points TPP, while the remaining metal traces 226a within the chip region CR are used as conductive contacts for other electrical signal transmissions.

[0100] The test point TPP may include at least three test point TPPs, which may be arranged on the circuit board 220 and positioned at multiple different locations on the diagonals DL1 and DL2 of the chip area CR, wherein one test point TPP is arranged at the center of the chip area CR (e.g., the intersection of diagonals DL1 and DL2). In some embodiments, Figure 4A Five test points (TPPs) are shown, one of which is located at the center of the chip area CR, while the remaining test points (TPPs) are located at different positions on diagonals DL1 and DL2. For example, the remaining test points (TPPs) are located at the corners of the chip area CR, which cross diagonals DL1 and DL2, as shown. Figure 4A As shown.

[0101] However, this disclosure is not limited thereto. The test point TPP may include three test point TPPs, one of which may be located at the center of the chip region CR, and the other two test point TPPs may be located on a diagonal (e.g., diagonal DL1) and positioned on two different sides of the center of the chip region CR, such as... Figure 8 As shown. On the other hand, the test point TPP may include five test point TPPs, one of which may be located at the center of the chip region CR, two test point TPPs may be located on a diagonal (e.g., diagonal DL1) and positioned on two different sides of the center of the chip region CR, and the other two test point TPPs are randomly arranged on the chip region CR, as shown. Figure 9 As shown. Furthermore, the test point TPP may include five test point TPPs, one of which may be located at the center of the chip region CR, while the remaining test point TPPs are randomly arranged on the chip region CR and surrounding its center, as shown. Figure 10 As shown.

[0102] Alternatively, test points TPPs can be arranged symmetrically along the centerline of the chip region CR (e.g., centerline CL1 and / or centerline CL2). Test points TPPs arranged symmetrically along the centerline CL1 and / or centerline CL2 of the chip region CR can be placed on centerline CL1 and / or centerline CL2. Alternatively, test points TPPs arranged symmetrically along the centerline CL1 and / or centerline CL2 of the chip region CR may not be placed on centerline CL1 and / or centerline CL2. In some embodiments, Figure 11 Six test points TPP are shown, where the test points are arranged symmetrically along the center line CL1 and / or center line CL2 of the chip area CR, and only two of the six test points TPP are arranged on the center line CL1 and / or center line CL2, while there are no test points TPP at the center of the chip area CR.

[0103] However, this disclosure is not limited thereto. The test point TPP may include eight test point TPPs, of which four test point TPPs may be located on the center line CL1, four test point TPPs may be located on the center line CL2, and no test point TPP is located at the center of the chip area CR, such as... Figure 12 As shown. On the other hand, the test point TPP may include twelve test point TPPs, of which four test point TPPs may be located on the center line CL1, four test point TPPs may be located on the center line CL2, and four test point TPPs may be randomly located on the chip area CR, and there are no test point TPPs at the center of the chip area CR, as shown. Figure 13 As shown in the above embodiment ( Figures 11 to 13 In this embodiment, no test point TPP is located at the center of the chip region CR (e.g., the intersection of center line CL1 and center line CL2). However, this disclosure is not limited thereto; alternatively, a test point TPP may be located at the center of the chip region CR.

[0104] It should be noted that the number and location of the test points TPPs are not limited to this disclosure, as long as the number of test points is greater than 3 and meets the following conditions (e.g., located at the center of the chip area CR or symmetrically configured). Due to the test points TPPs connected to the test pattern TP and their locations, the warpage of the DUT can be confirmed.

[0105] In one embodiment, if the resistance R of the contact point CP corresponding to the test point TPP located on the periphery of the chip region CR is considered good contact, and the resistance R of the contact point CP corresponding to the test point TPP located at or near the center of the chip region CR is considered no contact, then for the contact point CP corresponding to the test point TPP located at or near the center of the chip region CR, the cross-section of the test object DUT exhibits a concave warpage (i.e., a smile profile). In another embodiment, if the resistance R of the contact point CP corresponding to the test point TPP located on the periphery of the chip region CR is considered no contact, and the resistance R of the contact point CP corresponding to the test point TPP located at or near the center of the chip region CR is considered good contact, then for the contact point CP corresponding to the test point TPP located at or near the center of the chip region CR, the cross-section of the test object DUT exhibits a convex warpage (i.e., a crying profile). Through the above embodiments, warpage of the test object DUT is detected.

[0106] Furthermore, if the resistance R of the contact point CP corresponding to the test point TPP located on the periphery of the chip region CR is considered to be a good or bad contact, and the resistance R of the contact point CP corresponding to the test point TPP located at or near the center of the chip region CR is considered to be a good or bad contact, then the cross-section of the test object DUT is essentially flat. In other words, no warping of the test object DUT is detected.

[0107] In this disclosure, the state of a connection (e.g., a contact point CP) between the device under test (DUT) and the socket 300 is confirmed by the value of the resistance R at the contact point CP (corresponding to the test point TPP). Therefore, warpage of the DUT (e.g., semiconductor package 400) is detected by the state of the connection (related to the resistance R). In this disclosure, the resistance R can be calculated by performing a two-step measurement at each test point TPP using the test pattern TP.

[0108] In some embodiments, performing a two-step measurement can be achieved, but is not limited to, the following steps: (1) providing a first current I1 (generated by the test module 100) to the object under test (DUT), and measuring a first voltage V1 at one side of the DUT (i.e., at the merging edge ME of the conductor L2) and a voltage V3 at the other side of the DUT by the test module 100, as follows. Figure 17AAs shown; and (2) a second current I2 (generated by test module 100) is supplied to the object under test (DUT), and a second voltage V2 is measured at one side of the DUT (i.e., at the merging edge ME of conductor L2) and a voltage V4 is measured at the other side of the DUT by test module 100, as shown. Figure 17B As shown. Using a given first current I1, a second current I2, and measured voltages V1 through V4, the resistance R at each contact point between the object under test (DUT) and the socket 300 can be calculated. For example, voltages V3 and V4 are set to a reference voltage given by the test module 100. Voltages V3 and V4 are the same as each other, in some embodiments. Voltages V3 and V4 can be 0 volts (V). Alternatively, voltages V3 and V4 can be less than or substantially equal to 150 μV or any suitable volt, such as 100 μV. In some embodiments, voltage V3 is a reference voltage given by the test module 100. In this disclosure, the first current I1 is different from the second current I2. For example, the first current I1 is less than the second current I2, wherein the first current I1 is greater than or substantially equal to zero amperes (0.0 A). Using a two-step measurement, the current difference between the actual current supplied to conductor L1 by test module 100 and the expected current specified to test module 100, as well as the current loss on the current-carrying wire (e.g., conductor L1), are eliminated. Furthermore, the two-step measurement also eliminates the current loss across the current-carrying wire (e.g., conductor L1, i.e., resistor R). L1 ) and the branch L2b of conductor L2 (i.e., resistor R) L2b The voltage drop across the two ends is measured. Therefore, accurate measurement of resistance R is achieved at the contact point between the test object (DUT) and the socket 300, thereby improving the reliability of the test equipment 1000 used to confirm the warpage of the test object.

[0109] For example, such as Figure 4A and Figure 4B As shown, the test patterns TP (each including conductor L1 and conductor L2) are formed in the layer where the metal trace 226b is formed. That is, the test pattern TP and the metal trace 226b are formed simultaneously. However, the test pattern TP can be formed in any of the stacked layers included in the circuit board 220. The formation and material of the test pattern TP are related to... Figure 3The metal trace 226 described herein is formed and made of the same or similar material, and therefore will not be repeated for the sake of brevity. In some embodiments, the test pattern TP is electrically connected to its underlying metal via 224b for transmitting signals from or to the underlying connector (e.g., connector 230 of circuit board structure 200, conductive contact 120 of test module 100, etc.), and the test pattern TP is electrically connected to its overlying metal via 224a for transmitting signals from or to the overlying connector (e.g., metal trace 226a (also shown as test point TPP), connector of socket 300 (e.g., conductive connector 320), etc.). In some embodiments, the width D1 of conductor L1 is approximately in the range of 0.10 mm to 50.0 mm. In some embodiments, the width D2 of conductor L2 is approximately in the range of 0.10 mm to 50.0 mm. In one embodiment, width D1 and width D2 are the same. In an alternative embodiment, width D1 and width D2 are different.

[0110] In some embodiments, the distance SP1 between conductors L1 and L2 that are not yet merged in a test pattern TP is approximately between 1 mm and 500 mm. However, the distance SP1 is not limited to this disclosure and can be any suitable distance. In some embodiments, the distance SP2 between the merged edge ME of conductor L2 and the edge of the test point TPP electrically connected to it is less than or equal to 2.0 cm. In some embodiments, the distance SP3 between two adjacent test points TPP is greater than or equal to 1.0 cm.

[0111] Back Figures 2 to 3 In some embodiments, the socket 300 is located on and electrically connected to the circuit board structure 200 (e.g., surface S222t of the circuit board 220). For example, the socket 300 includes a base 310, a plurality of conductive connectors 320 extending through the base 310, and a cover 330 located on the base 310. In some embodiments, the conductive connectors 320 are electrically connected to metal traces 226a within a chip region CR of the circuit board 220. In some embodiments, the base 310 is electrically isolated from the circuit board structure 200.

[0112] In some embodiments, the base 310 includes a flange portion 312 and a central portion 314, wherein the flange portion 312 is located at the periphery of the central portion 314. For example, such as Figure 3As shown, the base 310 has an H-shaped cross-section. Alternatively, the base 310 can be rectangular. Or, in a top view, the base 310 can be square, circular, elliptical, or any suitable polygon. In some embodiments, the material of the base 310 includes a dielectric material capable of providing a specific stiffness that ensures the physical and mechanical strength of the socket 300. This stiffness (which can be quantified by its Young's modulus) can range from about 10 GPa to about 30 GPa.

[0113] For example, such as Figure 3 As shown, recess R1 is defined by the inner surface 312i of flange portion 312, surface 314t of central portion 314, and cover 330, while recess R2 is defined by the inner surface 312i of flange portion 312, surface 314b of central portion 314, and circuit board 220. For example, surfaces 314t and 314b are opposite each other along the stacking direction, with surface 314t facing away from circuit board 220 and surface 314b facing circuit board 220. In some embodiments, recess R1 is configured for a device under test (DUT) (e.g., Figures 5 to 7 The space for the semiconductor package 400.

[0114] The central portion 314 may include multiple openings (not marked). For example, such as Figure 3 As shown, the opening penetrates the central portion 314 in the stacking direction, wherein conductive connectors 320 are inserted into the opening and secured to the base 310. In some embodiments, the conductive connectors 320 contact the metal traces 226 of the circuit board 220 in the recess R2 of the socket 300.

[0115] For example, conductive connector 320 includes a plurality of conductive connectors 322 and a plurality of conductive connectors 324. In some embodiments, conductive connectors 322 contact metal traces 226a, which serve as test points TPP, for transmitting test electrical signals (e.g., current) and response electrical signals (e.g., voltage) to the device under test (DUT), while conductive connectors 324 contact the remaining metal traces 226a located in the chip region CR for electrically grounding the ground plane of the DUT or for providing a reference voltage to the ground plane of the DUT.

[0116] Each of the conductive connectors 322 may include a body portion 322c and two end portions 322a and 322b, respectively connected to two opposite sides of the body portion 322c. For example, such as... Figure 3As shown, a conductive connector 322 is connected via an end portion 322b to a corresponding metal trace 226a, which serves as a test point TPP. The end portion 322a of the conductive connector 322 is electrically connected to the object under test (DUT) (e.g., a semiconductor package 400). In other words, the end portion 322a is referred to as the contact point CP (e.g., ...). Figure 14B , Figure 15B and Figure 16B (As shown).

[0117] On the other hand, each of the conductive connectors 324 may include a main body portion 324c and two end portions 324a and 324b, respectively connected to two opposite sides of the main body portion 324c. For example, as Figure 3 As shown, a conductive connector 324 is connected to a corresponding metal trace 226a (not used as a test point TPP) via an end portion 324b, wherein the end portion 324a of the conductive connector 324 is electrically connected to the object under test (DUT) (e.g., semiconductor package 400).

[0118] In some embodiments, conductive connector 320 (including conductive connector 322 and conductive connector 324) is a pogo pin to establish proper physical contact between an end portion (e.g., end portions 322a / 322b, end portions 324a / 324b) and an overlying or underlying component (e.g., the object under test (DUT) or circuit board 220). This establishes an electrical connection path from test module 100 to receptacle 300. In this disclosure, the end portions of conductive connector 320 (e.g., end portions 322a, end portions 324a) are referred to as conductive terminals of test equipment 1000.

[0119] Alternatively, conductive connector 322 and / or conductive connector 324 can be any suitable conductive connector capable of establishing the aforementioned appropriate physical contact. Figure 3 Only three conductive connectors 322 and two conductive connectors 324 are shown for illustrative purposes, and this disclosure is not limited thereto. The number of conductive connectors 320 (including conductive connectors 322 and conductive connectors 324) can be selected and specified according to requirements and design needs.

[0120] In some embodiments, the cover 330 is composed of a material similar to or the same as that of the base 310. Furthermore, the cover 330 may include a heat dissipation element with high thermal conductivity, for example, between about 200 W / (m·K) and about 400 W / (m·K) or higher. The heat dissipation element may be formed in a block shape or a block shape with multiple fins thereon, using metals, metal alloys, and the like. In some embodiments, in addition to its heat dissipation function, the cover 330 may also provide physical protection for the device under test (DUT).

[0121] like Figure 3 As shown, for example, the socket 300 is mounted to the circuit board structure 200 via a clamping device 500. In some embodiments, the clamping device 500 includes a plurality of bolts 510 and a plurality of fasteners 530, such as... Figure 2 and Figure 3 As shown. In some embodiments, bolt 510 passes through socket 300 (including base 310 and cover 330) and circuit board 220, and fastener 530 is screwed onto bolt 510 and tightened to clamp socket 300 and circuit board 220. Fastener 530 may be, for example, a nut screwed onto bolt 510. Figure 3 As shown, for example, the flange portion 312 stands directly on the surface S222t of the circuit board 220.

[0122] However, this disclosure is not limited thereto; alternatively, a socket adopter (not shown) may be mounted on surface S222t of circuit board structure 200, wherein the socket adopter is configured to couple to socket 300 and to allow socket 300 to be electrically connected to circuit board 220 located below it. In such an alternative embodiment, clamping device 500 may be omitted.

[0123] Figure 5 This is a schematic exploded view of an assembly 10 of a test device 1000 and a semiconductor package 400 according to some embodiments of the present disclosure. Figure 6 yes Figure 5 A schematic cross-sectional view of assembly 10 depicted in the figure. Figure 7 yes Figure 5 The schematic plan view depicting the relative positions of a portion of the components of the test equipment 1000, including the circuit board 220 and the conductive element 450 of the semiconductor package 400, in the assembly 10, wherein Figure 6 Show along Figure 7The enlarged cross-sectional view is taken from the dashed line (diagonal DL1 or diagonal DL2) depicted in the figure. Components similar to or substantially the same as those described above will use the same reference numerals, and specific details or descriptions of the same components (e.g., materials, positioning structures, electrical connections, etc.) will not be repeated here.

[0124] In some embodiments, according to Figure 1 In step S120, the semiconductor package is mounted on the test equipment. For example, such as... Figure 5 , Figure 6 and Figure 7 As shown, a semiconductor package 400 (as previously mentioned, referred to as the object under test, DUT) is provided and placed in a receiving space (e.g., recess R1) of a socket 300, and the semiconductor package 400 is electrically coupled to a test device 1000 to form an assembly 10. For example, the semiconductor package 400 includes a plurality of semiconductor dies 410, a plurality of input / output (I / O) interface dies 420, an insulating enclosure 430, a redistribution circuitry 440, and a plurality of conductive elements 450, such as... Figure 6 As shown. In some embodiments, conductive element 450 serves as an interface for external connection to semiconductor package 400. That is, conductive element 450 acts as a conductive terminal of semiconductor package 400 to electrically connect to external devices / equipment (e.g., via conductive connector 320 to) socket 300 for transmitting (e.g., output and / or input) electrical signals, power signals, or ground signals. In alternative embodiments, semiconductor devices (not shown) are optionally bonded to semiconductor package 400 in a manner similar to conductive element 450. The semiconductor device may be an integrated passive device (IPD) or a surface mounting device (SMD), and this disclosure is not limited thereto. It should be understood that the thickness of the semiconductor device is less than the thickness of each of the conductive elements 450.

[0125] In some embodiments, if a top view along the stacking direction is considered, the semiconductor package 400 has a diameter greater than or substantially equal to 400 mm. 2The semiconductor package 400 is in chip-size form. Alternatively, it can be in wafer form or panel form. In other words, the semiconductor package 400 is processed as a reconstructed wafer / reconstructed panel. In an alternative embodiment, considering a top view along the stacking direction, the semiconductor package 400 is in wafer-size form with a diameter of about 4 inches or more. In other alternative embodiments, the semiconductor package 400 is in wafer-size form with a diameter of about 6 inches or more. In yet another alternative embodiment, the semiconductor package 400 is in wafer-size form with a diameter of about 8 inches or more. Alternatively, the semiconductor package 400 is in wafer-size form with a diameter of about 12 inches or more.

[0126] Semiconductor dies 410 and I / O interface dies 420 may be arranged side-by-side with each other in a horizontal direction. In some embodiments, semiconductor dies 410 are arranged in a matrix, such as an N'×N' array or an N'×M' array (N', M'>0, N' may be equal to or may not be equal to M'), while I / O interface dies 420 are arranged to surround semiconductor dies 410 (arranged in an array / matrix) to provide additional input / output circuitry to them, thereby providing more I / O counts for semiconductor dies 410. The matrix of I / O interface dies 420 may be an N”×N” array or an N”×M” array (N”, M”>0, N” may be equal to or may not be equal to M”). That is, in such an embodiment, I / O interface dies 420 are arranged in a matrix that surrounds the perimeter of the matrix of semiconductor dies 410.

[0127] However, this disclosure is not limited thereto. In alternative embodiments, the semiconductor die 410 and the I / O interface die 420 are arranged in a matrix, such as a Na×Na array or a Na×Ma array (Na, Ma>0, Na may or may not be equal to Ma). In such embodiments, the semiconductor die 410 and the I / O interface die 420 are arranged in an alternating matrix. In another alternative embodiment, the semiconductor die 410 is arranged in a first matrix, while the I / O interface die 420 is arranged in a second matrix, wherein the first and second matrices are Nb×Nb arrays or Nb×Mb arrays (Nb, Mb>0, Nb may or may not be equal to Mb), and the first and second matrices are placed adjacent to each other.

[0128] In some embodiments, the semiconductor die 410 has a plurality of vias 412, wherein the vias 412 serve as conductive terminals of the semiconductor die 410 for electrical connection to other devices / components (e.g., redistribution structure 440). Each semiconductor die 410 described herein may be referred to as a semiconductor chip or an integrated circuit (IC). For example, each semiconductor die 410 may be independently a logic chip, such as a central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), system-on-integrated-circuit (SoIC), microcontroller, or the like. However, this disclosure is not limited thereto; in alternative embodiments, each semiconductor die 410 may be independently a digital chip, analog chip, or mixed-signal chip, such as an application-specific integrated circuit (ASIC) chip, sensor chip, radio frequency (RF) chip, baseband (BB) chip, memory chip (e.g., high bandwidth memory (HBM) die), or voltage regulator chip. In other alternative embodiments, each of the semiconductor dies 410 is independently a combined chip or IC, such as a WiFi chip that includes both radio frequency (RF) and digital chips. In some embodiments, the type of the first group of semiconductor dies 410 differs from the type of the second group of semiconductor dies 410. In other words, the semiconductor dies 410 may include different types and / or the same types of semiconductor chips or ICs; this disclosure is not limited thereto. For example, the first group of semiconductor dies 410 includes multiple logic dies, while the second group of semiconductor dies 410 includes multiple memory dies.

[0129] In some embodiments, each I / O interface die 420 independently has a plurality of vias 422, wherein the vias 422 serve as conductive terminals of the I / O interface die 420 for electrical connection to other devices / components (e.g., redistribution wiring structure 440). Figure 6 As shown, for illustrative purposes, only two semiconductor dies 410 and two I / O interface dies 420 are presented. However, it should be noted that the number of semiconductor dies 410 and I / O interface dies 420 may be one or more, and this disclosure is not limited thereto.

[0130] In some embodiments, the semiconductor die 410 and the I / O interface die 420 are encapsulated in an insulating enclosure 430. For example, the insulating enclosure 430 laterally surrounds the semiconductor die 410 and the I / O interface die 420, wherein vias 412 of the semiconductor die 410 and vias 422 of the I / O interface die 420 are accessiblely exposed through the insulating enclosure 430. Figure 6 As shown, the bottom surfaces of vias 412 and 422 are substantially flush with the bottom surface of the insulating encapsulation 430. That is, in some embodiments, the bottom surfaces of vias 412, 422, and 430 are substantially coplanar to achieve a high degree of coplanarity to facilitate the formation of subsequently formed components (e.g., the redistribution structure 440). It should be understood that... Figure 6 The bottom surface of the via 412 and the bottom surface of the via 422 depicted in the figure correspond to the active side of the semiconductor die 410 and the active side of the I / O interface die 420, respectively.

[0131] In some embodiments, the insulating encapsulation 430 partially covers (e.g., physically contacts) the sidewalls of each via 412 in the semiconductor die 410. In some embodiments, the insulating encapsulation 430 partially covers (e.g., physically contacts) the sidewalls of each via 422 in the I / O interface die 420. However, this disclosure is not limited thereto; alternatively, neither the sidewalls of each via 412 nor the sidewalls of each via 422 may contact the insulating encapsulation 430. In other alternative embodiments, the insulating encapsulation 430 partially covers (e.g., physically contacts) the sidewalls of each via 412 in the semiconductor die 410, while the sidewalls of each via 422 in the I / O interface die 420 are not covered by the insulating encapsulation 430. In yet another alternative embodiment, the sidewalls of each via 412 in the semiconductor die 410 are not covered by the insulating encapsulation 430, while the insulating encapsulation 430 partially covers (e.g., physically contacts) the sidewalls of each via 422 in the I / O interface die 420.

[0132] On the other hand, such as Figure 6 As shown, the top surfaces (e.g., the non-active side) of the semiconductor die 410 and the I / O interface die 420 may be substantially flush with the top surface of the insulating enclosure 430. For example, the top surfaces of the semiconductor die 410 and the I / O interface die 420 may be substantially coplanar with the top surface of the insulating enclosure 430.

[0133] The insulating encapsulation 430 may include acceptable insulating encapsulation materials. For example, the insulating encapsulation 430 may include polymers (e.g., epoxy resins, phenolic resins, silicone resins, or other suitable resins), dielectric materials, or other suitable materials. The insulating encapsulation 430 may be a molding compound formed by a molding process. The insulating encapsulation 430 may also include inorganic fillers or inorganic compounds (e.g., silica, clay, etc.), which may be added herein to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulation 430. This disclosure is not limited thereto.

[0134] In some embodiments, the redistribution circuitry 440 is located above the semiconductor die 410, the I / O interface die 420, and the insulating enclosure 430. For example... Figure 6 As shown, for example, the redistribution structure 440 includes a fine-featured portion 440A and a coarse-featured portion 440B, and is electrically connected to the semiconductor die 410 and the I / O interface die 420 via vias 412 exposed by the insulating encapsulation 430 and vias 422 exposed by the I / O interface die 420. In some embodiments, the fine-featured portion 440A is located between the coarse-featured portion 440B and the semiconductor die 410, and between the coarse-featured portion 440B and the I / O interface die 420. In some embodiments, the fine-featured portion 440A of the redistribution structure 440 is formed on and electrically coupled to the semiconductor die 410 and the I / O interface die 420, and the coarse-featured portion 440B is electrically coupled to the semiconductor die 410 and the I / O interface die 420 through the fine-featured portion 440A. For example, as Figure 6 As shown, the fine feature portion 440A can provide local electrical communication between a plurality of semiconductor dies 410, between a plurality of I / O interface dies 420, and between semiconductor dies 410 and I / O interface dies 420, while the thick feature portion 440B can provide global electrical communication between an external device / equipment electrically connected to the conductive element 450 and the semiconductor die 410 and / or I / O interface die 420.

[0135] For example, a fine feature portion 440A includes a dielectric structure 442A and a metallization pattern 444A located within the dielectric structure 442A, and a thick feature portion 440B includes a dielectric structure 442B and a metallization pattern 444B located within the dielectric structure 442B. The metallization patterns 444A and 444B may each independently include one or more patterned conductive layers (collectively referred to as redistribution layers), while the dielectric structures 442A and 442B may each independently include one or more dielectric layers alternating with the patterned conductive layers. For example, one or more patterned conductive layers are electrically connected to each other, and the one or more patterned conductive layers have multiple line portions (also referred to as wires or conductive traces) extending in a horizontal plane and multiple via portions (also referred to as vias) extending in a stacking direction, the via portions electrically connecting the line portions (collectively referred to as internal routing circuitry) to provide routing functionality. Furthermore, the one or more patterned conductive layers also include a plurality of plane portions extending in a horizontal plane and a plurality of other via portions extending in a stacking direction, the other via portions being electrically connected to the plane portions (collectively referred to as ground planes) for electrically grounding. In this case, the plane portions are electrically isolated from the remainder of metallization pattern 444A and the remainder of metallization pattern 444B. For example, a line portion and a plane portion in the same patterned conductive layer located in fine feature portion 440A or thick feature portion 440B are electrically isolated from each other by a slit filled with dielectric material for forming dielectric structure 442A or dielectric structure 442B. The number of dielectric layers each contained in dielectric structure 442A or dielectric structure 442B and the number of patterned conductive layers each contained in metallization pattern 444A or metallization pattern 444B may not be limited to the figures of this disclosure and may be selected and specified based on requirements and design requirements.

[0136] The fine feature portion 440A and the thick feature portion 440B of the redistributed circuit structure 440 include metallization patterns and dielectric structures of different sizes, such as Figure 6As shown, for example, in a particular embodiment, the patterned conductive layer included in metallization pattern 444A is formed of the same conductive material and has the same thickness (e.g., a first thickness) and the same linewidth (e.g., a first linewidth), and the patterned conductive layer included in metallization pattern 444B is formed of the same conductive material and has the same thickness (e.g., a second thickness) and the same linewidth (e.g., a second linewidth). Similarly, in some embodiments, the dielectric layer included in dielectric structure 442A is formed of the same dielectric material and has the same thickness, while the dielectric layer included in dielectric structure 442B is formed of the same dielectric material and has the same thickness. In some embodiments, along the stacking direction, the patterned conductive layer included in metallization pattern 444A has a first thickness, which is less than the second thickness of the patterned conductive layer included in metallization pattern 444B. On the other hand, in a top view (e.g., on a horizontal plane), the patterned conductive layer included in the metallization pattern 444A has a first linewidth, which is smaller than the second linewidth of the patterned conductive layer included in the metallization pattern 444B.

[0137] The dielectric structures 442A and 442B may be made of polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer dielectric material, and may be formed by deposition, stacking, or spin coating. The metallization patterns 444A and 444B may be made of aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, and may be formed by electroplating or deposition. This disclosure is not limited thereto. The dielectric structures 442A, 442B and the metallization patterns 444A, 444B may also be independently patterned by photolithography and etching processes.

[0138] For example, the material of dielectric structure 442A is the same as the material of dielectric structure 442B. Alternatively, the materials of dielectric structure 442A and dielectric structure 442B may be different. For example, the material of metallization pattern 444A is the same as the material of metallization pattern 444B. Alternatively, the materials of metallization pattern 444A and metallization pattern 444B may be different. This disclosure is not limited thereto. In alternative embodiments, the redistribution circuit structure 440 may include metallization patterns and dielectric structures of the same size.

[0139] In some embodiments, the conductive element 450 is attached to the redistribution wiring structure 440 for electrical coupling between them, such as Figure 6 As shown. For example, as Figure 6As shown, the semiconductor package 400 has a top surface S1 and a bottom surface S2 opposite to the top surface S1 in the stacking direction, wherein the top surface S1 contacts the cover 330 of the socket 300, and conductive elements 450 are distributed on the bottom surface S2.

[0140] The conductive element 450 may include a plurality of conductive elements 452 and a plurality of conductive elements 454. For example, such as Figure 6 and Figure 7 As shown, conductive element 452 contacts (e.g., appropriately physically connects) conductive connector 322 for electrical connection to a metal trace 226a serving as a test point TPP, and conductive element 454 contacts (e.g., appropriately physically connects) conductive connector 324 for electrical connection to a metal trace 226a that is not a test point TPP. In some embodiments, conductive element 452 is electrically connected to a ground plane included in the redistribution wiring structure 440 for transmitting test electrical signals (e.g., current) and receiving response electrical signals (e.g., voltage). In some embodiments, some conductive elements 454 are electrically connected to internal routing circuitry included in the redistribution wiring structure 440 for identifying interconnect faults within the semiconductor package 400. In some embodiments, some conductive elements 454 are electrically connected to a ground plane included in the redistribution wiring structure 440 for electrically grounding the ground plane included in the redistribution wiring structure 440 or providing a reference voltage to the ground plane included in the redistribution wiring structure 440. That is, for example, through the redistribution of wiring structure 440, some of the conductive elements 454 are electrically connected to semiconductor die 410, and some of the conductive elements 454 are electrically connected to I / O interface die 420. The number of conductive elements 450 (e.g., conductive elements 452 / 454) is not limited to the figures of this disclosure and can be selected and specified based on requirements and design requirements.

[0141] Conductive element 450 can be disposed on redistributed circuitry 440 using a ball-mounting or reflow process. For example, conductive element 450 may be a solder ball, a ball grid array (BGA) ball, or a bump. Alternatively, conductive element 450 may include microbumps, metal pillars, bumps formed using an electroless nickel-electroless palladium-immersion gold technique (ENEPIG), controlled collapse chip connection (C4) bumps, or the like; and may be formed by plating. Conductive element 450 may not have solder. In alternative embodiments including semiconductor devices, semiconductor devices may be disposed on redistributed circuitry 440 using flip-chip bonding technology or surface device mounting technology.

[0142] In some alternative embodiments (not shown), prior to the arrangement / formation of conductive elements 450 on the redistribution structure 440, a plurality of under-bump metallurgy (UBM) patterns are optionally formed on and electrically coupled to the redistribution structure 440, wherein the strength of the connection between the conductive elements 450 and the redistribution structure 440 is enhanced. The conductive elements 450 can be placed onto the UBM patterns via a ball-mounting process. That is, the conductive elements 450 can be electrically coupled to the redistribution structure 440 via the UBM patterns. In some embodiments, the UBM patterns are made of a metallization layer comprising a single metal layer or a composite layer comprising multiple sublayers composed of different materials. In some embodiments, the UBM patterns include copper, nickel, molybdenum, titanium, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the UBM pattern includes a titanium layer and a copper layer above the titanium layer. For example, UBM patterns can be formed using electroplating, sputtering, physical vapor deposition (PVD), or similar methods. However, UBM patterns can be omitted from the redistributed circuit structure 440, and this disclosure is not limited thereto.

[0143] like Figure 6As shown, after the semiconductor package 400 is mounted into the test equipment 1000, in such an assembly 10, the semiconductor package 400 and the test equipment 1000 are temporarily electrically connected via the conductive connector 320 and conductive element 450 of the socket 300, wherein the socket 300 secures the semiconductor package 400 within the assembly 10. For example, this electrical connection between the test equipment 1000 and the semiconductor package 400 is used to prepare for testing the semiconductor package 400 by using the test equipment 1000.

[0144] In some embodiments, according to Figure 1 In step S130, an automated test sequence is performed on the semiconductor package using a test device. In the test method using the test device 1000, the assembly 10 may have several possible testing electrical transmitting paths to test the semiconductor package 400. For illustrative purposes, testing electrical transmitting paths are discussed below, but this disclosure is not limited thereto.

[0145] In some embodiments, a two-step measurement is performed via a test electrical transmission path for warpage detection of the semiconductor package 400. For example, via the test electrical transmission path, an electrical signal provided by the test module 100 (e.g., a first test electrical signal, as shown in the example) is transmitted through the test electrical transmission path. Figure 17A The current I1 generated from the controller of the test module 100 is sent from the test device 1000 to the semiconductor package 400 by means of the following components: conductive contacts 120 of the test module 100, connectors 230 of the circuit board structure 200, circuit board 220 of the circuit board structure 200 (including test pattern TP and test point TPP), conductive connectors 322 of the socket 300, conductive elements 452 of the semiconductor package 400, and redistribution line structure 440 of the semiconductor package 400, and a first initial voltage (e.g., voltage V1) is measured at the merge edge ME; and an electrical signal (e.g., a first response electrical signal, sometimes called a loopback signal, for example shown in Figure 17AThe voltage V3 is transmitted from the semiconductor package 400 to the controller of the test module 100 by means of the following components: the redistribution wiring structure 440 of the semiconductor package 400, the conductive element 454 of the semiconductor package 400, the conductive connector 324 of the socket 300, the circuit board 220 of the circuit board structure 200 (excluding the test pattern TP and test point TPP), the connector 230 of the circuit board structure 200, and the conductive contact 120 of the test module 100. For example, a current I1 is supplied through the conductor L1 of the test pattern TP to the conductive element 452 of the semiconductor package 400, which is electrically connected to the ground plane included in the redistribution wiring structure 440, and the voltage V1 is measured at the merging edge ME of the conductor L2 of the test pattern TP. In some embodiments, the voltage V3 is a reference voltage given by the test module 100.

[0146] Furthermore, via the test electrical transmission path, the electrical signal provided by the test module 100 (e.g., the second test electrical signal, for example shown in...) Figure 17B The current I2 generated from the controller of the test module 100 is sent from the test equipment 1000 to the semiconductor package 400 by means of the following components: conductive contacts 120 of the test module 100, connectors 230 of the circuit board structure 200, circuit board 220 of the circuit board structure 200 (including test pattern TP and test point TPP), conductive connectors 322 of the socket 300, conductive elements 452 of the semiconductor package 400, and redistribution line structure 440 of the semiconductor package 400, and a second initial voltage (e.g., voltage V2) is measured at the merge edge ME; and an electrical signal (e.g., a second response electrical signal, sometimes called a loopback signal, for example shown in Figure 17B The voltage V4 is transmitted from the semiconductor package 400 to the controller of the test module 100 by means of the following components: the redistribution wiring structure 440 of the semiconductor package 400, the conductive element 454 of the semiconductor package 400, the conductive connector 324 of the socket 300, the circuit board 220 of the circuit board structure 200 (excluding the test pattern TP and test point TPP), the connector 230 of the circuit board structure 200, and the conductive contact 120 of the test module 100. For example, a current I2 is supplied through the conductor L1 of the test pattern TP to the conductive element 452 of the semiconductor package 400 electrically connected to the ground plane included in the redistribution wiring structure 440, and the voltage V2 is measured at the merging edge ME of the conductor L2 of the test pattern TP. In some embodiments, the voltage V4 is a reference voltage given by the test module 100. In this disclosure, the current I1 is different from the current I2. For example, the current I1 is less than the current I2, wherein the current I1 is greater than or substantially equal to zero amperes (0.0A).

[0147] By measuring in this way, the resistance R at the contact point CP between the semiconductor package 400 and the socket 300 is obtained using the formula (I) described above. This allows the test equipment 100 to inspect the semiconductor package 400 to confirm whether there is a warping problem. Furthermore, the resistance R obtained through this two-step measurement can also confirm whether there is a fault in the internal interconnects of the semiconductor package 400 or whether the conductive elements 450 of the semiconductor package 400 are oxidized.

[0148] According to some embodiments, a test apparatus for a semiconductor package includes a circuit board, a plurality of test patterns, and a socket. The circuit board has a test area and includes a plurality of test contacts and a plurality of signal contacts distributed within the test area. The plurality of test patterns are embedded in the circuit board and electrically connected to the plurality of test contacts. Each of the plurality of test patterns includes a first conductor and a second conductor, the second conductor including a body portion and a branch portion connected to the body portion, wherein the first conductor is connected to the body portion. The socket is located on the circuit board and includes a plurality of connectors electrically connected to the circuit board, wherein the plurality of connectors are configured to transmit electrical signals from the test apparatus for testing the semiconductor package.

[0149] According to some embodiments, in the test apparatus, the first conductor and the second conductor are located on the same layer. According to some embodiments, in the test apparatus, in each of the plurality of test patterns, the first conductor connects to the second conductor at a merging point, and the distance between the merging point and a corresponding test contact is less than or substantially equal to 2.0 cm. According to some embodiments, in the test apparatus, the spacing between two adjacent test contacts among the plurality of test contacts is greater than or substantially equal to 1.0 cm. According to some embodiments, in the test apparatus, one of the plurality of test contacts is located at the center of the test area. According to some embodiments, in the test apparatus, some of the plurality of test contacts are located at multiple different positions on a diagonal line passing through the center of the test area. According to some embodiments, in the test apparatus, the multiple different positions are located at least on the diagonals on opposite sides of the center. According to some embodiments, in the test apparatus, some of the plurality of test contacts are located at multiple different positions on a first diagonal and a second diagonal line intersecting at the center of the test area. According to some embodiments, in the test apparatus, the plurality of different locations are at least located on the first diagonal lines opposite to the center and on the second diagonal lines opposite to the center. According to some embodiments, in the test apparatus, the plurality of test contacts are arranged symmetrically along the centerline of the test area. According to some embodiments, in the test apparatus, the plurality of test patterns includes three or more test patterns. According to some embodiments, the test apparatus further includes: a test module including a controller and a plurality of conductive contacts, the controller generating electrical signals for testing the semiconductor package, the plurality of conductive contacts being connected to the controller, and wherein a circuit board is located on the test module and electrically connected to the plurality of conductive contacts.

[0150] According to some embodiments, a testing apparatus for a semiconductor package includes a circuit board, three or more test patterns, a socket, and a test module. The circuit board includes a routing structure, a plurality of first contacts, and a plurality of second contacts connected to the routing structure. The three or more test patterns are embedded in the circuit board and electrically connected to the plurality of first contacts. Each of the three or more test patterns includes a first conductor and a second conductor, the second conductor including a body portion and a branch portion connected to the body portion, wherein the first conductor and the branch portion are connected at a junction point of the body portion. The socket is located on the circuit board and includes a plurality of first connectors electrically connected to the plurality of first contacts and a plurality of second connectors electrically connected to the plurality of second contacts. The test module is electrically connected to the circuit board and includes a controller, wherein the circuit board is located between the socket and the test module. The plurality of first connectors of the socket are configured to transmit test signals generated by the controller of the test module to the semiconductor package, and some of the plurality of second connectors are configured to transmit corresponding signals from the semiconductor package to the test module.

[0151] According to some embodiments, in the testing apparatus, in each of the three or more test patterns, the first conductor is connected to the second conductor at the merging point, and the distance between the merging point and a corresponding first contact is less than or substantially equal to 2.0 cm. According to some embodiments, in the testing apparatus, the spacing between two adjacent first contacts among the plurality of first contacts is greater than or substantially equal to 1.0 cm.

[0152] According to some embodiments, a method for testing a semiconductor package includes the following steps: providing a test device, the test device including a circuit board, a plurality of test patterns, and a socket, the circuit board having a test area and including a plurality of test contacts and a plurality of signal contacts distributed within the test area, the plurality of test patterns being embedded in the circuit board and electrically connected to the plurality of test contacts, the socket being located on the circuit board and including a plurality of connectors electrically connected to the circuit board, wherein each of the plurality of test patterns includes a first conductor and a second conductor, the second conductor including a main body and a branch portion connected to the main body, wherein the first conductor is connected to the second conductor at a merging edge; placing the semiconductor package in the test device, the semiconductor package including a semiconductor die, a redistribution structure, a plurality of first terminals and a plurality of second terminals, the redistribution structure including a signal routing structure electrically connected to the semiconductor die and a ground plane, the plurality of first terminals being electrically connected to the ground plane of the redistribution structure, the plurality of second terminals being electrically connected to the semiconductor die through the signal routing structure, wherein the plurality of connectors of the socket are electrically connected to the plurality of first terminals and the plurality of second terminals of the semiconductor package; and performing an automatic test sequence on the semiconductor package using the test device.

[0153] According to some embodiments, in the test method described above, performing the automatic test sequence on the semiconductor package using the test equipment includes: transmitting a first current to the semiconductor package through the plurality of first wires of the plurality of test patterns by the test equipment, and measuring a first initial voltage at the plurality of merging edges of the plurality of second wires of the plurality of test patterns by the test equipment; obtaining a first response voltage by the test equipment; transmitting a second current to the semiconductor package through the plurality of first wires of the plurality of test patterns by the test equipment, and measuring a second initial voltage at the plurality of merging edges of the plurality of second wires of the plurality of test patterns by the test equipment, wherein the first current is different from the second current; obtaining a second response voltage by the test equipment; and confirming the connection state between one of the plurality of connectors and a corresponding first terminal of the plurality of first terminals. According to some embodiments, in the test method described above, confirming the connection state between the one of the plurality of connectors and the corresponding first terminal of the plurality of first terminals includes obtaining the resistance at the contact point between the one of the plurality of connectors and the corresponding first terminal of the plurality of first terminals using formula (I), which is as follows: Wherein: R represents the resistance at the contact point between one of the plurality of connectors and a corresponding first terminal of the plurality of first terminals; V1 represents the first initial voltage; V2 represents the second initial voltage; V3 represents the first response voltage; V4 represents the second response voltage; I1 represents the first current; and I2 represents the second current. According to some embodiments, in the test method, obtaining the first response voltage includes obtaining a reference voltage directly provided by a controller included in the test equipment. According to some embodiments, in the test method, obtaining the second response voltage includes obtaining a reference voltage directly provided by a controller included in the test equipment.

[0154] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A testing device for semiconductor packages, comprising: A circuit board having a test area and including multiple test contacts and multiple signal contacts distributed within the test area; Multiple test patterns are embedded in the circuit board and electrically connected to the multiple test contacts, wherein each of the multiple test patterns includes: First conductor; and The second conductor includes a main body and a branch connected to the main body, wherein the first conductor is connected to the main body; and A socket, located on the circuit board, includes a plurality of connectors electrically connected to the circuit board, wherein the plurality of connectors are configured to transmit electrical signals from the test equipment for testing the semiconductor package.

2. The testing device according to claim 1, wherein the first wire and the second wire are located on the same layer.

3. The testing apparatus according to claim 1, wherein in each of the plurality of test patterns, the first conductor is connected to the second conductor at a merging portion, and the distance between the merging portion and a corresponding test contact is less than or equal to 2.0 cm.

4. The testing device according to claim 1, wherein the distance between two adjacent test contacts in the plurality of test contacts is greater than or equal to 1.0 cm.

5. The testing apparatus according to claim 1, wherein one of the plurality of test contacts is located at the center of the test area.

6. The test apparatus of claim 5, wherein some of the plurality of test contacts are located at multiple different positions on a diagonal line passing through the center of the test area.

7. The test apparatus of claim 6, wherein the plurality of different positions are located at least on the diagonals on opposite sides of the center.

8. The testing apparatus according to claim 5, wherein some of the plurality of test contacts are located at multiple different positions on a first diagonal and a second diagonal, the first diagonal and the second diagonal intersecting at the center of the test area.

9. The testing apparatus of claim 8, wherein the plurality of different positions are located at least in the first diagonal on opposite sides of the center and in the second diagonal on opposite sides of the center.

10. The testing apparatus of claim 1, wherein the plurality of test contacts are arranged symmetrically along the centerline of the test area.

11. The testing apparatus according to claim 1, wherein the plurality of test patterns comprises three or more test patterns.

12. The testing equipment according to claim 1, further comprising: The test module includes a controller and multiple conductive contacts. The controller generates electrical signals for testing the semiconductor package, and the multiple conductive contacts are connected to the controller. The circuit board is located on the test module and is electrically connected to the plurality of conductive contacts.

13. A testing apparatus for semiconductor packages, comprising: A circuit board includes a routing structure, a plurality of first contacts, and a plurality of second contacts, wherein the plurality of first contacts and the plurality of second contacts are connected to the routing structure; Three or more test patterns are embedded in the circuit board and electrically connected to the plurality of first contacts, wherein each of the three or more test patterns includes: First conductor; and The second conductor includes a main body and a branch connected to the main body, wherein the first conductor and the branch are connected to the second conductor at a junction point of the main body; A socket, located on the circuit board, includes a plurality of first connectors electrically connected to the plurality of first contacts and a plurality of second connectors electrically connected to the plurality of second contacts; and A test module, electrically connected to the circuit board and including a controller, wherein the circuit board is located between the socket and the test module. The plurality of first connectors of the socket are configured to transmit test signals generated by the controller of the test module to the semiconductor package, and some of the plurality of second connectors are configured to transmit corresponding signals from the semiconductor package to the test module.

14. The testing apparatus of claim 13, wherein in each of the three or more test patterns, the first conductor is connected to the second conductor at the merging point, and the distance between the merging point and a corresponding first contact is less than or equal to 2.0 cm.

15. The testing device according to claim 13, wherein the distance between two adjacent first contacts in the plurality of first contacts is greater than or equal to 1.0 cm.

16. A method for testing a semiconductor package, comprising: A testing device is provided, the testing device including a circuit board, multiple test patterns and a socket, the circuit board having a test area and including multiple test contacts and multiple signal contacts distributed in the test area, the multiple test patterns being embedded in the circuit board and electrically connected to the multiple test contacts, the socket being located on the circuit board and including multiple connectors electrically connected to the circuit board, wherein each of the multiple test patterns includes a first wire and a second wire, the second wire including a main body and a branch connected to the main body, wherein the first wire is connected to the second wire at a merging edge; The semiconductor package is placed in the test equipment. The semiconductor package includes a semiconductor die, a redistribution structure, a plurality of first terminals, and a plurality of second terminals. The redistribution structure includes a signal routing structure electrically connected to the semiconductor die and a ground plane. The plurality of first terminals are electrically connected to the ground plane of the redistribution structure. The plurality of second terminals are electrically connected to the semiconductor die through the signal routing structure. The plurality of connectors of the socket are electrically connected to the plurality of first terminals and the plurality of second terminals of the semiconductor package. as well as The semiconductor package is subjected to an automated test sequence using the test equipment.

17. The test method of claim 16, wherein performing the automatic test sequence on the semiconductor package using the test equipment comprises: The test equipment transmits a first current to the semiconductor package through the plurality of first wires of the plurality of test patterns, and measures a first initial voltage at the plurality of merged edges of the plurality of second wires of the plurality of test patterns. The first response voltage is obtained by the test equipment; The test equipment transmits a second current to the semiconductor package through the plurality of first wires of the plurality of test patterns, and measures a second initial voltage at the plurality of merged edges of the plurality of second wires of the plurality of test patterns, wherein the first current is different from the second current; The second response voltage is obtained by the test equipment; as well as Confirm the connection status between one of the plurality of connectors and a corresponding first terminal among the plurality of first terminals.

18. The test method according to claim 17, wherein confirming the connection state between the one of the plurality of connectors and the corresponding first terminal of the plurality of first terminals includes obtaining the resistance at the contact point between the one of the plurality of connectors and the corresponding first terminal of the plurality of first terminals using formula (I), wherein formula (I) is as follows: in: R represents the resistance at the contact point between one of the plurality of connectors and the corresponding first terminal of the plurality of first terminals; V1 represents the first initial voltage; V2 represents the second initial voltage; V3 represents the first response voltage; V4 represents the second response voltage; I1 represents the first current; as well as I2 represents the second current.

19. The test method of claim 17, wherein obtaining the first response voltage includes obtaining a reference voltage directly provided by a controller included in the test apparatus.

20. The test method of claim 17, wherein obtaining the second response voltage includes obtaining a reference voltage directly provided by a controller included in the test apparatus.

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