Storage system and information processing system

Abstract

An embodiment of the present application provides a storage system and an information processing system capable of reducing the processing cost of data mapping that manages the validity of data written into a nonvolatile memory. According to an embodiment, the storage system is provided with a nonvolatile memory and a controller. The controller controls the nonvolatile memory according to an instruction from a host. The controller manages the validity of data on the nonvolatile memory using data mapping. The data mapping includes a plurality of first segment tables. The plurality of first segment tables each hold first information and second information, the first information indicating the validity of each of pieces of data of a prescribed size that is data written into a range of physical addresses within the nonvolatile memory allocated to the first segment table, the second information indicating the validity of a plurality of pieces of data of the prescribed size in a predetermined number of entries.

Description

[0001] [Related Application]

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-100701 (filed on June 17, 2021). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to storage systems and information processing systems. Background Technology

[0004] In recent years, storage systems with non-volatile memory have become widely used. As an example of such storage systems, solid-state drives (SSDs) with NAND flash memory are known.

[0005] However, the validity of data written to the aforementioned non-volatile memory (i.e., whether the data is valid or invalid) is managed using data mapping, but it is desirable to manage the validity of this data efficiently. Additionally, it is desirable to reduce the processing cost of data mapping. Summary of the Invention

[0006] One embodiment of the present invention provides a storage system and an information processing system capable of reducing the processing cost of data mapping that effectively manages data written to non-volatile memory.

[0007] According to one embodiment, the storage system is capable of connecting to a host. The storage system includes non-volatile memory and a controller. The non-volatile memory includes multiple blocks. The controller, based on instructions from the host, controls the writing of data to or reading of data from the non-volatile memory. The controller uses a data map to manage the validity of data written to the non-volatile memory. The data map includes multiple first fragment tables. Each of the multiple first fragment tables holds first information and second information, the first information indicating the validity of data of a specified size, which is data written to a range of physical addresses within the non-volatile memory allocated to that first fragment table, and the second information indicating the validity of multiple specified sizes of data in a predetermined number of entries. The controller selects the target block for writing based on the size of the data to be written to the non-volatile memory requested by a write instruction from the host. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example of the structure of an information processing system, including a storage system with implementation methods.

[0009] Figure 2This is a diagram used to conceptually illustrate the LUT in the implementation method.

[0010] Figure 3 This is a diagram illustrating an example of the data structure of the LUT fragment table in the implementation method.

[0011] Figure 4 This is a diagram of the VDM used to illustrate a comparative example of the implementation method.

[0012] Figure 5 This is a diagram used to conceptually illustrate the VDM in the implementation method.

[0013] Figure 6 This is a diagram illustrating an example of the data structure of the first VDM segment table in the implementation method.

[0014] Figure 7 This is a diagram illustrating an example of the data structure of the second VDM segment table in the implementation method.

[0015] Figure 8 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0016] Figure 9 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0017] Figure 10 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0018] Figure 11 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0019] Figure 12 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0020] Figure 13 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0021] Figure 14 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0022] Figure 15This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0023] Figure 16 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0024] Figure 17 This is a graph showing the relationship between the number of PBAs managed by the LUT fragment table corresponding to each level and the number of PBAs managed by the VDM fragment table in the implementation method.

[0025] Figure 18 This is a flowchart illustrating an example of the processing sequence of a storage system in an implementation where a write command has been sent from the host.

[0026] Figure 19 This is a flowchart illustrating an example of the processing sequence of a storage system in an implementation where a Trim command is sent from the host.

[0027] Figure 20 This is a flowchart illustrating an example of the processing sequence of a storage system in an implementation that determines whether data written to a specific PBA in non-volatile memory is valid or invalid.

[0028] Figure 21 This diagram is a comparative example representing the general way in which multiple blocks of non-volatile memory are cyclically utilized.

[0029] Figure 22 It is a diagram showing the size of various management data that manage the validity of data mappings in the storage system of the implementation method.

[0030] Figure 23 This is a diagram illustrating an example of how a block in a storage system is utilized in an implementation.

[0031] Figure 24 This is a diagram illustrating a selection example of a write target block in a storage system for explaining an implementation method.

[0032] Figure 25 This is a flowchart illustrating an example of the selection order of write target blocks corresponding to data size included in the data write operation of a storage system according to an implementation method.

[0033] Explanation of reference numerals in the attached figures

[0034] 1…Information processing system, 2…Host, 3…Storage system, 4…Non-volatile memory, 5…Controller, 41…LUT (Address Translation Table), 41a…PBA storage (entries), 41b…LBA storage section, 41c…Management data storage section, 41d…Front pointer storage section, 41e…Rear pointer storage section, 42…VDM (Data Mapping), 42a…Mapping storage section, 42b…PBA storage section, 42c…Management data storage section, 42d…Front pointer storage section, 42e…Rear pointer storage section, 42f…PBA storage section, 51…Communication interface control section, 52…Write buffer memory, 53…Read buffer memory, 54…Non-volatile memory controller, 55…Memory, 56…Processor, 551…Cache memory, 561…Write control section, 562…Read control section, 563…Garbage collection control section, 564…Address translation section, 565…Management section, 566…Cache memory control section. Detailed Implementation

[0035] The embodiments will now be described with reference to the accompanying drawings.

[0036] Figure 1 This is a block diagram illustrating an example of the structure of an information processing system, including the storage system of this embodiment.

[0037] In this embodiment, the storage system is a semiconductor storage device configured to write data (user data) to and read data from the non-volatile memory. This storage system can be implemented as, for example, a solid-state drive (SSD) or as another storage device such as a memory card. In this embodiment, it is assumed that the storage system is implemented as an SSD.

[0038] like Figure 1 As shown, the information processing system 1 includes a host 2 and a storage system 3. The host 2 is an information processing device that acts as a host device relative to the storage system 3. For example, it can be implemented as a personal computer, server device, mobile phone, camera device, mobile terminal (tablet computer or smartphone, etc.), gaming device or vehicle terminal (car navigation system, etc.).

[0039] The storage system 3 is configured to connect to the host 2, and includes a non-volatile memory 4 and a controller 5 (control circuit) for controlling the writing and reading of data to the non-volatile memory 4. Furthermore, the non-volatile memory 4 can also be configured to be removable from the controller 5. Thus, the storage capacity of the storage system 3 can be freely expanded.

[0040] As described above, when the storage system 3 is implemented as an SSD, the non-volatile memory 4 is, for example, a NAND flash memory. In this case, the non-volatile memory 4 (NAND flash memory) includes multiple memory cells (memory cell array) configured in a matrix. Furthermore, the non-volatile memory 4 can be either a 2D NAND flash memory or a 3D NAND flash memory.

[0041] Furthermore, the non-volatile memory 4's storage cell array comprises multiple blocks, each of which is composed of multiple pages. In the storage system 3 (SSD), each block functions as a unit for data erasure. Additionally, each page serves as the unit for both data write and data read operations.

[0042] Furthermore, various data are written to the non-volatile memory 4, but the non-volatile memory 4 further stores an address translation table (hereinafter simply referred to as LUT) 41, which is called a LUT (Look Up Table). The LUT 41 is also known as L2P (Logical address to Physical address). The LUT 41 is essentially data used to manage the correspondence between logical addresses used when the host 2 accesses the storage system 3 (writing data to or reading data from the non-volatile memory 4) and physical addresses representing the physical locations of the written data within the non-volatile memory 4. In other words, the LUT 41 stores the physical address corresponding to each logical address.

[0043] Furthermore, when the non-volatile memory 4 is a NAND flash memory, the logical address managed in LUT41 is the logical block address (LBA), and the physical address is the physical block address (PBA). In the following explanation, the logical address will be referred to as LBA and the physical address as PBA.

[0044] In addition, the non-volatile memory 4 also stores a data map called VDM (Valid Data Map) 42. VDM 42 is equivalent to data used to manage the validity of data written to physical addresses in the non-volatile memory 4 (i.e., whether the data is valid or invalid).

[0045] Alternatively, at least one of LUT41 and VDM42 may be stored in a non-volatile memory other than non-volatile memory 4. Furthermore, non-volatile memory 4 may be configured to have memory (regions) partitioned for storing data, LUT41, and VDM42.

[0046] The controller 5 includes a communication interface control unit 51, a write buffer memory 52, a read buffer memory 53, a non-volatile memory controller 54, a memory 55, and a processor 56. Furthermore, the communication interface control unit 51, the write buffer memory 52, the read buffer memory 53, the non-volatile memory controller 54, the memory 55, and the processor 56 are electrically connected via an internal bus IB.

[0047] The communication interface control unit 51 controls the communication between an external device (e.g., host 2) and the storage system 3. Specifically, the communication interface control unit 51 receives various instructions from the host 2. These instructions from the host 2 include, for example, write instructions (write requests) and read instructions (read requests).

[0048] Furthermore, the write instruction received by the communication interface control unit 51 includes the data written to the non-volatile memory 4 based on the write instruction, as well as the LBA used by the host 2 when accessing the data. Additionally, the read instruction received by the communication interface control unit 51 includes the LBA used by the host 2 when accessing the data read based on the read instruction (i.e., the LBA corresponding to the data).

[0049] Here, upon receiving a write command via the communication interface control unit 51, data is written to the non-volatile memory 4 based on the write command, but the write buffer memory 52 temporarily stores the data written to the non-volatile memory 4. The data stored in the write buffer memory 52 is written to the non-volatile memory 4 via the non-volatile memory controller 54.

[0050] On the other hand, when a read command is received via the communication interface control unit 51, data is read from the non-volatile memory 4 based on the read command, but the read buffer memory 53 temporarily stores the data read from the non-volatile memory 4 via the non-volatile memory controller 54. Furthermore, the data stored in the read buffer memory 53 is transmitted to the host 2 via the communication interface control unit 51.

[0051] The non-volatile memory controller 54 controls the writing of data to and reading data from the non-volatile memory 4. Further detailed descriptions are omitted, but the non-volatile memory controller 54 may also be configured to include a DMAC (Direct Memory Access Controller), an error correction unit, a random number generator (or a scrambler), etc.

[0052] Memory 55 is the main storage device used as the working memory of processor 56. Memory 55 is, for example, DRAM (Dynamic Random Access Memory), but may also be other semiconductor memories such as SRAM (Static Random Access Memory).

[0053] Furthermore, compared to the non-volatile memory 4, memory 55 can be written to and read from at high speed, including cache memory 551 (the utilized area). Cache memory 551 stores cached data such as LUT41 and VDM42 stored in the non-volatile memory 4.

[0054] The processor 56 controls the overall operation of the controller 5 via the internal bus IB. The processor 56 performs various processes (such as processing various instructions received from the host 2) by executing a control program (firmware) stored in a ROM (Read Only Memory) not shown.

[0055] In this embodiment, the controller 5 functions as a flash translation layer (FTL) configured to perform data management and block management of the non-volatile memory 4 (NAND flash memory) via such a processor 56.

[0056] Alternatively, the processor 56 can be, for example, a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), or a DSP (Digital Signal Processor).

[0057] The processor 56 executes the above-described control program to implement functional units such as the write control unit 561, the read control unit 562, the garbage collection control unit 563, the address translation unit 564, the management unit 565, and the cache memory control unit 566.

[0058] Furthermore, these components 561 to 566 are implemented through a control program (i.e., software) as described above, but they can also be implemented through hardware or through a combination of software and hardware.

[0059] When the write control unit 561 receives a write command from the communication interface control unit 51, it controls the communication interface control unit 51, the write buffer memory 52, and the non-volatile memory controller 54 to execute the process of writing the data included in the write command to the non-volatile memory 4.

[0060] When the read control unit 562 receives a read instruction through the communication interface control unit 51, it controls the communication interface control unit 51, the read buffer memory 53, and the non-volatile memory controller 54 to perform the process of reading the data corresponding to the LBA included in the read instruction from the non-volatile memory 4.

[0061] The garbage collection control unit 563, for example, cooperates with the write control unit 561, the read control unit 562, and the non-volatile memory controller 54 to perform garbage collection (GC) on the non-volatile memory 4, referring to the VDM 42 described above. Garbage collection is a process of releasing unnecessary storage areas (memory regions) of the non-volatile memory 4. Additionally, compaction to eliminate fragmentation of the storage regions of the non-volatile memory 4 can also be performed concurrently with garbage collection.

[0062] When the address translation unit 564 receives the read instruction from the communication interface control unit 51, it performs a process of converting the LBA included in the read instruction into a PBA (physical address) using the LUT 41 stored in the non-volatile memory 4. In the storage system 3, data (data corresponding to the LBA) can be read from the non-volatile memory 4 based on the PBA converted from the LBA by the address translation unit 564.

[0063] When the management unit 565 receives the aforementioned write instruction from the communication interface control unit 51 and writes data to the non-volatile memory 4 based on the write instruction, it performs the process of updating LUT41 and VDM42.

[0064] The cache memory control unit 566 performs the following processing: for example, reading a portion of LUT41 or a portion of VDM42 from the non-volatile memory 4 via the read control unit 562, and storing the LUT41 or VDM42 in the cache memory 551. Additionally, the cache memory control unit 566 performs the following processing: reading a portion of LUT41 or a portion of VDM42 stored in the cache memory 551, and writing (writing back) the LUT41 or VDM42 to the non-volatile memory 4 via the write control unit 561.

[0065] In addition, Figure 1 The example described above illustrates a scenario where the storage system 3 is located externally to the host 2. However, as the interface between the host 2 and the storage system 3, MVMe over Fabrics could also be used, for example. Alternatively, the storage system 3 could be built into the host 2. Furthermore, the storage system 3 could be connected to multiple hosts 2, or multiple storage systems 3 could be connected to one or more hosts 2.

[0066] Here, the correspondence between LBA (Logical Address) and PBA (Physical Address) is managed in the LUT41. However, for example, when the communication interface control unit 51 receives a write command from the host 2 and writes data into the non-volatile memory 4 based on the write command, the management unit 565 needs to update the correspondence between the LBA included in the write command and the PBA in the non-volatile memory 4 where the data has been written (that is, to register the correspondence in the LUT41).

[0067] However, when a wide range of LBAs is specified in the above write instruction, the processing time for updating the correspondence between LBAs and PBAs in LUT41 is considerable.

[0068] Therefore, the LUT41 in this embodiment is configured to have a hierarchical structure consisting of multiple levels and includes multiple tables (hereinafter referred to as LUT fragment tables) corresponding to these multiple levels. Furthermore, the hierarchical structure of the LUT41 is determined, for example, based on setting information of the storage system 3, including the capacity of the non-volatile memory 4.

[0069] In such a LUT41, each of the multiple LUT fragment tables is, for example, set to the same size. Furthermore, as detailed later, in the LUT fragment table corresponding to the higher level among the multiple LUT fragment tables corresponding to multiple levels, reference target information (hereinafter referred to as LUT pointers) for reference LBAs (ranges) and reference target information for LUT fragment tables corresponding to lower levels is stored. Additionally, the LUT pointer includes, for example, PBAs stored in the non-volatile memory 4 of the LUT fragment table that serves as the reference target. Furthermore, in the hierarchical structure of the LUT41, the LUT fragment table corresponding to the lowest level stores the PBAs corresponding to each LBA allocated to that LUT fragment table.

[0070] That is, in this embodiment, LUT41 has a hierarchical structure that can sequentially refer to the LUT fragment table corresponding to the upper level and the LUT fragment table corresponding to the lower level, and manage the correspondence between LBA and PBA in the hierarchical structure.

[0071] The following is for reference Figure 2 This provides a conceptual explanation of the hierarchical structure of LUT41. Figure 2 In the example shown, it is assumed that LUT41 has a hierarchical structure consisting of four levels. In this case, LUT41 includes multiple first LUT fragment tables T411 to fourth LUT fragment tables T414.

[0072] like Figure 2 As shown, the first LUT fragment table T411 is the LUT fragment table corresponding to the lowest level (hereinafter referred to as the first level) in the hierarchical structure of LUT41. The second LUT fragment table T412 is the LUT fragment table corresponding to the level above the first LUT fragment table T411 (hereinafter referred to as the second level) in the hierarchical structure of LUT41. The third LUT fragment table T413 is the LUT fragment table corresponding to the level above the second LUT fragment table T412 (hereinafter referred to as the third level) in the hierarchical structure of LUT41. The fourth LUT fragment table T414 is the LUT fragment table corresponding to the level above the third LUT fragment table T413 (hereinafter referred to as the fourth level) in the hierarchical structure of LUT41. Furthermore, in Figure 2 In the example shown, the fourth level is the topmost level in the hierarchical structure of LUT41.

[0073] The following is a detailed explanation of the first LUT fragment table T411 to the fourth LUT fragment table T414.

[0074] First, multiple first LUT fragment tables T411 are each assigned a contiguous range of LBAs. Each first LUT fragment table T411 includes multiple entries C411. Furthermore, in each of the multiple entries C411 included in the first LUT fragment table T411, one distinct LBA from the range of LBAs assigned to that first LUT fragment table T411 is assigned, and the corresponding PBA (i.e., the PBA to which data corresponding to that LBA has been written) is stored.

[0075] Furthermore, in this embodiment, the entire range of LBAs used by host 2 when accessing storage system 3 is divided into a number of first LUT fragment tables T411, and the divided range of LBAs is assigned to each of the first LUT fragment tables T411. Thus, PBAs corresponding to each LBA of the entire range of LBAs used by host 2 when accessing storage system 3 can be managed in multiple first LUT fragment tables T411.

[0076] Next, multiple second LUT fragment tables T412 are each allocated a LBA range wider than the aforementioned first LUT fragment table T411. Each second LUT fragment table T412 includes multiple entries C412. Furthermore, in each of the multiple entries C412 included in the second LUT fragment table T412, a range of LBAs allocated to the first LUT fragment table T411 corresponding to the lower level of the second LUT fragment table T412 is allocated, and a LUT pointer representing the (position) of the first LUT fragment table T411 is stored. In this case, the range of LBAs allocated to each of the second LUT fragment tables T412 is equivalent to the range of LBAs allocated to all the first LUT fragment tables T411 represented by the LUT pointers stored in each of the multiple entries C412 included in the second LUT fragment table T412.

[0077] Furthermore, multiple third LUT fragment tables T413 are each allocated a wider LBA range than the aforementioned second LUT fragment table T412. Each third LUT fragment table T413 includes multiple entries C413. Additionally, in each of the multiple entries C413 included in the third LUT fragment table T413, a range of LBAs allocated to the second LUT fragment table T412 corresponding to the lower level of the third LUT fragment table T413 is allocated, and a LUT pointer representing the (position) of the second LUT fragment table T412 is stored. In this case, the range of LBAs allocated to each of the third LUT fragment tables T413 is equivalent to the range of LBAs allocated to all the second LUT fragment tables T412 represented by the LUT pointers stored in each of the multiple entries C413 included in the third LUT fragment table T413.

[0078] Furthermore, each of the multiple fourth LUT fragment tables T414 is allocated a wider LBA range than the aforementioned third LUT fragment table T413, and each fourth LUT fragment table T414 includes multiple entries C414. Additionally, in each of the multiple entries C414 included in the fourth LUT fragment table T414, a range of LBAs allocated to the third LUT fragment table T413 corresponding to the next lower level of the fourth LUT fragment table T414 is allocated, and a LUT pointer representing the (position) of the third LUT fragment table T413 is stored. In this case, the range of LBAs allocated to each of the fourth LUT fragment tables T414 is equivalent to the range of LBAs allocated to all of the third LUT fragment tables T413 represented by the LUT pointers stored in each of the multiple entries C414 included in the fourth LUT fragment table T414.

[0079] Here, the multiple fourth LUT fragment tables T414 corresponding to the fourth level (i.e., the highest level in the hierarchical structure) correspond to each of the multiple namespaces. A namespace is a region obtained by logically dividing the storage areas (multiple blocks) of the non-volatile memory 4. By allocating namespaces according to a defined range for each storage area, even if LBAs are repeated in two or more storage areas, for example, the appropriate data can be accessed using the namespace ID (identification information used to identify the namespace) and the LBA. Thus, access to different namespaces can be handled in the same way as access to different devices.

[0080] exist Figure 2 In this context, multiple fourth LUT fragment tables T414 correspond to namespaces NS1 to NSn (where n is a natural number greater than 2). In this case, the number of multiple fourth LUT fragment tables T414 is n.

[0081] In addition, such as Figure 2 As shown, LUT41 has a hierarchical structure based on namespaces NS1 to NSn (corresponding to the fourth LUT fragment table T414), but the number of levels for each namespace NS1 to NSn depends on the size of the storage area allocated to that namespace. For example, if the size of the storage area allocated to a namespace is small, the number of levels for that namespace is smaller. On the other hand, if the size of the storage area allocated to a namespace is large, the number of levels for that namespace is larger. Furthermore, in... Figure 2 The example shown illustrates the case where namespaces NS1 to NSn each have the same number of levels.

[0082] In the above-mentioned Figure 2 In the LUT41 of the hierarchical structure shown, the LUT pointers stored in each entry C414 of the fourth LUT fragment table T414 corresponding to the fourth level (the highest level) represent the third LUT fragment table T413 corresponding to the third level. The LUT pointers stored in each entry C413 of the third LUT fragment table T413 represent the second LUT fragment table T412 corresponding to the second level. The LUT pointers stored in each entry C412 of the second LUT fragment table T412 represent the first LUT fragment table T411 corresponding to the first level (the lowest level). The entries C411 of the first LUT fragment table T411 store the PBA corresponding to one LBA.

[0083] Based on such a LUT41, for example by referring sequentially to the fourth LUT fragment table T414, the third LUT fragment table T413, the second LUT fragment table T412, and the first LUT fragment table T411 based on the LBA specified in various instructions (LBAs included in various instructions), the PBA corresponding to the LBA can be determined.

[0084] Here, in Figure 2 In the example shown, the first LUT fragment table T411 is the LUT fragment table corresponding to the lowest level in the hierarchical structure of LUT41. Each entry C411 in the first LUT fragment table T411 stores a PBA corresponding to one LBA. In this case, if the size of the data written to one PBA is 4 KiB, and the first LUT fragment table T411 includes 32 entries C411, then the first LUT fragment table T411 corresponding to the first level is allocated a range of 32 LBAs (i.e., LBAs for accessing 128 KiB of data).

[0085] Similarly, if we assume that a second LUT fragment table T412 includes 32 entries C412, and the LUT pointer representing the first LUT fragment table T411, which is allocated 32 LBAs for accessing 128 KiB of data, is stored in each of the entries C412 (i.e., each entry C412 is allocated a range of 32 LBAs allocated to the first LUT fragment table T411), then a range of 32 × 32 = 1,024 LBAs (i.e., LBAs for accessing 4 MiB of data) is allocated in the second LUT fragment table T412 corresponding to the second level.

[0086] Furthermore, if we assume that a third LUT fragment table T413 includes 32 entries C413, and the LUT pointer representing a second LUT fragment table T412, which is allocated 1,024 LBAs for accessing 4 MiB of data, is stored in each of the entries C413 (i.e., each entry C413 is allocated a range of 1,024 LBAs allocated to the second LUT fragment table T412), then a range of 1,024 × 32 = 32,768 LBAs (i.e., LBAs for accessing 128 MiB of data) is allocated in the third LUT fragment table T413 corresponding to the third level.

[0087] Furthermore, if we assume that a fourth LUT fragment table T414 includes 32 entries C414, and the LUT pointer representing the third LUT fragment table T413, which is allocated 32,768 LBAs for accessing 128 MiB of data, is stored in each of the entries C414 (i.e., each entry C414 is allocated a range of 32,768 LBAs allocated to the third LUT fragment table T413), then the fourth LUT fragment table T414 corresponding to the fourth level is allocated a range of 32,768 × 32 = 1,048,576 LBAs (i.e., LBAs for accessing 4 GiB of data).

[0088] That is, in Figure 2 In the example of LUT41 shown, each first LUT fragment table T411 manages the range of LBAs for accessing 128 KiB of data, each second LUT fragment table T412 manages the range of LBAs for accessing 4 MiB of data, each third LUT fragment table T413 manages the range of LBAs for accessing 128 MiB of data, and each fourth LUT fragment table T414 manages the range of LBAs for accessing 4 GiB of data.

[0089] In addition, Figure 2 For example, it has been described that LUT pointers are stored in each of the multiple entries C414 included in the fourth LUT fragment table T414. However, if the multiple third LUT fragment tables T413 represented by these LUT pointers are consecutively arranged in the non-volatile memory 4, the fourth LUT fragment table T414 can also be configured to store only the LUT pointers representing the first third LUT fragment table T413 among the multiple third LUT fragment tables T413 (that is, the LUT pointers representing the third LUT fragment table T413 that is not the first are omitted). This allows for a reduction in the size of the LUT 41. The fourth LUT fragment table T414 has been described here, but the same applies to other LUT fragment tables.

[0090] Alternatively, if the continuity of the PBA in the non-volatile memory 4, which contains data corresponding to the range of LBAs allocated to a LUT fragment table, is ensured, the LUT fragment table corresponding to a lower level than the LUT fragment table (i.e., represented by LUT pointers stored in the entries included in the LUT fragment table) may be omitted.

[0091] Specifically, for example, the second LUT segment table T412 manages the range of LBAs used to access 4 MiB of data. However, when 4 MiB of data accessed through the LBAs managed in the second LUT segment table T412 is written to consecutive PBAs, the entry C413 included in the third LUT segment table T413 can also replace the LUT pointer representing the second LUT segment table T412 to store the first PBA of the data written to the 4 MiB. Thus, it is not necessary to refer to the second LUT segment table T412 and the first LUT segment table T411, which are lower than the third LUT segment table T413, so LUT41 can be referenced efficiently, and the access speed of data written to the non-volatile memory 4 can be improved.

[0092] Figure 3 This illustrates an example of the data structure of the LUT fragment table included in LUT41 in this embodiment. Here, the data structure of the first LUT fragment table T411 will be mainly described.

[0093] The first LUT segment table T411 includes, for example, multiple PBA storage units 41a, LBA storage units 41b, and management data storage units 41c.

[0094] PBA storage unit 41a is equivalent to in Figure 2 The first LUT segment table T411 described herein includes entries C411. That is, the number of PBA storage units 41a is, for example, 32. Each PBA storage unit 41a stores a PBA corresponding to one LBA allocated to it (i.e., the PBA to which data corresponding to that LBA has been written). In addition, when the data corresponding to one LBA allocated to the PBA storage unit 41a is stored in the cache memory 551, the address information (PBA) within the cache memory 551 is stored in the PBA storage unit 41a. The size of the PBA stored in the PBA storage unit 41a is, for example, 32 bits.

[0095] Additionally, the PBA stored in the PBA storage unit 41a includes, for example, 8 bits of management data MD1, which is stored together with the PBA in the PBA storage unit 41a. Thus, the management data MD1 attached to the PBA includes, for example, data that manages the address information of whether the PBA is in the non-volatile memory 4 or in the cache memory 551.

[0096] In this case, the size of each PBA storage unit 41a is 40 bits, which is obtained by adding the size of the PBA (32 bits) to the size of the management data MD1 (8 bits). The total size of the 32 PBA storage units 41a is 160 bytes.

[0097] LBA storage unit 41b stores the first LBA within the LBA range allocated to the first LUT segment table T411.

[0098] The management data storage unit 41c stores a namespace ID for identifying the namespace to which the first LUT fragment table T411 belongs, and a Grain corresponding to the range of LBAs assigned to the first LUT fragment table T411 (the range of LBAs managed by the first LUT fragment table T411).

[0099] Additionally, other information may be stored in the management data storage unit 41c. Specifically, the management data storage unit 41c may also store identification information (level ID) for identifying the level (first level) corresponding to the first LUT fragment table T411.

[0100] In this embodiment, for example, when LUT41 is updated, a portion of LUT41 (the LUT fragment table that becomes the object of the update) is stored in cache memory 551. In this case, a portion of LUT41 is stored on a cache line basis. Additionally, the portion of LUT41 updated in cache memory 551 is written back to non-volatile memory 4 on a cache line basis.

[0101] Assume that the first LUT segment table T411 is stored in the cache memory 551 in units of the aforementioned cache lines. If the first LUT segment table T411 stored in the cache memory 551 is set as LUT cache data, then in addition to the aforementioned PBA storage unit 41a, LBA storage unit 41b, and management data storage unit 41c, this LUT cache data also includes, for example, pointers representing LUT cache data that should be associated with each other in the cache memory 551.

[0102] Specifically, the LUT cache data includes: a front pointer storage section 41d, which stores pointers to LUT cache data referenced before the LUT cache data; and a rear pointer storage section 41e, which stores pointers to other LUT cache data referenced after the LUT cache data.

[0103] The pointers stored in the aforementioned front pointer storage section 41d and rear pointer storage section 41e can be, for example, a PBA that stores other LUT cache data, but other forms of addresses can also be used.

[0104] By utilizing pointers to the preceding and following LUT cache data that should be referenced to the LUT cache data, access to the cache memory 551 can be accelerated, enabling sequential access. Furthermore, the LUT cache data can also include other management data.

[0105] exist Figure 3 The data structure of one first LUT fragment table T411 is described, but all the multiple first LUT fragment tables T411 included in LUT41 have the same data structure.

[0106] Furthermore, the data structures of the LUT fragment tables other than the first LUT fragment table T411 (the second LUT fragment table T412 to the fourth LUT fragment table T414) are the same as those of the first LUT fragment table T411. However, in each of the PBA storage sections 41a included in the second LUT fragment table T412 to the fourth LUT fragment table T414, a PBA (32 bits) stored in the non-volatile memory 4 is stored as a LUT pointer representing the LUT fragment table corresponding to the lower level. In addition, when the LUT fragment table corresponding to the lower level is stored in the cache memory 551, the address information in the cache memory 551 is stored in the PBA storage section 41a.

[0107] Furthermore, even in the PBA storage section 41a included in the second LUT fragment table T412 to the fourth LUT fragment table T414, there may be cases where data corresponding to the range of LBAs allocated to the PBA storage section 41a (entry C412, C413 or C424) is written to the beginning of the PBA.

[0108] In addition, Figure 3 In the example shown, the size of each of the first LUT fragment table T411 to the fourth LUT fragment table T414 is, for example, a fixed length of 168 bytes, and the size of each of the LUT cache data stored in the cache memory 551 is, for example, a fixed length of 188 bytes. However, in this embodiment, it is assumed that the first LUT fragment table T411 to the fourth LUT fragment table T414 (i.e., the multiple LUT fragment tables included in LUT41) have the same data structure.

[0109] Here, LUT41 is described as having a hierarchical structure consisting of multiple levels, but in this embodiment, VDM42 also has a hierarchical structure similar to LUT41.

[0110] The VDM42 in this embodiment will be described below. First, refer to... Figure 4The VDM in the comparative example of this embodiment will be described. The VDM in the comparative example of this embodiment is configured to manage the validity of data written to physical addresses in the non-volatile memory 4 in a single level.

[0111] like Figure 4 As shown, in the comparative example of this embodiment, VDM42' includes multiple VDM fragment tables T421' corresponding to a single level. Different ranges of PBAs (Physical Addresses) are allocated to each of the multiple VDM fragment tables T421', and in each of these VDM fragment tables T421', the validity (i.e., whether the data is valid or invalid) of the data stored within the range of the PBA allocated to that VDM fragment table T421' is managed.

[0112] In this case, for example, the entire range of PBAs within the non-volatile memory 4, which can be written to based on write instructions from host 2, is divided into a number of VDM segment tables T421', and the divided range of PBAs is allocated to each of the first VDM segment table T421'. Thus, the validity of data written within the entire range of PBAs within the non-volatile memory 4, which can be written to based on write instructions from host 2, can be managed in the plurality of VDM segment tables T421'. Furthermore, the validity of data written within the range of PBAs allocated to each of the plurality of VDM segment tables T421' is managed using a bitmap (BMP) described later.

[0113] Here, for example, when data is written to a PBA in non-volatile memory 4 based on a write instruction from host 2, in order to update the validity of the data written to the PBA, it is necessary to refer to the VDM segment table T421' to which the PBA is allocated. However, in order to refer to the VDM segment table T421', it is necessary to hold (unfold) a pointer to each (position) of the aforementioned plurality of VDM segment tables T421' in memory 55 beforehand. The pointer held in memory 55 in advance includes, for example, the PBA in non-volatile memory 4 that stores each of the plurality of VDM segment tables T421'.

[0114] For example, if the size of the storage area of ​​the non-volatile memory 4 whose data validity is managed is 2 PiB, and the size of the data written into 1 PBA (i.e., the unit of data for managing validity) is 4 KiB, then 2 PiB ÷ 4 KiB = 549,755,813,888, and approximately 512G of 4 KiB of data validity needs to be managed in VDM42'.

[0115] Alternatively, if we assume that 1,280 4KiB data items are managed in one VDM fragment table T421', then it becomes 512G ÷ 1,280 = 429,496,729.6, and the number of VDM fragment tables T421' required in VDM42' becomes 429,496,730.

[0116] Furthermore, if we assume that the size of the pointer representing each of the multiple VDM fragment tables T421' is 32 bits (4 bytes), then the total size of the pointers representing all 429,496,730 VDM fragment tables T421' is 429,496,730 × 4 bytes = 1,717,986,920 bytes, which is approximately 1.6 GiB.

[0117] That is, when using the VDM42' of the comparative example of this embodiment to manage the validity of data written to the PBA in the non-volatile memory 4, it is necessary to keep the pointers representing the full 1.6 GiB VDM fragment table T421' always in memory 55 beforehand (i.e., the information required for the management of VDM42' continuously occupies memory 55), which may sometimes impair usability. Specifically, keeping LUT41 in memory 55 (cache memory 551) is useful for improving the response speed (IO response speed) to instructions from host 2, but it may not be possible to ensure sufficient storage area for keeping LUT41 through the various pointers of the VDM fragment table T421'.

[0118] In addition, the non-volatile memory 4 is composed of multiple chips, but if, for example, the number of chips or the capacity of the chips themselves is increased, the number of PBAs in the non-volatile memory 4 (i.e., the storage area managed by the storage system 3) increases.

[0119] As a result, the number of VDM fragment tables T421' increases, and consequently the number of pointers representing VDM fragment tables T421' also increases, requiring a larger storage area in memory 55 for these pointers.

[0120] Similarly, as the number of PBAs in the non-volatile memory 4 increases, the size of the VDM42' itself also increases, so the storage area used for caching the VDM42' must sometimes be expanded as needed.

[0121] To address this, for example, one could consider adding memory (DRAM) to ensure storage space, but this would require avoiding increased costs. In other words, in the comparative example VDM42' of this embodiment, the difficulty in addressing the technological innovation of the non-volatile memory 4 (i.e., the increase in storage capacity) is high.

[0122] Therefore, when starting the storage system 3, it is necessary to expand all the pointers representing the VDM segment table T421' on the memory 55 as described above.

[0123] Furthermore, when terminating (stopping) the storage system 3, it is necessary to make all pointers held in memory 55 non-volatile. Specifically, for example, if a VDM segment table T421' is cached in memory 55 (cache memory 551), the pointer representing the VDM segment table T421' held in memory 55 is changed to the address information in the cache memory 551. When terminating the storage system 3, such a VDM segment table T421' is written back to non-volatile memory 4 (i.e., non-volatile), but in this case, it is necessary to change the pointer representing the VDM segment table T421' (the address information in the cache memory 551) to the PBA written to the non-volatile memory 4 of the VDM segment table T421', and write the changed PBA (i.e., the pointer) in the non-volatile memory 4 into the non-volatile memory 4. When storage system 3 is terminated, such processing is performed on all VDM segment tables T421' cached in cache memory 551.

[0124] That is, in the VDM42' of the comparative example of this embodiment, the internal processing (startup processing and shutdown processing) for starting and ending the storage system 3 takes time.

[0125] Therefore, in this embodiment, by employing a VDM42 with a hierarchical structure similar to the LUT41 described above, the effectiveness of managing the data written to the non-volatile memory 4 is achieved efficiently.

[0126] Specifically, the VDM42 in this embodiment is configured to have a hierarchical structure consisting of multiple levels, and includes multiple VDM fragment tables for the multiple levels.

[0127] In such a VDM42, multiple VDM fragment tables are configured to have the same size, for example. Further details will be described later. In the VDM fragment table corresponding to the higher-level hierarchy, information such as the range of reference PBAs and reference target information (hereinafter referred to as VDM pointers) for VDM fragment tables corresponding to lower-level hierarchies is stored. The VDM pointer includes, for example, the PBA stored in the non-volatile memory 4 of the VDM fragment table that serves as the reference target. Furthermore, in the hierarchical structure of the VDM42, the VDM fragment table corresponding to the lowest-level hierarchy manages the validity of data of a predetermined size (e.g., 4 KiB of data) stored within the range of the PBA allocated to that VDM fragment table.

[0128] The following is for reference Figure 5 This embodiment provides a conceptual description of the hierarchical VDM42. Figure 5 In the example shown, for convenience, it is assumed that VDM42 has a hierarchical structure consisting of four levels. In this case, VDM42 includes multiple first VDM fragment tables T421 to fourth VDM fragment tables T424.

[0129] like Figure 5 As shown, the first VDM fragment table T421 is the VDM fragment table corresponding to the lowest level (hereinafter referred to as the first level) in the hierarchical structure of VDM42. The second VDM fragment table T422 is the VDM fragment table corresponding to the level above the first VDM fragment table T421 (hereinafter referred to as the second level) in the hierarchical structure of VDM42. The third VDM fragment table T423 is the VDM fragment table corresponding to the level above the second VDM fragment table T422 (hereinafter referred to as the third level) in the hierarchical structure of VDM42. The fourth VDM fragment table T424 is the VDM fragment table corresponding to the level above the third VDM fragment table T423 (hereinafter referred to as the fourth level) in the hierarchical structure of VDM42. Furthermore, in Figure 5 In the example shown, the fourth level is the topmost level in the hierarchical structure of VDM42. In VDM42, the number of VDM fragment tables (i.e., the fourth VDM fragment table T424) corresponding to the topmost level is, for example, one. In this embodiment, it is described that the number of fourth VDM fragment tables T424 (the VDM fragment table corresponding to the topmost level) is one, but the number of fourth VDM fragment tables T424 can also be multiple.

[0130] The first VDM segment table T421 to the fourth VDM segment table T424 mentioned above will be described in detail below.

[0131] First, multiple first VDM fragment tables T421 are each assigned a contiguous range of PBAs. Each first VDM fragment table T421 includes multiple entries C421. Furthermore, in each of the multiple entries C421 included in the first VDM fragment table T421, a bitmap (BMP) consisting of 1 bit information is stored. This bitmap (BMP) manages the validity of the data stored in each of the multiple PBAs corresponding to the range of PBAs assigned to the first VDM fragment table T421. In such a bitmap, for each PBA, for example, a bit information of 1 indicates that the data stored in the PBA is valid, and a bit information of 0 indicates that the data stored in the PBA is invalid.

[0132] In addition, multiple first VDM fragment tables T421 are equivalent to the above. Figure 4 The multiple VDM segment tables T421' shown represent a number of VDM segment tables, each containing a range of PBAs within the non-volatile memory 4 that can be written to based on write commands from the host 2. Each of these ranges of PBAs is assigned to one of the first VDM segment tables T421. Thus, the validity of data written to the entire range of PBAs within the non-volatile memory 4 that can be written to based on write commands from the host 2 can be managed within the multiple VDM segment tables T421.

[0133] Next, a plurality of second VDM fragment tables T422 are each allocated a PBA range wider than the aforementioned first VDM fragment table T421. Each second VDM fragment table T422 includes a plurality of entries C422. Furthermore, in each of the plurality of entries C422 included in the second VDM fragment table T422, a range of PBA allocated to the first VDM fragment table T421 corresponding to the lower level of the second VDM fragment table T422 is allocated, and a VDM pointer representing the (position) of the first VDM fragment table T421 is stored. In this case, the range of PBA allocated to each second VDM fragment table T422 is equivalent to the range of PBA allocated to all first VDM fragment tables T421 represented by the VDM pointer stored in each of the plurality of entries C422 included in the second VDM fragment table T422.

[0134] Furthermore, multiple third VDM fragment tables T423 are each allocated a PBA range wider than the aforementioned second VDM fragment table T422, and each third VDM fragment table T423 includes multiple entries C423. Additionally, in each of the multiple entries C423 included in the third VDM fragment table T423, a range of PBA allocated to the second VDM fragment table T422 corresponding to the lower level of the third VDM fragment table T423 is allocated, and a VDM pointer representing the (position) of the second VDM fragment table T422 is stored. In this case, the range of PBA allocated to each third VDM fragment table T423 is equivalent to the range of PBA allocated to all second VDM fragment tables T422 represented by the VDM pointer stored in each of the multiple entries C423 included in the third VDM fragment table T423.

[0135] Furthermore, a wider PBA range than the aforementioned third VDM fragment table T423 is allocated in the fourth VDM fragment table T424, which includes multiple entries C424. Additionally, in each of the multiple entries C424 included in the fourth VDM fragment table T424, a range of PBAs allocated to the third VDM fragment table T423, which is at a lower level relative to the fourth VDM fragment table T424, is allocated, and a VDM pointer representing the (position) of the third VDM fragment table T423 is stored. In this case, the range of LBAs allocated to the fourth VDM fragment table T424 is equivalent to the range of all PBAs allocated to the third VDM fragment table T423 represented by the VDM pointers stored in each of the multiple entries C424 included in the fourth VDM fragment table T424.

[0136] Furthermore, as described above, when the number of fourth VDM segment tables T424 corresponding to the highest level in the hierarchical structure of VDM42 is 1, the range of PBAs allocated to the fourth VDM segment table T424 covers the entire range of PBAs within the non-volatile memory 4 where the validity of the data is managed.

[0137] In the above-mentioned Figure 5In the VDM42 of the shown hierarchical structure, the following configuration is made: the VDM pointers stored in each entry C424 of the fourth VDM fragment table T424 corresponding to the fourth level (the highest level) represent the third VDM fragment table T423 corresponding to the third level; the VDM pointers stored in each entry C423 of the third VDM fragment table T423 represent the second VDM fragment table T422 corresponding to the second level; the VDM pointers stored in each entry C422 of the second VDM fragment table T422 represent the first VDM fragment table T421 corresponding to the first level (the lowest level); and the entries C421 of the first VDM fragment table T421 store flag information (bit mapping) indicating the validity of data of a specified size stored in multiple PBAs.

[0138] Based on such a VDM42, for example by referring sequentially to the fourth VDM fragment table T424, the third VDM fragment table T423, the second VDM fragment table T422, and the first VDM fragment table T421 based on the PBA containing the data whose validity should be verified, the validity of the data can be determined.

[0139] That is, in Figure 5 In the VDM42 shown, the validity of all data stored in the PBA (i.e., the validity of data managed in the first VDM fragment table) can be obtained from the fourth VDM fragment table T424 corresponding to the fourth level. Therefore, it is consistent with the above-mentioned... Figure 4 Unlike the VDM42' in the comparative example of this embodiment described herein, only the VDM pointer representing the fourth VDM segment table T424 (i.e., one pointer) needs to be stored in the memory 55.

[0140] Here, in Figure 5 In the example shown, the first VDM fragment table T421 is the VDM fragment table corresponding to the lowest level in the hierarchical structure of VDM42. Each entry C421 in this first VDM fragment table T421 stores flag information (bit mapping) indicating the validity of data of a specified size stored within a consecutive PBA range. In this case, if one first VDM fragment table T421 includes 32 entries C421, and each entry C421 stores a 32-bit bit mapping indicating the validity of 32 data items, then a range of 32 × 32 = 1,024 PBAs is allocated in one first VDM fragment table T421 corresponding to the first level. In this case, if the size of the data written in one PBA is 4 KiB as described above, then the validity of 4 KiB × 1,024 = 4 MiB of data can be managed in one first VDM fragment table T421.

[0141] Similarly, if we assume that a second VDM fragment table T422 includes 32 entries C422, and the VDM pointer representing a first VDM fragment table T421 allocated 4 MiB of data storage for 1,024 PBAs is stored in each of those entries C422 (i.e., each entry C422 is allocated a range of 1,024 PBAs allocated to the first VDM fragment table T421), then a range of 1,024 × 32 = 32,768 PBAs is allocated to the second VDM fragment table T422 corresponding to the second level. In this case, the validity of 4 KiB × 32,768 = 128 MiB of data can be managed in a single second VDM fragment table T422.

[0142] Furthermore, if we assume that a third VDM fragment table T423 includes 32 entries C423, and a pointer representing a second VDM fragment table T422 allocated for 128 MiB of data storage (32,768 PBAs) is stored in each of these entries C423 (i.e., each entry C423 is allocated a range of 32,768 PBAs allocated to the second VDM fragment table T422), then a range of 32,768 × 32 = 1,048,576 PBAs is allocated to the third VDM fragment table T423 corresponding to the third level. In this case, the validity of 4 KiB × 1,048,576 = 4 GiB of data can be managed within a single third VDM fragment table T423.

[0143] Furthermore, if we assume that a fourth VDM fragment table T424 includes 32 entries C414, and a pointer to a third VDM fragment table T423, which is allocated 1,048,576 PBAs for 4 GiB of data storage, is stored in each of those entries C424 (i.e., each entry C424 is allocated a range of 1,048,576 PBAs allocated to the third VDM fragment table T423), then a range of 1,048,576 × 32 = 33,554,432 PBAs is allocated to the fourth VDM fragment table T424 corresponding to the fourth level. In this case, the validity of 4 KiB × 33,554,432 = 128 GiB of data can be managed within a single fourth VDM fragment table T424.

[0144] That is, in Figure 5In the example of VDM42 shown, the first VDM fragment table T421 manages the range of PBAs for 4 MiB data storage, the second VDM fragment table T422 manages the range of PBAs for 128 MiB data storage, the third VDM fragment table T423 manages the range of PBAs for 4 GiB data storage, and the fourth VDM fragment table T424 manages the range of PBAs for 128 GiB data storage.

[0145] In addition, Figure 5 In this text, it has been described that, for example, a VDM pointer is stored in each of the multiple entries C424 included in the fourth VDM segment table T424. However, if the multiple third VDM segment tables T423 represented by each of these VDM pointers are consecutively arranged in the non-volatile memory 4, the fourth VDM segment table T424 can also be configured to store only the VDM pointers representing the first third VDM segment table T423 among the multiple third VDM segment tables T423 (i.e., omitting the VDM pointers representing third VDM segment tables T423 that are not the first). This allows for a reduction in the size of the VDM 42. The fourth VDM segment table T424 has been described here, but the same applies to other VDM segment tables.

[0146] Additionally, for example, if the validity (valid or invalid) of 4 KiB of data written within the range of a PBA allocated to a VDM fragment table is common, the validity of the data written within the range of the PBA in the VDM fragment table can also be managed together, and the VDM fragment table corresponding to a lower level than the VDM fragment table (i.e., represented by pointers stored in the entries included in the VDM fragment table) can be omitted.

[0147] Specifically, for example, suppose the second VDM fragment table T422 manages the range of PBAs for storing 128 MiB of data, but the 128 MiB of data (all 4 KiB of data constituting the 128 MiB of data) is either all valid or all invalid. In this case, it is also possible to keep the management data indicating whether the 128 MiB of data stored in the range of the PBA allocated to the second VDM fragment table T422 is all valid or all invalid in the third VDM fragment table T423, which corresponds to the upper level of the second VDM fragment table T422 (i.e., includes entries for storing VDM pointers representing the second VDM fragment table T422), thereby discarding the second VDM fragment table T422 and the first VDM fragment table T421, which corresponds to the lower level of the second VDM fragment table T422. Therefore, it is not necessary to refer to the second VDM fragment table T422, which is lower than the third VDM fragment table T423, and the first VDM fragment table T421, thus improving the access speed to VDM42.

[0148] Figure 6 This represents an example of the data structure of the first VDM segment table T421 included in VDM42 in this embodiment.

[0149] The first VDM segment table T421 includes, for example, multiple mapping storage units 42a, PBA storage units 42b, and management data storage units 42c.

[0150] Mapped storage unit 42a is equivalent to Figure 5 The first VDM segment table T421 described herein includes entry C421. That is, the number of mapping storage units 42a is, for example, 32. The mapping storage unit 42a stores a bitmap consisting of 1 bit flag information, which manages the validity (valid or invalid) of each 4 KiB of data written within the range of PBAs allocated to the mapping storage unit 42a (entry C421). When a range of 32 PBAs is allocated in the mapping storage unit 42a, the size of the bitmap stored in the mapping storage unit 42a is 1 bit × 32 = 32 bits.

[0151] Additionally, an 8-bit management data MD2 is appended to the bitmap stored in the mapping memory unit 42a, and this management data MD2 is stored together with the bitmap in the mapping memory unit 42a. As such management data MD2 appended to the bitmap, a magic number known as the VDM mode is set, for example. The magic number set as management data MD2 includes "0xff" and "0x00".

[0152] Furthermore, the bit mapping stored in the mapping storage unit 42a as described above consists of a 1-bit flag information, which indicates the validity of 4 KiB of data stored in each of the 32 PBAs allocated to the mapping storage unit 42a. In the following description, for convenience, the 4 KiB of data stored in each of the 32 PBAs will be referred to as the data managed in the bit mapping.

[0153] The magic number "0xff" indicates that all data managed in the bitmap with the magic number appended (management data MD2) is valid (i.e., all the flags constituting the bitmap are 1). In other words, based on the magic number "0xff", the validity of data written within a certain PBA range can be managed simultaneously, and the validity of all data managed in the bitmap can be determined without referring to the bitmap with the magic number appended.

[0154] The magic number "0x00" indicates that all data managed in the bitmap with this magic number (management data MD2) is invalid (i.e., all the flag information constituting the bitmap is 0). In other words, based on the magic number "0x00", the validity of data written within a certain PBA range can be managed in the same way as the aforementioned magic number "0xff", allowing one to know that all data managed in the bitmap with this magic number is invalid without referring to the bitmap with this magic number attached.

[0155] Furthermore, if the magic numbers “0xff” and “0x00” are not set for the management data MD2, it means that the bit map to which the management data MD2 is attached consists of valid flag information and invalid flag information (that is, valid flag information and invalid flag information are mixed in the bit map).

[0156] When bit mapping and management data MD2 are stored in the mapping storage unit 42a as described above, the size of each mapping storage unit 42a is 40 bits, which is obtained by adding the size of the bit mapping (32 bits) and the size of the management data MD2 (8 bits). The total size of the 32 mapping storage units 42a is 160 bytes.

[0157] PBA storage unit 42b stores the first PBA in the range of PBAs allocated to the first VDM segment table T421.

[0158] The management data storage unit 42c stores a Valid ADU Count, which represents the number of valid data items among multiple 4KiB data items stored within the range of the PBA allocated to the first VDM fragment table T421, and a Grain corresponding to the range of PBAs allocated to the first VDM fragment table T421 (the range of PBAs managed by the first VDM fragment table T421). In the case of the first VDM fragment table T421, the maximum value of the Valid ADU Count is 1,024.

[0159] Additionally, other information can also be stored in the management data storage unit 42c. Specifically, the management data storage unit 42c can also store identification information (level ID) for identifying the level (first level) corresponding to the first VDM fragment table T421.

[0160] In this embodiment, for example, when VDM42 is updated, a portion of VDM42 (the VDM fragment table to which the update is applied) is stored in cache memory 551. In this case, a portion of VDM42 is stored in units of cache lines. Furthermore, the updated portion of VDM42 in cache memory 551 is written back to non-volatile memory 4 in units of cache lines.

[0161] Assume that the first VDM segment table T421 is stored in the cache memory 551 in units of the aforementioned cache lines. If the first VDM segment table T421 stored in the cache memory 551 is designated as VDM cache data, then in addition to the aforementioned mapping memory 42a, PBA memory 42b, and management data memory 42c, this VDM cache data also includes, for example, pointers representing VDM cache data that should be associated with each other in the cache memory 551.

[0162] Specifically, the VDM cache data includes a front pointer storage section 42d that stores pointers to VDM cache data referenced before it, and a rear pointer storage section 42e that stores pointers to other VDM cache data referenced after it. Additionally, pointers to the LUT cache data described above may also be stored in the front pointer storage section 42d and the rear pointer storage section 42e.

[0163] The pointers stored in the aforementioned front pointer storage section 42d and rear pointer storage section 42e can be, for example, a PBA containing other VDM cache data, but other forms of addresses can also be used.

[0164] By utilizing pointers to the preceding and following VDM cache data that should be referenced in this way, access to the cache memory 551 can be accelerated, enabling sequential access. Furthermore, the VDM cache data can further include other management data.

[0165] exist Figure 6 The data structure of one first VDM segment table T421 is described, but all the multiple first VDM segment tables T421 included in VDM42 have the same data structure.

[0166] then, Figure 7 This illustrates an example of the data structure of the second VDM segment table T422 included in VDM42 in this embodiment. Furthermore, the following description primarily focuses on the data structure described above. Figure 6 The first VDM segment table T421 shows different points.

[0167] exist Figure 6 In the description, the first VDM fragment table T421 is described as including the mapping storage unit 42a, but the second VDM fragment table T422 replaces the mapping storage unit 42a and includes the PBA storage unit 42f.

[0168] PBA storage unit 42f is equivalent to Figure 5 The second VDM segment table T422 described herein includes entries C422. That is, the number of PBA storage units 42f is, for example, 32. The PBA storage unit 42f stores the PBAs stored in the non-volatile memory 4 as pointers to the first VDM segment table T421 corresponding to the lower level of the second VDM segment table T422. Furthermore, when the first VDM segment table T421 corresponding to the lower level is stored in the cache memory 551, the address information in the cache memory 551 is stored in the PBA storage unit 42f. The size of the PBA stored in the PBA storage unit 42f is, for example, 32 bits.

[0169] Additionally, an 8-bit management data MD3 is appended to the PBA stored in the PBA storage unit 42f. This management data MD3 is stored in the PBA storage unit 42f together with the bitmap. As such, the management data MD3 appended to the bitmap, as described above... Figure 6 Similarly, the management data MD2 described in the document is set with a magic number known as the VDM mode.

[0170] In addition, the management data MD2 is described as having “0xff” and “0x00” set as magic numbers, but the magic numbers set as management data MD3 include “0xfc” and “0xfd” in addition to “0xff” and “0x00”.

[0171] The magic number "0xfc" indicates that the PBA with the magic number (management data MD3) appended is a PBA within non-volatile memory 4. Based on the magic number "0xfc", the first VDM segment table T421 stored in non-volatile memory 4 can be referenced (obtained) based on the PBA with the magic number appended.

[0172] The magic number "0xfd" indicates that the PBA with the magic number (management data MD3) appended is address information within the cache memory 551. Based on the magic number "0xfd", the first VDM segment table T421 stored in the cache memory 551 can be referenced (obtained) based on the PBA with the magic number appended.

[0173] Furthermore, as described above, the first VDM fragment table T421 referenced based on the PBA stored in the PBA storage unit 42f is a VDM fragment table corresponding to the first level of the range of PBAs allocated to the PBA storage unit 42f (entry C422).

[0174] Alternatively, the aforementioned magic number "0xff" or "0x00" can be set as the management data MD3. When the magic number "0xff" is set as the management data MD3, it means that all 4 KiB of data stored within a range of PBAs (e.g., 1,024 PBAs) is valid. These PBAs (e.g., 1,024 PBAs) are PBAs allocated to the PBA storage unit 42f that stores the PBAs with the magic number appended to them. On the other hand, when the magic number "0x00" is set as the management data MD3, it means that all 4 KiB of data stored within a range of PBAs (e.g., 1,024 PBAs) is invalid. These PBAs (e.g., 1,024 PBAs) are PBAs allocated to the PBA storage unit 42f that stores the PBAs with the magic number appended to them.

[0175] That is, when the magic number "0xff" or "0x00" is set as the management data MD3, it is possible to determine whether all data stored within the range of the PBA allocated to the PBA storage section 42f (entry C422) that stores the PBA with the magic number attached is valid or invalid. In this case, it is not necessary to refer to the first VDM fragment table T421 corresponding to the lower level based on the PBA with the magic number "0xff" or "0x00".

[0176] On the other hand, when the management data MD3 is not assigned the magic number "0xff" or "0x00" (i.e., the magic number "0xfc" or "0xfd" is assigned), it is possible to detect a situation where valid and invalid data coexist within the range of PBAs allocated to the PBA storage section 42f (entry C422) that stores PBAs with the attached magic number. In this case, it is necessary to refer to the first VDM fragment table T421 corresponding to the lower level based on the PBA with the attached magic number "0xfc" or "0xfd".

[0177] In the case where the PBA storage unit 42f stores the PBA and the management data MD3 as described above, the size of each PBA storage unit 42f is 40 bits, which is obtained by adding the size of the PBA (32 bits) and the size of the management data MD3 (8 bits). The total size of the 32 PBA storage units 42f is 160 bytes.

[0178] In addition, the second VDM segment table T422 includes PBA storage unit 42b and management data storage unit 42c, besides PBA storage unit 42f. However, since PBA storage unit 42b and management data storage unit 42c are as follows... Figure 6 As explained in the text, its detailed description is omitted here.

[0179] Furthermore, the second VDM segment table T422 (VDM cache data) stored in the cache memory 551 includes a front pointer storage section 42d and a rear pointer storage section 42e, but since the front pointer storage section 42d and the rear pointer storage section 42e are also as in Figure 6 As explained in the text, its detailed explanation is omitted here.

[0180] exist Figure 7 The data structure of one second VDM segment table T422 is described, but all the multiple second VDM segment tables T422 included in VDM42 have the same data structure.

[0181] Furthermore, the data structures of the VDM fragment tables other than the second VDM fragment table T422 (the third VDM fragment table T423 and the fourth VDM fragment table T424) are also the same as those of the second VDM fragment table T422. That is, for example, in the third VDM fragment table T423, when one of the two values, "0xff" and "0x00", is set as the management data MD3, it is not necessary to refer to the second VDM fragment table T422 corresponding to the lower level based on the PBA with the magic number attached. The same applies to the fourth VDM fragment table T424.

[0182] In addition, in the above Figure 6 and Figure 7 In the example shown, the size of each of the first VDM fragment table T421 to the fourth VDM fragment table T424 is, for example, a fixed length of 168 bytes, and the size of each of the VDM cache data stored in the cache memory 551 is, for example, a fixed length of 188 bytes. However, in this embodiment, the first VDM fragment table T421 to the fourth VDM fragment table T424 (i.e., the multiple VDM fragment tables included in VDM42) are configured to have the same data structure.

[0183] In addition, as mentioned above Figure 3 , Figure 6 as well as Figure 7 As explained above, LUT41 (the LUT fragment tables included) and VDM42 (the VDM fragment tables included) in this embodiment are configured to have the same data structure. The relationship between LUT41 and VDM42 described above will be explained below.

[0184] First, if LUT41 is configured as described above to manage the data of PBAs corresponding to LBAs, and a first LUT fragment table T411 corresponding to the lowest level (first level) includes 32 entries C411 (PBA storage unit 41a), then 32 LBAs (corresponding PBAs) can be managed in the first LUT fragment table T411. Furthermore, if a second LUT fragment table T412 corresponding to the level one level above the lowest level (second level) also includes 32 entries C412, then 32 × 32 = 1,024 LBAs (corresponding PBAs) can be managed in the second LUT fragment table T412. Here, the explanation extends up to the second level, but the same applies to levels above the second level.

[0185] On the other hand, if VDM42 is configured as data used to manage the validity of data stored in each PBA, and stores a 32-bit bit mapping in one entry C421 (mapping storage unit 42a) of one first VDM fragment table T421 corresponding to the lowest level (first level), then 32 bits × 32 = 1,024 PBAs (data stored in them) can be managed in this first VDM fragment table T421. Furthermore, if a second VDM fragment table T422 corresponding to the next higher level (second level) also includes 32 entries C422, then 1,024 × 32 = 32,768 PBAs (data stored in them) can be managed in this second VDM fragment table T422. Here, the explanation extends up to the second level, but the same applies to levels higher than the second level.

[0186] That is, in this embodiment, LUT41 and VDM42 can each manage one fragment table corresponding to the lower level through one entry. In either LUT41 or VDM42, whenever the level becomes one higher level, it can manage 32 times the number of PBAs.

[0187] Here, we assume that 4 MiB of data corresponding to a range of 1,024 consecutive LBAs is written (sequentially written) into 1,024 consecutive PBAs in the non-volatile memory 4. Furthermore, we assume that 4 KiB of data is written into each of the 1,024 PBAs.

[0188] In this case, it is necessary to manage the correspondence between the LBA corresponding to the 4 MiB of data written to the non-volatile memory 4 and the PBA to which the data was written in LUT41. However, as mentioned above, the second LUT segment table T412 can manage 1,024 LBAs (corresponding PBAs).

[0189] Therefore, when the 1,024 LBAs managed by the second LUT fragment table T412 (i.e., allocated to the second LUT fragment table T412) are consistent with the 1,024 LBAs corresponding to the aforementioned 4MiB of data, the LUT pointers representing the second LUT fragment table T412 stored in the multiple entries C413 of the third LUT fragment table T413, which corresponds to the upper level of the second LUT fragment table T412, can be updated to the first PBA among the 1,024 PBAs to which the 4MiB of data was written. Thus, the correspondence between the LBAs corresponding to the aforementioned 4MiB of data and the PBAs to which that data was written can be managed through a single entry C413 of the third LUT fragment table T413.

[0190] On the other hand, if 4 MiB of data is written into 1,024 consecutive PBAs in the non-volatile memory 4 as described above, the 4 MiB of data needs to be managed as valid data in the VDM 42. However, as mentioned above, the first VDM segment table T421 can manage 1,024 PBAs.

[0191] Therefore, when the 1,024 PBAs managed by the first VDM fragment table T421 (i.e., allocated to the first VDM fragment table T421) are the same as the 1,024 PBAs to which the aforementioned 4 MiB of data has been written, the management data MD3 (magic number) appended to the VDM pointer representing the first VDM fragment table T421 can be updated to "0xff" in the VDM pointers stored in the multiple entries C422 of the second VDM fragment table T422, which corresponds to the higher level of the first VDM fragment table T421. Thus, it is effective to manage the aforementioned 4 MiB of data stored in the 1,024 PBAs through a single entry C422 included in the second VDM fragment table T422.

[0192] That is, when 4 MiB of data corresponding to a range of 1,024 consecutive LBAs as described above is written into 1,024 consecutive PBAs, the correspondence between the LBAs and PBAs can be managed by changing one entry (PBA) in the LUT segment table corresponding to the two levels above the lowest level included in LUT41. Furthermore, the validity of the 4 MiB of data written into the non-volatile memory 4 can be managed by changing one entry (magic number) in the VDM segment table corresponding to the one level above the lowest level included in VDM42.

[0193] Thus, in this embodiment, by setting the fragment tables included in LUT41 and VDM42 to the same data structure and making the management units in LUT41 and VDM42 consistent, the LUT41 and VDM42 can be updated simply by changing the entries included in the fragment table of the upper level without updating the fragment table corresponding to the lowest level.

[0194] Here, in order to update LUT41 and VDM42 by changing the entries included in the fragment table corresponding to the higher level, as described above, the VDM fragment table included in VDM42, which has the same data structure as the LUT fragment table included in LUT41, needs to satisfy...

[0195] M = y × N ^ x (hereinafter, expressed as a conditional expression).

[0196] Furthermore, in the above conditional expression, N is the number of entries included in the first VDM fragment table T421 corresponding to the lowest level, and M is the number of 4KiB of data (i.e., the PBA used to store this data) whose validity is managed in one entry of the first VDM fragment table T421 corresponding to the lowest level. Additionally, in the conditional expression, x is an integer greater than or equal to 0, and y is an integer greater than or equal to 1 and less than N, or the reciprocal of an integer greater than or equal to 1 and less than N.

[0197] The relationship between N and M mentioned above will be explained in detail below. Here, the number of LBAs (corresponding PBAs) allocated to each LUT fragment table is called the PBA management number of that LUT fragment table, and the number of PBAs allocated to each VDM fragment table is called the PBA management number of that VDM fragment table.

[0198] In addition, the number of LBAs (corresponding PBAs) allocated to one entry in the LUT fragment table (first LUT fragment table T411) corresponding to the first level (lowest level) is 1, and this is also assumed to be the case in the following description.

[0199] Figure 8 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table when N=32 and M=32.

[0200] Here, with N=32 and M=32, the PBA management count of the LUT fragment table corresponding to the first level is 32, and the PBA management count of the VDM fragment table (first VDM fragment table T421) corresponding to the first level is 1,024. Furthermore, the PBA management count of the LUT fragment table (second LUT fragment table T412) corresponding to the second level is 1,024, and the PBA management count of the VDM fragment table (second VDM fragment table T422) corresponding to the second level is 32,768.

[0201] Additionally, detailed explanations regarding the number of PBAs in the LUT fragment table and the VDM fragment table corresponding to a higher level than the second level are omitted. However, when N=32, the number of PBAs in both the LUT fragment table and the VDM fragment table increases by 32 times when the level becomes one level higher.

[0202] If the LUT fragment table and VDM fragment table corresponding to the same level are compared as described above, the number of PBA managements in the VDM fragment table is greater than the number of managements in the LUT fragment table. Furthermore, when the number of PBA managements for LUT41 as a whole is the same as the number of PBA managements for VDM42 as a whole, the number of levels in the hierarchical structure of VDM42 in this embodiment is less than the number of levels in the hierarchical structure of LUT41.

[0203] Furthermore, when N=32 and M=32, the above conditional expression is satisfied when x=1 and y=1. In this conditional expression, x represents the difference in levels between the LUT fragment table and the VDM fragment table, and y represents the ratio of the PBA management count of the LUT fragment table to the PBA management count of the VDM fragment table (i.e., "PBA management count of VDM fragment table / PBA management count of LUT fragment table"). Specifically, considering the LUT fragment table corresponding to the second level with a level difference of 1 (i.e., x=1) and the VDM fragment table corresponding to the first level, the PBA management count of the LUT fragment table is 1,024, the PBA management count of the VDM fragment table is 1,024, and "PBA management count of VDM fragment table / PBA management count of LUT fragment table" is 1 (i.e., y=1).

[0204] Thus, if N and M satisfy the above conditions, for example, when data corresponding to the range of 1,024 LBAs allocated to the LUT segment table corresponding to the second level is written into the non-volatile memory 4, the LUT 41 can be updated by changing one entry (the PBA stored in the PBA storage unit 41a) included in the LUT segment table corresponding to the third level. Similarly, when data corresponding to the range of 1,024 LBAs is written into the 1,024 PBAs allocated to the VDM segment table corresponding to the first level, the VDM 42 can be updated by changing one entry (the magic number stored in the mapping storage unit 42a) included in the VDM segment table corresponding to the second level.

[0205] That is, when N=32 and M=32, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i (where i is an integer greater than or equal to 1) to the number of PBA managed by the VDM fragment table corresponding to level i-1 is 1:1. For example, if the continuity of LBA and PBA is ensured, the update of LUT41 can be handled by changing 1 entry of LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of VDM42.

[0206] In addition, Figure 8The example of N=32 and M=32 described above is one of the most effective ways to manage LUT41 (the correspondence between LBA and PBA) and VDM42 (data validity). However, even if N is changed, efficient management of LUT41 and VDM42 can be achieved as long as the above conditions are met.

[0207] The following explains the cases where N is changed, but for those cases not mentioned above... Figure 8 For parts that are the same as those described above, their detailed descriptions are omitted.

[0208] Figure 9 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of managed by the VDM fragment table, assuming N=8 and M=32.

[0209] Here, with N=8 and M=32, the PBA management count of the LUT fragment table corresponding to the first level is 8, and the PBA management count of the VDM fragment table corresponding to the first level is 256. Furthermore, the PBA management count of the LUT fragment table corresponding to the second level is 64, and the PBA management count of the VDM fragment table corresponding to the second level is 2,048.

[0210] Additionally, detailed explanations regarding the number of PBAs in the LUT fragment table and the VDM fragment table corresponding to a higher level than the second level are omitted. However, when N=8, the number of PBAs in both the LUT fragment table and the VDM fragment table increases by 8 times when the level becomes one level higher.

[0211] Furthermore, with N=8 and M=32, the above condition is satisfied when x=1 and y=4. Specifically, considering the LUT fragment table corresponding to the second level with a difference of 1 (i.e., x=1) and the VDM fragment table corresponding to the first level, the PBA management number of the LUT fragment table is 64, the PBA management number of the VDM fragment table is 256, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 4 (i.e., y=4).

[0212] Thus, if N and M satisfy the above conditions, for example, when data corresponding to the range of 256 LBAs allocated to the four LUT segment tables corresponding to the second level is written to the non-volatile memory 4, LUT41 can be updated by changing the four entries included in the LUT segment table corresponding to the third level. Similarly, when data corresponding to the range of 256 LBAs is written to the 256 PBAs allocated to the VDM segment table corresponding to the first level, VDM42 can be updated by changing one entry included in the VDM segment table corresponding to the second level.

[0213] That is, when N=8 and M=32, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-1 is 1:4. As long as the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 4 entries of the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of VDM42.

[0214] Furthermore, when N=8 and M=32, the above conditional expression is also satisfied when x=2 and y=1 / 2. Although detailed explanations are omitted, in this case, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-2 is 2:1. With the continuity of LBA and PBA ensured as described above, the update of LUT41 can be handled by changing 1 entry of the LUT fragment table, and the update of VDM42 can be handled by changing 2 entries of the VDM fragment table.

[0215] Figure 10 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, assuming N=16 and M=32.

[0216] Here, with N=16 and M=32, the PBA management count for the LUT fragment table corresponding to the first level is 16, and the PBA management count for the VDM fragment table corresponding to the first level is 512. Furthermore, the PBA management count for the LUT fragment table corresponding to the second level is 256, and the PBA management count for the VDM fragment table corresponding to the second level is 8,192.

[0217] Additionally, detailed explanations regarding the number of PBAs in the LUT fragment table and the VDM fragment table corresponding to a higher level than the second level are omitted. However, when N=16, the number of PBAs in both the LUT fragment table and the VDM fragment table becomes 16 times when the level becomes one level higher.

[0218] Furthermore, when N=16 and M=32, the above condition is satisfied when x=1 and y=2. Specifically, considering the LUT fragment table corresponding to the second level with a difference of 1 (i.e., x=1) and the VDM fragment table corresponding to the first level, the PBA management number of the LUT fragment table is 256, the PBA management number of the VDM fragment table is 512, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 2 (i.e., y=2).

[0219] Thus, if N and M satisfy the above conditions, for example, when data corresponding to the range of 512 LBAs allocated to the two LUT segment tables corresponding to the second level is written to the non-volatile memory 4, LUT41 can be updated by changing the two entries included in the LUT segment table corresponding to the third level. Similarly, when data corresponding to the range of 512 LBAs is written to the 512 PBAs allocated to the VDM segment table corresponding to the first level, VDM42 can be updated by changing the one entry included in the VDM segment table corresponding to the second level.

[0220] That is, when N=16 and M=32, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-1 is 1:2. As long as the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 2 entries of the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of the VDM fragment table.

[0221] Furthermore, when N=16 and M=32, the above conditional expression is also satisfied when x=2 and y=1 / 8. Detailed explanations are omitted, but in this case, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-2 is 8:1. As described above, with the continuity of LBA and PBA ensured, updates to LUT41 can be handled by changing one entry in the LUT fragment table, and updates to VDM42 can be handled by changing eight entries in the VDM fragment table.

[0222] Figure 11 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, assuming N=64 and M=32.

[0223] Here, with N=64 and M=32, the PBA management count of the LUT fragment table corresponding to the first level is 64, and the PBA management count of the VDM fragment table corresponding to the first level is 2,048. Furthermore, the PBA management count of the LUT fragment table corresponding to the second level is 4,096, and the PBA management count of the VDM fragment table corresponding to the second level is 131,072.

[0224] Additionally, detailed explanations regarding the number of PBAs in the LUT fragment table and the VDM fragment table corresponding to a higher level than the second level are omitted. However, when N=64, the number of PBAs in both the LUT fragment table and the VDM fragment table increases by 64 times when the level becomes one level higher.

[0225] Furthermore, when N=64 and M=32, the above condition is satisfied when x=0 and y=32. Specifically, considering the LUT fragment table corresponding to the first level where the difference between levels is 0 (i.e., x=0) and the VDM fragment table corresponding to the first level, the PBA management number of the LUT fragment table is 64, the PBA management number of the VDM fragment table is 2,048, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 32 (i.e., y=32).

[0226] Thus, if N and M satisfy the above conditions, for example, when data corresponding to the range of 2,048 LBAs allocated to the 32 LUT fragment tables corresponding to the first level is written to the non-volatile memory 4, LUT41 can be updated by changing the 32 entries included in the LUT fragment table corresponding to the second level. Similarly, when data corresponding to the range of 2,048 LBAs is written to the 2,048 PBAs allocated to the VDM fragment table corresponding to the first level, VDM42 can be updated by changing one entry included in the VDM fragment table corresponding to the second level.

[0227] That is, when N=64 and M=32, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i is 1:32. As described above, when the continuity of LBA and PBA is ensured, the update of LUT41 can be handled by changing 32 entries of the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of the VDM fragment table.

[0228] Furthermore, when N=64 and M=32, the above conditional expression is also satisfied when x=1 and y=1 / 2. Detailed explanations are omitted, but in this case, the ratio of the number of PBAs managed by the LUT fragment table corresponding to level i to the number of PBAs managed by the VDM fragment table corresponding to level i-1 is 2:1. With the continuity of LBAs and PBAs ensured as described above, updates to LUT41 can be handled by changing one entry in the LUT fragment table, and updates to VDM42 can be handled by changing two entries in the VDM fragment table.

[0229] Figure 12 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, assuming N=128 and M=32.

[0230] Here, with N=128 and M=32, the PBA management count for the LUT fragment table corresponding to the first level is 128, and the PBA management count for the VDM fragment table corresponding to the first level is 4,096. Furthermore, the PBA management count for the LUT fragment table corresponding to the second level is 16,384, and the PBA management count for the VDM fragment table corresponding to the second level is 524,288.

[0231] Additionally, detailed explanations regarding the number of PBAs in the LUT fragment table and the VDM fragment table corresponding to a higher level than the second level are omitted. However, when N=128, the number of PBAs in both the LUT fragment table and the VDM fragment table increases by 128 times when the level becomes one level higher.

[0232] Furthermore, when N = 128 and M = 32, the above condition is satisfied when x = 0 and y = 32. Specifically, considering the LUT fragment table corresponding to the first level where the difference between levels is 0 (i.e., x = 0) and the VDM fragment table corresponding to the first level, the PBA management number of the LUT fragment table is 128, the PBA management number of the VDM fragment table is 4,096, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 32 (i.e., y = 32).

[0233] Thus, if N and M satisfy the above conditions, for example, when data corresponding to the range of 4,096 LBAs allocated to the 32 LUT fragment tables corresponding to the first level is written to the non-volatile memory 4, LUT41 can be updated by changing the 32 entries included in the LUT fragment table corresponding to the second level. Similarly, when data corresponding to the range of 4,096 LBAs is written to the 4,096 PBAs allocated to the VDM fragment table corresponding to the first level, VDM42 can be updated by changing one entry included in the VDM fragment table corresponding to the second level.

[0234] That is, when N=128 and M=32, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i is 1:32. As described above, when the continuity of LBA and PBA is ensured, the update of LUT41 can be handled by changing 32 entries of the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of the VDM fragment table.

[0235] Furthermore, when N=128 and M=32, the above conditional expression is also satisfied when x=1 and y=1 / 4. Detailed explanations are omitted, but in this case, the ratio of the number of PBAs managed by the LUT fragment table corresponding to level i to the number of PBAs managed by the VDM fragment table corresponding to level i-1 is 4:1. With the continuity of LBAs and PBAs ensured as described above, updates to LUT41 can be handled by changing one entry in the LUT fragment table, and updates to VDM42 can be handled by changing four entries in the VDM fragment table.

[0236] In the above Figures 8-12 The case of M=32 was explained in the previous section. The following will refer to... Figures 13-17 The case where M=64 will be explained. Furthermore, aside from the change in M, it is similar to the above... Figures 8-12 The same applies, therefore, the explanation should be appropriately simplified. Figures 13-17 .

[0237] Figure 13 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table when N=64 and M=64.

[0238] When N=64 and M=64, the above condition is satisfied when x=1 and y=1. That is, when N=64 and M=64, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-1 is 1:1. With the continuity of LBA and PBA ensured as described above, the update of LUT41 can be handled by changing one entry of the LUT fragment table, and the update of VDM42 can be handled by changing one entry of VDM42.

[0239] In addition, as mentioned above Figure 8 As explained, when N=32 and M=32, updates to LUT41 can be handled by changing one entry in the LUT fragment table, and updates to VDM42 can be handled by changing one entry in VDM42. In other words, in this embodiment, it can be said that more efficient management of LUT41 and VDM42 can be achieved when N=M.

[0240] Figure 14 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, given N=8 and M=64.

[0241] When N=8 and M=64, the above condition is satisfied when x=2 and y=1. That is, when N=8 and M=64, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-2 is 1:1. With the continuity of LBA and PBA ensured as described above, the update of LUT41 can be handled by changing one entry of the LUT fragment table, and the update of VDM42 can be handled by changing one entry of VDM42.

[0242] Thus, even when N is not equal to M, there exists a situation where the update of VDM42 can also be performed using a single entry within the update of LUT41. Therefore, for example, even when M = N... ^ When x is established, more efficient management of LUT41 and VDM42 can also be achieved.

[0243] Figure 15 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, given N=16 and M=64.

[0244] When N=16 and M=32, the above condition is satisfied when x=1 and y=4. That is, when N=16 and M=64, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-1 is 1:4. As long as the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 4 entries in the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry in the VDM fragment table.

[0245] Furthermore, when N=16 and M=64, the above conditional expression is also satisfied when x=2 and y=1 / 4. In this case, the ratio of the number of PBAs managed by the LUT fragment table corresponding to level i to the number of PBAs managed by the VDM fragment table corresponding to level i-2 is 4:1. With the continuity of LBA and PBA ensured as described above, the update of LUT41 can be handled by changing 1 entry in the LUT fragment table, and the update of VDM42 can be handled by changing 4 entries in the VDM fragment table.

[0246] Figure 16 This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, given N=32 and M=64.

[0247] When N=32 and M=64, the above condition is satisfied when x=1 and y=2. That is, when N=32 and M=64, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i-1 is 1:2. As long as the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 2 entries in the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry in the VDM fragment table.

[0248] Furthermore, when N=32 and M=64, the above conditional expression is also satisfied when x=2 and y=1 / 16. In this case, the ratio of the number of PBAs managed by the LUT fragment table corresponding to level i to the number of PBAs managed by the VDM fragment table corresponding to level i-2 is 16:1. With the continuity of LBA and PBA ensured as described above, updates to LUT41 can be handled by changing 1 entry in the LUT fragment table, and updates to VDM42 can be handled by changing 16 entries in the VDM fragment table.

[0249] Figure 17This represents the relationship between the number of PBA managed by the LUT fragment table corresponding to each level and the number of PBA managed by the VDM fragment table, given N=128 and M=64.

[0250] When N=128 and M=64, the above condition is satisfied when x=0 and y=64. That is, when N=128 and M=64, the ratio of the number of PBA managed by the LUT fragment table corresponding to level i to the number of PBA managed by the VDM fragment table corresponding to level i is 1:64. As the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 64 entries in the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry in the VDM fragment table.

[0251] Furthermore, when N=128 and M=64, the above conditional expression is also satisfied when x=1 and y=1 / 2. In this case, the ratio of the number of PBAs managed by the LUT fragment table corresponding to level i to the number of PBAs managed by the VDM fragment table corresponding to level i-1 is 2:1. With the continuity of LBA and PBA ensured as described above, the update of LUT41 can be handled by changing 1 entry in the LUT fragment table, and the update of VDM42 can be handled by changing 2 entries in the VDM fragment table.

[0252] In this embodiment, the cases of M=32 and M=64 are described, but M can also be determined in a way that corresponds to the operation bit width (e.g., 32 bits or 64 bits) in the storage system 3.

[0253] Next, the operation of the storage system 3 in this embodiment will be explained. First, refer to... Figure 18 The flowchart illustrates an example of the processing sequence of the storage system 3 when a write command is sent from the host 2.

[0254] When a write command is sent from host 2 as described above, communication interface control unit 51 receives the write command (step S1). Furthermore, the write command received in step S1 includes data (hereinafter referred to as object data) to be written to non-volatile memory 4 based on the write command, and an LBA (hereinafter referred to as object LBA) for accessing the data. Additionally, the object data is temporarily stored in write buffer memory 52.

[0255] Next, the write control unit 561 writes the object data stored in the write buffer memory 52 to the non-volatile memory 4 via the non-volatile memory controller 54 (step S2). In the following description, for convenience, the PBA in the non-volatile memory 4 where the object data was written in step S2 will be referred to as the object PBA.

[0256] After performing step S2, the management unit 565, for example, in cooperation with the non-volatile memory controller 54 and the cache memory control unit 566, updates the VDM42 based on the object PBA (step S3). In step S3, the VDM42 is updated in a manner that manages the situation where the object data is valid (i.e., the data written to the object PBA is valid).

[0257] In this embodiment, VDM42 has a hierarchical structure, including multiple VDM fragment tables corresponding to each level. In this case, in step S3, one or more VDM fragment tables for which the object PBA has been allocated are determined by referring to VDM42, and the determined VDM fragment tables are read from non-volatile memory 4 as needed. The VDM fragment tables read from non-volatile memory 4 are then stored in cache memory 551 and updated on cache memory 551. Furthermore, if the VDM fragment tables determined as described above have already been stored in cache memory 551, it is not necessary to read the VDM fragment tables from non-volatile memory 4.

[0258] Next, the entries in the VDM segment table that have been determined in this way that have been allocated to objects PBA are modified. The VDM segment table with the modified entries is then read from cache memory 551 and written back to non-volatile memory 4.

[0259] In addition, the VDM fragment table of the modified entry can be either the VDM fragment table corresponding to the lowest level in the hierarchy as described above, or the VDM fragment table corresponding to a higher level.

[0260] Specifically, if the object PBA is a relatively narrow range of PBAs, and the object data written to the object PBA cannot be managed if the entries included in the VDM fragment table corresponding to the lowest level are not changed, then the entries included in the VDM fragment table corresponding to that lowest level are changed. In this case, the bit mapping flag information (flag information corresponding to the object PBA) stored in the entry (mapping storage unit 42a) in the entries included in the VDM fragment table corresponding to the lowest level that has been allocated the object PBA is changed. In addition, if the entire range of consecutive PBAs allocated to at least one entry included in the VDM fragment table corresponding to the lowest level is the object PBA, the magic number (management data MD2) stored in that entry is changed to "0xff".

[0261] On the other hand, if the object PBA is a relatively wide range of consecutive PBAs, and it is effective to manage the object data written to the object PBA by changing the entries included in the VDM fragment table corresponding to the level other than the lowest level, then it is sufficient to change only the entries included in the VDM fragment table corresponding to the level other than the lowest level. In this case, the magic number (management data MD3) stored in the entry (PBA storage unit 42f) of the VDM fragment table corresponding to the level other than the lowest level that has been allocated the object PBA is changed to "0xff".

[0262] Furthermore, if the entries included in the VDM fragment table corresponding to a level other than the lowest level are changed, the validity of the object data can be managed solely through this VDM fragment table, thus allowing the discarding of VDM fragment tables corresponding to levels lower than this VDM fragment table (i.e., VDM fragment tables represented by pointers stored in those entries).

[0263] On the other hand, if it is necessary to change the entries included in the VDM fragment table corresponding to the lowest level, and if the VDM fragment table does not exist (is discarded), a new VDM fragment table is created, including the entries that have been assigned to the object PBA.

[0264] In step S3, by performing this process, VDM42 stored in non-volatile memory 4 can be updated. Furthermore, the write-back of VDM42 to non-volatile memory 4 can be performed at any time after step S3.

[0265] After performing step S3, the management unit 565, for example, cooperates with the non-volatile memory controller 54 and the cache memory control unit 566 to update the LUT41 based on the write instruction (object LBA) and object PBA (step S4). In this step S4, the LUT41 is updated in a way that manages the correspondence between object LBA and object PBA (i.e., it can transform object LBA into object PBA).

[0266] In this embodiment, LUT41 has a hierarchical structure, including multiple LUT fragment tables corresponding to each level. In this case, in step S4, one or more LUT fragment tables that have been assigned object LBAs are determined by referring to LUT41, and the determined LUT fragment tables are read from non-volatile memory 4 as needed. Thus, the LUT fragment tables read from non-volatile memory 4 are stored in cache memory 551 and updated on cache memory 551. Furthermore, if the LUT fragment tables determined as described above are already stored in cache memory 551, it is not necessary to read the LUT fragment tables from non-volatile memory 4.

[0267] Next, the entries in the LUT fragment table that have been assigned an object LBA are modified. In this case, the PBA stored in the entry assigned an object LBA (PBA storage unit 41a) is changed to the object PBA. The LUT fragment table with the modified entries is read from the cache memory 551 and written back to the non-volatile memory 4.

[0268] In addition, the LUT fragment table of the modified entry can be either the LUT fragment table corresponding to the lowest level in the hierarchy as described above, or the LUT fragment table corresponding to a higher level.

[0269] Specifically, if the object LBA is a relatively narrow range of LBAs and the entries included in the LUT fragment table corresponding to the lowest level are not changed, then the correspondence between the object LBA and the object PBA cannot be managed, and the entries included in the LUT fragment table corresponding to the lowest level will be changed.

[0270] On the other hand, if the object LBA is, for example, a relatively wide range of consecutive LBAs, and the object data is written into consecutive PBAs, then if the correspondence between the object LBA and the object PBA can be managed by changing the entries included in the LUT fragment table corresponding to the level other than the lowest level, then only the entries included in the LUT fragment table corresponding to the level other than the lowest level need to be changed.

[0271] In step S4, by performing this process, the LUT41 stored in the non-volatile memory 4 can be updated. Furthermore, the write-back of the LUT41 to the non-volatile memory 4 can be performed at any time after step S4.

[0272] After the processing of step S4 is performed, the management unit 565 sends a response (completion response) to the host 2 via the communication interface control unit 51 for the write command received in step S1 (step S5).

[0273] Here, the case of updating LUT41 and VDM42 based on write commands from host 2 is explained, but the case of sending, for example, a Trim command from host 2 also requires updating LUT41 and VDM42.

[0274] The following is for reference Figure 19 The flowchart illustrates an example of the processing sequence of storage system 3 when a Trim command is sent from host 2.

[0275] The Trim command is used to invalidate data corresponding to a specified file in a file system used by host 2, for example, when that file is deleted. Depending on the interface standard used to connect storage devices, the Trim command is also known as, for example, the Unmap command. Furthermore, data written to non-volatile memory 4 via the Trim command is not erased; instead, it is erased through garbage collection.

[0276] When the aforementioned Trim command is sent from host 2, the communication interface control unit 51 receives the Trim command (step S11). Furthermore, the Trim command received in step S11 includes an LBA (range) for accessing data that should be invalidated. In the following description, the LBA included in the Trim command will be referred to as the object LBA.

[0277] After performing step S11, the address translation unit 564 sequentially refers to the LUT segment table included in LUT 41 from the higher level and transforms the object LBA into PBA (step S12). Thus, the address translation unit 564 obtains the PBA corresponding to the object LBA. In the following description, the PBA obtained by the address translation unit 564 will be referred to as the object PBA.

[0278] Next, the management unit 565 updates the VDM42 in a manner that the data stored in object PBA (i.e., the data corresponding to object LBA) is invalid (step S13). In addition to updating the VDM42 in a manner that the data is invalid, the update process of the VDM42 based on the Trim command also... Figure 18 The process shown in step S3 is the same, so its detailed description is omitted here.

[0279] Additionally, if the object PBA is a relatively wide range of consecutive PBAs, and the data written to the object PBA is invalid, the magic number stored in the entry of the VDM fragment table corresponding to the level other than the lowest level is changed to "0x00".

[0280] Additionally, if the entire range of a contiguous PBA is an object PBA, in the case that at least one entry in the VDM fragment table corresponding to the lowest level is assigned, the magic number stored in that entry is changed to "0x00".

[0281] Furthermore, the management unit 565 updates the LUT41 in a manner that invalidates the correspondence between object LBA and object PBA (the PBA storing data that should be invalidated) (step S14). When invalidating the correspondence between LBA and PBA in the LUT41, for example, a magic number is set for the entry (PBA storage unit 41a) included in the LUT fragment table that assigned the LBA. In addition to invalidating the correspondence between LBA and PBA, the LUT41 update process based on the Trim instruction also involves the following steps: Figure 18 Step S4 is the same as shown, so its detailed description is omitted here.

[0282] After updating LUT41 and VDM42 as described above, the management unit 565 sends a response (completion response) to the host 2 for the Trim command via the communication interface control unit 51 (step S15).

[0283] exist Figure 19 The example shown is illustrated by sending a completion response to host 2 after LUT41 and VDM42 are updated, but it is also possible to use a structure such as the update of VDM42 being performed after the completion response is sent (i.e., delayed execution).

[0284] Here, the aforementioned VDM42 is necessary for efficient garbage collection, but when performing garbage collection, it is necessary to refer to the VDM42 to confirm whether the data written in each PBA in the non-volatile memory 4 is valid or invalid.

[0285] The following is for reference Figure 20 The flowchart illustrates an example of the processing order of the storage system 3 when determining whether data written to a specific PBA (hereinafter referred to as object PBA) in the non-volatile memory 4 is valid or invalid.

[0286] First, in this embodiment, VDM42 has a hierarchical structure consisting of multiple levels, and memory 55 stores a VDM pointer (PBA storing the VDM fragment table) that represents the VDM fragment table corresponding to the topmost level among these multiple levels. Furthermore, if the VDM fragment table corresponding to the topmost level is stored in non-volatile memory 4, the VDM pointer stored in memory 55 is the PBA within non-volatile memory 4. Additionally, if the VDM fragment table corresponding to the topmost level is stored in cache memory 551, the VDM pointer stored in memory 55 is address information within cache memory 551.

[0287] In this case, the management unit 565 reads the VDM fragment table from the non-volatile memory 4 or the cache memory 551 based on the VDM pointer stored in the memory 55 (step S21).

[0288] Next, the management unit 565 refers to the magic number (hereinafter referred to as the object magic number) stored in the entry of the VDM fragment table (the VDM fragment table corresponding to the topmost level) that was read in step S1 and which was assigned the object PBA (step S22).

[0289] In addition, if the VDM fragment table read in step S21 is not the VDM fragment table corresponding to the lowest level, then the magic number (management data MD3) stored in the entries included in the VDM fragment table is set to one of the above-mentioned "0xff", "0x00", "0xfc" and "0xfd".

[0290] Management Unit 565 determines whether the magic number of the referenced object is "0xff" or "0x00" (step S23).

[0291] If the object magic number is determined to be neither "0xff" nor "0x00" (No in step S23), the management unit 565 determines whether the object magic number is "0xfc" or "0xfd" (step S24).

[0292] If the object magic number is determined to be "0xfc" or "0xfd" (as in step S24), the management unit 565 obtains the VDM pointer with the object magic number appended to it (step S25). If step S25 has been executed, the process returns to step S21 and repeats.

[0293] Here, the magic number "0xfc" indicates that the VDM pointer (PBA) with the magic number appended as described above is a PBA within non-volatile memory 4. Therefore, when the object magic number is "0xfc", in step S21 executed after step S25, the VDM segment table corresponding to the next level (lower level) is read from non-volatile memory 4 based on the VDM pointer obtained in step S24.

[0294] On the other hand, the magic number "0xfd" indicates that the VDM pointer (PBA) with the magic number appended as described above is address information within the cache memory 551. Therefore, when the object magic number is "0xfd", in step S21 executed after step S25, the VDM fragment table corresponding to the next level (lower level) is read from the cache memory 551 based on the VDM pointer obtained in step S24.

[0295] In this embodiment, by repeatedly performing steps S21 to S25, the VDM fragment tables corresponding to each level can be referenced sequentially.

[0296] On the other hand, assume that in step S23 the object magic number is determined to be "0xff" or "0x00" (that is, step S23).

[0297] Here, a magic number "0xff" indicates that all data written to the entire range of the PBA allocated to the entry storing that magic number is valid. That is, when the object's magic number is "0xff", it is possible to determine that the data stored in the object's PBA is valid. Figure 20 The processing shown is now complete.

[0298] Furthermore, a magic number "0x00" indicates that data written to the entire range of the PBA allocated to the entry storing that magic number is invalid. That is, when the object's magic number is "0x00", it is known that the data stored in the object's PBA is invalid. Figure 20 The processing shown is now complete.

[0299] Furthermore, if in step S24 it is determined that the object magic number is not "0xfc" or "0xfd" (No in step S24), then in the entries of the assigned object PBA, the magic numbers "0xff", "0x00", "0xfc", and "0xfd" are not set. In this case, it is known that the VDM fragment table read in step S21 is the VDM fragment table corresponding to the lowest level, and the validity of the data stored within the scope of the PBA, including the object PBA included in this VDM fragment table, is not common (i.e., valid data and invalid data are mixed). In this case, the management unit 565 obtains the bit mapping stored in the entries of the object PBA assigned to the VDM fragment table (the VDM fragment table corresponding to the lowest level) read in step S21 (step S26). The management unit 565 can determine whether the data is valid or invalid based on the flag information (i.e., the flag information corresponding to the object PBA) among the multiple flag information of the bit mapping obtained in step S26 that indicates the validity of the data stored in the object PBA.

[0300] As described above, in this embodiment, the VDM42 (data map) stored in the non-volatile memory 4 has a hierarchical structure consisting of at least a first level (the lowest level) and a second level (a level higher than the lowest level), including multiple first VDM fragment tables corresponding to the first level and second VDM fragment tables corresponding to the second level. Furthermore, in this embodiment, each of the multiple first VDM fragment tables manages the validity of data of a predetermined size (e.g., 4 KiB) written within the PBA (physical address) range allocated to that first VDM fragment table in the non-volatile memory 4. Additionally, in this embodiment, the second VDM fragment tables manage the VDM pointers (reference target information for referring to the first VDM fragment table) representing each first VDM fragment table according to each first VDM fragment table.

[0301] Here, in the case where VDM42' is configured to include only multiple VDM fragment tables T421' corresponding to a single level, as described in the comparative example of this embodiment above, it is necessary to store all the pointers (PBAs storing the VDM fragment table T421') representing each of the multiple VDM fragment tables T421' in memory 55 beforehand. In contrast, in this embodiment, with the above-described structure, only the VDM pointer representing the VDM fragment table corresponding to the highest level needs to be stored in memory 55. Therefore, the amount of data continuously occupying a certain storage area in memory 55 (as management information of VDM42, which is infinitely close to 0) can be reduced, and the validity of data written to the non-volatile memory 4 can be managed efficiently.

[0302] Furthermore, in this embodiment, as described above, by reducing the data stored in memory 55 (e.g., DRAM) (representing the VDM pointer of the VDM fragment table), LUT41 can be preferentially expanded on memory 55 (cached in cache memory 551), thus shortening the response time (I / O response time) to instructions from host 2. Moreover, when processing read instructions from host 2, VDM42 does not need to be updated, further reducing the I / O response time. Alternatively, the processing of updating VDM42 can be delayed when processing the aforementioned Trim instruction; however, even with such a structure, the memory area allocated to LUT41 and VDM42 (i.e., memory ratio) can be dynamically changed.

[0303] Furthermore, in the comparative example of this embodiment, the internal processing (startup processing and termination processing) for starting and ending the storage system 3 takes time, as described above. However, in this embodiment, as long as the VDM pointer representing the VDM fragment table corresponding to the highest level is expanded in the memory 55 during startup processing and the VDM pointer is made non-volatile during termination processing, the time required for internal processing can be shortened.

[0304] Furthermore, in this embodiment, when the validity of data of a predetermined size written to the PBA allocated to the first VDM fragment table is not common (i.e., valid data and invalid data are mixed together as data written to the PBA), the second VDM fragment table manages the VDM pointer representing the first VDM fragment table corresponding to the lower level. Conversely, when the validity of data of a predetermined size written to the PBA allocated to the first VDM fragment table is common (i.e., all data of a predetermined size written to the PBA is either valid or invalid), the second VDM fragment table manages the validity of the data simultaneously.

[0305] In this embodiment, with such a structure, for example, when updating the validity of data written in a continuous wide range of PBAs, the VDM42 can be updated simply by changing the entry (magic number) included in the second VDM segment table, thus simplifying the processing for managing data validity. Specifically, for example, in the case of a storage system 3 (non-volatile memory 4) capable of storing several PiBs of data, for example, the range of several G PBAs can be operated (updated) simultaneously by simply changing the magic number (8 bits) stored in one entry included in the VDM segment table corresponding to the highest level.

[0306] That is, in this embodiment, for example, bit operations such as individually updating the bit mappings included in the first VDM fragment table can be suppressed, thereby reducing processing costs.

[0307] Furthermore, in this embodiment, the range (granularity) of the PBA allocated to the VDM fragment table varies depending on the hierarchy, thus enabling flexible updates to the VDM42.

[0308] Furthermore, for example, in the second VDM fragment table, while managing the validity of data of a specified size written within the range of the PBA allocated to the first VDM fragment table, the first VDM fragment table can be discarded, freeing up the storage area storing the first VDM fragment table. Thus, in this embodiment, the storage area required to store the VDM42 can be reduced.

[0309] Furthermore, in this embodiment, the first VDM fragment table corresponding to the first level and the second VDM fragment table corresponding to the second level have the same data structure. Specifically, the first VDM fragment table manages the validity of multiple data of a specified size (4KiB) in each of a predetermined number (e.g., 32) of entries. Additionally, the second VDM fragment table manages the VDM pointers representing each of the first VDM fragment data in each of a predetermined number (e.g., 32) of entries.

[0310] In this embodiment, the hierarchical structure of VDM42 is simplified through this structure, reducing the computational cost when referencing VDM42 (each VDM fragment table). Furthermore, for example, referencing a VDM fragment table assigned an object PBA would require traversing multiple levels, but the processing in such cases can be smoothed out regardless of the level (i.e., the same software code can be used), thus enabling efficient referencing of VDM42.

[0311] Furthermore, the VDM42 in this embodiment only needs to have a hierarchical structure that includes at least a first level and a second level, but the number of levels constituting the hierarchical structure of the VDM42 can also be 3 or more. In addition, the number of levels constituting the hierarchical structure of the VDM42 can be appropriately changed, for example, based on the storage capacity of the non-volatile memory 4 (the number of PBAs).

[0312] Furthermore, in this embodiment, like VDM42, LUT41 (address translation table) also has a hierarchical structure, but the multiple LUT fragment tables included in LUT41 have the same data structure as the VDM fragment tables included in VDM42.

[0313] Based on this structure, even when traversing multiple levels for reference to LUT41, the same software code as VDM42 can be used, thus enabling efficient processing. Furthermore, for example, LUT41 (LUT fragment table) and VDM42 (VDM fragment table) updated on cache memory 551 need to be written back to non-volatile memory 4 (i.e., without non-volatility), but since the LUT fragment table and VDM fragment table are configured to be of the same size, they can be non-volatile together without distinguishing between them. Therefore, the write efficiency of the LUT fragment table and VDM fragment table to non-volatile memory 4 is improved, and non-volatility costs are reduced.

[0314] In addition, in this embodiment, the number of PBA managements of the LUT fragment table corresponding to the lowest level is less than the number of PBA managements of the VDM fragment table corresponding to that level. Therefore, the number of levels constituting the hierarchical structure of VDM42 (first number) is less than the number of levels constituting the hierarchical structure of LUT41 (second number).

[0315] Furthermore, in this embodiment, the above-mentioned condition (M = y × N) is satisfied. ^ The method of determining the number of entries N in the VDM fragment table and the number M of data of a specified size (i.e., the PBA managed in the entry) in one entry of the VDM fragment table corresponding to the lowest level, is configured such that the LUT fragment table and the VDM fragment table have the same data structure.

[0316] In this embodiment, with this structure, LUT41 can be updated simply by changing the entries (PBAs) in the LUT fragment table corresponding to the higher-level hierarchy, and VDM42 can be updated simply by changing the entries (magic numbers) in the VDM fragment table without changing the bit mapping (performing bit operations). Therefore, this embodiment can achieve both efficient management of the correspondence between LBAs and PBAs in LUT41 and efficient management of the validity of data in VDM42.

[0317] In addition, to achieve more efficient management in LUT41 and VDM42, the methods described above can be used. Figure 14 As explained in the text, N=8, M=64, satisfying the condition M=N ^ N and M such that x (i.e., M is a power of N) can also be expressed as follows: Figure 8 The description states that N=32, M=32, and... Figure 13 The N and M values ​​described herein satisfy the condition M = N (i.e., M is equal to N). Furthermore, the values ​​of N and M can be appropriately set or changed by the administrator of storage system 3, etc.

[0318] Here, for example, in C, the pointer size is the same as the operand width. In this case, if M is set to be less than the operand width, it is impossible to store the pointer (address information in cache memory 551) as is in the entry of the segment table. One approach is to store the pointer in segments, but this incurs high processing costs.

[0319] On the other hand, if M is larger than the bit width of the operands, the pointer can be stored as is in the entry of the fragment table, but this is inefficient due to the presence of unused bits (the cache is wasted). Furthermore, in this case, the cost of non-volatile conversion increases because the size of the fragment table becomes larger. One possible solution is to perform a process to remove unnecessary parts before making the fragment table non-volatile, but this is costly.

[0320] Therefore, in this embodiment, M can be determined, for example, in a manner corresponding to (e.g., consistent with) the bit width (32 bits or 64 bits) in the storage system 3. With this structure, pointers (address information in the cache memory 551) with the same bit width and size as the operations can be stored in the fragment table entries without processing them, thus enabling efficient management of LUT41 and VDM42. Furthermore, with this structure, it is not necessary to unnecessarily increase the size of the fragment table.

[0321] Furthermore, in this embodiment, the controller 5 included in the storage system 3 is described as functioning as a flash translation layer (FTL) configured to perform data management and block management of the non-volatile memory 4 (NAND flash memory). However, the function of this FTL can also be performed on the host 2 side connected to the storage system 3. In this configuration, the LUT 41 and VDM 42 described in this embodiment are managed by the host 2, and update processing of the LUT 41 and VDM 42 is performed on the host 2 side. In addition, in this configuration, there is a case where address translation from LBA to PBA is also performed on the host 2 side, and in this case, the instructions from the host 2 (e.g., read instructions) may also include the PBA.

[0322] Next, the control measures implemented by the storage system 3 of this embodiment, which has a VDM42 with the structure described above, i.e., data mapping, to reduce the processing cost of the data mapping will be explained.

[0323] As described above, the storage cell array of the non-volatile memory 4 comprises multiple blocks, each of which is composed of multiple pages. In the storage system 3 (SSD), each block functions as a unit for data erasure. Furthermore, each page is a unit for both data write and data read operations. The block size is, for example, an integer multiple of the size of the valid data that the management data MD3 of the second VDM segment table T422 can manage (here, 4kiB × 32 × 32 = 4MiB).

[0324] Here, regarding the method of cyclically utilizing each of multiple blocks, firstly, refer to... Figure 21The general approach will be used as a comparative example for explanation. Furthermore, this comparative example will be explained using the structure of the storage system 3 of this embodiment (write control unit 561, garbage collection control unit 563).

[0325] The blocks are roughly classified into blocks belonging to the free block group a1 (free block a11) and blocks belonging to the allocated block group a2 (block a21 being written and block a22 being written).

[0326] Free block a11 is a block that has not been written to. The write control unit 561 receives the free block a11 and writes the write data requested from the host 2 to the non-volatile memory 4. After the write data is written, the block is transferred from free block a11 to the writing block a21. That is, the writing block a21 is the block that the write control unit 561 targets for writing data.

[0327] While there are free pages in the write-in block a21, the write control unit 561 performs write data writing on that block. When all pages in the write-in block a21 have been written, the block is transferred from write-in block a21 to write-complete block a22. That is, write-complete block a22 is the block where the write of data based on the data from the write control unit 561 has been completed. When the write control unit 561 completes the write of data to a certain write-in block a21, it receives a new free block a11 and performs write data writing on it.

[0328] If the above process proceeds, the number of free blocks a11 decreases, while the number of written blocks a22 increases. Furthermore, in SSDs where data overwriting is not possible, the data stored in a certain page before the update is invalidated, and the updated data is written to another page, thus performing the data update. Therefore, in a written block a22, invalid data may occupy a large portion of the space.

[0329] The garbage collection control unit 563 moves the valid data in N written blocks a22 containing a large amount of invalid data to M (M < N) blocks, forming NM free blocks a11. That is, through garbage collection (GC) by the garbage collection control unit 563, a portion of the written blocks a22 are transferred to the free blocks a11.

[0330] In this way, each of the multiple blocks is used cyclically as: free block a11 → writing block a21 → writing completed block a22 → free block a11.

[0331] Here, refer to Figure 22The size of the data that confirms the validity of the data mapping (VDM42) flag information and various management data (MD2, MD3) management of the storage system 3 in this embodiment. Figure 22 In this context, symbol b1 indicates the size of the data for managing the validity of the flag information in the first VDM segment table T421. The flag information uses 1 bit to indicate the validity of data written to one PBA (in this case, 4kiB).

[0332] As described above, the first VDM segment table T421 has, for example, 32 entries. Each entry includes, for example, 32 flag information. Regarding these 32 flag information in each entry, a 32-bit bitmap is formed for each bit representing the validity of the 4kiB of data written to the 32 PBAs (4kiB × 32 = 128kiB of data).

[0333] Symbol b2 represents the size of the management data MD2 for managing validity in the first VDM segment table T421. Management data MD2 is set once in each entry of the first VDM segment table T421. Management data MD2 can be configured as a magic number that represents the validity of 128 kiB of data represented by a 32-bit bitmap formed by 32 flag information. That is, management data MD2 can represent the validity of 128 kiB of data at once.

[0334] Symbol b3 represents the size of the management data MD3 managing the validity of the data in the second VDM fragment table T422. One management data MD3 is provided for each of the first VDM fragment tables T421. The management data MD3 can be set as a magic number that represents the validity of 128 kiB × 32 = 4 MiB of data represented by the 32 management data MD2s of the first VDM fragment table T421 (the validity of data written in 1024 PBAs represented by 32 × 32 = 1024 flag information). That is, the management data MD3 can represent the validity of 4 MiB of data simultaneously.

[0335] In the storage system 3 of this embodiment, which has a data mapping (VDM42) including the aforementioned flag information and management data (MD2, MD3), when all the data written in one block is, for example, an integer multiple of the size (128 kB) of the data whose validity can be managed by the management data MD2, the operation (bit operation) of the flag information becomes unnecessary. Furthermore, for example, when it is an integer multiple of the size (4 miB) of the data whose validity can be managed by the management data MD3, the operation of the management data MD2 further becomes unnecessary.

[0336] In other words, when the data size is smaller than the size of the data whose validity can be managed by management data MD2 (128 kiB), or is an integer multiple of that size plus data smaller than that size (including data smaller than the last digit of that size), a flagging operation is required. Therefore, the data written by host 2 is preferably an integer multiple of the size of the data whose validity can be managed by management data MD2 (128 kiB), or an integer multiple of the size of the data whose validity can be managed by management data MD3 (4 MiB).

[0337] However, host 2, for example, with respect to the file system used by the operating system (OS) to manage files, directories, etc., generates extremely small data accesses, such as less than 4 kiB, at a high frequency for storage system 3. Furthermore, host 2 can, for example, change the unit of data access for storage system 3 based on the processing of applications operating under the control of the OS.

[0338] Assuming that after the write control unit 561 receives the supply of free block a11, it first writes data smaller than the size (128 kiB) of the data whose validity can be managed along with the management data MD2. In this case, even if data that is an integer multiple of the size (128 kiB) of the data whose validity can be managed along with the management data MD2 is subsequently sent as write data, for the write data written to the write block a21 (after being transferred from the aforementioned free block a11) immediately following the preceding data, the last part (the preceding and following tails) of this part also needs to be marked with flag information.

[0339] Based on this, the following will refer to Figure 23 An example of how to utilize a block in the storage system 3 of this embodiment will be described.

[0340] In the storage system 3 of this embodiment, the write control unit 561 also writes write data to the free block a11. Unlike the aforementioned comparative example, in this embodiment, the write control unit 561 ensures that multiple write targets in blocks a21 (e.g., first block a21-1, second block a21-2, third block a21-3) are written based on the size of the write data. More specifically, the write control unit 561 controls the writing of data so that data smaller than the size (128 kB) of the data that can be managed together with the management data MD2, or data that is an integer multiple of that size plus data smaller than that size, or data that is an integer multiple of that size (including data smaller than the last digit of that size), are not mixed in one block. In other words, the write control unit 561 aggregates data necessary for the operation of the flag information into blocks of the same type.

[0341] Furthermore, as explained in the aforementioned comparative example, each of the multiple blocks is cyclically utilized as: free block a11 → writing block a21 → writing completed block a22 → free block a11. Therefore, for example, if a block used for writing as the first block a21-1 is transferred to the writing completed block a22 → free block a11, the write control unit 561 can still be supplied even if the next block is not limited to the first block a21-1, but is instead one of the first block a21-1, the second block a21-2, or the third block a21-3. That is, each block is not pre-associated with one of the first block a21-1, the second block a21-2, or the third block a21-3.

[0342] Alternatively, each block can, for example, determine its multiple pages each time it transitions from a state belonging to the free block group a1 to a state belonging to the allocated block group a2. That is, the multiple pages of each block in the process of weaving multiple blocks can also be appropriately reorganized.

[0343] Figure 24 This is a diagram illustrating an example of selecting a target block for writing based on the write control unit 561 in this embodiment.

[0344] First, the write control unit 561 determines whether the size of the data to be written by the host 2 is an integer multiple of the size (128 kiB) of the data whose validity can be managed together with the management data MD2. If it is not an integer multiple of 128 kiB, the write control unit 561 selects the second block a21-2 as the write target of the data at that moment. That is, the second block a21-2 is the block that aggregates the necessary data for the operation of the flag information.

[0345] If the size is an integer multiple of 128 kiB, the write control unit 561 then determines whether the size of the data to be written by the host 2 is an integer multiple of the size (4 MiB) of the data whose validity can be managed together with the management data MD3. Furthermore, assuming that the data map (VDM42) has a hierarchical structure including a first VDM fragment table T421 (first level [lowest level]) and a second VDM fragment table T422 (second level [above level of the first level]), but in the case of a lack of hierarchical structure, such as only having a first VDM fragment table T421, the write control unit 561 may also select the first block a21-1 as the write target of the data when it determines that the size of the data to be written by the host 2 is an integer multiple of 128 kiB.

[0346] When the value is not a multiple of 4 MiB, the write control unit 561 selects the first block a21-1 as the write target for the data. The first block a21-1 does not require flag information operations, but is a necessary block for managing data MD2 operations. Conversely, when the value is a multiple of 4 MiB, the write control unit 561 selects the third block a21-3 as the write target for the data. The third block a21-3 does not require flag information or management data MD2 operations; it is a block for managing data MD3 operations only.

[0347] For example, when writing data to the first block a21-1, if the block is full, even if there is free space in the second block a21-2 or the third block a21-3, the write control unit 561 will not select them as the data writing targets. Instead, it will accept the supply of a new free block a11 and set it as the first block a21-1, and perform the writing of the remaining data.

[0348] In this way, by switching the target block for writing based on the size of the data being written by host 2, in the storage system 3 of this embodiment, for the first block a21-1 and the third block a21-3 other than the second block a21-2, operations on the flag information (bit operations) can be eliminated during data writing and data updating (when invalidating data before updating). Regarding the third block a21-3, operations on the management data MD2 can be further eliminated.

[0349] Furthermore, during garbage collection (GC), for blocks moved from the first block a21-1 (one of the blocks being written, a21) to the completed block a22, reference to the flag information (bit scan) becomes unnecessary when moving valid data within that block. For blocks moved from the third block a21-3 to the completed block a22, further reference to manage data MD2 also becomes unnecessary. Not only in the source block, but also in the target block, flag information operations are unnecessary; operations managing data MD2 and data MD3, or only data MD3, are sufficient.

[0350] Furthermore, during garbage collection (GC), when a block that has been moved from the first block a21-1 or the third block a21-3 to the write-complete block a22 is selected as an object, overhead reduction can also be expected. For example, when the page size is 16kiB, if only 4kiB of the 16kiB is valid, a useless 12kiB read occurs, resulting in a "16kiB read, 4kiB write". In the block that has been moved from the first block a21-1 or the third block a21-3 to the write-complete block a22, there may only be large data of 128kiB units or 4MiB units, so such waste is avoided. Moreover, it is possible to perform the reading of valid data and the writing of that valid data to the move target at the aggregate size of multiple pages.

[0351] Furthermore, when the data mapping (VDM42) has a hierarchical structure, address continuity is guaranteed by switching the write target block based on the size of the written data. This can, for example, improve the compression ratio of table compression and reduce the storage capacity secured on memory 55 for the data mapping. This reduction in storage capacity can also be used to improve the performance of storage system 3, or the capacity of memory 55 itself can be reduced.

[0352] Figure 25 It indicates a reference. Figure 18 This is a flowchart illustrating an example of the selection order of write target blocks corresponding to data size included in the data write operation of the storage system 3 of this embodiment. This step is... Figure 18 The steps executed by the control unit 561 are written in step S2.

[0353] The write control unit 561 determines whether the size of the data is an integer multiple of 128 kiB (the size of the data is such that the validity of the data MD2 can be managed together) (step S31). If it is not an integer multiple of 128 kiB (no in step S31), the write control unit 561 selects the second block a21-2 as the data write target (step S32).

[0354] If the data size is a multiple of 128 kB (Yes in step S31), the write control unit 561 then determines whether the data size is a multiple of 4 MiB (for managing the validity of the MD3 data) (step S33). If it is a multiple of 4 MiB (Yes in step S33), the write control unit 561 selects the third block a21-3 as the data write target (step S34). On the other hand, if the data size is not a multiple of 4 MiB (No in step S33), the write control unit 561 selects the first block a21-1 as the data write target (step S35).

[0355] As described above, the storage system 3 of this embodiment can reduce the processing cost of data mapping (VDM42) by switching the block to be written according to the size of the data.

[0356] Alternatively, as described above, host 2 can function as an FTL, managing LUT41 and VDM42, and performing update processing on LUT41 and VDM42 on the host 2 side. In this case, the selection of write target blocks to reduce the processing cost of data mapping can also be performed on the host 2 side. Furthermore, in this case, the number M of managed valid data (the PBA storing this data) in one entry of the first VDM fragment table T421 corresponding to the lowest level can also be determined in a manner corresponding to the bit width in host 2.

[0357] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system capable of connecting to a host, comprising: Including non-volatile memory in multiple blocks; and The controller, based on instructions from the host, controls the writing of data to or reading of data from the non-volatile memory. The controller uses data mapping to manage the validity of data written to the non-volatile memory. The data mapping includes multiple first fragment tables. Each of the multiple first fragment tables maintains first information and second information. The first information indicates the validity of data of a predetermined size, which is data written to a range of physical addresses within the non-volatile memory allocated to the first fragment table. The second information indicates the validity of the multiple data of the predetermined size in each predetermined number of entries. The controller selects the block to be written to based on the size of the data to be written, which is the size of the data to be written to the non-volatile memory requested by the host write instruction.

2. The storage system according to claim 1, wherein, The controller selects a first block as the target block for writing if the size of the written data is an integer multiple of the total amount of data whose validity is represented by the second information, and selects a second block as the target block for writing if the size is not an integer multiple.

3. The storage system according to claim 2, wherein, In each of the predetermined number of entries in the plurality of first fragment tables, a bitmap is formed, which is a bitmap that arranges the first information representing the validity of each of the plurality of data of the predetermined size whose validity is represented by the second information. The size of the bitmap corresponds to the width of the operational bits in the controller.

4. The storage system according to any one of claims 1 to 3, wherein, The data mapping has a hierarchical structure consisting of at least a first level corresponding to multiple first fragment tables and a second level above the first level, and also includes a second fragment table corresponding to the second level. The second fragment table maintains third and fourth information for each of the first fragment tables. The third information is information used to refer to the first fragment table, and the fourth information is information that indicates the validity of the data of the specified size, assuming that the validity of the data written to the range of the physical address allocated to the first fragment table is common. If the size of the written data is an integer multiple of the total amount of data whose validity is represented by the fourth information, the controller selects the third block as the block to be written.

5. An information processing system comprising a host computer and a storage system communicatively connected to the host computer. The storage system has a non-volatile memory comprising multiple blocks. The host uses data mapping to manage the validity of data written to the non-volatile memory. The data mapping includes multiple first fragment tables. Each of the multiple first fragment tables maintains first information and second information. The first information indicates the validity of data of a predetermined size, which is data written to a range of physical addresses within the non-volatile memory allocated to the first fragment table. The second information indicates the validity of the multiple data of the predetermined size in each predetermined number of entries. The host selects the block to be written to based on the size of the data to be written, which is the size of the data to be written to the non-volatile memory requested by the storage system.

6. The information processing system according to claim 5, wherein, The host selects a first block as the target block for writing if the size of the written data is an integer multiple of the total amount of data whose validity is represented by the second information; otherwise, it selects a second block as the target block for writing.

7. The information processing system according to claim 6, wherein, In each of the predetermined number of entries in the plurality of first fragment tables, a bitmap is formed, which is a bitmap that arranges the first information representing the validity of each of the plurality of data of the predetermined size whose validity is represented by the second information. The size of the bitmap corresponds to the operational bit width in the host.

8. The information processing system according to any one of claims 5 to 7, wherein, The data mapping has a hierarchical structure consisting of at least a first level corresponding to multiple first fragment tables and a second level above the first level, and also includes a second fragment table corresponding to the second level. The second fragment table maintains third and fourth information for each of the first fragment tables. The third information is information used to refer to the first fragment table, and the fourth information is information that indicates the validity of the data of the specified size, assuming that the validity of the data written to the range of the physical address allocated to the first fragment table is common. If the size of the data to be written is an integer multiple of the total amount of data whose validity is represented by the fourth information, the host selects the third block as the block to be written.

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