Data prefetching method and data prefetching device

Abstract

A data prefetch method and a data prefetch device are provided. The data prefetch method includes: receiving a first memory access instruction, the address corresponding to the first memory access instruction belongs to a first storage area of ​​the memory; determining prefetch data according to a historical memory access mode of the first storage area, the historical memory access mode is used to indicate the historical access data of the first storage area, and the prefetch data includes part or all of the historical access data; according to the prefetch data, sending a prefetch instruction to the memory controller, the prefetch instruction is used to store the prefetch data in a prefetch cache area. The embodiment of the present application stores part or all of the historical access data of the area to which the address corresponding to the memory access instruction belongs in advance in the cache area, so that the memory access instruction to be executed can obtain the data to be used from the cache area. This method can make the prefetched data cover the data required for the instruction to be executed as much as possible with the least number of operations, thereby helping to reduce the power consumption of the memory.

Description

Technical Field

[0001] The present application relates to the technical field of data prefetching, and in particular to a data prefetching method and a data prefetching device. Background Art

[0002] The rapid growth of modern processor speeds and the slowdown of memory speeds mean that processors spend significant time waiting for memory data to be returned. Data prefetching, pre-storing soon-to-be-used data in the cache, can mitigate this latency. Related technologies, which increase prefetch coverage by issuing a large number of prefetches, may negatively impact memory power consumption. Summary of the Invention

[0003] The present application provides a data pre-fetching method and a data pre-fetching device. The following introduces various aspects involved in the embodiments of the present application.

[0004] In a first aspect, a data prefetching method is provided, comprising: receiving a first memory access instruction, wherein an address corresponding to the first memory access instruction belongs to a first storage area of ​​a memory; determining prefetched data based on a historical memory access pattern of the first storage area, wherein the historical memory access pattern is used to indicate historical access data of the first storage area, and the prefetched data includes part or all of the historical access data; and sending a prefetch instruction to a memory controller based on the prefetched data, wherein the prefetch instruction is used to store the prefetched data in a prefetch cache area.

[0005] In a second aspect, a data prefetch device is provided, including: a prefetch cache area for storing prefetched data; a processor for performing the following operations: receiving a first memory access instruction, the address corresponding to the first memory access instruction belongs to a first storage area of ​​the memory; determining prefetched data based on a historical memory access pattern of the first storage area, the historical memory access pattern being used to indicate historical access data of the first storage area, the prefetched data including part or all of the historical access data; sending a prefetch instruction to a memory controller based on the prefetched data, the prefetch instruction being used to store the prefetched data in the prefetch cache area.

[0006] The embodiment of the present application pre-stores part or all of the historical access data of the area to which the address corresponding to the memory access instruction belongs in the cache area according to the historical memory access pattern of the area to which the address corresponds to the memory access instruction belongs. This can ensure that the pre-fetched data covers the data required for the instruction to be executed as much as possible with the least number of operations, thereby ensuring the accuracy and coverage of data pre-fetching, and thus helping to reduce the power consumption of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 The figure is a flow chart of the data pre-fetching method provided in an embodiment of the present application.

[0008] Figure 2 Shown is a structural diagram of a data pre-fetching device provided by an embodiment of the present application.

[0009] Figure 3 Shown is a structural diagram of a data pre-fetching device provided in yet another embodiment of the present application.

[0010] Figure 4 FIG. 3 is a schematic diagram of a working process of the data pre-fetching device 300 .

[0011] Figure 5 Shown is a schematic diagram of a data prefetching system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0013] During operation, a processor typically needs to access or store data or instructions in memory to perform its functions. A memory controller acts as a bridge between the processor and memory. For example, the memory controller can perform read and / or write operations based on memory access instructions (memory access instructions) sent by the processor.

[0014] The rapid growth of modern processor speeds and the slowdown of memory speeds mean that processors spend significant time waiting for memory data to be returned, causing processor stalls or operational delays. Data prefetching technology can pre-store future memory access data in a prefetch cache, preventing cache invalidation when the data is actually needed, thereby eliminating processor delays caused by data access delays.

[0015] The principle behind data prefetching is that program execution exhibits locality. For example, locality can include temporal locality and spatial locality. Temporal locality means that the data to be used soon may be the same data currently being used. Temporal locality can be used to store currently accessed data in a cache for future use. Examples include for and while loops and recursive calls in C++. Spatial locality means that the data to be used soon may be adjacent or close to the data currently being used in the address space.

[0016] Based on temporal and spatial locality, data prefetching techniques typically store currently used data and nearby data in a cache for subsequent memory access instructions. Related technologies issue a large number of prefetch operations to ensure that the prefetched data covers more data available for subsequent memory access instructions.

[0017] Excessive prefetching reduces data prefetch accuracy. This means that more prefetched data may not be needed for subsequent memory accesses. This approach improves data prefetch coverage at the expense of accuracy. However, excessive prefetch errors can negatively impact memory power consumption.

[0018] In power-sensitive scenarios, data prefetching power consumption is crucial. For example, mobile devices are particularly sensitive to this. This article will use mobile devices as an example to explain data prefetching power consumption.

[0019] With the widespread adoption of mobile platforms, the power consumption of mobile devices has become a focus of attention. Due to the slow development of battery technology, low-power design has become an effective way to improve the battery life of mobile devices.

[0020] In mobile devices, memory power consumption accounts for a significant portion of overall power consumption, so optimizing memory power consumption can effectively reduce the overall power consumption of the mobile phone's on-chip processor. Prefetch strategies in related technologies can achieve higher coverage by issuing a large number of prefetches. However, excessive prefetch errors can increase DMC bandwidth, increase the number of row activations per unit time, and reduce the DMC idle rate, potentially leading to a significant increase in power consumption.

[0021] It can be seen that improving the accuracy of data prefetching helps reduce the negative impact of data prefetching on power consumption. In some embodiments, by obtaining the instruction address, the content of the instruction to be executed can be obtained, thereby locating the data to be accessed, so as to achieve high-precision data prefetching. For example, in the last level of cache, the instruction address of the memory access instruction can be obtained, so as to distinguish accesses to the same address from different instructions. However, devices that access memory include central processing units (CPUs), graphics processing units (GPUs), and other devices, and it is difficult for some devices to obtain instruction addresses.

[0022] To solve the above problems, an embodiment of the present application provides a data prefetching method. Based on the historical memory access pattern of the area to which the address corresponding to the memory access instruction belongs, part or all of the historical access data of the area to which it belongs is pre-stored in a cache area so that the memory access instruction to be executed can quickly obtain the data to be used from the cache area. This method can, in the absence of an instruction address, make the prefetched data cover the data required by the instruction to be executed as much as possible with the minimum number of operations, thereby ensuring the accuracy and coverage of data prefetching, thereby helping to reduce the power consumption of the memory.

[0023] Figure 1 The data pre-fetching method 100 includes steps S110, S120, and S130.

[0024] In step S110 , a first memory access instruction is received, where an address corresponding to the first memory access instruction belongs to a first storage area of ​​the memory.

[0025] The first memory access instruction may be sent by a device that accesses the memory. For example, the device that accesses the memory may be a CPU, a GPU, etc.

[0026] The first memory access instruction can be used to write data or instructions into the memory, or can be used to access data or instructions in the memory. As an implementation, during the memory access process, the first memory access instruction can be used to indicate the location of the data or instruction to be accessed. For example, the first memory access instruction can include the address or address range of the data to be accessed and the access type. As an example, the first memory access instruction can include a read enable instruction and the address of the data to be read.

[0027] The address corresponding to the first memory access instruction belongs to the first storage area of ​​the memory. In other words, the location to be accessed by the first memory access instruction belongs to the first storage area. The address corresponding to the first memory access instruction in the memory can be a target address included in the first memory access instruction, or can be a target address mapped by the first memory access instruction.

[0028] The first storage area is a storage area in the memory. For example, the first storage area can be a storage area of ​​any size in the memory. As an example, the first storage area can be a memory page in the memory. As another example, a memory page in the memory can include multiple memory blocks, and the first storage area can be a memory block in the multiple memory blocks. As yet another example, the first storage area can be one or more memory rows in the memory page.

[0029] During data prefetching, there are multiple methods for locating the first storage area. As one implementation, the first storage area can be located using an index. For example, when the first storage area is a page in a memory, the memory page number can be used as the index of the first storage area.

[0030] In step S120 , pre-fetched data is determined according to a historical memory access pattern of the first storage area. The historical memory access pattern is used to indicate historical access data of the first storage area. The pre-fetched data includes part or all of the historical access data.

[0031] The historical access pattern of the first storage area can be used to indicate historical access data of the first storage area. As an implementation, the historical access pattern of the first storage area can indicate the historical access data of the first storage area via a historical access address. In some cases, the specific value stored in the historical access address may be modified or updated, but the historical access address generally does not change. The historical access data may also be the modified or updated value stored in the historical access address.

[0032] For example, consider historically accessed data a. In the a++ operation, the value of a is incremented by 1 each time the program is executed. The updated value of a is typically stored at the same address, overwriting the original value of a. Therefore, historically accessed data a can be indicated by its storage address.

[0033] The historical access data can include all data accessed in the first storage area, or data accessed by an application in the first storage area. The historical access data can also include data accessed in the first storage area within a historical time window. As an implementation, a historical time window can be divided according to the number of accesses. For example, every 3,000 accesses constitutes a historical time window.

[0034] Accordingly, the historical memory access pattern may consist of memory access behaviors for the first storage area, memory access behaviors for the first storage area by an application, or memory access behaviors for the first storage area within a historical time window.

[0035] Different applications or programs can access data in the first storage area, but the data accessed by different applications or programs in the first storage area may not be exactly the same. Therefore, the historical memory access pattern can also include multiple patterns. For example, the multiple patterns can be the access behaviors of multiple applications to the first storage area. Each pattern can indicate the behavior of an application accessing the first storage area. In other words, the historical access data can include multiple groups, each group of data being the historical data of an application accessing the first storage area.

[0036] The pre-fetched data may be determined based on the historical memory access pattern of the first storage area, that is, based on the historical memory access behavior of the first storage area. As an implementation, the pre-fetched data may be determined based on the historical access data of the first storage area.

[0037] In order to make the pre-fetched data cover all the data to be used as much as possible, that is, to improve the coverage rate of the pre-fetched data, the pre-fetched data can be all the data in the historical access data. However, when the historical access data includes a large amount of data, the pre-fetched data can be part of the data in the historical access data. For example, the pre-fetched data can be a certain amount of data adjacent to the currently accessed data in the historical access data. As an example, the pre-fetched data can be the historical access data contained in the row where the currently accessed data is located and the data in the two adjacent rows. As another example, the amount of pre-fetched data can be determined by the size of the cache area used to store the pre-fetched data and the power consumption requirements. Among them, the larger the amount of pre-fetched data, the greater the power consumption consumed by the pre-fetch operation may be. For another example, the pre-fetched data can be all the historical data of the application corresponding to the currently accessed data in the historical access data.

[0038] In step S130 , a prefetch instruction is sent to the memory controller according to the prefetch data, where the prefetch instruction is used to store the prefetch data in a prefetch buffer.

[0039] A prefetch instruction is generated based on the address corresponding to the prefetched data. As an implementation method, the prefetch instruction may include the address corresponding to the prefetched data and a read enable command. The prefetch instruction is sent to the memory controller, and the prefetched data can be read from the memory.

[0040] The pre-fetch buffer area can be used to store pre-fetched data read from the memory. The pre-fetch buffer area can be a part of the existing buffer area or a newly added dedicated buffer area.

[0041] Based on the historical memory access patterns of the region corresponding to the address of the memory access instruction, some or all of the historically accessed data in that region is pre-stored in a cache, allowing the memory access instruction to be executed to quickly retrieve the data to be used from the cache. This method can ensure that the pre-fetched data covers the data required by the instruction to be executed as much as possible with the minimum number of operations, even without the instruction address, ensuring the accuracy and coverage of data pre-fetching, thereby helping to reduce memory power consumption.

[0042] Additional data prefetching operations will bring a burden on power consumption. Therefore, data prefetching operations can be reduced as much as possible while ensuring data coverage. As an implementation method, prefetching data can be determined based on historical memory access patterns and current memory access patterns.

[0043] The current memory access mode can be the memory access mode of the currently executed instruction for the first storage area, or it can be the memory access mode for the first storage area within a certain time or a certain number of accesses from the current moment forward. The certain time and the certain number of accesses can be determined based on the actual usage scenario. For example, the certain number of accesses can be 3000 times. The current memory access mode can also be the memory access mode for the first storage area within the time window of the current moment.

[0044] The current memory access mode is used to indicate the current access data of the first storage area. The current access data may be the data accessed in the first storage area in the current memory access mode. The current access data may be completely different from the historical access data. For example, the historical access data and the current access data correspond to different programs, and the data accessed by the processor in the process of running different programs is also different. The current access data may also be part or all of the historical access data. For example, when the processor executes the same program again, if the current moment is the moment when the execution of the program ends, the current access data may be the same as the historical access data corresponding to the last time the processor executed the program. If the current moment is during the execution of the program, the current access data may be part of the historical access data corresponding to the last time the processor executed the program. For another example, when the processor executes different programs, some of the data accessed are the same.

[0045] As described above, the prefetched data may be part or all of the historical access data. Considering that some of the prefetched data determined by the method described above may be the same as the data corresponding to the current memory access mode, the current access data is removed from the prefetched data determined by the method described above to serve as the final prefetched data. In other words, the prefetched data is part or all of the historical access data excluding the current access data.

[0046] Throughout its lifecycle, the programs running on the processor may be updated or modified, and new programs may be added. The processor's memory access behavior within the first storage area may also change accordingly. Therefore, it is necessary to update the historical memory access pattern to improve the coverage of data prefetching. As an implementation method, the historical memory access pattern of the first storage area can be updated based on the current memory access pattern of the first storage area.

[0047] In some embodiments, the historical memory access pattern may include a historical pattern and a historical candidate pattern. According to the current memory access pattern, the historical pattern and the historical candidate pattern, an updated historical pattern and the historical candidate pattern may be determined based on a scoring rule.

[0048] The updated historical pattern can be obtained through the following steps. First, the union of the current memory access pattern and the historical candidate pattern and the union of the current memory access pattern and the historical pattern can be obtained. For example, the union of the current memory access pattern and the historical candidate pattern can be the union of the addresses included in the current memory access pattern and the addresses included in the historical candidate pattern. In other words, the union of the current memory access pattern and the historical candidate pattern includes both the data indicated by the current memory access pattern and the data indicated by the historical candidate pattern.

[0049] Secondly, the above two unions can be scored according to the scoring rules. The scoring results can be associated with the coverage and accuracy of the memory access pattern to be evaluated for the actual memory access behavior. As an implementation method, the memory access behavior included in the current memory access pattern can be used as the actual memory access behavior, and the above two unions can be scored to evaluate the coverage and accuracy of the new memory access pattern for the actual memory access. As an example, the memory access pattern that completely covers the actual memory access has the highest score. As another example, the memory access pattern can be scored according to the accuracy, and the higher the accuracy, the higher the score. As yet another example, the memory access pattern can be scored according to the number of accesses covered by the memory access pattern, and the more accesses covered, the higher the score.

[0050] Finally, the union with the highest score among the above unions can be used as the updated historical pattern. Since all of the above unions can include the current memory access pattern, they can completely cover the actual memory access behavior. When all memory access behaviors are completely covered, the fewer prefetch operations, the higher the accuracy. In other words, in one implementation, the smaller set in the above union has the higher score, and this set can be used as the updated historical pattern.

[0051] The updated historical candidate pattern can be obtained through the following steps. First, the intersection of the current memory access pattern and the historical candidate pattern and the intersection of the current memory access pattern and the historical pattern can be obtained. For example, the intersection of the current memory access pattern and the historical candidate pattern can be the intersection of the address included in the current memory access pattern and the address included in the historical candidate pattern. In other words, the intersection includes the common data in the data indicated by the current memory access pattern and the historical candidate pattern.

[0052] Next, the two intersections can be scored according to a scoring rule. The scoring result can be associated with the coverage and accuracy of the memory access pattern to be evaluated for the actual memory access behavior. As an implementation method, the scoring rule can be the same as the scoring rule described above.

[0053] Finally, the intersection with the highest score in the above intersections can be used as the updated historical candidate pattern. Because the data indicated by the above intersection can be common data among the data indicated by multiple patterns, the data in the above intersection, when used as prefetched data, has a higher probability of hitting the data to be accessed, that is, a higher accuracy rate. In this case, the larger set in the above intersection has a higher coverage rate. That is, in one implementation, the larger set in the above intersection has a higher score, and this set can be used as the updated historical candidate pattern.

[0054] The embodiments provided in this application can not only determine pre-fetched data based on historical memory access patterns, but also learn memory access behaviors and generate historical memory access patterns. As an implementation method, memory access behaviors can be learned by combining the use of a filter table, an aggregation table, and a historical pattern table. The following text introduces the learning process of memory access patterns by taking the index of the filter table, the aggregation table, and the historical pattern table as the page number of the memory page as an example.

[0055] In some cases, memory access behavior may include some random, scattered accesses. It is difficult to learn the memory access patterns of these memory access behaviors, and learning them will increase overhead. As an implementation method, a filter table can be used to filter out scattered, random, and difficult-to-learn memory access behaviors. For example, when the access to the first storage area is less than a first threshold, the memory access behavior is recorded in the filter table. As an example, the first threshold can refer to the number of accesses to the first storage area, or it can refer to the number of accesses to different locations in the first storage area.

[0056] Before recording the memory access behavior in the filter table, you can first query the filter table to see whether there is any memory access behavior for the first storage area. In other words, query whether the memory access behavior for the first storage area has occurred recently. For example, the memory page number can be obtained through the address corresponding to the memory access instruction, and the table entry in the filter table can be queried based on the page number to obtain whether there is a record of the memory access behavior of the page. If there is a table entry corresponding to the page in the filter table, the table entry corresponding to the page can be updated according to the current memory access behavior. If there is no table entry corresponding to the page in the filter table, a new item can be allocated in the filter table to record the current memory access behavior.

[0057] In order to ensure that the filter table can fully record effective memory access behaviors, the table entries of the filter table can be managed. For example, when the time interval between the last access to a certain table entry and the current access exceeds the preset time, the table entry is reset to record the new memory access behavior. In other words, the memory access behavior corresponding to the table entry is a random, scattered access, and the content in the table entry can be discarded. As an example, the preset time can be the time of 3000 accesses. For another example, when the filter table is full and a new memory access mode needs to be recorded, the table entry in the filter table can be replaced with the new memory access mode. As an example, the replacement rule of the table entry in the filter table can adopt the SRRIP policy. The SRRIP policy can replace the table entry according to the access frequency.

[0058] Because each entry in the filter table has a corresponding overhead, controlling the number of entries in the filter table can reduce overhead. As an implementation, the filter table can be a 128-entry lookup table. As an example, the structure of each entry in the filter table can be shown in Table 1. Each entry has an overhead of 7.875 KB, requiring a total of 0.98 KB. For example, using a four-channel dynamic random access memory, the total overhead of the filter table is 3.93 KB.

[0059] Table 1 Filter table entry structure

[0060] valid tag offsets wrFlag POS last Access may reuse rrpv 1 (mid(3bit)+pn(20bit))23bit 18 1 2 16 1 2

[0061] See Table 1, where valid is a valid bit. For example, when valid is 1, it indicates that the content of the table entry is valid. When valid is 0, it indicates that the content of the table entry is invalid and can be used to store new table entries. tag can represent the page number, that is, the index of the table entry. offsets can be used to record the offset of the address corresponding to the access behavior in the memory page. For example, the first threshold can be the value for offsets. wrFlag can be a flag bit for write memory access behavior. pos and lastAccess can be associated with the position corresponding to the last memory access behavior. may reuse and rrpv can reflect the frequency of the table entry being called or the probability of being accessed again. Among them, rrpv can be a flag bit for the SRRIP replacement strategy.

[0062] When the access associated with a certain item in the filter table exceeds a first threshold, the content of the item can be moved into the aggregation table. In other words, the access associated with the certain item may be non-random and non-scattered.

[0063] The aggregation table can be used to observe memory access behavior over a period of time. As an implementation method, upon receiving a memory access instruction, a match can be first performed in the aggregation table. If the aggregation table includes an entry associated with the memory access instruction—that is, if the aggregation table includes an entry for the memory page corresponding to the address of the memory access instruction—then the entry can be updated based on the memory access instruction. If the aggregation table does not include an entry associated with the memory access instruction, the memory access instruction can be forwarded to the filter table.

[0064] For ease of use, the entries in the aggregation table are usually managed. For example, the SRRIP replacement algorithm can be used to manage the aggregation table in the same way as cache.

[0065] In some embodiments, the structure of each item in the aggregation table may be as shown in Table 2.

[0066] Table 2: Item structure of the aggregation table

[0067]

[0068] See Table 2, where valid is a valid bit. For example, when valid is 1, it indicates that the content of the table entry is valid. When valid is 0, it indicates that the content of the table entry is invalid and can be used to store new table entries. tag can represent the page number, that is, the index of the table entry. wrFlag can be a flag bit for write memory access behavior. last Access can be the data location corresponding to the last memory access behavior. may reuse and rrpv can reflect the frequency of the table entry being called or the probability of being accessed again. Among them, rrpv can be a flag bit for the SRRIP replacement strategy.

[0069] Pattern can be used to indicate the data accessed in the current pattern. As an implementation, a bitmap can be used to indicate the accessed data. For example, if a page in memory is divided into 16 data blocks, 16-bit binary data can be used to sequentially represent the memory access status of the 16 data blocks. As an example, when the fourth bit in the binary data of 16 is 1, it can indicate that the data in the fourth data block in the memory page is accessed. When the sixth bit in the binary data of 16 is 0, it can indicate that the data in the sixth data block in the memory page is not accessed.

[0070] The historical pattern table can be used to store learned memory access patterns. In response to the number of accesses between the current access and the last access to the first storage area in the aggregate table being greater than a second threshold, the memory access pattern in the aggregate table is moved to the historical pattern table. In other words, the entries in the aggregate table that meet the above conditions can be considered to have been learned at this stage.

[0071] The historical pattern table can also be used to confirm prefetched data. As an implementation, upon receiving a memory access instruction, the historical pattern table can be searched for a matching entry. If a matching entry exists in the historical pattern table, the historical access data for the page can be determined based on the access pattern of that entry.

[0072] Prefetched data can be determined based on historical access data. For example, all historical access data can be used as prefetched data. For another example, there are also table entries in the aggregation table that match the memory access instruction, and the prefetched data can be data in the historical access data other than the currently accessed data indicated by the table entry in the aggregation table. Taking the memory page divided into multiple data blocks as mentioned above as an example, the prefetched data includes data blocks in the historical access data blocks other than the currently accessed data blocks. As an example, the address of the prefetched data block can be determined based on the address range of each data block when the memory page is divided into data blocks.

[0073] In some embodiments, the structure of each item in the history pattern table may be as shown in Table 3.

[0074] Table 3 History mode entry structure

[0075]

[0076] Refer to Table 3. The historical pattern table contains two memory access modes: historical pattern and historical candidate pattern. Among them, tag can represent the page number, that is, the index of the table entry. wrFlags can be the flag bit of the write memory access behavior. Read counts can be the number of reads. wrType can be the write type of the write behavior in the memory access behavior. May reuse can reflect the probability that the table entry will be accessed again. High score high can be used to mark the updated historical pattern, and scorecandidate can be used to mark the updated historical candidate pattern. Pattern can be used to indicate the data accessed in the historical pattern. Pattern candidate can be used to indicate the data accessed in the historical candidate pattern.

[0077] For ease of understanding, the following text combines the flow process of memory access instructions to provide a complete and coherent introduction to a data prefetching method provided in an embodiment of the present application from the two perspectives of data prefetching and learning memory access mode.

[0078] This is introduced from the perspective of data prefetching. When the processor needs to access data in the memory during operation, a corresponding memory access instruction can be generated. Based on the memory access instruction, the prefetch buffer (which stores data prefetched before the current memory access instruction) can be queried to see if there is any data to be used. If there is data to be used in the prefetch buffer, the data can be returned to the processor. If there is no data to be used in the prefetch buffer, the memory access instruction can be forwarded to the memory controller to read the data to be used from the memory.

[0079] At the same time, the entries in the historical pattern table and the aggregation table can be queried based on the memory access instruction to pre-fetch data for subsequent instructions. For example, if there is an entry corresponding to the memory access instruction in the historical pattern table, the pre-fetched data can be determined based on the historical access data indicated in the entry. For another example, if there is an entry corresponding to the memory access instruction in the historical pattern table and there is also a corresponding entry in the aggregation table, the pre-fetched data can be determined based on the historical access data indicated by the entry in the historical pattern table and the current access data indicated by the entry in the aggregation table. As an example, the pre-fetched data can be other data in the historical access data except the current access data.

[0080] Finally, a prefetch instruction corresponding to the prefetched data may be sent to the memory controller to store the prefetched data in the prefetch buffer.

[0081] This article will introduce the memory access mode from a learning perspective. The aggregation table receives memory access instructions and, based on the address corresponding to the memory access instruction, determines whether the aggregation table includes a memory access record for the page where the memory access instruction's target address is located. If the aggregation table contains an entry corresponding to the memory access record for the page where the memory access instruction's target address is located, the entry can be updated based on the memory access instruction. If the aggregation table does not contain an entry corresponding to the memory access record for the page where the memory access instruction's target address is located, the memory access instruction can be forwarded to the filter table.

[0082] After receiving a memory access instruction, the filter table determines whether a corresponding entry exists in the filter table. If an entry corresponding to the memory access instruction exists in the filter table, the entry can be updated based on the memory access instruction. If an entry corresponding to the memory access instruction does not exist in the filter table, a new entry can be created to store the memory access behavior corresponding to the memory access instruction.

[0083] The table item management and flow methods of the aggregation table and filter table are as follows.

[0084] When the number of accesses between the last access and the current access interval for an entry in the aggregate table exceeds a second threshold, the learning of the access behavior of the memory page corresponding to the entry is considered complete, and the entry can be moved to the historical pattern table. Additionally, when the aggregate table is full and there is no place to store the newly generated memory access pattern, the entry in the aggregate table with the largest number of accesses between the last access and the current access interval can be moved to the historical pattern table based on access frequency, and the newly generated memory access pattern can be stored in the aggregate table.

[0085] When the number of accesses to the memory page corresponding to a table entry in the filter table exceeds a first threshold, the table entry can be moved to the aggregation table. When the interval between the last access and the current access of a table entry in the filter table exceeds a certain number of accesses, the content of the table entry is discarded. When the table entries in the filter table are full and there is no place to store the newly generated memory access pattern, the table entry in the filter table with the largest number of accesses between the last access and the current access can be deleted according to the access frequency, and the newly generated memory access pattern can be stored in the filter table at the same time.

[0086] When an entry in the aggregate table is moved to the historical pattern table, a determination is made as to whether there is an entry in the historical pattern table corresponding to the same memory page as the entry in the aggregate table. If there is no entry in the historical pattern table corresponding to the same memory page as the entry in the aggregate table, a new entry can be created in the historical pattern table to store the entry in the aggregate table. If there is an entry in the historical pattern table corresponding to the same memory page as the entry in the aggregate table, the corresponding entry in the historical pattern table can be updated based on the entry in the aggregate table. The update rules for the entries in the historical pattern table can adopt the update strategy described above.

[0087] Combined with the previous article Figure 1 The method embodiment of the present application is described in detail. Figures 2 to 5 , the device embodiment of the present application is described in detail. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, so for parts not described in detail, reference can be made to the previous method embodiment.

[0088] Figure 2 The data pre-fetching device 200 may include a pre-fetching buffer 210 and a processor 220 .

[0089] The pre-fetch buffer area 210 is used to store pre-fetched data.

[0090] The processor 220 is configured to perform the following operations:

[0091] receiving a first memory access instruction, where an address corresponding to the first memory access instruction belongs to a first storage area of ​​a memory;

[0092] determining pre-fetched data according to a historical memory access pattern of the first storage area, wherein the historical memory access pattern is used to indicate historical access data of the first storage area, and the pre-fetched data includes part or all of the historical access data;

[0093] A prefetch instruction is sent to a memory controller according to the prefetch data, where the prefetch instruction is used to store the prefetch data in a prefetch buffer.

[0094] Optionally, determining the pre-fetched data based on the historical memory access pattern of the first storage area includes: determining the pre-fetched data based on the historical memory access pattern and the current memory access pattern, wherein the current access mode is used to indicate the current access data of the first storage area; and the pre-fetched data is data in part or all of the historical access data except the current access data.

[0095] Optionally, the historical memory access mode is updated according to the current memory access mode of the first storage area.

[0096] Optionally, the historical memory access mode includes a historical mode and a historical candidate mode, and updating the historical memory access mode according to the current memory access mode of the first storage area includes:

[0097] Optionally, the updated historical pattern and the historical candidate pattern are determined based on the scoring rules according to the current memory access pattern, the historical pattern and the historical candidate pattern; wherein, the updated historical pattern is determined by the union of the current memory access pattern and the historical candidate pattern, and the result with a high score in the union of the current memory access pattern and the historical pattern, and the updated historical candidate pattern is determined by the intersection of the current memory access pattern and the historical candidate pattern, and the result with a high score in the intersection of the current memory access pattern and the historical pattern.

[0098] Optionally, the result of the scoring rule is associated with the coverage and accuracy of the memory access pattern to be evaluated for the actual memory access behavior.

[0099] Optionally, the index of the first storage area is a page number of a memory page.

[0100] Optionally, the processor is also used to: record memory access behavior for the first storage area; if the number of memory accesses for the first storage area is less than a first threshold, record the memory access behavior in a filter table; if the number of memory accesses for the first storage area is greater than the first threshold, move the memory access behavior record from the filter table to the aggregation table.

[0101] Optionally, the processor is further configured to: in response to the number of accesses between the access to the memory and the last access to the first storage area being greater than a second threshold, move the memory access behavior record from the aggregation table to a historical pattern table.

[0102] Figure 3 This is a schematic diagram of the structure of a data prefetch device provided in another embodiment of the present application. The data prefetch device 300 includes a controller 310, a memory access request queue 320, a prefetch request queue 330, a prefetch buffer 340, a filter table 350, an aggregation table 360, and a historical pattern table 370. The filter table 350, the aggregation table 360, and the historical pattern table 370 constitute a prefetch component 380.

[0103] The memory access request queue 320 can be used to store memory access instructions. The controller 310 can be used to control the prefetch component 380 to determine the prefetch data corresponding to the memory access instruction according to the data prefetch method described above. The prefetch request queue 330 can be used to access the prefetch instruction, which can be used to cache the prefetch data corresponding to the memory access instruction in the prefetch buffer 340. The prefetch buffer 340 can be used to store the prefetch data.

[0104] Figure 4 4 is a schematic diagram of a workflow of the data pre-fetching device 300. The workflow diagram 400 includes steps S410 to S460.

[0105] In step S410, a memory access request is received.

[0106] In step S420 , the memory access request is stored in the memory access request queue 320 .

[0107] In step S430, access behavior is observed in the aggregate table.

[0108] In step S440, scattered access requests are filtered through the filter table.

[0109] In step S450 , the memory access mode is recorded in a history mode table.

[0110] In step S460 , a prefetch request is issued according to the memory access mode in the historical mode table.

[0111] Figure 5 Schematic diagram of a data prefetching system provided in an embodiment of the present application. The data prefetching system 500 includes an upper layer device 510 , a data prefetching apparatus 300 , and a memory controller 520 .

[0112] The data prefetching device 300 can determine the prefetched data based on the memory access instruction of the upper-layer device 510. At the same time, the data prefetching device 300 can send the prefetch instruction corresponding to the prefetched data to the memory controller 520. The memory controller 520 can read the prefetched data from the memory according to the prefetch instruction and return it to the data prefetching device 300.

[0113] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0114] It should be understood that in the embodiments of the present application, "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A, but B can also be determined based on A and / or other information.

[0115] It should be understood that the term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0116] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0118] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0119] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0120] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be read by a computer or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0121] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data prefetching method, characterized in that: The data prefetching method comprises: receiving a first memory access instruction, where an address corresponding to the first memory access instruction belongs to a first storage area of ​​a memory; determining pre-fetched data according to a historical memory access pattern of the first storage area, wherein the historical memory access pattern is used to indicate historical access data of the first storage area, and the pre-fetched data includes part or all of the historical access data; Sending a prefetch instruction to a memory controller according to the prefetch data, wherein the prefetch instruction is used to store the prefetch data in a prefetch buffer area; The historical memory access mode includes a historical mode and a historical candidate mode, and the data prefetching method further includes: Determining updated historical patterns and historical candidate patterns based on scoring rules according to the current memory access mode, the historical patterns, and the historical candidate patterns; The updated historical pattern is determined by the union of the current memory access pattern and the historical candidate pattern, and the result with a higher score in the union of the current memory access pattern and the historical pattern; the updated historical candidate pattern is determined by the intersection of the current memory access pattern and the historical candidate pattern, and the result with a higher score in the intersection of the current memory access pattern and the historical pattern; The current memory access mode is used to indicate the current access data of the first storage area, the historical mode is the currently used historical memory access mode, and the historical candidate mode is a candidate historical memory access mode.

2. The data prefetching method according to claim 1, wherein: The determining of pre-fetched data according to a historical memory access pattern of the first storage area includes: The pre-fetched data is determined according to the historical memory access mode and the current memory access mode, where the pre-fetched data is data in part or all of the historical memory access data except the current memory access data.

3. The data prefetching method according to claim 1 or 2, characterized in that: The result of the scoring rule is associated with the coverage and accuracy of the memory access pattern to be evaluated for the actual memory access behavior.

4. The data prefetching method according to claim 1, wherein: The index of the first storage area is the page number of the memory page.

5. The data prefetching method according to claim 1, wherein: The data prefetching method further includes: Recording memory access behavior for the first storage area; If the number of memory accesses to the first storage area is less than a first threshold, recording the memory access behavior in a filter table; If the number of memory accesses to the first storage area is greater than a first threshold, the memory access behavior record is moved from the filter table to the aggregation table.

6. The data prefetching method according to claim 5, characterized in that: The data prefetching method further includes: In response to the number of accesses between the access to the memory and the last access to the first storage area being greater than a second threshold, the memory access behavior record is moved from the aggregation table to a historical pattern table.

7. A data pre-fetching device, characterized in that: The data pre-fetching device comprises: A prefetch buffer area for storing prefetched data; A processor that performs the following operations: receiving a first memory access instruction, where an address corresponding to the first memory access instruction belongs to a first storage area of ​​a memory; determining pre-fetched data according to a historical memory access pattern of the first storage area, wherein the historical memory access pattern is used to indicate historical access data of the first storage area, and the pre-fetched data includes part or all of the historical access data; Sending a prefetch instruction to a memory controller according to the prefetch data, wherein the prefetch instruction is used to store the prefetch data in a prefetch buffer area; The historical memory access mode includes a historical mode and a historical candidate mode, and the processor is further configured to perform the following operations: Determining updated historical patterns and historical candidate patterns based on scoring rules according to the current memory access mode, the historical patterns, and the historical candidate patterns; The updated historical pattern is determined by the union of the current memory access pattern and the historical candidate pattern, and the result with a higher score in the union of the current memory access pattern and the historical pattern; the updated historical candidate pattern is determined by the intersection of the current memory access pattern and the historical candidate pattern, and the result with a higher score in the intersection of the current memory access pattern and the historical pattern; The current memory access mode is used to indicate the current access data of the first storage area, the historical mode is the currently used historical memory access mode, and the historical candidate mode is a candidate historical memory access mode.

8. The data pre-fetching device according to claim 7, characterized in that: The determining of pre-fetched data according to a historical memory access pattern of the first storage area includes: The pre-fetched data is determined according to the historical memory access mode and the current memory access mode, where the pre-fetched data is data in part or all of the historical memory access data except the current memory access data.

9. The data pre-fetching device according to claim 7 or 8, characterized in that: The result of the scoring rule is associated with the coverage and accuracy of the memory access pattern to be evaluated for the actual memory access behavior.

10. The data pre-fetching device according to claim 7, characterized in that: The index of the first storage area is the page number of the memory page.

11. The data pre-fetching device according to claim 7, characterized in that: The processor is further configured to: Recording memory access behavior for the first storage area; If the number of memory accesses to the first storage area is less than a first threshold, recording the memory access behavior in a filter table; If the number of memory accesses to the first storage area is greater than a first threshold, the memory access behavior record is moved from the filter table to the aggregation table.

12. The data pre-fetching device according to claim 11, characterized in that: The processor is further configured to: In response to the number of accesses between the access to the memory and the last access to the first storage area being greater than a second threshold, the memory access behavior record is moved from the aggregation table to a historical pattern table.

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