Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a driving transistor, a dual-gate transistor and a clamping module; the gate of the driving transistor and one end of the dual-gate transistor are both connected to a first node; the dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a second node; the anode of the light-emitting element is connected to a third node; the working process of the pixel circuit includes a light-emitting stage, and the clamping module is used to clamp the potential of the second node to the potential of the third node during at least part of the time period of the light-emitting stage. In the present invention, after the potential of the second node is clamped to the third node by the clamping module, the voltage difference between the second node and the first node is greatly reduced, the leakage phenomenon of the first sub-transistor is suppressed to a large extent, the stability of the light-emitting brightness of the light-emitting element is improved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle and fast response speed, and has become one of the research hotspots in the current display field. Electronic display products will use different refresh rates for display in different application scenarios. For example, a higher refresh rate driving method is used to drive the display of dynamic images to ensure the smoothness of the display; a lower refresh rate driving method is used to drive the display of static images to reduce power consumption.

[0003] In the prior art, when an OLED display device displays at a low frequency, the brightness of the light-emitting element decreases within a frame, resulting in flickering, which affects the display effect of the display device. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device to enhance the light luminance stability of a light emitting element and improve the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, comprising a plurality of pixel circuits and a plurality of light-emitting elements;

[0006] The pixel circuit includes a driving transistor, a dual-gate transistor and a clamping module;

[0007] The driving transistor is used to provide a driving current for the light emitting element, and the gate of the driving transistor and one end of the double-gate transistor are both connected to a first node;

[0008] The dual-gate transistor includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node;

[0009] The anode of the light emitting element is connected to the third node;

[0010] The working process of the pixel circuit includes a light emitting phase, during which the first sub-transistor and the second sub-transistor are both turned off;

[0011] The clamping module is connected to the second node and the third node respectively, and is used to clamp the potential of the second node to the potential of the third node during at least a partial period of time of the light emitting stage.

[0012] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect of the present invention.

[0013] In an embodiment of the present invention, the display panel includes a plurality of pixel circuits and a plurality of light-emitting elements; the pixel circuit includes a driving transistor, a dual-gate transistor and a clamping module; the driving transistor is used to provide a driving current for the light-emitting element, and the gate of the driving transistor and one end of the dual-gate transistor are both connected to a first node; the dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a second node; the anode of the light-emitting element is connected to a third node; the working process of the pixel circuit includes a light-emitting phase, and in the light-emitting phase, the first sub-transistor and the second sub-transistor are both turned off; the clamping module is respectively connected to the second node and the third node, and the clamping module is used to clamp the potential of the second node to the potential of the third node during at least part of the time period of the light-emitting phase. In the present invention, after the potential of the second node is clamped to the third node by the clamping module, the voltage difference between the second node and the first node is greatly reduced, the leakage phenomenon of the first sub-transistor is suppressed to a large extent, the stability of the light-emitting brightness of the light-emitting element is improved, and the display effect of the display panel is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a pixel circuit in a display panel in the related art provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of the structure of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention;

[0016] Figure 3 A graph showing a change in potential of each node under different driving timings provided by an embodiment of the present invention;

[0017] Figure 4 A schematic structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0018] Figure 5 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0019] Figure 6 A schematic structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0020] Figure 7 A working timing diagram of a clamping module provided by an embodiment of the present invention;

[0021] Figure 8 A schematic structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0022] Fig. 9 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0023] Fig.10 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0024] Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0025] Fig.12 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0026] Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0028] Figure 1 A schematic diagram of a pixel circuit in a display panel in a related art according to an embodiment of the present invention is shown in FIG. Figure 1 As shown in , in the related art, the first node N1 in the pixel circuit 1' is respectively connected to the gate of the driving transistor T3 and one end of the first dual-gate transistor T1. Those skilled in the art can understand that the pixel circuit 1' may include a reset phase, a data writing phase and a light emitting phase, wherein in the data writing phase, the first dual-gate transistor T1 writes a data signal to the first node N1 and compensates the threshold voltage of the driving transistor T3 to the potential of the first node N1; in the light emitting phase, the driving transistor T3 drives the light emitting element 2' to emit light using the data signal stored in the gate, i.e., the first node N1 and after threshold compensation.

[0029] Among them, the dual-gate transistor includes two sub-transistors. It can be understood that when the two sub-transistors are controlled to be turned on or off by the scanning signal, the voltage signal received by the gate of the sub-transistor will affect the potential of the connection point of the two sub-transistors. Figure 1The first dual-gate transistor T1 shown in the figure is a P-type dual-gate transistor as an example, which is turned off when the gate receives a high-level signal VGH. The connection node between the first sub-transistor T11 and the second sub-transistor T12 in the first dual-gate transistor T1 is the second node N2. When the gate of the first dual-gate transistor T1 receives the scanning signal S2 which jumps from a low-level signal to a high-level signal VGH, the potential of the second node N2 will be raised to a potential close to the high-level signal VGH under the coupling effect of the parasitic capacitance between it and the gate of the first dual-gate transistor T1, resulting in the potential of the second node N2 being greater than the potential of the first node N1, the first sub-transistor T11 generates a leakage current, and the potential of the first node N1 gradually increases. It is found through experiments that at this stage, when the driving transistor T3 drives the light-emitting element 2' to light up, the light-emitting brightness of the light-emitting element 2' will be affected by the potential of the first node N1. The potential change of the first node N1 causes the light-emitting brightness of the light-emitting element 2' to be unstable, and flickering occurs, which affects the display effect of the display panel.

[0030] Based on the above defects of the prior art, the inventor proposes the technical solution in the present application. Specifically, the present application proposes a display panel including a plurality of pixel circuits and a plurality of light-emitting elements;

[0031] The pixel circuit includes a driving transistor, a dual-gate transistor and a clamping module;

[0032] The driving transistor is used to provide a driving current for the light emitting element, and the gate of the driving transistor and one end of the double-gate transistor are both connected to the first node;

[0033] The dual-gate transistor includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node;

[0034] The anode of the light emitting element is connected to the third node;

[0035] The operation process of the pixel circuit includes a light emitting phase, during which the first sub-transistor and the second sub-transistor are both turned off;

[0036] The clamping module is connected to the second node and the third node respectively, and is used to clamp the potential of the second node to the potential of the third node during at least a part of the time period of the light emitting stage.

[0037] In the above technical solution, after the potential of the second node is clamped to the third node by the clamping module, the voltage difference between the second node and the first node is greatly reduced, and the potential at the first node can be basically maintained, which greatly suppresses the leakage of the first sub-transistor, improves the stability of the brightness of the light-emitting element, and improves the display effect of the display panel.

[0038] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Figure 2 A schematic diagram of a structure of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention, referring to Figure 2 The display panel includes a plurality of pixel circuits 1 and a plurality of light-emitting elements 2; the pixel circuit 1 includes a driving transistor T3, a dual-gate transistor 3 and a clamping module 4; the driving transistor T3 is used to provide a driving current for the light-emitting element 2, and the gate of the driving transistor T3 and one end of the dual-gate transistor 3 are both connected to the first node N1; the dual-gate transistor 3 includes a first sub-transistor 31 and a second sub-transistor 32, and the connection node between the first sub-transistor 31 and the second sub-transistor 32 is the second node N2; the anode of the light-emitting element 2 is connected to the third node N3; the working process of the pixel circuit 1 includes a light-emitting stage, and in the light-emitting stage, the first sub-transistor 31 and the second sub-transistor 32 are both turned off; the clamping module 4 is respectively connected to the second node N2 and the third node N3, and the clamping module 4 is used to clamp the potential of the second node N2 to the potential of the third node N3 during at least part of the time period of the light-emitting stage.

[0040] Specifically, please refer to Figure 2 In the present application, the display panel includes a plurality of pixel circuits 1 and a plurality of light-emitting elements 2. The pixel circuit 1 is used to drive the light-emitting element 2 to emit light, so as to complete the display of the display panel. Among them, the pixel circuit 1 can be arranged in an array in the display panel. The pixel circuit 1 is provided with a driving transistor T3, a dual-gate transistor 3 and a clamping module 4. When the light-emitting element 2 is controlled to emit light, the driving transistor T3 provides a driving current to the light-emitting element 2, and the gate of the driving transistor T3 is connected to the first node N1. At the same time, one end of the dual-gate transistor 3 is also connected to the first node N1. The dual-gate transistor 3 includes a first sub-transistor 31 and a second sub-transistor 32. The first sub-transistor 31 and the first sub-transistor 31 are connected through the second node N2. The gates of the first sub-transistor 31 and the second sub-transistor 32 are connected to the same scanning signal line and are controlled by the same scanning signal (for example, the data writing control signal S2). The anode of the light-emitting element 2 is connected to the third node N3, and one end of the driving transistor T3 is also connected to the third node N3 to pass the driving current to the light-emitting element 2. The first end of the clamping module 4 is connected to the second node N2, and the other end is connected to the third node N3.

[0041] If necessary, Figure 2The display panel shown only illustrates the pixel circuit 1 and the light emitting element 2 , and the display panel may also include other known structures, such as a substrate.

[0042] The working process of the pixel circuit 1 and the clamping principle of the clamping module 4 are introduced below. First, the working process of the pixel circuit 1 includes a light-emitting stage. In the light-emitting stage, the first sub-transistor 31 and the second sub-transistor 32 are turned off, the cathode and the anode of the light-emitting element 2 are turned on, and the driving current flows into the light-emitting element 2, and the light-emitting element 2 emits light. According to the description of the above-mentioned related art, if the clamping module 4 does not exist, in the light-emitting stage, the potential of the second node N2 will be charged into the first node N1, resulting in the phenomenon that the potential of the first node N1 increases. In the present application, after the clamping module 4 is set, the clamping module 4 can clamp the potential of the second node N2 to the potential of the third node N3 during at least part of the light-emitting stage, that is, during at least part of the light-emitting stage, the potential of the third node N3 is charged into the second node N2 through the clamping module 4. Since the third node N3 is connected to the anode of the light-emitting element 2, the third node N3 is set between the two power supply voltage terminals, and it can also be understood that the third node N3 is an active node, and the potential of the third node N3 is relatively stable and continuous. Compared with the coupling effect of the high level signal VGH received by the gates of the first sub-transistor 31 and the second sub-transistor 32 on the potential of the second node N2, the potential of the third node N3 has a greater influence on the potential of the second node N2, and the potential of the third node N3 is more easily charged into the second node N2. The potential of the third node N3 is closer to the potential of the first node N1, so that the potential of the second node N2 is close to or the same as the potential of the first node N1.

[0043] Those skilled in the art will know that, in addition to the driving transistor T3, the pixel circuit 1 is generally provided with a compensation module 6 and a reset module 5, etc. The compensation module 6 is turned on or off under the control of the data writing control signal S2. In the threshold compensation stage, the compensation module 6 is turned on to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3. The embodiment of the present invention does not limit the specific position of the dual-gate transistor, and those skilled in the art can set it according to actual needs. Figure 2 exemplarily shows that the compensation module 6 is configured as a dual-gate transistor 3. In this embodiment, in the time dimension, the threshold compensation phase and the data writing phase may overlap, that is, detection and threshold compensation are performed in the data writing phase.

[0044] The following takes the compensation module 6 including the dual-gate transistor 3 as an example to explain the technical principle of the present invention: It can be seen from the above content that when the clamping module 4 is not provided in the related art, in the light-emitting stage, the potential of the second node N2 will be coupled by the high-level signal VGH and raised to a potential close to the high-level signal VGH, while the potential of the first node N1 is V N1Vdata-|Vth|, Vdata represents the voltage value of the data signal, Vth is the threshold voltage of the driving transistor T3, and the voltage difference ΔV' between the second node N2 and the first node N1 is V N2 -V N1 ≈VGH-(Vdata-|Vth|). In general, the potential of the high-level signal VGH is about 8V, Vdata-|Vth| is about 0.5V, and the voltage difference between the second node N2 and the first node N1 is ΔV'=V N2 -V N1 ≈VGH-(Vdata-|Vth|)≈8-0.5=7.5V. In the present application, a clamping module 4 is provided between the third node N3 and the second node N2 in the compensation module 6. In the light-emitting stage, the potential of the third node N3 is the potential of the anode of the light-emitting element 2. Normally, the voltage between the cathode and the anode of the light-emitting element 2 is about 4V, and the power supply voltage signal connected to the cathode of the light-emitting element 2 is about -3.5V, that is, the potential V N3 It is about 4-3.5=0.5V. After the potential of the third node N3 is written into the second node N2 by the clamp module 4, the potential of the second node N2 becomes 0.5V. At this time, the voltage difference ΔV between the second node N2 and the first node N1 is V N2 -V N1 =V N3 -V N1 ≈0.5-0.5=0 V. It can be seen that the clamping module 4 can reduce the voltage difference between the second node N2 and the first node N1 to a large extent, avoid leakage of the sub-transistor, and ensure the stability of the potential of the first node N1.

[0045] Figure 3 A graph showing the potential variation of each node under different driving timings provided by an embodiment of the present invention. Figure 3 1 shows a timing diagram of the reset control signal S1, the data writing control signal S2 and the light emitting control signal EM in different working stages of the display panel, as well as the potential changes of the first node N1 and the second node N2 in different timings. Figure 3 Curve 1 and curve 2 are Figure 1 The potential change curves of the first node N1 and the second node N2 in the pixel circuit of the related art are shown; Curve 3 and Curve 4 are respectively Figure 2The potential change curves of the first node N1 and the second node N2 in the pixel circuit shown. In the related art, as shown in curves 1 and 2, in the data writing stage tb, the data signal is written into the first node N1, and the potential of the first node N1 increases; in the light-emitting stage tc, since the potential of the second node N2 is higher than the potential of the first node N1, the potential of the first node N1 is gradually increased by the action of the second node N2; at the same time, since the second node N2 leaks to the first node N1, the potential of the second node N2 gradually decreases, and the potentials of the first node N1 and the second node N2 cannot be maintained. In the present application, as shown in curves 3 and 4, in the light-emitting stage tc, since the potential of the third node N3 is written into the second node N2, the potentials of the first node N1 and the second node N2 are basically the same, and the potentials of the first node N1 and the second node N2 can be maintained, and the potential of the first node N1 will not be affected by the potential of the second node N2.

[0046] In this embodiment, when the light-emitting element 2 is turned on, after the potential of the second node N2 is clamped to the potential of the third node N3 by the clamping module 4, the voltage difference between the second node N2 and the first node N1 is greatly reduced, and the potential at the first node N1 can be basically maintained, thereby suppressing the leakage of the first sub-transistor 31 to a large extent, improving the stability of the light-emitting brightness of the light-emitting element 2, and improving the display effect of the display panel.

[0047] Optionally, the embodiment of the present invention does not limit the specific configuration of the clamping module 4, and those skilled in the art may configure it according to actual needs. Any specific design scheme for realizing the function of the clamping module 4 is within the scope of the technical solution protected by the present invention.

[0048] In addition, it should be noted that the display panel includes a plurality of pixel circuits 1 and a plurality of light-emitting elements 2. The above-mentioned clamping module 4 and the pixel circuit 1 may be in a one-to-one correspondence relationship, and each clamping module 4 may clamp the potential of the second node N2 of the corresponding pixel circuit 1 to the potential of the third node N3 of the same pixel circuit 1; the clamping module 4 and the pixel circuit 1 may also be in a one-to-many relationship, and each clamping module 4 may clamp the potential of the second node N2 of a certain pixel circuit 1 to the potential of the third node N3 of a different pixel circuit 1. The specific clamping method of the clamping module 4 may be set by those skilled in the art according to actual needs, and any method that can realize the charging of the potential of the third node N3 into the second node N2 is within the scope of the technical solution protected by the embodiment of the present invention.

[0049] In an embodiment of the present invention, a display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a driving transistor, a dual-gate transistor and a clamping module; the driving transistor is used to provide a driving current for the light-emitting element, and the gate of the driving transistor and one end of the dual-gate transistor are both connected to a first node; the dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a second node; the anode of the light-emitting element is connected to a third node; the working process of the pixel circuit includes a light-emitting phase, and in the light-emitting phase, the first sub-transistor and the second sub-transistor are both turned off; the clamping module is respectively connected to the second node and the third node, and the clamping module is used to clamp the potential of the second node to the potential of the third node during at least part of the time period of the light-emitting phase. In the present invention, after the potential of the second node is clamped to the third node by the clamping module, the voltage difference between the second node and the first node is greatly reduced, the leakage phenomenon of the first sub-transistor is suppressed to a large extent, the stability of the light-emitting brightness of the light-emitting element is improved, and the display effect of the display panel is improved.

[0050] Optional, Figure 4 A schematic diagram of a structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, referring to Figure 4 In other possible embodiments, the pixel circuit 1 further includes a reset module 5 , the reset module 5 is used to provide a reset signal Vref to the first node N1 in a reset phase, and the reset module 5 includes a dual-gate transistor 3 .

[0051] like Figure 4 As shown, in the embodiment of the present invention, the reset module 5 may also include the above-mentioned dual-gate transistor 3. That is, the reset module 5 is provided with a first sub-transistor 31 and a second sub-transistor 32. At this time, the connection point between the first sub-transistor 31 and the second sub-transistor 32 in the reset module 5 is the second node N2, and the clamping module 4 may clamp the potential of the second node N2 to the third node N3, and also suppress the leakage from the second node N2 to the first node N1. When the reset module 5 is a dual-gate transistor 3, the working principle of the clamping module 4 is the same as in the above-mentioned embodiment, and no further explanation is given here.

[0052] Of course, in other optional embodiments, the reset module 5 and the compensation module 6 may also be configured to both include a dual-gate transistor 3 .

[0053] In a possible embodiment, if Figure 2 As shown in the figure, the clamping module 4 may include a first transistor 41, the two ends of the first transistor 41 are respectively connected to the second node N2 and the third node N3, and the control end of the first transistor 41 receives the clamping control signal SCQ; the first transistor 41 is used to be controlled by the clamping control signal SCQ and turned on during at least a part of the time period of the light-emitting stage.

[0054] As a possible embodiment, a transistor can be used to implement the function of the clamping module 4. Specifically, a first transistor 41 can be provided in the clamping module 4, the first end of the first transistor 41 is connected to the second node N2, the second end of the first transistor 41 is connected to the third node N3, and the control end of the first transistor 41 is used to receive the clamping control signal SCQ. The clamping control signal SCQ controls the first transistor 41 to be in an on state at least part of the time during the light-emitting stage. The first transistor 41 shown in the figure is a P-type transistor, and the actual setting method is not limited to this. When the first transistor 41 is a P-type transistor, the clamping control signal SCQ is a low level during at least part of the time period of the light-emitting stage to control the first transistor 41 to be turned on. In this embodiment, the pixel circuit 1 and the clamping module 4 are in a one-to-one correspondence, that is, each pixel circuit 1 is provided with a first transistor 41, and the first transistor 41 can charge the potential of the third node N3 of the pixel circuit 1 into the second node N2 of the pixel circuit 1.

[0055] In addition, it should be noted that, in order to ensure the reset function of the reset module 5 on the potential of the first node N1, or the compensation function of the compensation module 6 on the potential of the first node N1, the first transistor 41 should be turned off in the reset stage or the compensation stage to prevent the first transistor 41 from charging the potential of the third node N3 into the first node N1. Therefore, in the embodiment of the present invention, when the reset module 5 includes the dual-gate transistor 3, the first transistor 41 can be set to be controlled by the clamp control signal SCQ and turned off in the reset stage; when the compensation module 6 includes the dual-gate transistor 3, the first transistor 41 can be set to be controlled by the clamp control signal SCQ and turned off in the threshold compensation stage.

[0056] Specifically, when the reset module 5 is a dual-gate transistor 3 ( Figure 4 As shown in FIG. 1 , in the reset phase, the clamp control signal SCQ controls the first transistor 41 to be turned off; when the compensation module 6 is a dual-gate transistor 3 ( Figure 2 As shown in ), in the threshold compensation stage, the clamp control signal SCQ controls the first transistor 41 to turn off. Exemplarily, when the first transistor 41 is a P-type transistor, in the reset stage or the compensation stage, the clamp control signal SCQ should be at a high level to control the first transistor 41 to turn off.

[0057] You can continue to refer to Figure 2 The pixel circuit 1 may further include a light emitting control module 7, which is respectively connected in series with the driving transistor T3 and the light emitting element 2 to control whether the driving current flows through the light emitting element 2; the light emitting control module 7 receives a light emitting control signal EM, and in the light emitting stage, the light emitting control signal EM turns on the light emitting control module 7; the light emitting control signal EM is multiplexed into a clamping control signal SCQ.

[0058] Specifically, the light-emitting control module 7, the driving transistor T3 and the light-emitting element 2 are connected in series. The light-emitting control module 7 can be turned on or off under the control of the light-emitting control signal EM. When the light-emitting control signal EM controls the light-emitting control module 7 to be turned on, the driving current of the driving transistor T3 flows through the light-emitting element 2, and the light-emitting element 2 emits light.

[0059] It is worth mentioning that, in the present embodiment, the light emitting control signal EM may be multiplexed into the clamping control signal SCQ, that is, the first transistor 41 is turned on or off under the control of the light emitting control signal EM.

[0060] Figure 5 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention, such as Figure 2 and Figure 5 As shown, the functional modules and driving process of the pixel circuit 1 in the embodiment of the present invention are introduced. Figure 2 In the pixel circuit 1 of this embodiment, the reset module 5 may include a reset transistor 51, and the compensation module 6 includes a dual-gate transistor 3; the light-emitting control module 7 may include a first light-emitting control transistor 71 and a second light-emitting control transistor 72, and the first light-emitting control transistor 71 and the second light-emitting control transistor 72 are both connected to the light-emitting control signal terminal EM. The pixel circuit 1 is also provided with a data writing module 8 and an initialization module 9, and the data writing module 8 may include a data writing transistor 81, and the initialization module 9 may include an initialization transistor 91. The control end of the data writing transistor 81 is connected to the data writing control signal S2, and when the data writing transistor 81 is turned on, the data signal Vdata is written to the first node N1 through the data writing transistor 81. The control end of the initialization transistor 91 can also be connected to the reset control signal S1, and when the initialization transistor 91 is turned on, the reset signal Vref is written to the anode of the light-emitting element 2 through the initialization transistor 91 to initialize the anode. In addition, the above-mentioned transistors can be set to be P-type transistors, and the transistor is turned off when the control signal provided to its gate is high level, and the transistor is turned on when the control signal is low level. The specific setting method of the above-mentioned pixel circuit 1 is only an optional method. In the actual application process, those skilled in the art can adjust it according to needs.

[0061] refer to Figure 5 The driving process of the pixel circuit 1 includes a reset phase ta, a data writing phase tb and a light emitting phase tc. In the reset phase ta, the reset control signal S1 changes from a high level to a low level. At this time, the reset transistor 51 is turned on, and the reset signal Vref is written into the first node N1. At the same time, the initialization transistor 91 is turned on, and the reset signal Vref is written into the anode of the light emitting element 2. The reset phase is used to reset the first node N1 and the anode of the light emitting element 2 to avoid the influence of the voltage signal written in the previous frame.

[0062] In the data writing stage tb: the data writing control signal S2 changes from a high level to a low level, at which time the data writing transistor 81 is turned on, and at the same time, the dual-gate transistor 3 is turned on, and the data signal Vdata flows into the first node N1 through the data writing transistor 81, the driving transistor T3 and the dual-gate transistor 3 in sequence, and since the voltage of the fifth node is Vdata, when the voltage of the first node N1 reaches Vdata-|Vth|, the driving transistor T3 will be turned off. That is, in this stage, the threshold-compensated data voltage signal Vdata-|Vth| is written into the first node N1. Among them, in the above-mentioned reset stage ta and data writing stage tb, the light emitting control signal EM is all high level, and the first light emitting control transistor 71, the second light emitting control transistor 72 and the first transistor 41 are all turned off.

[0063] Light-emitting stage tc: the light-emitting control signal EM changes from a high level to a low level, at which time the first light-emitting control transistor 71 and the second light-emitting control transistor 72 are turned on, a path is formed from the first power supply voltage terminal PVDD to the second power supply voltage terminal PVEE, and the light-emitting element 2 emits light. At the same time, the first transistor 41 is turned on, and the potential of the third node N3 is charged into the second node N2. According to the above analysis, the potential of the third node N3 is close to the potential of the first node N1. In the light-emitting stage, leakage of the first sub-transistor 31 can be avoided, and the potential of the first node N1 is kept at Vdata-|Vth|, thereby ensuring the brightness of the light-emitting element 2.

[0064] In this embodiment, the light-emitting control signal EM is multiplexed into the clamping control signal SCQ. When the light-emitting element 2 starts to emit light, the first transistor 41 can write the potential of the third node N3 into the second node N2. The potential is written in a timely manner to ensure that the potential of the second node N2 is close to the potential of the first node N1 at the beginning of the light-emitting stage, so that the potential of the first node N1 remains stable, avoiding the problem of decreased brightness of the light-emitting element 2.

[0065] Figure 6 A schematic diagram of the structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, Figure 6 In the illustrated embodiment, the clamping module 4 may adopt other structures. Figure 6In this embodiment, the clamping module 4 may include a potential grabbing unit 42 and a potential writing unit 43, the potential grabbing unit 42 is used to grab and store the potential of the third node N3 in the pixel circuit 1 in a first time period; the potential writing unit 43 is used to write the potential of the third node N3 to the second node N2 of the same or different pixel circuit 1 in a second time period; wherein, in the time dimension, the first time period at least partially overlaps with the light-emitting phase of the pixel circuit 1 where the third node N3 is located, the second time period at least partially overlaps with the light-emitting phase of the pixel circuit 1 where the second node N2 is located, and the second time period is located after the first time period.

[0066] Specifically, Figure 6 As shown in FIG. 4 , the clamping module 4 is provided with a potential grabbing unit 42 and a potential writing unit 43. The potential grabbing unit 42 is connected to the third node N3 of the pixel circuit 1, so as to grab and store the potential of the third node N3 in the pixel circuit 1. It should be noted that it is not limited here that the potential grabbing unit 42 grabs the potential of the third node N3 in which pixel circuit 1, and can grab the potential of the third node N3 in the corresponding pixel circuit 1, or the potential of the third node N3 in other pixel circuits 1 (for example, the potential of the third node N3 in a pixel circuit 1 in an adjacent row).

[0067] The potential writing unit 43 is connected to the potential grabbing unit 42 and the second node N2 of the pixel circuit 1 respectively, and the potential writing unit 43 is used to write the potential of the third node N3 in a certain pixel circuit 1 captured by the potential grabbing unit 42 into the second node N2 of the pixel circuit 1. It should be noted here that when the potential captured by the potential grabbing unit 42 belongs to the pixel circuit 1 to which the potential writing unit 43 is about to write, the potential writing unit 43 writes the potential of the third node N3 to the second node N2 of the pixel circuit 1 which is the same as the captured potential, and when the potential captured by the potential grabbing unit 42 does not belong to the pixel circuit 1 to which the potential writing unit 43 is about to write, the potential writing unit 43 writes the potential of the third node N3 to the second node N2 of the pixel circuit 1 which is different from the captured potential.

[0068] It is understandable that when the clamping module 4 works in the light-emitting phase, the potential capture unit 42 and the potential writing unit 43 should at least complete the corresponding work in a partial time period covered by the light-emitting phase, and there should be a certain timing relationship between the working processes of the two. Figure 7 A working timing diagram of a clamp module provided in an embodiment of the present invention, referring to Figure 6 and Figure 7, the potential capture unit 42 can be set to capture and store the potential of the third node N3 in the first time period t1, and the potential writing unit 43 can write the potential of the third node N3 into the second node N2 in the second time period t2, wherein, in the time dimension, the first time period t1 can overlap with the light-emitting phase tc-N3 of the pixel circuit 1 where the third node N3 is located, that is, the potential capture unit 42 at least works in the partial time period of the light-emitting phase tc-N3 of the pixel circuit 1 where it captures the potential; at the same time, the second time period t2 can overlap with the light-emitting phase tc-N2 of the pixel circuit 1 where the second node N2 is located, that is, the potential writing unit 43 at least works in the partial time period of the light-emitting phase tc-N2 of the pixel circuit 1 where it writes the potential. Moreover, the second time period t2 is located after the first time period t1, that is, the working period of the potential writing unit 43 is later than the working period of the potential capture unit 42. When the pixel circuit 1 whose potential is captured by the potential capture unit 42 and the pixel circuit 1 into which the potential is written by the potential writing unit 43 are the same pixel circuit 1, the light-emitting stage tc-N3 of the pixel circuit 1 where the third node N3 is located and the light-emitting stage tc-N2 of the pixel circuit 1 where the second node N2 is located are the same light-emitting stage; when the pixel circuit 1 whose potential is captured by the potential capture unit 42 and the pixel circuit 1 into which the potential writing unit 43 writes the potential are different pixel circuits 1, the light-emitting stage tc-N3 of the pixel circuit 1 where the third node N3 is located and the light-emitting stage tc-N2 of the pixel circuit 1 where the second node N2 is located are different light-emitting stages.

[0069] Those skilled in the art will appreciate that compared to Figure 2 In the embodiment shown, the third node N3 is directly electrically connected to the second node N2 of the corresponding pixel circuit 1. Under this configuration of the embodiment, there is a transition phase of potential capture, and the operation of the entire pixel circuit 1 is more stable.

[0070] Optionally, the embodiment of the present invention does not limit the specific setting method of the potential capture unit 42 and the potential writing unit 43. Those skilled in the art can set them according to actual needs. Any method that can achieve potential capture and potential writing is within the scope of the technical solution protected by the embodiment of the present invention.

[0071] Figure 8 A schematic diagram of a structure of a pixel circuit and a light-emitting element in another display panel provided in an embodiment of the present invention can be combined with reference to Figure 6 and Figure 8In a possible embodiment, the potential capture unit 42 may include a second transistor 44 and a first storage capacitor 45, the two ends of the second transistor 44 are respectively electrically connected to the third node N3 in the pixel circuit 1 and the first plate c1 of the first storage capacitor 45, and the second plate c2 of the first storage capacitor 45 is connected to a fixed potential; the control end of the second transistor 44 receives the potential capture control signal S3, and the second transistor 44 is used to be turned on in the first time period under the control of the potential capture control signal S3; the potential writing unit 43 includes a third transistor 46, the two ends of the third transistor 46 are respectively electrically connected to the second node N2 in the same or different pixel circuit 1 and the first plate c1 of the first storage capacitor 45, the control end of the third transistor 46 receives the potential write control signal S4, and the third transistor 46 is used to be turned on in the second time period under the control of the potential write control signal S4.

[0072] Specifically, Figure 6 and Figure 8 As shown in , the potential capture unit 42 is composed of a second transistor 44 and a first storage capacitor 45. The control end of the second transistor 44 receives the potential capture control signal S3. The second transistor 44 is also used to connect the third node N3 of the pixel circuit 1 and a certain plate of the first storage capacitor 45 (which may be the first plate c1), and the other plate of the first storage capacitor 45 (which may be the second plate c2) is connected to the fixed potential signal. Taking a certain pixel circuit 1 as an example, one end of the second transistor 44 in the pixel circuit 1 is connected to the first storage capacitor 45 in the pixel circuit 1, and the other end is connected to the third node N3 of the pixel circuit 1, or one end of the second transistor 44 is connected to the first storage capacitor 45 in the pixel circuit 1, and the other end is connected to the third node N3 of other pixel circuits 1. In the first time period t1, the potential capture control signal S3 controls the second transistor 44 to be turned on. When the second transistor 44 is turned on, the potential of the third node N3 connected to the second transistor 44 is stored in the first storage capacitor 45.

[0073] Continue to refer Figure 6 and Figure 8, the potential writing unit 43 can be composed of a third transistor 46, the control end of the third transistor 46 receives the potential writing control signal S4, and within the same pixel circuit 1, the third transistor 46 can be used to connect the second node N2 of the pixel circuit and the first plate c1 of the first storage capacitor 45. When the second transistor 44 is connected to the third node N3 of the pixel circuit, the two ends of the third transistor 46 are connected to the second node N2 and the first storage capacitor 45 of the same pixel circuit 1, and the third transistor 46 writes the potential of the third node N3 of the pixel circuit 1 to the second node N2 of the pixel circuit 1; when the second transistor 44 is connected to the third node N3 of other pixel circuits 1, the two ends of the third transistor 46 are connected to the second node N2 of other pixel circuits 1 different from the pixel circuit 1 and the first storage capacitor 45 of the pixel circuit 1, and the third transistor 46 writes the potential of the third node N3 of other pixel circuits 4 to the second node N2 of the pixel circuit 1.

[0074] Figure 6 In a certain pixel circuit 1 shown in the figure, the two ends of the second transistor 44 are respectively the fourth node N3 of the pixel circuit 1 and the first storage capacitor 45. After the second transistor 44 captures and stores the potential of the third node N3 of the pixel circuit, the third transistor 46 writes the captured potential to the second node N2 of the same pixel circuit 1. Since the distance between the second node N2 and the third node N3 in the same pixel circuit 1 is relatively close, the connection line length between the second node N2 and the third node N3 is relatively short under this setting, and the wiring method is relatively simple. Figure 8 In a certain pixel circuit 1 shown in the figure, the two ends of the second transistor 44 are respectively connected to the third node N3 of other pixel circuits 1 (pixel circuits 1 at the corresponding position of the previous row) and the first storage capacitor 45 in the pixel circuit 1. After the second transistor 44 captures the potential of the third node N3 in the pixel circuit 1 of the previous row and stores it, the third transistor 46 writes the captured potential to the second node N2 of the pixel circuit 1 of this row.

[0075] Optionally, when the reset module 5 includes a dual-gate transistor 3, the third transistor 46 is also used to be turned off in the reset phase under the control of the potential writing control signal S4; when the compensation module 6 includes a dual-gate transistor 3, the third transistor 46 is also used to be turned off in the threshold compensation phase under the control of the potential writing control signal S4.

[0076] Specifically, when the reset module 5 is a dual-gate transistor 3, in the reset stage, the potential writing control signal S4 controls the third transistor 46 to be turned off; when the compensation module 6 is a dual-gate transistor 3, in the compensation stage, the potential writing control signal S4 controls the third transistor 46 to be turned off. Exemplarily, when the third transistor 46 is a P-type transistor, in the reset stage or the compensation stage, the potential writing control signal S4 should be a high level to control the third transistor 46 to be turned off.

[0077] In this way, the resetting effect of the reset module 5 on the potential of the first node N1, or the compensation effect of the compensation module 6 on the potential of the first node N1 can be guaranteed. In the reset stage or the compensation stage, the third transistor 46 should be turned off to prevent the third transistor 46 from charging the potential of the third node N3 into the first node N1.

[0078] You can continue to refer to Figure 6 or Figure 8 The pixel circuit 1 may further include a data writing module 8 and a data storage module 10; the reset module 5 is connected between the reset signal terminal Vref and the first node N1, the control terminal of the reset module 5 receives the reset control signal S1, and the reset module 5 is used to provide the reset signal Vref to the first node N1 under the control of the reset control signal S1; the data writing module 8 is connected between the data signal terminal Vdata and the first end of the driving transistor T3, and the control end of the data writing module 8 receives the data writing control signal S2; the compensation module 6 is connected between the second end of the driving transistor T3 and the first node N1; the data storage module 10 is connected between the first power supply voltage terminal PVDD and the first node N1; the data writing module 8 is used to write the data signal Vdata to the first node N1 through the driving transistor T3 and the compensation module 6 in sequence under the control of the data writing control signal S2, and the data storage module 10 is used to store the data signal written to the first node N1.

[0079] Among them, the data writing module 8, the reset module 5 and the compensation module 6 are mentioned in the above embodiments. The two ends of the reset module 5 can be specifically located between the reset signal terminal Vref and the first node N1, and the control end of the reset module 5 receives the reset control signal S1, thereby resetting the first node N1. The data writing module 8 can be specifically located between the data signal terminal Vdata and the first end of the driving transistor T3; the compensation module 6 can be specifically located between the second end of the driving transistor T3 and the first node N1. In the data writing stage, the data signal Vdata is written to the first node N1 after passing through the driving transistor T3 and the compensation module 6. The specific working principle of each stage can refer to the above embodiments, which will not be repeated here.

[0080] In addition, the pixel circuit 1 is also provided with a data storage module 10, which is located between the first power supply voltage terminal PVDD and the first node N1, and the data signal Vdata written in the data writing phase can be stored in the data storage module 10. The data storage module 10 can be a storage capacitor, but is not limited thereto.

[0081] Optional, Fig. 9 A schematic diagram of a display panel provided by an embodiment of the present invention can be referred to Figure 2 and Fig. 9In a possible embodiment, the display panel may include N rows of pixel circuits 1 and M cascaded shift registers 11, wherein N and M are both positive integers greater than or equal to 1, and N<M; the shift register 11 is used to provide a scan signal to the pixel circuit 1, and the scan signals provided by the shift registers 11 at each level are shifted sequentially by the same distance in timing; in the pixel circuit 1 of the nth row, the nth-level shift register 11 provides a scan signal to the control end of the reset module 5 as a reset control signal S1, and the n+1th-level shift register 11 provides a scan signal to the control end of the data writing module 8 as a data writing control signal S2; wherein n is a positive integer greater than or equal to 1 and less than or equal to N.

[0082] Specifically, Fig. 9 As shown in the figure, a total of N rows of pixel circuits 1 and M shift registers 11 for providing scanning signals to the pixel circuits 1 can be arranged in the display panel. The M shift registers 11 are cascaded, that is, M cascaded shift registers 11 can be arranged in the row direction where the pixel circuits 1 are located. Those skilled in the art can know the specific meaning of the cascade setting, which will not be described in detail here.

[0083] It can be understood that both M and N should be positive integers greater than or equal to 1, and the number of shift registers 11 is greater than the number of rows of pixel circuits 1. The M shift registers 11 provide the N pixel circuits 1 with the signals required by each device in the pixel circuit 1. The direction from top to bottom shown in the figure is the first direction X. Along the first direction X, the scanning signals provided by the shift registers 11 of each level are sequentially delayed by the same time, that is, after the nth stage shift register 11 sends out the scanning signal, the n+1th stage shift register 11 sends out the scanning signal after delaying the preset time.

[0084] In addition, those skilled in the art will appreciate that, generally, a row of pixel circuits 1 is controlled by a multi-stage shift register 11. Figure 6 and Fig. 9 In this embodiment, for a certain row of pixel circuits 1, for example, the nth row of pixel circuits 1 (n is a positive integer, and 1≤n≤N), the nth shift register 11 provides a scan signal to its reset module 5, and the scan signal is used as a reset control signal S1 to control the on or off of the reset module 5; and the n+1th shift register 11 provides a scan signal to its data writing module 8, and the scan signal is used as a data writing control signal S2 to control the on or off of the data writing module 8. At the same time, the scan signal provided by the n+1th shift register 11 also serves as the reset control signal S1 of the reset module 5 in the n+1th row of pixel circuits 1. In simple terms, it can also be understood that the data writing control signal S2 received by the current row of pixel circuits 1 also serves as the reset control signal S1 of the next row of pixel circuits 1.

[0085] For example, when n=1, the scanning signal output by the first-stage shift register 11 is used as the reset control signal S1 to the first-row pixel circuit 1. After a preset delay, the second-stage shift register 11 outputs a scanning signal, which is used as both the data writing control signal S2 for the first-row pixel circuit 1 and the reset control signal S1 for the second-row pixel circuit 1, and so on. It can be understood that the scanning signal output by the first-stage shift register 11 is also used as a start signal to control the shift registers 11 at each stage to start and transmit the scanning signal after a preset delay.

[0086] Among them, the above Figure 6 and Figure 8 Two optional working modes of the potential capture unit 42 and the potential writing unit 43 in the clamping module 4 are shown. Based on the difference in the working modes, the control timings of the second transistor 44 in the potential capture unit 42 and the third transistor 46 in the potential writing unit 43 are different, and the number of shift registers 11 and the number of pixel circuit rows 1 are also different.

[0087] It can be seen from the above embodiments that the scan signal output by the n-th shift register 11 is used as the reset control signal S1 of the n-th row pixel circuit 1, and the scan signal output by the n+1-th shift register 11 is used as the data write control signal S2 of the n-th row pixel circuit 1. Taking the pixel circuit 1 as an example in which each module includes a P-type transistor, when the scan signal output by the n-th shift register 11 is low level, a certain pixel circuit 1 of the n-th row enters the reset stage, and after a preset delay time, the n+1-th shift register 11 outputs a low level scan signal, and the pixel circuit 1 enters the data write stage; after a preset delay time, the n+2-th shift register 11 outputs a low level scan signal, and this period corresponds to the light-emitting stage of the pixel circuit 1.

[0088] Therefore, in Figure 6 Under the working mode of the clamping module 4 corresponding to the illustrated embodiment, that is, when the potential writing unit 43 writes the potential of the third node N3 to the second node N2 of the same pixel circuit 1 within the second time period, M=N+3 can be set; in the pixel circuit 1 of the nth row, the n+2th stage shift register 11 provides a scanning signal to the control end of the second transistor 44 as the potential grabbing control signal S3, and the n+3th stage shift register 11 provides a scanning signal to the control end of the third transistor 46 as the potential writing control signal S4.

[0089] Specifically, refer to Figure 6 and Fig. 9, the first time period t1 of the potential capture unit 42 and the second time period t2 of the potential writing unit 43 should be located after the data writing stage of the pixel circuit 1. At this time, in order to ensure that the shift register 11 accurately controls the second transistor 44 in the potential capture unit 42 and the third transistor 46 in the potential writing unit 43, the number of shift registers 11 can be set to be 3 more than the number of pixel circuit 1 rows. And the scanning signal provided by the n+2-stage shift register 11 is multiplexed into the potential capture control signal S3 received by the second transistor 44 in the n-row pixel circuit 1, and the second transistor 44 of the potential capture unit 42 in the n-row pixel circuit 1 is turned on or off according to the scanning signal output by the n+2-stage shift register 11. When the n+2-stage shift register 11 outputs a low-level scanning signal, the second transistor 44 in the n-row pixel circuit 1 is turned on, and the second transistor 44 captures and stores the potential of the third node N3 of the pixel circuit 1.

[0090] Further, since the second time period t2 of the potential writing unit 43 is located after the first time period t1, at this time, the scanning signal output by the n+3-th stage shift register 11 can be used to control the on or off of the third transistor 46 of the potential writing unit 43 in the pixel circuit 1, that is, the scanning signal output by the n+3-th stage shift register 11 is multiplexed into the potential writing control signal S4 received by the third transistor 46 in the n-th row pixel circuit 1. When the n+3-th stage shift register 11 outputs a low-level scanning signal, the third transistor 46 in the n-th row pixel circuit 1 is turned on, and the potential of the third node N3 of the pixel circuit 1 stored in the first storage capacitor 45 is written into the second node N2.

[0091] Fig.10 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention, Figure 6 The pixel circuit shown can be driven according to this driving timing. Taking the driving process of a pixel circuit 1 in the nth row as an example, combined with Figure 6 , Fig. 9 and Fig.10 , the driving process of the pixel circuit 1 in this embodiment is introduced.

[0092] like Figure 6 , Fig. 9 and Fig.10As shown, the driving process of the pixel circuit 1 includes a reset phase ta, a data writing phase tb and a light emitting phase tc, wherein the light emitting phase tc includes a first time period t1 and a second time period t2. In the reset phase ta: the reset control signal S1 output by the n-th stage shift register 11 jumps from a high level to a low level, the reset transistor 51 is turned on, and the reset signal Vref is written into the first node N1; at the same time, the initialization transistor 91 is turned on, and the reset signal Vref is written into the anode of the light emitting element 2, completing the reset of the first node N1 and the anode of the light emitting element 2.

[0093] In the data writing stage tb: the data writing control signal S2 output by the n+1th stage shift register 11 changes from a high level to a low level, the data writing transistor 81 is turned on, and the data signal is written into the first node N1 after passing through the driving transistor T3 and the compensation module 6. In the above reset stage ta and the data writing stage tb, the light emitting control signal EM is both at a high level, and the first light emitting control transistor 71 and the second light emitting control transistor 72 are both turned off.

[0094] In the light-emitting stage tc: in the first time period t1, the potential capture control signal S3 output by the n+2-th stage shift register 11 changes from a high level to a low level, the second transistor 44 is turned on, and the potential of the third node N3 of the pixel circuit 1 is charged into the first storage capacitor 45. Further, in the second time period t2, the potential write control signal S4 output by the n+3-th stage shift register 11 changes from a high level to a low level, the third transistor 46 is turned on, and the potential of the third node N3 stored in the first storage capacitor 45 is charged into the second node N2. In the entire time period of the light-emitting stage tc, the light-emitting control signal EM remains at a low level.

[0095] Optional, Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.11 The shift register shown in can be used to drive Figure 8 The pixel circuit shown. Figure 8 and Fig.11 When the potential writing unit 43 writes the potential of the third node N3 to the second node N2 of the pixel circuit 1 in the next row within the second time period t2, M=N+2 can be set; in the pixel circuit 1 of the nth row, the n+1th stage shift register 11 provides a scanning signal to the control end of the second transistor 44 as the potential grabbing control signal S3, and the n+2th stage shift register 11 provides a scanning signal to the control end of the third transistor 46 as the potential writing control signal S4.

[0096] Among them, the potential writing unit 43 writes the potential of the third node N3 to the second node N2 of the pixel circuit 1 of the next row in the second time period t2, which can also be interpreted as that in the same clamping module 4, the potential grabbing unit 42 can grab the potential of the third node N3 of the pixel circuit 1 of the previous row in the light-emitting phase of the pixel circuit 1 of the previous row, and the potential writing unit 43 writes the captured potential of the third node N3 into the second node N2 of the pixel circuit 1 of the current row in the light-emitting phase of the pixel circuit 1 of the current row. At this time, in order to ensure that the shift register 11 accurately controls the second transistor 44 in the potential grabbing unit 42 and the third transistor 46 in the potential writing unit 43, the number of shift registers 11 can be set to be 2 more than the number of pixel circuit 1 rows. And the scanning signal provided by the n+1-th stage shift register 11 is multiplexed into the potential grabbing control signal S3 received by the second transistor 44 in the pixel circuit 1 of the n-th row, and the second transistor 44 of the potential grabbing unit 42 in the pixel circuit 1 of the n-th row is turned on or off according to the scanning signal output by the n+1-th stage shift register 11. When the (n+1)th stage shift register 11 outputs a low level scanning signal, the second transistor 44 in the pixel circuit 1 of the nth row is turned on, and the second transistor 44 captures and stores the potential of the third node N3 of the pixel circuit 1 of the (n-1)th row.

[0097] Further, the scanning signal output by the n+2-th shift register 11 can be used to control the on or off of the third transistor 46 of the potential writing unit 43 in the clamping module 4, that is, the scanning signal output by the n+2-th shift register 11 is multiplexed into the potential writing control signal S4 received by the third transistor 46 in the n-th row pixel circuit 1. When the n+2-th shift register 11 outputs a low-level scanning signal, the third transistor 46 in the n-th row pixel circuit 1 is turned on, and the potential of the third node N3 of the n-1-th row pixel circuit 1 stored in the first storage capacitor 45 is written into the second node N2 of the pixel circuit 1.

[0098] Fig.12 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention, Figure 8 The pixel circuit 1 shown can be driven according to this driving timing. Taking the driving process of a pixel circuit 1 in the nth row as an example, Figure 8 , Fig.11 and Fig.12 , the driving process of the pixel circuit 1 in this embodiment is introduced. Fig.12 The subscripts of the stage marks in the figure indicate the row of pixel circuits 1. For example, tc n represents the light-emitting phase of the pixel circuit 1 in the nth row, tc n-1 It shows the light emitting phase of the pixel circuit 1 in the n-1th row.

[0099] like Figure 8 , Fig.11and Fig.12 As shown, the driving process of the pixel circuit 1 includes a reset phase ta n , Data writing phase tb n and luminous phase tc n During the reset phase, n : The reset control signal S1 output by the nth stage shift register 11 jumps from a high level to a low level, the reset transistor 51 is turned on, and the reset signal Vref is written into the first node N1; at the same time, the initialization transistor 91 is turned on, and the reset signal Vref is written into the anode of the light-emitting element 2, completing the resetting of the first node N1 and the anode of the light-emitting element 2.

[0100] In the data writing phase tb n : The data writing control signal S2 output by the n+1-th stage shift register 11 changes from a high level to a low level, the data writing transistor 81 is turned on, and the data signal Vdata is written into the first node N1 after passing through the driving transistor T3 and the compensation module 6; at the same time, the data writing control signal S2 is multiplexed into the potential grabbing control signal S3, and the second transistor 44 corresponding to the pixel circuit 1 is turned on. It can be understood by those skilled in the art that, under normal circumstances, there is an overlapping moment of the light emitting phases between the pixel circuits 1 in the adjacent row direction, and the pixel circuit 1 in the n-1th row can be set to be in the light emitting phase tc n-1 When the pixel circuit 1 of the nth row writes the data signal (such as Fig.11 As shown in FIG. 1 , the data writing phase tb of the pixel circuit 1 in the nth row n The light emitting phase tc of the pixel circuit 1 located in the n-1th row n-1 At this time, when the second transistor 44 of the pixel circuit 1 of the nth row is turned on, the second transistor 44 can capture the potential of the third node N3 of the pixel circuit 1 of the nth row in the light-emitting stage and store it in the first storage capacitor 45. In terms of time dimension, the first time period t1 and the data writing stage tb of the pixel circuit 1 of this row are n and the light emitting phase tc of the pixel circuit 1 in the previous row n-1 Partial overlap. In the above reset phase ta n and data writing phase tb n , the light emitting control signal EM(n) received by the pixel circuit 1 of the nth row is high level, and the light emitting control signal EM(n-1) received by the pixel circuit of the n-1th row is low level. In the data writing phase tb n , the light emitting control signal EM(n-1) received by the pixel circuit in the n-1th row is at a low level.

[0101] In the light-emitting stage tc n : The second time period t2 is in the light-emitting stage tc nIn the n+2nd stage, the potential writing control signal S4 output by the shift register 11 changes from high level to low level, the third transistor 46 is turned on, and the potential of the third node N3 of the pixel circuit 1 in the n-1th row stored in the first storage capacitor 45 is charged into the second node N2 of the pixel circuit 1 in the nth row. n During the entire time period, the light emitting control signal EM(n-1) of the pixel circuit 1 in this row (the pixel circuit 1 in the nth row) remains at a low level.

[0102] Fig.12 The advantage of the driving timing shown is that the effective time of the potential writing control signal S4 is earlier than the effective time of the light-emitting control signal EM(n-1) of this row, that is, before the light-emitting element 2 of this row emits light, the potential of the third node N3 stored in the first storage capacitor 45 has been written into the second node N2, which better ensures that the voltage difference between the second node N2 and the first node N1 is close to 0 during the entire light-emitting stage, thereby avoiding leakage.

[0103] It should be noted that the above embodiment only shows a group of shift registers 11 that transmit scan signals and are cascaded. Any shift register group known to those skilled in the art may also be set in the display panel, such as a light-emitting control shift register group 12, etc., but it is not limited thereto. In addition, the figure only shows the shift register 11 located on one side of the pixel circuit 1. If the pixel circuit is bilaterally driven, the shift registers 11 are set on both sides of the pixel circuit 1.

[0104] In the above embodiment, it is mentioned that the second plate c2 of the first storage capacitor 45 is connected to a fixed potential. The fixed potential can be set by those skilled in the art according to actual needs. It can be a newly added fixed potential or an existing fixed potential in the display panel.

[0105] You can continue to refer to Figure 6 and Figure 7 As an optional embodiment, the second plate c2 of the first storage capacitor 45 can be electrically connected to the cathode of the light emitting element 2. The cathode of the light emitting element 2 is connected to a fixed low potential, and the cathode of the light emitting element 2 can be directly connected to the second plate c2, thereby simplifying the preparation process of the potential grabbing unit 42.

[0106] In the display panel shown in the above embodiment, the clamping module 4 corresponding to each pixel circuit 1 includes a potential grabbing unit 42 and a potential writing unit 43. Optionally, in other possible embodiments, the display panel may include a plurality of pixel circuits 1 arranged in sequence along the row direction and the column direction respectively; all pixel circuits 1 or the clamping modules 4 in the pixel circuits 1 of the same row share the same potential grabbing unit 42.

[0107] Specifically, a plurality of pixel circuits 1 are arranged in sequence along the row direction and the column direction, and the column direction is the first direction. Among them, since the potential capture unit 42 is used to capture and store the potential of the third node N3 in the pixel circuit 1, different pixel circuits 1 can be set to share a potential capture unit 42, and the potential writing unit 43 in the pixel circuit 1 sharing the potential capture unit 42 is electrically connected to the same potential capture unit 42. For example, the clamping modules 4 of all pixel circuits 1 share a potential capture unit 42, and each clamping module 4 extracts the potential from the potential capture unit 42, and only one potential capture unit 42 can be set in the display panel. For another example, the clamping modules 4 of the pixel circuits 1 in the same row share a potential capture unit 42, and the clamping modules 4 in the same row extract the potential from the same potential capture unit 42. When N rows of pixel circuits 1 are provided in the display panel, N potential capture units 42 can be provided in the display panel.

[0108] Different pixel circuits 1 are provided with a common potential grabbing unit 42 , and there is no need to provide too many potential grabbing units 42 . The clamping module 4 occupies less space on the display panel, which is conducive to achieving a high PPI.

[0109] The control end of each transistor in the embodiment of the present invention may be a gate of the transistor, and the two ends of the transistor may be a source and a drain of the transistor.

[0110] Based on the same concept, an embodiment of the present invention further provides a display device, Fig.13 A schematic diagram of a display device according to an embodiment of the present invention is provided. Fig.13 , the display device may include any one of the display panels 100 provided in the above embodiments. Moreover, since the display device is made of the above display panel, it has the same or corresponding technical effects of the above display panel. It should be noted that the display device also includes other devices for supporting the normal operation of the display device. Specifically, the display device can be a mobile phone, a tablet, a computer, a television, a wearable smart device, etc., which is not limited by the embodiments of the present invention.

[0111] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: comprising a plurality of pixel circuits and a plurality of light emitting elements; The pixel circuit includes a driving transistor, a dual-gate transistor and a clamping module; The driving transistor is used to provide a driving current for the light emitting element, and the gate of the driving transistor and one end of the double-gate transistor are both connected to a first node; The dual-gate transistor includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node; The anode of the light emitting element is connected to the third node; The working process of the pixel circuit includes a light emitting phase, during which the first sub-transistor and the second sub-transistor are both turned off; The clamping module is connected to the second node and the third node respectively, and is used to clamp the potential of the second node to the potential of the third node during at least a part of the time period of the light emitting stage; The clamping module comprises a first transistor, two ends of the first transistor are respectively connected to the second node and the third node, and a control end of the first transistor receives a clamping control signal; the first transistor is used to be controlled by the clamping control signal and turned on during at least a part of the time period of the light emitting stage; or, The clamping module includes a potential grabbing unit and a potential writing unit, the potential grabbing unit is used to grab and store the potential of the third node in the pixel circuit within a first time period; the potential writing unit is used to write the potential of the third node to the same or different second node of the pixel circuit within a second time period; wherein, in the time dimension, the first time period at least partially overlaps with the light-emitting phase of the pixel circuit where the third node is located, the second time period at least partially overlaps with the light-emitting phase of the pixel circuit where the second node is located, and the second time period is located after the first time period.

2. The display panel according to claim 1, characterized in that: The pixel circuit further includes a reset module, the reset module is used to provide a reset signal for the first node in a reset phase, and the reset module includes the dual-gate transistor; or, The pixel circuit further includes a compensation module, which is used to detect and self-compensate for a deviation of a threshold voltage of the driving transistor during a threshold compensation stage, and the compensation module includes the dual-gate transistor.

3. The display panel according to claim 2, characterized in that: When the clamping module includes a first transistor and the reset module includes the dual-gate transistor, the first transistor is further configured to be controlled by the clamping control signal and to be turned off during the reset phase; When the compensation module includes the dual-gate transistor, the first transistor is further configured to be controlled by the clamp control signal and to be turned off during the threshold compensation stage.

4. The display panel according to claim 2, characterized in that: The pixel circuit further comprises a light emitting control module, which is connected in series with the driving transistor and the light emitting element respectively, and is used to control whether the driving current flows through the light emitting element; The light-emitting control module receives a light-emitting control signal, and in the light-emitting stage, the light-emitting control signal turns on the light-emitting control module; The light emitting control signal is multiplexed into the clamping control signal.

5. The display panel according to claim 2, characterized in that: When the clamping module includes the potential grabbing unit and the potential writing unit, the potential grabbing unit includes a second transistor and a first storage capacitor, two ends of the second transistor are electrically connected to a third node in the pixel circuit and a first plate of the first storage capacitor respectively, and a second plate of the first storage capacitor is connected to a fixed potential; The control end of the second transistor receives a potential grabbing control signal, and the second transistor is used to be turned on in the first time period under the control of the potential grabbing control signal; The potential writing unit includes a third transistor, the two ends of the third transistor are respectively electrically connected to the second node in the same or different pixel circuit and the first plate of the first storage capacitor, the control end of the third transistor receives a potential writing control signal, and the third transistor is used to be turned on in the second time period under the control of the potential writing control signal.

6. The display panel according to claim 5, characterized in that: When the reset module includes the dual-gate transistor, the third transistor is further used to be turned off during the reset phase under the control of the potential writing control signal; When the compensation module includes the dual-gate transistor, the third transistor is further configured to be turned off during the threshold compensation phase under the control of the potential writing control signal.

7. The display panel according to claim 5, characterized in that: The pixel circuit also includes a data writing module and a data storage module; The reset module is connected between the reset signal terminal and the first node, the control terminal of the reset module receives a reset control signal, and the reset module is used to provide a reset signal to the first node under the control of the reset control signal; The data writing module is connected to the data signal terminal and the first terminal of the driving transistor, and the control terminal of the data writing module receives a data writing control signal; The compensation module is connected between the second terminal of the driving transistor and the first node; the data storage module is connected between the first power supply voltage terminal and the first node; The data writing module is used to write a data signal to the first node via the driving transistor and the compensation module in sequence under the control of the data writing control signal, and the data storage module is used to store the data signal written to the first node.

8. The display panel according to claim 7, characterized in that: The display panel includes N rows of pixel circuits and M cascaded shift registers, wherein N and M are both positive integers greater than or equal to 1, and N<M; The shift register is used to provide a scanning signal to the pixel circuit, and the scanning signals provided by the shift registers at each level are sequentially shifted by the same distance in time sequence; In the pixel circuit of the nth row, the nth-stage shift register provides the scanning signal as the reset control signal to the control end of the reset module, and the n+1th-stage shift register provides the scanning signal as the data write control signal to the control end of the data write module; Here, n is a positive integer greater than or equal to 1 and less than or equal to N.

9. The display panel according to claim 8, characterized in that: When the potential writing unit writes the potential of the third node to the second node of the same pixel circuit in the second time period, M=N+3; In the pixel circuit of the nth row, the n+2th level shift register provides the scanning signal as the potential grabbing control signal to the control end of the second transistor, and the n+3th level shift register provides the scanning signal as the potential writing control signal to the control end of the third transistor.

10. The display panel according to claim 8, characterized in that: When the potential writing unit writes the potential of the third node into the second node of the pixel circuit of the next row in the second time period, M=N+2; In the pixel circuit of the nth row, the n+1th level shift register provides the scanning signal as the potential grabbing control signal to the control end of the second transistor, and the n+2th level shift register provides the scanning signal as the potential writing control signal to the control end of the third transistor.

11. The display panel according to claim 5, characterized in that: The second electrode plate of the first storage capacitor is electrically connected to the cathode of the light emitting element.

12. The display panel according to claim 1, characterized in that: The display panel comprises a plurality of pixel circuits sequentially arranged in a row direction and a column direction respectively; All the pixel circuits or the clamping modules in the pixel circuits in the same row share the same potential grabbing unit.

13. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-12.

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