Method of forming a semiconductor structure and semiconductor structure

By employing chemical mechanical polishing (CMP) technology in semiconductor structures to reduce the height difference of spin coatings, the problem of insufficient surface planarization of spin coatings is solved, thereby improving the performance and yield of semiconductor structures.

CN115497822BActive Publication Date: 2026-07-07CHANGXIN MEMORY TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHANGXIN MEMORY TECH INC
Filing Date
2022-10-18
Publication Date
2026-07-07

AI Technical Summary

Technical Problem

Because the patterned structures on the substrate have different pattern density effects, the spin coating has different thicknesses in dense and sparse regions with nested patterns, resulting in poor surface planarization, which affects subsequent process fabrication and reduces the performance of the semiconductor structure.

Method used

After forming a spin coating on the substrate, chemical mechanical polishing is used to reduce the height difference between the spin coating and the peripheral circuit area, thereby improving the planarization of the spin coating.

Benefits of technology

Chemical mechanical polishing technology reduces the step height difference of the spin coating, improves the flatness of the spin coating, reduces structural defects in subsequent processes, and improves product yield.

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Abstract

The present disclosure relates to a semiconductor structure forming method and a semiconductor structure. The semiconductor structure forming method comprises the following steps: providing a substrate, forming a pattern structure on the substrate, the pattern structure comprising an array region and a peripheral circuit region; forming a spin-on layer covering the array region and the peripheral circuit region on the substrate, wherein the spin-on layer has a height difference between a surface of the array region and a surface of the peripheral circuit region; and performing chemical mechanical polishing on the spin-on layer to reduce the height difference between the surface of the array region and the surface of the peripheral circuit region, thereby improving the planarization degree of the spin-on layer, reducing structural defects in subsequent processes, and improving product yield.
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