Test system and test method for power supply interference in semiconductor devices

Abstract

This invention relates to the field of semiconductor testing equipment, and discloses a testing system and method for power supply interference within semiconductor devices. The testing system includes a test circuit board with a power management chip and dynamic random access memory (DRAM) mounted on it, the power management chip being connected to the DRAM. The test circuit board also includes a capacitor module connected between the power management chip and the DRAM, and the capacitance value of the capacitor module is adjustable. When using the testing system for power supply interference within semiconductor devices provided by this disclosure, the capacitance value of the capacitor module can be continuously adjusted to discover the influence of the capacitance value on the interference signal, and even obtain a better interference signal. This allows for a clearer understanding of the impact of power supply noise on DRAM products during design and development, enabling more accurate analysis and troubleshooting, thereby increasing the testing coverage of DRAM products.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing equipment, and in particular to a testing system and method for testing power supply interference within semiconductor devices. Background Technology

[0002] In modern power electronic circuit design, the switching transistors of switching power supplies generate high-frequency interference during the on and off processes, and this interference (power noise) can affect the logic relationships of digital circuits to some extent. In the design, testing, and development of dynamic random access memory (DRAM), the quality of the power noise signal is a crucial parameter that directly determines whether the DRAM can function properly.

[0003] Therefore, there is an urgent need to provide a testing system that can more clearly understand the impact of power noise on DRAM products. Summary of the Invention

[0004] This invention discloses a test system and method for power noise in semiconductor devices. The test system can provide a clearer understanding of the impact of power noise on DRAM products.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] According to a first aspect of this disclosure, a test system for power supply interference in a semiconductor device is provided, comprising: a test circuit board, wherein a power management chip and a dynamic random access memory (DRAM) are disposed on the test circuit board, and the power management chip is connected to the DRAM;

[0007] The test circuit board is also equipped with a capacitor module, which is connected between the power management chip and the DRAM, and the capacitance value of the capacitor module is adjustable.

[0008] In one embodiment of this disclosure, the capacitor module includes a plurality of capacitors, each of which can be selectively connected between the power management chip and the DRAM, and the plurality of capacitors can be connected in parallel.

[0009] In one embodiment of this disclosure, a driving mechanism is further included. The driving mechanism is fixed in position relative to the test circuit board, and the output terminal of the driving mechanism is connected to the capacitor module to drive the capacitor in the capacitor module to move along a direction perpendicular to the test circuit board so as to selectively connect between the power management chip and the DRAM.

[0010] In one embodiment of this disclosure, the drive assembly includes a bracket and a cylinder, wherein:

[0011] The bracket is fixed in position relative to the test circuit board;

[0012] The cylinder includes a cylinder body and a piston rod. The cylinder body is fixed relative to the bracket. The output end of the piston rod extends from the cylinder body and is used to drive the capacitor module to move in a direction perpendicular to the test circuit board.

[0013] In one embodiment of this disclosure, a pressure head is further included, the pressure head being connected to the output end of the piston rod;

[0014] Multiple capacitors are mounted on the side of the pressure head facing the test circuit board, and the position of each capacitor relative to the pressure head is adjustable along the direction perpendicular to the test circuit board.

[0015] In one embodiment of this disclosure, the test circuit board is further provided with a wiring group, which connects the power management chip and the DRAM;

[0016] The capacitors in the capacitor module are arranged sequentially along the extension direction of the wiring group, and each capacitor can be selectively connected to the wiring group.

[0017] In one embodiment of this disclosure, the trace group is exposed on the surface of the test circuit board.

[0018] In one embodiment of this disclosure, the trace group includes a first metal line and a second metal line, wherein: a first end of the first metal line is connected to a voltage pin of the DRAM, and a second end of the first metal line is connected to a switch control pin of the power management chip; a first end of the second metal line is connected to a ground pin of the DRAM memory, and a second end of the second metal line is connected to a ground pin of the power management chip;

[0019] The capacitor in the capacitor module has an input pin and an output pin. The input pin is used to connect to the first metal wire, and the output pin is used to connect to the second metal wire.

[0020] In one embodiment of this disclosure, an impedance detection module is further included. The impedance detection module has a first pin and a second pin. The first pin is connected to a capacitor in the capacitor module that is connected to the test circuit board, and the second pin is connected to the ground pin of the test circuit board.

[0021] According to a second aspect of this disclosure, a method for testing power supply interference within a semiconductor device is provided, comprising:

[0022] Adjust the capacitance value of the capacitor module on the test circuit board that connects the power management chip and the dynamic random access memory (DRAM);

[0023] Test the DRAM and obtain the power supply noise value and operating status of the DRAM when it operates corresponding to the capacitance value.

[0024] In one embodiment of this disclosure, adjusting the capacitance value of the capacitor module connected between the power management chip and the DRAM on the test circuit board includes:

[0025] Adjust the number of capacitors in the capacitor module that connect the power management chip and the DRAM to adjust the capacitance value of the capacitor module.

[0026] In one embodiment of this disclosure, adjusting the number of capacitors in the capacitor module connected between the power management chip and the DRAM includes:

[0027] By adjusting the height difference of multiple capacitors in the capacitor module, a predetermined number of capacitors in the capacitor module are connected between the power management chip and the DRAM.

[0028] In one embodiment of this disclosure, the method of adjusting the height difference of multiple capacitors in the capacitor module includes:

[0029] Fine-tune the height difference of some capacitors in the capacitor module mounted on the same pressure head along the direction perpendicular to the test circuit board;

[0030] By driving the pressure head, the capacitor module is moved synchronously along the direction of the vertical test circuit board, so that a preset number of capacitors are connected between the power management chip and the DRAM.

[0031] In one embodiment of this disclosure, after obtaining the power supply noise value and operating state of the DRAM when it operates corresponding to the capacitance value, the testing method further includes:

[0032] By repeatedly adjusting the capacitance value of the capacitor module, the correspondence between the preset number of capacitors and the power supply noise value of the DRAM is obtained.

[0033] The system sends a correspondence relationship to the system so that after receiving the power noise value selected by the user, the system automatically adjusts the height values ​​of multiple capacitors on the pressure head according to the correspondence relationship and the input power noise value, so as to obtain a preset number of capacitors corresponding to the noise value.

[0034] In one embodiment of this disclosure, prior to testing the DRAM, the testing method further includes:

[0035] An impedance test is performed on each capacitor connected to the test circuit board in the capacitor module to determine whether the impedance value of the capacitor is less than or equal to a preset impedance value. If the impedance value of each capacitor is less than or equal to the preset impedance value, the impedance test is passed; if the impedance value of at least one capacitor is greater than the preset impedance value, the cylinder pressure is adjusted.

[0036] The semiconductor device internal power supply interference testing system disclosed herein includes a power management chip, a capacitor module, and dynamic random access memory (DRAM) on the test circuit board. The capacitor module is connected between the power management chip and the DRAM. When using this semiconductor device internal power supply interference testing system, the capacitance value of the capacitor module can be continuously adjusted to discover the effect of the capacitance value on the interference signal, and even obtain a better interference signal. This allows for a clearer understanding of the impact of power supply noise on DRAM products during the design and development process, enabling more accurate analysis and troubleshooting, thereby increasing the testing coverage of DRAM products. Attached Figure Description

[0037] Figure 1 A simplified schematic diagram of the structure of a test system for power supply interference within a semiconductor device provided in an embodiment of this disclosure;

[0038] Figure 2 for Figure 1 A magnified schematic diagram of the power management chip;

[0039] Figure 3 Another schematic diagram of a test system for power supply interference within a semiconductor device provided in an embodiment of this disclosure;

[0040] Figure 4 Another simplified structural diagram of a test system for power supply interference within a semiconductor device provided in an embodiment of this disclosure;

[0041] Figure 5 A schematic diagram of the user interface when using the test system for power supply interference in semiconductor devices provided in the embodiments of this disclosure;

[0042] Figure 6 An application flowchart of a test system for power supply interference within semiconductor devices provided in an embodiment of this disclosure;

[0043] Figure 7 A flowchart of a test method for power supply interference within a semiconductor device provided in an embodiment of this disclosure.

[0044] Icons: 1. Test circuit board; 100. Power management chip; 200. DRAM; 300. Capacitor module; 310. Capacitor; 400. Wiring group; 410. First metal line; 420. Second metal line; 2. Drive mechanism; 210. Bracket; 220. Cylinder; 230. Pressure head; 3. Impedance detection module. Detailed Implementation

[0045] Typical embodiments embodying the features and advantages of this disclosure will be described in detail in the following description. It should be understood that this disclosure can have various variations in different embodiments without departing from the scope of this disclosure, and the descriptions and drawings therein are illustrative in nature and not intended to limit this disclosure.

[0046] In the following description of various exemplary embodiments of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure, and which illustrate by way of example different exemplary structures, systems, and steps that may implement various aspects of this disclosure. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of this disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of this disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this disclosure.

[0047] In a first aspect, embodiments of this disclosure provide a test system for power supply interference within a semiconductor device. Figure 1 This is a schematic diagram of the structure of a test system for power supply interference within semiconductor devices, as shown below. Figure 1 The structure shown indicates that the test system for power supply interference within the semiconductor device includes: a test circuit board 1, on which a power management chip 100 (PMIC) and dynamic random access memory (DRAM) are provided, and the power management chip 100 is connected to the DRAM 200.

[0048] The test circuit board 1 is also equipped with a capacitor module 300, which is connected between the power management chip 100 and the DRAM 200, and the capacitance value of the capacitor module 300 is adjustable.

[0049] When using the test system for power supply interference in semiconductor devices provided in this embodiment, the capacitance value of the capacitor module 300 can be continuously adjusted to discover the effect of the capacitance value on the interference signal, and even obtain a better interference signal. This allows for a clearer understanding of the impact of power supply noise on DRAM200 products during the design and development process, enabling more accurate analysis and troubleshooting, thereby increasing the test coverage of DRAM200 products.

[0050] It should be understood that the value of the capacitance reflects the magnitude of the power supply noise (i.e., interference signal); and the power supply noise is the noise generated by the power supply, which will affect the operation of the DRAM. When the DRAM200 is working, there are certain requirements for the power supply noise. The test system provided in this embodiment can obtain a better power supply noise value to ensure the stable operation of the DRAM200.

[0051] It is worth noting that the power supply interference testing system for semiconductor devices provided in this disclosure can achieve batch testing of interference signals during production and testing. Specifically, for the same DRAM, the capacitance value of the capacitor module 300 can be continuously adjusted to test for shmoo interference signals; different DRAMs 200 can be placed sequentially on the test circuit board 1 for testing.

[0052] It should be understood that shmoo refers to obtaining a reasonable noise value for DRAM200 during operation by measuring power supply noise under different capacitance values.

[0053] Furthermore, it is worth noting that the semiconductor device power supply interference testing system provided in this disclosure can be widely applied to production line testing and R&D processes of memory modules such as PCs (personal computers) and servers.

[0054] When specifically configuring the capacitor module 300, there are multiple possibilities for its structure in order to achieve the function of adjusting the capacitance value.

[0055] In one embodiment, please refer to... Figure 1 As shown in the structure, the capacitor module 300 includes multiple capacitors 310, each of which can be selectively connected between the power management chip 100 and the DRAM 200, and the multiple capacitors 310 can be connected in parallel.

[0056] Specifically, the resistance value of the capacitor module 300 can be adjusted by changing the number of capacitors 310 connected to the power management chip 100 and the DRAM 200. It should be understood that when the multiple capacitors 310 in the capacitor module 300 are connected to the power management chip 100 and the DRAM 200, the multiple capacitors 310 form a parallel relationship.

[0057] It should be noted that in this embodiment, the method of adjusting the capacitance value of the capacitor module 300 is to adjust the number of capacitors 310. This method allows the power supply noise to change proportionally according to the number of capacitors 310 connected between the power management chip 100 and the DRAM 200, so as to more easily discover the influence of the capacitance value on the interference signal, and even obtain a better interference signal. In the design and development process, the impact of power supply noise on the DRAM 200 product can be more clearly understood, and the faults can be analyzed and eliminated more accurately, thereby increasing the test coverage of the DRAM 200 product.

[0058] It is worth noting that the more capacitors 310 there are, the greater the power supply noise becomes, and the power supply noise value increases proportionally with the number of capacitors 310. For example, the power supply noise value corresponding to one capacitor 310 is 200mV, two capacitors 310 correspond to 150mV, three capacitors 310 correspond to 100mV, and four capacitors 310 correspond to 50mV.

[0059] Of course, a variable capacitance value capacitor 310 can also be used as the capacitor module 300. However, the adjustment effect of using a variable capacitance value capacitor 310 to adjust the capacitance value cannot completely achieve the effect of adjusting the number of capacitors. The filtering effect of the variable capacitance value capacitor 310 on the DRAM200 needs to be considered. The specific settings can be made according to the requirements, which will not be elaborated here.

[0060] In one embodiment, please refer to Figure 3 and Figure 4 As shown in the structure, the test system for power interference in semiconductor devices provided in this embodiment of the present disclosure further includes a drive mechanism 2. The drive mechanism 2 is fixed in position relative to the test circuit board 1, and the output end of the drive mechanism 2 is connected to the capacitor module 300 to drive the capacitor 310 in the capacitor module 300 to move along the direction perpendicular to the test circuit board 1 so as to selectively connect between the power management chip 100 and the DRAM 200.

[0061] It should be noted that by controlling the selective connection between the capacitor module 300 and the test circuit board 1 through the drive mechanism 2, the automation level of the entire system can be improved, which facilitates the improvement of testing efficiency. At the same time, since the drive mechanism 2 controls the connection between the capacitor module 300 and the test circuit board 1, the magnitude of the force between the capacitor module 300 and the test circuit board 1 can be controlled, which can improve the contact effect between the capacitor 310 and the test circuit board 1.

[0062] When configuring the driver component, there are several possible structures for it, at least one of the following structures.

[0063] In one embodiment, please refer to... Figure 3 and Figure 4 The structure shown includes a drive assembly comprising a bracket 210 and a cylinder 220, wherein:

[0064] The bracket 210 is fixed in position relative to the test circuit board 1;

[0065] The cylinder 220 includes a cylinder body and a piston rod. The cylinder body is fixed relative to the bracket 210. The output end of the piston rod extends from the cylinder body and is used to drive the capacitor module 300 to move along the direction perpendicular to the test circuit board 1.

[0066] It should be noted that the method of using cylinder 220 to press down on capacitor 310 to make capacitor 310 contact with test circuit board 1 has the following advantages compared with traditional robotic arms: uniform force, which allows capacitor 310 to make good contact with test circuit board 1 of the test platform; and strong pressure controllability, which avoids capacitor 310 being damaged due to excessive pressure.

[0067] In setting the specific structure of the drive component and capacitor module 300, in one embodiment, please continue to refer to... Figure 2 and Figure 3 The structure shown in this disclosure, the test system for power supply interference in semiconductor devices provided in this embodiment also includes a pressure head 230, which is connected to the output end of the piston rod;

[0068] Multiple capacitors 310 are mounted on the side of the pressure head 230 facing the test circuit board 1, and the position of each capacitor 310 relative to the pressure head 230 is adjustable along the direction perpendicular to the test circuit board 1.

[0069] It should be noted that in the semiconductor device power interference test system provided in this embodiment, multiple capacitors 310 are mounted on the same pressure head 230. In other words, multiple capacitors 310 are driven by the same cylinder 220, which can improve the uniformity of the descent height of multiple capacitors 310, ensure that the pressure between multiple capacitors 310 and the test circuit board 1 is the same, facilitate control, and simplify the overall structure of the system.

[0070] Please continue to refer to Figure 3 and Figure 4 The structure shown allows for selective connection of each capacitor 310 in the capacitor module 300 to the test circuit board 1, and the height of each capacitor 310 relative to the pressure head 230 can be finely adjusted. It should be understood that any mechanical mechanism capable of fine-tuning the capacitor 310 relative to the pressure head 230 can be applied to the semiconductor device power supply interference testing system provided in this embodiment of the disclosure, and will not be elaborated further here.

[0071] For example, when applying the test system for power supply interference in semiconductor devices provided in this disclosure, taking four capacitors 310 as an example, before the system starts testing DRAM 200, three of the four capacitors 310 are pre-connected to the test circuit board 1. Then, one capacitor 310 is finely adjusted relative to the pressure head 230 and moves away from the test circuit board 1. At this time, the other three capacitors 310 are at the same height on the side surface facing the test circuit board 1. Afterwards, the driving mechanism 2 can be used to drive the capacitor module 300 to move closer to the test circuit board 1 so that the three capacitors 310 contact the test circuit board 1.

[0072] In another embodiment, each capacitor 310 can be driven by a set of cylinders 220 to achieve individual driving function for each capacitor 310. It is worth noting that in this embodiment, the distance between each capacitor 310 and the test circuit board 1 can be controlled individually, which can improve the automation level of the device.

[0073] In one embodiment, please refer to... Figure 1 As shown in the structure, the test circuit board 1 is also provided with a wiring group 400, which connects the power management chip 100 and the DRAM 200.

[0074] Multiple capacitors 310 within the capacitor module 300 are arranged sequentially along the extension direction of the wiring group 400, and each capacitor 310 can be selectively connected to the wiring group 400.

[0075] It should be noted that the multiple capacitors 310 are arranged in sequence, which makes it easy to adjust which position of the capacitor 310 in the capacitor module 300 is in contact with the test circuit board 1, thereby reducing the difficulty of operation and improving the efficiency of operation.

[0076] In one embodiment, please refer to... Figure 1 As shown in the diagram, trace group 400 is exposed on the surface of test circuit board 1.

[0077] It should be noted that this structural design facilitates the connection of capacitor 310 in capacitor module 300 to test circuit board 1, which can reduce testing difficulty and improve testing efficiency.

[0078] When setting the structure of the trace group 400, the trace group 400 can be exposed on the surface of the test circuit board 1 as a whole, or it can be exposed on the surface of the test circuit board 1 at the mounting position of the corresponding capacitor module 300. The specific settings can be made according to the requirements, and will not be elaborated here.

[0079] In one embodiment, please refer to... Figure 1As shown in the structure, the trace group 400 includes a first metal line 410 and a second metal line 420, wherein: the first end of the first metal line 410 is connected to the voltage pin of the DRAM 200, and the second end of the first metal line 410 is connected to the switch control pin of the power management chip 100; the first end of the second metal line 420 is connected to the ground pin of the DRAM 200 memory, and the second end of the second metal line 420 is connected to the ground pin of the power management chip 100;

[0080] The capacitor 310 in the capacitor module 300 has an input pin and an output pin. The input pin is used to connect to the first metal line 410, and the output pin is used to connect to the second metal line 420.

[0081] Specifically, the test circuit board 1 has a first metal line 410 (VDD high potential) and a second metal line 420 (GND ground) exposed on the surface; the capacitors 310 in the capacitor module 300 can be selectively connected to the trace group 400. When the capacitors 310 are connected to the trace group 400, the input pin of each capacitor 310 is connected to the first metal line, and the output pin of each capacitor 310 is connected to the second metal line 420.

[0082] Regarding the connection relationship between the first metal line 410 and the second metal line 420 and the DRAM 200: the first end of the first metal line 410 is connected to the voltage pin of the DRAM 200, and the first end of the second metal line 420 is connected to the ground pin of the DRAM 200.

[0083] Regarding the connection relationship between the first metal line 410 and the second metal line 420 and the power management chip 100: the second end of the first metal line 410 is connected to the switch control pin (SW) of the power management chip 100; the second end of the second metal line 420 is connected to the ground pin (GND) of the power management chip 100.

[0084] It is worth noting that the power management chip 100 also has many other pins, and these pins can be configured as needed. For examples, please refer to [link / reference needed]. Figure 1 and Figure 2 As shown in the diagram, the power management chip 100 also includes the following pins:

[0085] Vin: Power input pin, used to connect to the input power supply; BST: Booster pin; SW: Switch control pin; EN: Enable pin; FB: Input voltage feedback pin; GND: Ground pin;

[0086] C1: First capacitor 310, used for filtering; C2: Second capacitor 310, also known as bootstrap capacitor 310, which is connected to BST and SW; L1: Inductor, used for voltage reduction and energy storage; Resistors R1 and R2 form a voltage divider network; C3: Third capacitor 310, used to improve feedback speed; C4: Fourth capacitor 310, used for filtering.

[0087] It should be understood that the power management chip 100 can also adopt other pin layouts, which will not be elaborated here.

[0088] In one embodiment, please refer to... Figure 4 As shown in the diagram, the semiconductor device power supply interference testing system provided in this embodiment of the disclosure further includes an impedance detection module 3. The impedance detection module 3 has a first pin and a second pin. The first pin is connected to the capacitor 310 in the capacitor module 300, and the second pin is connected to the ground pin of the test circuit board 1. It should be understood that the ground pin of the test circuit board 1 can be a separate pin or it can be integrated into the second metal line 420.

[0089] It should be noted that an impedance detection module 3 is provided at the contact point between capacitor 310 and test circuit board 1. The contact impedance between capacitor 310 and test circuit board 1 can be adjusted by adjusting the pressure of cylinder 220. When the impedance test value is less than or equal to the preset impedance value, it indicates that the contact is good and can be tested.

[0090] It is worth noting that after the power supply noise and the working relationship between DRAM 200 are tested using the power supply interference test system provided in this embodiment of the semiconductor device, an automated test system can be subsequently formed. For example, a ratio between the number of capacitors 310 and the power supply noise can be preset to form a test interface. For example, as shown... Figure 5 As shown, a test interface can be created, displaying different power supply noise values, such as 200mV, 150mV, 100mV, and 50mV. When applying this, please combine it with... Figures 1 to 5 refer to Figure 6The structure shown allows selection of a power noise option for shmoothing. The system automatically adjusts the height difference of capacitors 310 on the pressure head 230 to control the number of capacitors 310 in contact with the test circuit board 1. Once the heights of multiple capacitors 310 on the pressure head 230 are adjusted, the cylinder 220 presses down as a whole, causing some capacitors 310 to make contact with the test circuit board 1. At this point, an impedance test can be performed on each capacitor 310 connected to the test circuit board 1 in the capacitor module 300 to determine whether the impedance value Z1 of the capacitor 310 is less than or equal to the preset impedance value Zspec. If the impedance value Z1 of each capacitor 310 is less than or equal to the preset impedance value Zspec, the impedance test is passed. If the impedance value Z1 of at least one capacitor 310 is greater than the preset impedance value Zspec, the pressure of the cylinder 220 is adjusted to control the downward pressure of the pressure head 230.

[0091] Please continue to refer to this. Figure 6 The structure shown allows for formal testing of the DRAM200's operating status after passing impedance testing.

[0092] Secondly, embodiments of this disclosure also provide a method for testing power supply interference within a semiconductor device. Figure 7 A flowchart illustrating a method for testing power supply interference within a semiconductor device according to embodiments of this disclosure. Please refer to... Figure 7 The method for testing power supply interference within a semiconductor device, as shown in this embodiment, includes:

[0093] Step S702: Adjust the capacitance value of the capacitor module 300 on the test circuit board 1, which is connected between the power management chip 100 and the dynamic random access memory DRAM 200.

[0094] Step S704: Test DRAM200 and obtain the power supply noise value and operating status of DRAM200 when it is operating according to the capacitance value.

[0095] It should be noted that in the test method for power supply interference in semiconductor devices provided in this embodiment, the capacitor module 300 connected between the capacitor 310 management chip and the DRAM 200 memory can be adjusted as needed. Specifically, the power supply noise value and working status of the DRAM 200 with each corresponding capacitance value can be obtained. The capacitance value of the capacitor module 300 can be continuously adjusted to discover the influence of the capacitance value on the interference signal of the DRAM 200 memory, and even obtain a better interference signal. This allows for a clearer understanding of the impact of power supply noise on the DRAM 200 product during the design and development process, more accurate analysis and troubleshooting, and thus increased test coverage of the DRAM 200 product.

[0096] In one embodiment, step S702, adjusting the capacitance value of the capacitor module 300 connected between the power management chip 100 and the DRAM 200 on the test circuit board 1, includes:

[0097] Adjust the number of capacitors 310 in capacitor module 300 that are connected between power management chip 100 and DRAM 200 to adjust the capacitance value of capacitor module 300.

[0098] It should be noted that since the number of capacitors 310 varies by a specific value, for example, the number of capacitors 310 in capacitor module 300 used to connect to test circuit board 1 varies by an integer multiple, such as 1, 2, 3, etc., which can more accurately determine the impact of the size of capacitors 310 on power supply noise.

[0099] In one embodiment, adjusting the number of capacitors 310 in the capacitor module 300 connected between the power management chip 100 and the DRAM 200 includes:

[0100] By adjusting the height difference of multiple capacitors 310 in the capacitor module 300, a preset number of capacitors 310 in the capacitor module 300 are connected between the power management chip 100 and the DRAM 200.

[0101] It should be noted that, taking a single capacitor 310 as an example, by adjusting the height difference between capacitor 310 in capacitor module 300 and test circuit board 1, it is possible to control whether capacitor 310 can be connected between power management chip 100 and DRAM 200. Therefore, by adjusting the height difference of multiple capacitors 310 in capacitor module 300, a preset number of capacitors 310 in capacitor module 300 can be controlled to be connected between power management chip 100 and DRAM 200. This control process is simple, easy to implement, and can improve operational efficiency.

[0102] In one embodiment, adjusting the height difference of multiple capacitors 310 in the capacitor module 300 includes:

[0103] Along the direction of the vertical test circuit board 1, fine-tune the height difference of some capacitors 310 in the capacitor module 300 installed on the same pressure head 230.

[0104] By driving the pressure head 230, the capacitor module 300 is moved synchronously along the direction of the vertical test circuit board 1, so that a preset number of capacitors 310 are connected between the power management chip 100 and the DRAM 200.

[0105] It is worth noting that, in order to allow each capacitor 310 in the capacitor module 300 to be selectively connected to the test circuit board 1, the height of each capacitor 310 relative to the pressure head 230 can be finely adjusted. It should be understood that any mechanical mechanism capable of finely adjusting the capacitor 310 relative to the pressure head 230 can be used, and the application of the test method for power supply interference within semiconductor devices provided in this disclosure embodiment will not be elaborated further here.

[0106] After the height difference of each capacitor 310 on the pressure head 230 is adjusted, the pressure head 230 can be moved to synchronously drive each capacitor 310 to move. For example, multiple capacitors 310 can be installed on the same pressure head 230 and driven by the same cylinder 220 to improve the uniformity of the descent height of the multiple capacitors 310, ensuring that the pressure between each capacitor 310 and the test circuit board 1 is the same, facilitating control and simplifying the overall system structure. Of course, other structures can also be used to drive the pressure head 230, which will not be elaborated further. It should be understood that the "preset number" refers to the number of capacitors 310 in the capacitor module 300 that will be connected to the test circuit board 1, and this preset number varies according to testing requirements.

[0107] In addition, it should be noted that the method of using cylinder 220 to press down capacitor 310 to make capacitor 310 contact with test circuit board 1 has the following advantages compared with traditional robotic arms: uniform force, which allows capacitor 310 to make good contact with test circuit board 1 of test platform; and strong pressure controllability, which avoids capacitor 310 being damaged due to excessive pressure.

[0108] In one embodiment, after obtaining the power supply noise value and operating state of the DRAM200 when operating corresponding to the capacitance value, the testing method further includes:

[0109] By repeatedly adjusting the capacitance value of capacitor module 300, the corresponding relationship between the preset number of capacitors 310 and the power supply noise value of DRAM200 is obtained.

[0110] The system sends a correspondence relationship to the power noise value selected by the user, so that after receiving the power noise value, the system can automatically adjust the height of multiple capacitors 310 on the pressure head 230 according to the correspondence relationship and the input power noise value, so as to obtain a preset number of capacitors 310 corresponding to the noise value.

[0111] It should be noted that, based on the testing method provided in this disclosure, after multiple tests, a correspondence between the noise value and the preset number of capacitors 310 can be obtained. This known relationship can then be applied in reverse to adjust the capacitors 310, simplifying the testing process. For example, the correspondence between the noise value and the preset number can be sent to the system so that, upon receiving the noise value selected by the user, the system automatically adjusts the height of multiple capacitors 310 on the pressure head 230 according to the correspondence and the input noise value, thereby obtaining the preset number of capacitors 310 corresponding to the noise value for testing the DRAM 200.

[0112] In one embodiment, a predetermined number of capacitors 310 are connected between the power management chip 100 and the DRAM 200, including:

[0113] Different numbers of capacitors 310 in the control capacitor module 300 contact the trace group 400 exposed on the surface of the test circuit board 1. The trace group 400 connects the power management chip 100 and the DRAM 200.

[0114] It should be noted that by controlling the capacitor 310 in the capacitor module 300 to be connected to the trace group 400 exposed on the surface of the test circuit board 1, the testing difficulty can be reduced and the testing efficiency can be improved.

[0115] In one embodiment, before performing step S704 (testing DRAM200), the test method further includes:

[0116] An impedance test is performed on each capacitor 310 in the capacitor module 300 that is connected to the test circuit board 1 to determine whether the impedance value of the capacitor 310 is less than or equal to the preset impedance value. If the impedance value of each capacitor 310 is less than or equal to the preset impedance value, the impedance test is passed. If the impedance value of at least one capacitor 310 is greater than the preset impedance value, the pressure of the cylinder 220 is adjusted.

[0117] It should be noted that by performing impedance testing on each capacitor 310 in the capacitor module 300 connected to the test circuit board 1, the connection status between the capacitor 310 and the test circuit board 1 can be detected; and by setting a preset impedance value, it can be ensured that the impedance between the capacitor 310 and the test circuit board 1 meets the measurement requirements, so as to obtain a more accurate ratio between the capacitor 310 and the power supply noise.

[0118] In one specific embodiment, the method for performing impedance testing on each capacitor 310 in the capacitor module 300 connected to the test circuit board 1 includes:

[0119] Connect the first pin of the impedance test module to the capacitor 310 in the capacitor module 300, and connect the second pin of the impedance detection module 3 to the ground pin of the test circuit board 1.

[0120] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and exemplary embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0121] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A test system for power supply interference within a semiconductor device, characterized in that, include: A test circuit board, wherein a power management chip and a dynamic random access memory (DRAM) are provided on the test circuit board, and the power management chip is connected to the DRAM. The test circuit board is also equipped with a capacitor module, which is connected between the power management chip and the DRAM, and the capacitance value of the capacitor module is adjustable. The capacitor module includes multiple capacitors, each of which can be selectively connected between the power management chip and the DRAM, and the multiple capacitors can be connected in parallel. It also includes a drive mechanism, which is fixed in position relative to the test circuit board, and the output end of the drive mechanism is connected to the capacitor module to drive the capacitor in the capacitor module to move along a direction perpendicular to the test circuit board so as to selectively connect between the power management chip and the DRAM.

2. The test system for power supply interference within a semiconductor device according to claim 1, characterized in that, The drive mechanism includes a bracket and a cylinder, wherein: The bracket is fixed in position relative to the test circuit board; The cylinder includes a cylinder body and a piston rod. The cylinder body is fixed relative to the bracket. The output end of the piston rod extends from the cylinder body and is used to drive the capacitor module to move in a direction perpendicular to the test circuit board.

3. The test system for power supply interference within a semiconductor device according to claim 2, characterized in that, It also includes a pressure head, which is connected to the output end of the piston rod; Multiple capacitors are mounted on the side of the pressure head facing the test circuit board, and the position of each capacitor relative to the pressure head is adjustable along the direction perpendicular to the test circuit board.

4. The test system for power supply interference in semiconductor devices according to any one of claims 1-3, characterized in that, The test circuit board is also provided with a wiring group, which connects the power management chip and the DRAM. The capacitors in the capacitor module are arranged sequentially along the extension direction of the wiring group, and each capacitor can be selectively connected to the wiring group.

5. The test system for power supply interference within a semiconductor device according to claim 4, characterized in that, The trace group is exposed on the surface of the test circuit board.

6. The test system for power supply interference within a semiconductor device according to claim 5, characterized in that, The trace group includes a first metal line and a second metal line, wherein: a first end of the first metal line is connected to the voltage pin of the DRAM, and a second end of the first metal line is connected to the switch control pin of the power management chip; a first end of the second metal line is connected to the ground pin of the DRAM memory, and a second end of the second metal line is connected to the ground pin of the power management chip; The capacitor in the capacitor module has an input pin and an output pin. The input pin is used to connect to the first metal wire, and the output pin is used to connect to the second metal wire.

7. The test system for power supply interference in a semiconductor device according to any one of claims 1-3, characterized in that, It also includes an impedance detection module, which has a first pin and a second pin. The first pin is connected to the capacitor in the capacitor module that is connected to the test circuit board, and the second pin is connected to the ground pin of the test circuit board.

8. A method for testing power supply interference within a semiconductor device, characterized in that, include: Adjust the capacitance value of the capacitor module on the test circuit board that connects the power management chip and the dynamic random access memory (DRAM); Test the DRAM and obtain the power supply noise value and operating status of the DRAM when it operates corresponding to the capacitor value; Adjusting the capacitance value of the capacitor module connected between the power management chip and the DRAM on the test circuit board includes: Adjust the number of capacitors in the capacitor module that connect the power management chip and the DRAM to adjust the capacitance value of the capacitor module; Adjusting the number of capacitors in the capacitor module connected between the power management chip and the DRAM includes: By adjusting the height difference of multiple capacitors in the capacitor module, a predetermined number of capacitors in the capacitor module are connected between the power management chip and the DRAM.

9. The method for testing power supply interference within a semiconductor device as described in claim 8, characterized in that, The method for adjusting the height difference of multiple capacitors in the capacitor module includes: Fine-tune the height difference of some capacitors in the capacitor module mounted on the same pressure head along the direction perpendicular to the test circuit board; By driving the pressure head, the capacitor module is moved synchronously along the direction of the vertical test circuit board, so that a preset number of capacitors are connected between the power management chip and the DRAM.

10. The method for testing power supply interference within a semiconductor device as described in claim 9, characterized in that, After obtaining the power supply noise value and operating state of the DRAM when it operates corresponding to the capacitance value, the testing method further includes: By repeatedly adjusting the capacitance value of the capacitor module, the correspondence between the preset number of capacitors and the power supply noise value of the DRAM is obtained. The system sends a correspondence relationship to the system so that after receiving the power noise value selected by the user, the system automatically adjusts the height values ​​of multiple capacitors on the pressure head according to the correspondence relationship and the input power noise value, so as to obtain a preset number of capacitors corresponding to the noise value.

11. The method for testing power supply interference within a semiconductor device according to any one of claims 8-10, characterized in that, Before testing the DRAM, the testing method further includes: An impedance test is performed on each capacitor in the capacitor module connected to the test circuit board to determine whether the impedance value of the capacitor is less than or equal to a preset impedance value. If the impedance value of each capacitor is less than or equal to the preset impedance value, the impedance test is passed. If the impedance value of at least one capacitor is greater than the preset impedance value, the cylinder pressure is adjusted. The cylinder pressure is used to adjust the contact impedance between the capacitor and the test circuit board.

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