A structure for testing the on-resistance of silicon-silicon bonding and its fabrication method

Abstract

This invention provides a structure and its fabrication method for testing the on-resistance of silicon-silicon bonding. The method includes taking a first SOI silicon wafer and a second SOI silicon wafer; fabricating a boss bonded to the second SOI silicon wafer and a lower structural layer silicon lead connected to the boss on the top silicon layer of the first SOI silicon wafer; forming a protective oxide layer on the surface of the top silicon layer of the first SOI silicon wafer; removing the oxide layer from the surface of the boss; directly bonding the second SOI top silicon layer to the boss surface to form upper and lower layers; removing the second SOI silicon substrate to expose the top silicon layer; and fabricating metal PADs and upper structural layer silicon leads on the surface of this layer. This invention features simple steps, a clear and straightforward three-dimensional cross structure, and is suitable for non-destructive evaluation of silicon-silicon bonding quality in SOI bulk silicon MEMS processes.

Description

Technical fields:

[0001] This invention relates to the field of microelectromechanical technology, specifically to a structure for testing the on-resistance of a silicon-silicon bonded three-dimensional cross structure in MEMS and its fabrication method. Background technology:

[0002] SOI (Solid Silicon Insulation) MEMS fabrication technology uses silicon-to-silicon bonding to connect two SOI wafers together to form a three-dimensional structure. The thickness of the structural layers of the MEMS device is precisely controlled by the thickness of the top layer of the SOI wafer, effectively ensuring the stability and high precision of the device's performance. It is suitable for the mass production of high-performance MEMS inertial devices, including gyroscopes, accelerometers, and vibration sensors, as well as MEMS optical devices, including optical switches, 2D scanning mirrors, and attenuators. It is currently a mainstream fabrication process and a development trend.

[0003] Two SOI silicon wafers can be directly bonded together through high-temperature treatment without any adhesive or external electric field. This bonding technology is called silicon-to-silicon direct bonding (SDB). The quality of the bond depends on the bonding temperature, the flatness of the silicon wafer surface, and the cleanliness of the silicon wafer surface. Currently, the quality of silicon-to-silicon bonding can only be assessed through a highly destructive method such as shear force testing; no standardized testing and evaluation method for MEMS silicon-to-silicon bonding quality has yet been established. Summary of the Invention:

[0004] The present invention aims to overcome the shortcomings of the prior art by providing a structure for testing the on-resistance of silicon-silicon bonding and its preparation method.

[0005] This application provides the following technical solution:

[0006] A structure for testing the on-resistance of silicon-silicon bonding includes a first SOI silicon wafer, characterized in that: a set of recesses are provided on the first SOI silicon wafer, thereby forming a set of protrusions on the first SOI silicon wafer, a silicon lead is connected in the recess between two of the protrusions, a second top layer silicon on the same second SOI silicon wafer is connected to the protrusion, a second silicon lead is connected between the top layer silicon above two of the protrusions, and a set of PAD points are provided on the second top layer silicon.

[0007] Based on the above technical solutions, the following further technical solutions are also possible:

[0008] The set of protrusions consists of five protrusions, one of which is located at the center of the first SOI silicon wafer, and the other four are distributed in different directions, so that the five protrusions are arranged in a cross shape.

[0009] The silicon leads and the second silicon lead are arranged in a cross shape along their axial direction.

[0010] A method for fabricating a silicon-silicon bonding on-resistance structure, characterized by comprising the following steps:

[0011] S1. Fabrication of the lower structure: Take the first SOI silicon wafer and the second SOI silicon wafer, and use photolithography and ICP deep silicon etching technology to fabricate a set of protrusions on the top silicon layer of the first SOI silicon wafer to form the lower structure.

[0012] S2. Fabrication of lower structure layer silicon leads: Using photolithography and ICP deep silicon etching technology, the top silicon of the first SOI silicon wafer is etched to the buried oxide layer, and the silicon between several protrusions is retained as silicon leads. Then, an oxide layer is grown on the protrusions and silicon leads through an oxidation process.

[0013] S3. Remove the oxide layer on the bonding surface: Use photolithography and wet etching techniques to remove the oxide layer on the upper surface of the boss, and remove a certain thickness of SiO2 to ensure the flatness of the upper surface of the boss.

[0014] S4. Direct bonding between the lower and upper structural layers: The second top silicon layer of the second SOI silicon wafer is used as the upper structural layer. The top silicon layers of the first and second SOI silicon wafers are directly bonded using a silicon-to-silicon direct bonding process. The bottom silicon layer and buried oxide layer of the second SOI silicon wafer are removed using CMP thinning and polishing technology and KOH etching technology.

[0015] S5. Prepare metal PAD points on the surface of the upper structural layer: Sputter a pure aluminum layer on the surface of the bonded upper structural layer, and then apply photoresist on the pure aluminum layer according to the silicon lead pattern and the PAD point pattern.

[0016] S6. Fabrication of upper structural layer silicon leads: The silicon lead pattern of the upper structural layer is obtained through photolithography. Then, the structure is released using ICP deep silicon etching technology to form the upper second silicon lead that contacts the upper and lower structural layers. A certain gap is formed between the second silicon lead and the lower structure.

[0017] Advantages of the invention:

[0018] This invention features simple steps, a clear and straightforward three-dimensional cross structure, and is suitable for non-destructive evaluation of silicon-silicon bonding quality in SOI bulk silicon MEMS processes. Attached image description:

[0019] Figure 1 This is a top view of the completed product of this invention.

[0020] Figure 2 yes Figure 1 A sectional view of line A-A' in the diagram;

[0021] Figure 3 yes Figure 1The sectional view of B-B' in the diagram;

[0022] Figure 4 yes Figure 1 A sectional view of A-B' in the diagram;

[0023] Figure 5 This is a schematic diagram of the three-dimensional structure during testing after molding;

[0024] Figure 6 This is a structural diagram after step S2 is completed;

[0025] Figure 7 This is a structural diagram after step S3 is completed;

[0026] Figure 8 This is a structural diagram after step S4 is completed;

[0027] Figure 9 This is a structural diagram after step S5 is completed;

[0028] Figure 10 This is a structural diagram after step S6 is completed. Detailed implementation method:

[0029] like Figure 1-5 As shown, a structure for testing silicon-silicon bonding on-resistance includes a first SOI silicon wafer 1, with a set of recesses 9 on the top silicon layer of the first SOI silicon wafer 1, thereby forming a set of protrusions 10 on the first SOI silicon wafer 1.

[0030] The set of protrusions 10 consists of five protrusions, one of which is located at the center of the first SOI silicon wafer 1, and the other four are distributed in different directions, so that the five protrusions 10 are arranged in a cross shape. The protrusion 10 located at the center has a smaller area than the other protrusions 10. This forms the on-resistance structure of the first SOI silicon wafer 1 and the second SOI silicon wafer 2 (mentioned below).

[0031] Silicon leads 12 are distributed within the recesses 9 between the three protrusions 10 and are connected in a straight line. The thickness of the silicon leads 12 is less than the thickness of the protrusions 10.

[0032] A second top layer silicon 2a from the same second SOI silicon wafer 2 is bonded to the upper end of all the bosses 10. A section of the second top layer silicon is retained between the top layer silicon 2a above two bosses 10, thereby forming a second silicon lead 16 connecting the two top layer silicon 2a. The middle part of the second silicon lead 16 is connected to the top of the boss 10 located at the center of the first SOI silicon wafer 1, and is distributed in a cross shape with the silicon lead 12 along the axial direction.

[0033] PAD points 15 are provided on the second top layer silicon 2a bonded to the four protrusions 10 except for the protrusion 10 at the center of the first SOI silicon wafer 1.

[0034] like Figure 5-10 As shown, a method for fabricating a silicon-silicon bonding on-resistance structure is characterized by comprising the following steps:

[0035] S1. Fabrication of the lower structural layer: Take the first SOI silicon wafer 1 and the second SOI silicon wafer 2. Use photolithography and ICP deep silicon etching technology to etch the top silicon 8 on the first SOI silicon wafer 1 to form a set of protrusions 10. Between the protrusions 10 are etched recesses 9. This forms the main body of the lower structural layer.

[0036] S2. Fabrication of the lower structural layer silicon leads: Using photolithography and ICP deep silicon etching technology, the top silicon 8 in the recess 9 of the first SOI silicon wafer 1 is etched down to the buried oxide layer 11, and the silicon between the three protrusions 10 is retained as silicon leads 12. These three protrusions 10 are distributed in a straight line. Then, an oxide layer 13 is grown on the protrusions 10 and silicon leads 12 through an oxidation process.

[0037] S3. Remove the oxide layer on the bonding surface: Use photolithography and wet etching techniques to remove the oxide layer 13 on the upper surface of the boss 10, and then remove a certain thickness of SiO2 to ensure the flatness of the upper surface of the boss 10.

[0038] S4. Direct bonding between the lower and upper structural layers: Using the second top silicon layer 2a of the second SOI silicon wafer 2 as the upper structural layer, a direct silicon-to-silicon bonding process is employed to directly bond the top of the protrusion 10 on the first SOI silicon wafer 1 to the second top silicon layer 2a of the second SOI silicon wafer 2. Then, CMP thinning and polishing techniques and KOH etching techniques are used to remove the bottom silicon and buried oxide layer of the second SOI silicon wafer 2, thereby forming the upper structural layer.

[0039] S5. Fabrication of metal PADs on the surface of the upper structural layer: A pure aluminum layer 14 is sputtered onto the surface of the bonded upper structural layer. Then, photoresist is applied to the pure aluminum layer 14 to form a pattern of PADs 15 corresponding to the protrusions 10. Next, photoresist is applied between two PADs 15 to form a pattern of second silicon leads. The pattern of the second silicon leads is arranged in a cross shape with the axis of the silicon leads 12.

[0040] S6. Fabrication of upper structural layer silicon leads: The silicon lead pattern of the upper structural layer is obtained through photolithography. Then, ICP deep silicon etching technology is used to remove all the second top layer silicon 2a outside the pattern of PAD point 15 and the pattern of the second silicon lead, thereby completing the structural release. The resulting four PAD points 15 and the upper second silicon lead 16 in contact with the upper and lower structural layers are formed. The second silicon lead 16 is mounted on the boss and forms a certain gap between it and the lower structure.

[0041] This forms a three-dimensional cross-bridge structure for testing the on-resistance of MEMS silicon-silicon bonding. The four-wire method allows for precise measurement of the on-resistance of the bonding surfaces of the upper and lower structural layers. Four leads are drawn from bonding surface 17, forming two lead paths passing through the bonding surface. One lead path is connected to a current source, allowing a constant current to be applied. A voltmeter is connected to the other lead path, allowing the voltage across the bonding surface to be measured, and the on-resistance of the bonding surface to be calculated. The four-wire method is used to evaluate the on-resistance of MEMS silicon-silicon bonding, characterizing the bonding quality of the MEMS silicon-silicon bonding.

Claims

1. A structure for testing the on-resistance of silicon-silicon bonding, comprising a first SOI silicon wafer (1), characterized in that: A set of recesses (9) are provided on the first SOI silicon wafer (1), thereby forming a set of protrusions (10) on the first SOI silicon wafer (1). A silicon lead (12) is connected in the recess (9) between two of the protrusions (10). A second top layer silicon (2a) on the same second SOI silicon wafer (2) is connected to the protrusion (10). A second silicon lead (16) is connected between the top layer silicon (2a) above two of the protrusions (10). A set of PAD points (15) are provided on the second top layer silicon (2a). The set of protrusions (10) consists of five protrusions. One of them is located at the top of the center of the first SOI silicon wafer (1) and is connected to the second silicon lead (16). The other four are distributed in different directions, so that the five protrusions (10) are arranged in a cross shape. The silicon lead (12) and the second silicon lead (16) are arranged in a cross shape.

2. The method for preparing a structure for testing the on-resistance of silicon-silicon bonding as described in claim 1, characterized in that: It includes the following steps: S1. Fabrication of the lower structure: Take the first SOI silicon wafer (1) and the second SOI silicon wafer (2), and use photolithography and ICP deep silicon etching to fabricate a set of bosses (10) on the top silicon (8) of the first SOI silicon wafer (1) to form the lower structure. S2. Fabrication of the lower structure layer silicon leads: Using photolithography and ICP deep silicon etching technology, the top silicon (8) of the first SOI silicon wafer (1) is etched to the buried oxide layer (11), and the silicon between several protrusions (10) is retained as silicon leads (12). Then, an oxide layer (13) is grown on the protrusions (10) and silicon leads (12) through an oxidation process. S3. Remove the oxide layer on the bonding surface: Use photolithography and wet etching techniques to remove the oxide layer (13) on the upper surface of the boss (10) and ensure the flatness of the upper surface of the boss (10); S4. Direct bonding between the lower and upper structural layers: The second top silicon layer (2a) of the second SOI silicon wafer (2) is used as the upper structural layer. The top silicon layers of the first SOI silicon wafer (1) and the second SOI silicon wafer (2) are directly bonded using a silicon-to-silicon direct bonding process. The bottom silicon layer and buried oxide layer of the second SOI silicon wafer (2) are removed using CMP thinning and polishing technology and KOH etching technology. S5. Prepare metal PAD points on the surface of the upper structure layer: Sputter a pure aluminum layer (14) on the surface of the bonded upper structure layer, and then apply photoresist on the pure aluminum layer (14) according to the silicon lead pattern and the pattern of PAD points (15). S6. Fabrication of upper structure layer silicon leads: The silicon lead pattern of the upper structure layer is obtained by photolithography, and the structure is released by ICP deep silicon etching technology to form the upper second silicon lead (16) that contacts the upper structure layer and the lower structure layer. A certain gap is formed between the second silicon lead (16) and the lower structure.

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