Display substrate and display device

Abstract

A display substrate comprises: a substrate, a plurality of first light-emitting elements located in a first display area, and a plurality of first pixel circuits located in a second display area. At least one first pixel circuit comprises: a driving subcircuit, a data writing subcircuit, and an anode resetting subcircuit. The driving subcircuit is connected between the data writing subcircuit and the anode resetting subcircuit, and the anode resetting subcircuit is electrically connected to the anode of the first light-emitting element. The data writing subcircuit is electrically connected to the first scanning line and configured to provide a data signal to the driving subcircuit under the control of the first scanning line. The anode resetting subcircuit is electrically connected to the second scanning line and configured to reset the anode of the first light-emitting element under the control of the second scanning line. The period of the second scanning signal provided by the second scanning line is greater than the period of the first scanning signal provided by the first scanning line.

Description

Technical Field

[0001] The present invention relates to but is not limited to display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. Under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a substrate having a first display area and a second display area located at least on one side of the first display area, a plurality of first light-emitting elements located in the first display area, and a plurality of first pixel circuits located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and is configured to drive the at least one first light-emitting element to emit light. At least one first pixel circuit comprises: a driving subcircuit, a data writing subcircuit, and an anode reset subcircuit. The driving subcircuit is connected between the data writing subcircuit and the anode reset subcircuit, and the anode reset subcircuit is electrically connected to the anode of at least one first light-emitting element. The data writing subcircuit is electrically connected to the first scan line, and is configured to provide a data signal to the driving subcircuit under the control of the first scan line. The anode reset subcircuit is electrically connected to the second scan line, and is configured to reset the anode of at least one first light-emitting element under the control of the second scan line. The period of the second scan signal provided by the second scan line is greater than the period of the first scan signal provided by the first scan line.

[0006] In some exemplary embodiments, a period of the second scanning signal is twice a period of the first scanning signal.

[0007] In some exemplary embodiments, the substrate further comprises: a peripheral region located outside the first display area and the second display area; the peripheral region is provided with a first scan drive circuit and a second scan drive circuit. The first scan drive circuit is electrically connected to the first scan line and configured to provide the first scan signal to the first scan line; the second scan drive circuit is electrically connected to the second scan line and configured to provide the second scan signal to the second scan line.

[0008] In some exemplary embodiments, the substrate further includes: a peripheral area located outside the first display area and the second display area; a first scan drive circuit is disposed in the peripheral area, the first scan drive circuit is electrically connected to the first scan line, and is configured to provide the first scan signal to the first scan line; the first scan drive circuit is electrically connected to the second scan line through a control circuit, and is configured to provide the second scan signal to the second scan line under the control of the control circuit.

[0009] In some exemplary embodiments, the control circuit includes: a control transistor; a gate of the control transistor is electrically connected to a control line, a first electrode of the control transistor is electrically connected to an output end of the first scan drive circuit and the first scan line, and a second electrode of the control transistor is electrically connected to the second scan line.

[0010] In some exemplary embodiments, the driving subcircuit includes a driving transistor, the data writing subcircuit includes a data writing transistor, and the anode reset subcircuit includes an anode reset transistor. The first electrode of the driving transistor is electrically connected to the second electrode of the data writing transistor, the first electrode of the data writing transistor is electrically connected to the data line, and the gate of the data writing transistor is electrically connected to the first scan line; the second electrode of the driving transistor is electrically connected to the second electrode of the anode reset transistor, the first electrode of the anode reset transistor is electrically connected to the second initial signal line, the gate of the anode reset transistor is electrically connected to the second scan line, and the second electrode of the anode reset transistor is electrically connected to the anode of the at least one first light-emitting element.

[0011] In some exemplary embodiments, the first pixel circuit further includes: a threshold compensation transistor, a first reset transistor, a first light emission control transistor, a second light emission control transistor, and a storage capacitor. The gate of the threshold compensation transistor is electrically connected to the first scan line, the first electrode is electrically connected to the gate of the driving transistor, and the second electrode is electrically connected to the second electrode of the driving transistor. The gate of the first reset transistor is electrically connected to the reset control line, the first electrode is electrically connected to the first initial signal line, and the second electrode is electrically connected to the gate of the driving transistor. The gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode is electrically connected to the first power line, and the second electrode is electrically connected to the first electrode of the driving transistor. The gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the second electrode of the anode reset transistor. The first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the first power line.

[0012] In some exemplary embodiments, the orthographic projection of the second scan line on the substrate is located between the orthographic projection of the second initial signal line and the light emitting control line on the substrate.

[0013] In some exemplary embodiments, the gate of the anode reset transistor and the second scan line are located in different film layers; the gate of the data write transistor and the first scan line are an integrated structure.

[0014] In some exemplary embodiments, in the second display area, the second scan line is located on a side of the first scan line away from the substrate.

[0015] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate of the second display area includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed on the substrate. The second scan line is located in the third conductive layer, and the first scan line is located in the first conductive layer.

[0016] In some exemplary embodiments, the display substrate of the second display area further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate. The fourth conductive layer at least includes: the data line.

[0017] In some exemplary embodiments, a frame time period of the first pixel circuit includes: a reset phase, a data writing phase, and a light emitting phase; in the reset phase, the gate of the driving transistor is reset; in the data writing phase, a data signal is provided to the driving transistor through the data writing transistor; and in the light emitting phase, the first light emitting element is driven to emit light. Taking two adjacent frame time periods as a group of time periods, the data writing transistor is turned on under the control of the first scanning signal during the data writing phase of the first frame time period and the data writing phase of the second frame time period in a group of time periods; the anode reset transistor is turned on under the control of the second scanning signal during the data writing phase of the first frame time period in a group of time periods, and is turned off under the control of the second scanning signal during the data writing phase of the second frame time period in the group of time periods.

[0018] In some exemplary embodiments, the display substrate further includes: a plurality of second light-emitting elements and a plurality of second pixel circuits located in the second display area, at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and is configured to drive the at least one second light-emitting element to emit light. The second pixel circuit includes at least a driving transistor, a data writing transistor, and an anode reset transistor, a first electrode of the driving transistor is electrically connected to the data writing transistor, and a second electrode of the driving transistor is electrically connected to the anode reset transistor; a gate of the anode reset transistor and a gate of the data writing transistor are both electrically connected to the first scan line.

[0019] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate as described above and an optical sensor, wherein the optical sensor is located on a non-display surface side of the display substrate, and an orthographic projection of the optical sensor on the display substrate overlaps with the first display area.

[0020] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0022] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0023] Figure 2is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0024] Figure 3 is an equivalent circuit diagram of a first pixel circuit of at least one embodiment of the present disclosure;

[0025] Figure 4 is an equivalent circuit diagram of a second pixel circuit of at least one embodiment of the present disclosure;

[0026] Figure 5 for Figure 3 The working timing diagram of the first pixel circuit shown;

[0027] Figure 6 is a partial plan view of a display substrate according to at least one embodiment of the present disclosure;

[0028] Figure 7 for Figure 6 A schematic diagram of a local cross section along the Q-Q' direction;

[0029] Fig. 8A for Figure 6 A schematic diagram of a display substrate after a semiconductor layer is formed;

[0030] Figure 8B for Figure 6 A schematic diagram of a display substrate after forming a first conductive layer;

[0031] Figure 8C for Figure 6 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0032] Fig.8D for Figure 6 A schematic diagram of a display substrate after a third insulating layer is formed;

[0033] Fig. 8E for Figure 6 A schematic diagram of a display substrate after a third conductive layer is formed;

[0034] Fig.8F for Figure 6 A schematic diagram of a display substrate after a fourth insulating layer is formed;

[0035] Fig. 9 A schematic diagram of a method for providing a first scanning signal and a second scanning signal according to at least one embodiment of the present disclosure;

[0036] Fig.10 A timing diagram of a first scan start signal and a second scan start signal according to at least one embodiment of the present disclosure;

[0037] Fig.11 A schematic diagram of another method for providing a first scanning signal and a second scanning signal according to at least one embodiment of the present disclosure;

[0038] Fig.12 is a working timing diagram of a control circuit of at least one embodiment of the present disclosure;

[0039] Fig.13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0041] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0042] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0043] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0044] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0045] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0046] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0047] In this specification, in order to distinguish the two electrodes of a transistor except the gate, one of the electrodes is called the first electrode and the other electrode is called the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate electrode of the transistor is called a control electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0048] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0049] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0050] The "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.

[0051] In the present disclosure, "about" and "substantially" mean that the limits are not strictly defined and the situation within the range of process and measurement errors is allowed. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0052] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" means "the main part of A extends along direction B".

[0053] With the development of display technology, the existing notch screen or water drop screen design is gradually unable to meet the user's demand for a high screen-to-body ratio of display devices, and a series of display devices with a light-transmitting display area have emerged. In this type of display device, hardware such as optical sensors (such as cameras) can be set in the light-transmitting display area. Since there is no need to punch holes, a true full screen becomes possible while ensuring the practicality of the display device.

[0054] The embodiment of the present disclosure provides a display substrate, comprising: a substrate having a first display area and a second display area located at least on one side of the first display area, a plurality of first light-emitting elements located in the first display area, and a plurality of first pixel circuits located in the second display area. At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, and is configured to drive the at least one first light-emitting element to emit light. At least one first pixel circuit comprises: a driving subcircuit, a data writing subcircuit, and an anode reset subcircuit. The driving subcircuit is connected between the data writing subcircuit and the anode reset subcircuit, and the anode reset subcircuit is electrically connected to the anode of at least one first light-emitting element. The data writing subcircuit is electrically connected to the first scan line, and is configured to provide a data signal to the driving subcircuit under the control of the first scan line. The anode reset subcircuit is electrically connected to the second scan line, and is configured to reset the anode of at least one first light-emitting element under the control of the second scan line. The period of the second scan signal provided by the second scan line is greater than the period of the first scan signal provided by the first scan line.

[0055] In some examples, the light transmittance of the first display area may be greater than the light transmittance of the second display area. For example, the first display area may be a light-transmitting display area, and the second display area may be a non-light-transmitting display area. By arranging the first pixel circuit driving the first light-emitting element in the first display area in the second display area instead of the first display area, it is possible to ensure that the light transmittance of the first display area is better.

[0056] The display substrate provided in this embodiment can increase the light-emitting time of the first light-emitting element and improve the darkening condition of the first display area by providing a first scanning signal to the data writing subcircuit and a second scanning signal to the anode reset subcircuit, and the period of the second scanning signal is greater than the period of the first scanning signal.

[0057] In some exemplary embodiments, the driving subcircuit may include a driving transistor, the data writing subcircuit may include a data writing transistor, and the anode reset subcircuit may include an anode reset transistor. A first electrode of the driving transistor is electrically connected to a second electrode of the data writing transistor, a first electrode of the data writing transistor is electrically connected to a data line, and a gate of the data writing transistor is electrically connected to a first scan line; a second electrode of the driving transistor is electrically connected to a second electrode of an anode reset transistor, a first electrode of the anode reset transistor is electrically connected to a second initial signal line, a gate of the anode reset transistor is electrically connected to a second scan line, and a second electrode of the anode reset transistor is electrically connected to an anode of at least one first light emitting element.

[0058] In some examples, a frame time period of the first pixel circuit may include: a reset phase, a data writing phase, and a light emitting phase; in the reset phase, the gate of the driving transistor is reset; in the data writing phase, a data signal is provided to the driving transistor through the data writing transistor; in the light emitting phase, the first light emitting element is driven to emit light. Taking two adjacent frame time periods as a group of time periods, the data writing transistor is turned on under the control of the first scanning signal during the data writing phase of the first frame time period and the data writing phase of the second frame time period in a group of time periods; the anode reset transistor is turned on under the control of the second scanning signal during the data writing phase of the first frame time period in a group of time periods, and is turned off under the control of the second scanning signal during the data writing phase of the second frame time period in the group of time periods. By controlling the second scanning signal to turn off the anode reset transistor in the second frame time period in a group of time periods, the anode of the first light emitting element may not be reset in the second frame time period, and the charge amount of the anode of the first light emitting element may be reduced, thereby increasing the light emitting time of the first light emitting element and improving the darkening of the first display area.

[0059] In some exemplary embodiments, the substrate may further include: a peripheral area located outside the first display area and the second display area. The peripheral area may be provided with a first scan drive circuit and a second scan drive circuit. The first scan drive circuit is electrically connected to the first scan line and configured to provide a first scan signal to the first scan line. The second scan drive circuit is electrically connected to the second scan line and configured to provide a second scan signal to the second scan line. In this example, the first scan signal and the second scan signal are provided respectively by two scan drive circuits, which can facilitate signal generation and transmission.

[0060] In some exemplary embodiments, the substrate may further include: a peripheral area located outside the first display area and the second display area. A first scan drive circuit may be provided in the peripheral area. The first scan drive circuit is electrically connected to the first scan line and configured to provide a first scan signal to the first scan line. The first scan drive circuit is electrically connected to the second scan line through a control circuit and configured to provide a second scan signal to the second scan line under the control of the control circuit. In this example, the first scan signal and the second scan signal may be provided by a scan drive circuit and a control circuit, which may save the circuit setting area of ​​the peripheral area and is conducive to achieving a narrow frame.

[0061] The solution of this embodiment is described below by means of some examples.

[0062] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate may include: a display area AA and a peripheral area BB surrounding the periphery of the display area AA. The display area AA of the display substrate may include: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. In this example, the second display area A2 may surround the first display area A1.

[0063] In some examples, such as Figure 1 As shown, the first display area A1 can be a light-transmitting display area, which can also be called a Full Display With Camera (FDC) area, configured to display images and transmit light; the second display area A2 can be a normal display area, configured to display images. For example, the orthographic projection of an optical sensor (such as a camera or other hardware) on the display substrate can be located in the first display area A1 of the display substrate. In some examples, such as Figure 1 As shown, the first display area A1 may be circular, and the size of the orthographic projection of the optical sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the optical sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0064] In some examples, such as Figure 1 As shown, the ratio of the resolution of the second display area A2 to the resolution of the first display area A1 can be about 0.8 to 1.2. Alternatively, the resolution of the second display area A2 can be substantially the same as the resolution of the first display area A1. The resolution of the first display area A1 can be greater than 400, for example.

[0065] In some examples, such as Figure 1As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other positions such as the upper left corner or the upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0066] In some examples, such as Figure 1 As shown, the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon or other shapes.

[0067] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number in front of T represents the number of thin film transistors in the circuit, and the number in front of C represents the number of capacitors in the circuit.

[0068] In some examples, the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0069] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, namely an LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0070] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0071] In some examples, a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0072] In some examples, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square pattern. However, this embodiment is not limited to this.

[0073] Figure 2 FIG. 1 is a partial schematic diagram of a display substrate of at least one embodiment of the present disclosure. Figure 2 As shown, the second display area A2 of the display substrate may include: a transition area A2a and a non-transition area A2b. The transition area A2a may be located on at least one side (e.g., one side; another example, both sides; another example, all around, i.e., including both sides, upper and lower sides and both sides, left and right sides) outside the first display area A1.

[0074] In some examples, such as Figure 2As shown, the first display area A1 may include a plurality of first light-emitting elements 10 arranged in an array. The transition area A2a of the second display area A2 may include: a plurality of first pixel circuits 41 and a plurality of second pixel circuits 42 arranged in an array, and may also include a plurality of second light-emitting elements (not shown). At least one first pixel circuit 41 in the transition area A2a may be electrically connected to at least one first light-emitting element 10 through a connecting line L, and is configured to drive the at least one first light-emitting element 10 to emit light. For example, one first pixel circuit 41 may be configured to drive one, two, three, or four first light-emitting elements 10 emitting light of the same color to emit light. The orthographic projection of the first light-emitting element 10 on the substrate may not overlap with the orthographic projection of the electrically connected first pixel circuit 41 on the substrate. At least one second pixel circuit 42 in the transition area A2a may be electrically connected to at least one second light-emitting element, and is configured to drive the at least one second light-emitting element to emit light. For example, one second pixel circuit 42 may be configured to drive a second light-emitting element to emit light. The orthographic projection of the second pixel circuit 42 on the substrate may at least partially overlap with the orthographic projection of the electrically connected second light-emitting element on the substrate. In this example, by arranging the first pixel circuit 41 driving the first light emitting element in the transition area A2a, the light shielding by the pixel circuit can be reduced, thereby increasing the light transmittance of the first display area A1.

[0075] In some examples, such as Figure 2 As shown, the non-transition region A2b may include a plurality of second pixel circuits 42 and a plurality of invalid pixel circuits 43 arranged in an array, and may also include a plurality of second light-emitting elements. The transition region A2a may also include: a plurality of invalid pixel circuits 43. The provision of the invalid pixel circuits 43 may help improve the uniformity of the components of the plurality of film layers in the etching process. For example, the structure of the invalid pixel circuit 43 and the second pixel circuit 42 in its row or column may be substantially the same, except that it is not electrically connected to any light-emitting element.

[0076] In some examples, since the second display area A2 is provided with not only the second pixel circuit 42 electrically connected to the second light-emitting element, but also the first pixel circuit 41 electrically connected to the first light-emitting element 10, the number of pixel circuits in the second display area A2 may be greater than the number of second light-emitting elements. Figure 2 As shown, the area for setting the newly added pixel circuit (including the first pixel circuit and the invalid pixel circuit) can be obtained by reducing the size of the second pixel circuit in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the second light-emitting element in the first direction D1. Figure 2As shown, each original a column of pixel circuits can be compressed along the first direction D1, thereby adding an arrangement space for a column of pixel circuits, and the space occupied by the a column of pixel circuits before compression and the a+1 column of pixel circuits after compression can be the same. Wherein, a can be an integer greater than 1. In some examples, a can be equal to 4. However, this embodiment is not limited to this. For example, a can be equal to 2 or 3.

[0077] In other examples, the original row b of pixel circuits can be compressed along the second direction D2 to add a row of pixel circuit arrangement space, and the space occupied by the row b of pixel circuits before compression and the row b+1 of pixel circuits after compression is the same. Wherein, b can be an integer greater than 1. Alternatively, the area for arranging the newly added pixel circuit can be obtained by reducing the size of the second pixel circuit in the first direction D1 and the second direction D2.

[0078] In the embodiment of the present disclosure, a row of pixel circuits may include a plurality of pixel circuits arranged in sequence along the first direction D1. A row of pixel circuits may all be connected to the same gate line (e.g., scan line). A row of light-emitting elements may include a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged along the first direction D1.

[0079] Figure 3 is an equivalent circuit diagram of the first pixel circuit of at least one embodiment of the present disclosure. In some examples, the first pixel circuit may include at least: a driving subcircuit 501, a data writing subcircuit 502, and an anode reset subcircuit 503. The driving subcircuit 501 is connected between the data writing subcircuit 502 and the anode reset subcircuit 503, and the anode reset subcircuit 503 is electrically connected to the anode connection node N14. The data writing subcircuit 502 is electrically connected to the first scan line GL1, and is configured to provide a data signal to the driving subcircuit 501 under the control of the first scan line GL1. The anode reset subcircuit 503 is electrically connected to the second scan line GL2, and is configured to reset the anode connection node N14 under the control of the second scan line GL2. The first pixel circuit of this exemplary embodiment is illustrated by taking a 7T1C structure as an example. However, this embodiment is not limited to this.

[0080] In some examples, such as Figure 3As shown, the driving subcircuit 501 of the first pixel circuit of this example may include a driving transistor T3, the data writing subcircuit 502 may include a data writing transistor T4, the anode reset subcircuit 503 may include an anode reset transistor T7, and the first pixel circuit may also include: a first reset transistor T1, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6 and a storage capacitor Cst1. The first pixel circuit is electrically connected to the first light emitting element EL1, and the first light emitting element EL1 may include an anode, a cathode and an organic light emitting layer arranged between the anode and the cathode.

[0081] In some examples, such as Figure 3 As shown, the display substrate may include: a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, and a reset control line RST. In some examples, the first power line PL1 may be configured to provide a constant first voltage signal VDD to the first pixel circuit, the second power line PL2 may be configured to provide a constant second voltage signal VSS to the first pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 may be configured to provide a first scan signal SCAN1 to the first pixel circuit, the second scan line GL2 may be configured to provide a second scan signal SCAN2 to the first pixel circuit, the data line DL may be configured to provide a data signal to the first pixel circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the first pixel circuit, and the reset control line RST may be configured to provide a reset control signal RESET to the first pixel circuit.

[0082] In some examples, in the nth row of pixel circuits, the reset control line RST may be electrically connected to the first scan line GL1 of the n-1th row of pixel circuits to be input with the first scan signal SCAN1(n-1), that is, the reset control signal RESET(n) is the same as the first scan signal SCAN1(n-1). Wherein n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be realized. However, this embodiment is not limited to this.

[0083] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the first pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the first pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.

[0084] In some examples, such as Figure 3 As shown, the driving transistor T3 of the first pixel circuit can output a driving current to drive the first light-emitting element EL1 to emit light under the control of the first scanning signal SCAN1, the second scanning signal SCAN2, the data signal, the first voltage signal VDD, the second voltage signal VSS and other signals. The gate of the data writing transistor T4 is electrically connected to the first scanning line GL1, the first electrode of the data writing transistor T4 is electrically connected to the data line DL, and the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the first scanning line GL1, the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power line PL1, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is electrically connected to the anode of the light emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The anode reset transistor T7 is electrically connected to the anode of the first light emitting element EL1 and is configured to reset the anode of the first light emitting element EL1. The gate of the first reset transistor T1 is electrically connected to the reset control line RST, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the anode reset transistor T7 is electrically connected to the second scanning line GL2, the first electrode of the anode reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the anode reset transistor T7 is electrically connected to the anode of the first light emitting element EL1. A first plate of the storage capacitor Cst1 is electrically connected to the gate of the driving transistor T3 , and a second plate of the storage capacitor Cst1 is electrically connected to the first power line PL1 .

[0085] In this example, if Figure 3 As shown, the first node N11 is a connection point of the storage capacitor Cst1, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N12 is a connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N13 is a connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N14 is a connection point of the second light-emitting control transistor T6, the anode reset transistor T7 and the first light-emitting element EL1. The fourth node N14 is the anode connection node of the first pixel circuit.

[0086] In some examples, such as Figure 3 As shown, since the first pixel circuit and the first light-emitting element are located in different display areas, the first pixel circuit and the first light-emitting element EL1 are electrically connected via a connecting wire, and the connecting wire overlaps with other film layers to generate a capacitor Cito. Figure 3 The capacitance Cito of the anode connection node (i.e., the fourth node N14) in the first pixel circuit shown is too large, so that the anode connection node needs a long time to charge after being reset to reach the light-emitting threshold voltage of the first light-emitting element EL1. In this way, the lighting time of the first light-emitting element EL1 will be affected, resulting in the first display area being displayed darkly, causing a display brightness difference between the first display area and the second display area. In this example, the conduction of the anode reset transistor T7 is controlled by the second scan line GL2, so that the conduction control of the anode reset transistor T7 is different from the conduction control of the data writing transistor T4. When the data writing transistor T4 is turned on, the anode reset transistor T7 can be disconnected and the anode connection node is not reset, which can effectively reduce the charge amount of the anode connection node and reduce the time required for the anode connection node to reach the light-emitting threshold voltage of the first light-emitting element, thereby improving the brightness of the first light-emitting element. For example, the brightness of the first light-emitting element can be within an adjustable range (for example, an adjustable range that can be achieved by adjusting methods such as Gamma or Demura), thereby improving the display effect of the display substrate and improving the poor brightness caused by the dark brightness of the first display area.

[0087] Below Figure 3 The working process of the schematic first pixel circuit is described below. Figure 5 for Figure 3 The working timing diagram of the first pixel circuit shown in FIG. Figure 3 The pixel circuit shown is illustrated by taking the case where the plurality of transistors included therein are all P-type transistors as an example.

[0088] In some exemplary embodiments, in a frame period, the operation process of the first pixel circuit may include: a first stage S1, a second stage S2, and a third stage S3. The first stage S1 to the third stage S3 of the first frame period F1 are taken as an example for description.

[0089] The first stage S1 is called the reset stage. The reset control signal RESET provided by the reset control line RST is a low-level signal, which turns on the first reset transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N11, and the first node N11 is initialized to clear the original data voltage in the storage capacitor Cst1. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, which turns off the data writing transistor T4, the threshold compensation transistor T2, the first light control transistor T5, the second light control transistor T6 and the anode reset transistor T7. In this stage, the first light emitting element EL1 does not emit light.

[0090] The second stage S2 is called the data writing stage or the threshold compensation stage. The first scanning signal SCAN1 provided by the first scanning line GL1 is a low level signal, the second scanning signal SCAN2 provided by the second scanning line GL2 is a low level signal, the reset control signal RESET provided by the reset control line RST and the light control signal EM provided by the light control line EML are both high level signals, and the data line DL outputs the data signal. In this stage, since the first plate of the storage capacitor Cst1 is at a low level, the driving transistor T3 is turned on. The first scanning signal SCAN1 is a low level signal, which turns on the threshold compensation transistor T2 and the data writing transistor T4, and the second scanning signal SCAN2 is a low level signal, which turns on the anode reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N11 through the second node N12, the turned-on driving transistor T3, the third node N13, and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst1, and the voltage of the first plate (i.e., the first node N11) of the storage capacitor Cst1 is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the driving transistor T3. The anode reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N14, the fourth node N14 is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the first light-emitting element EL1 is ensured not to emit light. The reset control signal RESET provided by the reset control line RST is a high-level signal, which turns off the first reset transistor T1. The light emitting control signal EM provided by the light emitting control line EML is a high level signal, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off.

[0091] The third stage S3 is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, and the first scan signal SCAN1 provided by the first scan line GL1, the second scan signal SCAN2 provided by the second scan line GL2, and the reset control signal RESET provided by the reset control line RST are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the first light-emitting element EL1 through the turned-on first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6, thereby driving the first light-emitting element EL1 to emit light.

[0092] During the driving process of the first pixel circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0093] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0094] Among them, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the first light-emitting element EL1, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0095] It can be seen from the above formula that the current flowing through the first light emitting element EL1 has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the first pixel circuit of this embodiment can better compensate for the threshold voltage of the driving transistor T3.

[0096] In some examples, such as Figure 5 As shown, the period of the first scanning signal SCAN1 may be less than the period of the second scanning signal SCAN2. For example, the period of the second scanning signal SCAN2 may be twice the period of the first scanning signal SCAN1. The first scanning signal SCAN1 and the second scanning signal SCAN2 may be pulse signals. In this example, the period of a signal may refer to the duration from one rising edge to the next rising edge of the signal.

[0097] In some examples, such as Figure 5As shown, taking two adjacent frame time periods as a group of time periods, in the second stage S2 of the first frame time period F1 in a group of time periods, the first scan signal SCAN1 and the second scan signal SCAN2 can both be low-level signals, so that the data write transistor T4, the threshold compensation transistor T2 and the anode reset transistor T7 are all turned on. In the second stage S2 of the second frame time period F2 in a group of time periods, the first scan signal SCAN1 can be a low-level signal, and the second scan signal SCAN2 can be a high-level signal, so that the data write transistor T4 and the threshold compensation transistor T2 are all turned on, and the anode reset transistor T7 can be disconnected, and the fourth node N14 will not be reset, so that the fourth node N14 will not be reset, and the fourth node N14 can reach the light-emitting threshold voltage of the first light-emitting element EL1 without a long time of charging in the second frame time period F2. In this way, the charge amount of the anode connection node can be effectively reduced, and the time required for the anode connection node to reach the light-emitting threshold voltage of the first light-emitting element can be reduced, thereby improving the brightness of the first light-emitting element.

[0098] Figure 4 is an equivalent circuit diagram of a second pixel circuit of at least one embodiment of the present disclosure. Figure 4 As shown, the second pixel circuit of this example may include: a driving transistor M3, a data writing transistor M4, a threshold compensation transistor M2, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a first reset transistor M1, an anode reset transistor M7 and a storage capacitor Cst2. The second pixel circuit of this example takes a 7T1C structure as an example. Compared with the first pixel circuit, the anode reset transistor M7 of the second pixel circuit can be electrically connected to the first scan line GL1. The connection relationship between the remaining transistors and the storage capacitor of the second pixel circuit can refer to the relevant description of the first pixel circuit, so it will not be repeated here. The working timing of the second pixel circuit can refer to the working timing of the first pixel circuit in the first frame time period, so it will not be repeated here.

[0099] Figure 6 It is a partial plan view of a display substrate according to at least one embodiment of the present disclosure. Figure 7 for Figure 6 Schematic diagram of the local cross-section along the Q-Q' direction.

[0100] In some examples, such as Figure 6 As shown, the second display area may include: a first circuit area A21 and a second circuit area A22 arranged at intervals, the first circuit area A21 may be provided with a plurality of first pixel circuits (e.g., a column of first pixel circuits), and the second circuit area A22 may be provided with a plurality of second pixel circuits (e.g., two columns or more of second pixel circuits). Figure 6In the embodiment, a first pixel circuit in a first circuit area A21 and a second pixel circuit in a second circuit area A22 on two adjacent sides of the first circuit area A21 are taken as examples for illustration.

[0101] In some examples, in a direction perpendicular to the display substrate, such as Figure 7 As shown, the second display area may include: a substrate 100, and a circuit structure layer disposed on the substrate 100. The circuit structure layer may include at least: a semiconductor layer 201, a first insulating layer 101, a first conductive layer (also referred to as a first gate metal layer) 202, a second insulating layer 102, a second conductive layer (also referred to as a second gate metal layer) 203, a third insulating layer 103, a third conductive layer (also referred to as a first source-drain metal layer) 204, a fourth insulating layer 104, and a fourth conductive layer (also referred to as a second source-drain metal layer) 205, which are sequentially disposed on the substrate 100. In some examples, the first insulating layer 101 to the third insulating layer 103 may be an inorganic insulating layer, and the fourth insulating layer 104 may be an organic insulating layer. However, this embodiment is not limited thereto.

[0102] The structure and preparation process of the display substrate are exemplarily described below. The "patterning process" mentioned in the embodiments of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are the same layer structure" or "A and B are arranged in the same layer" in the embodiments of the present disclosure means that A and B are formed simultaneously through the same patterning process, or the distance between the surfaces of A and B close to the substrate side and the substrate is basically the same, or the surfaces of A and B close to the substrate side are in direct contact with the same film layer. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0103] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0104] (1) Provide a substrate. In some examples, the substrate may be a flexible substrate or a rigid substrate. For example, the rigid substrate may be made of materials such as glass or quartz. The flexible substrate may be made of materials such as polyimide (PI), and the flexible substrate may be a single-layer structure or a laminated structure consisting of an inorganic material layer and a flexible material layer. However, this embodiment is not limited to this.

[0105] (2) Forming a semiconductor layer. In some examples, a semiconductor film is deposited on the substrate in the second display region, and the semiconductor film is patterned by a patterning process to form a semiconductor layer in the second display region.

[0106] Fig. 8A for Figure 6 Schematic diagram of a display substrate after a semiconductor layer is formed in the display substrate. In some examples, such as Fig. 8A As shown, the semiconductor layer of the first circuit area A21 of the second display area may include: active layers of multiple transistors of the first pixel circuit (for example, the active layer T10 of the first reset transistor of the first pixel circuit, the active layer T20 of the threshold compensation transistor, the active layer T30 of the driving transistor, the active layer T40 of the data writing transistor, the active layer T50 of the first light-emitting control transistor, the active layer T60 of the second light-emitting control transistor, and the active layer T70 of the anode reset transistor); the semiconductor layer of the second circuit area A22 may include: active layers of multiple transistors of the second pixel circuit (for example, the active layer M10 of the first reset transistor of the second pixel circuit, the active layer M20 of the threshold compensation transistor, the active layer M30 of the driving transistor, the active layer M40 of the data writing transistor, the active layer M50 of the first light-emitting control transistor, the active layer M60 of the second light-emitting control transistor, and the active layer M70 of the anode reset transistor).

[0107] In some examples, such as Fig. 8AAs shown, the active layer T10 of the first reset transistor of the first pixel circuit, the active layer T20 of the threshold compensation transistor, the active layer T40 of the data writing transistor, the active layer T30 of the driving transistor, the active layer T50 of the first light emission control transistor, the active layer T60 of the second light emission control transistor, and the active layer T70 of the anode reset transistor can be an integrated structure. The active layer M10 of the first reset transistor of the second pixel circuit, the active layer M20 of the threshold compensation transistor, the active layer M40 of the data writing transistor, the active layer M30 of the driving transistor, the active layer M50 of the first light emission control transistor, the active layer M60 of the second light emission control transistor, and the active layer M70 of the anode reset transistor can be an integrated structure. The active layer M70 of the anode reset transistor of the second pixel circuit can be adjacent to the active layer M10 of the first reset transistor of the second pixel circuit of the next row in the first direction D1.

[0108] In some examples, such as Fig. 8A As shown, the shape of the active layer T10 of the first reset transistor may be in the shape of an "n", the shape of the active layer T20 of the threshold compensation transistor and the active layer T60 of the second light-emitting control transistor may be in the shape of an "L", the shape of the active layer T30 of the driving transistor may be in the shape of an "J", and the shape of the active layer T40 of the data writing transistor, the active layer T50 of the first light-emitting control transistor, and the active layer T70 of the anode reset transistor may be in the shape of an "I". However, this embodiment is not limited to this. The shape of the active layer of the multiple transistors of the second pixel circuit may be similar to the shape of the active layer of the multiple transistors of the first pixel circuit, so it will not be repeated here.

[0109] In some examples, the material of the semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and a first region and a second region located at both ends of the channel region. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be on both sides of the channel region and are doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

[0110] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer covering the semiconductor layer, and a first conductive layer disposed on the first insulating layer in the second display area.

[0111] Figure 8B for Figure 6Schematic diagram of a display substrate after forming a first conductive layer. In some examples, such as Figure 8B As shown, the first conductive layer of the first circuit area A21 of the second display area may at least include: gates of multiple transistors of the first pixel circuit (for example, including the gate of the first reset transistor T1 of the first pixel circuit, the gate of the threshold compensation transistor T2, the gate of the driving transistor T3, the gate of the data writing transistor T4, the gate of the first light emission control transistor T5, the gate of the second light emission control transistor T6, and the gate T71 of the anode reset transistor T7), and the first electrode plate Cst1-1 of the storage capacitor Cst1. The first conductive layer of the second circuit area A22 may at least include: gates of multiple transistors of the second pixel circuit (for example, including the gate of the first reset transistor M1 of the second pixel circuit, the gate of the threshold compensation transistor M2, the gate of the driving transistor M3, the gate of the data writing transistor M4, the gate of the first light emission control transistor M5, the gate of the second light emission control transistor M6, and the gate of the anode reset transistor M7) and the first electrode plate Cst2-1 of the storage capacitor Cst2.

[0112] In some examples, such as Figure 8B As shown, the first conductive layer of the second display area may further include: a first scan line GL1(n) extending along the first direction D1, reset control lines RST(n) and RST(n+1), and a light emitting control line EML(n). The first scan line GL1(n) may be located between the reset control line RST(n) and the light emitting control line EML(n) in the second direction D2.

[0113] In some examples, such as Figure 8B As shown, the first plate Cst1-1 of the storage capacitor Cst1 of the first pixel circuit can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first plate Cst1-1 of the storage capacitor Cst1 on the substrate and the orthographic projection of the active layer of the driving transistor T3 on the substrate have an overlapping area. The first plate Cst1-1 of the storage capacitor Cst1 and the gate of the driving transistor T3 can be an integral structure, and the first plate Cst1-1 of the storage capacitor Cst1 can also serve as the gate of the driving transistor T3. The first plate Cst2-1 of the storage capacitor Cst2 of the second pixel circuit and the gate of the driving transistor M3 can be an integral structure, and the first plate Cst2-1 of the storage capacitor Cst2 can also serve as the gate of the driving transistor M3.

[0114] In some examples, such as Figure 8BAs shown, the first scan line GL1(n), the gate of the threshold compensation transistor T2 of the first pixel circuit, the gate of the data writing transistor T4, the gate of the threshold compensation transistor M2 of the second pixel circuit located in the same row as the first pixel circuit, and the gate of the data writing transistor M4 can be an integrated structure. The reset control line RST(n), the gate of the first reset transistor T1 of the first pixel circuit, the gate of the first reset transistor M1 of the second pixel circuit located in the same row as the first pixel circuit, and the gate of the anode reset transistor M7 of the second pixel circuit located in the row above the second pixel circuit can be an integrated structure. The reset control line RST(n+1), the gate of the anode reset transistor M7 of the second pixel circuit, and the gate of the first reset transistor M1 of the second pixel circuit located in the row below the second pixel circuit can be an integrated structure. The light emission control line EML(n) and the gate of the first light emission control transistor T5 of the first pixel circuit, the gate of the second light emission control transistor T6, the gate of the first light emission control transistor M5 of the second pixel circuit located in the same row as the first pixel circuit, and the gate of the second light emission control transistor M6 can be an integrated structure. The gate T71 of the anode reset transistor T7 of the first pixel circuit of this row may be located between the light emission control line EML(n) and the reset control line RST(n+1).

[0115] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on a substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer disposed on the second insulating layer in the second display area.

[0116] Figure 8C for Figure 6 Schematic diagram of a display substrate after forming a second conductive layer. In some examples, such as Figure 8C As shown, the second conductive layer of the first circuit area A21 of the second display area may include at least: the second plate Cst1-2 of the storage capacitor Cst1 of the first pixel circuit. The second conductive layer of the second circuit area A22 may include at least: the second plate Cst2-2 of the storage capacitor Cst2 of the second pixel circuit.

[0117] In some examples, such as Figure 8C As shown, the second conductive layer of the second display area may further include: a first initial signal line INIT1 and a second initial signal line INIT2 extending along the first direction D1. The first initial signal line INIT1 may be located on a side of the second initial signal line INIT2 close to the first scan line. The positive projection of the reset control line on the substrate may be located between the first initial signal line INIT1 and the second initial signal line INIT2.

[0118] In some examples, such as Figure 8B and Figure 8C As shown, the orthographic projection of the second plate Cst1-2 of the storage capacitor of the first pixel circuit on the substrate may overlap with the orthographic projection of the first plate Cst1-1 of the storage capacitor on the substrate. The second plate Cst1-2 of the storage capacitor may have a first hollow area, and the orthographic projection of the first hollow area on the substrate may be located within the orthographic projection range of the first plate Cst1-1 on the substrate. The orthographic projection of the second plate Cst2-2 of the storage capacitor of the second pixel circuit on the substrate may overlap with the orthographic projection of the first plate Cst2-1 of the storage capacitor on the substrate. The second plate Cst2-2 of the storage capacitor of the first pixel circuit in the first circuit area A21 and the second plate Cst2-2 of the storage capacitor of the second pixel circuit in the adjacent second circuit area A22 may be an integrated structure to realize the transmission of the first voltage signal along the first direction D1, thereby improving the uniformity of the first voltage signal in the display substrate.

[0119] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate forming the aforementioned structure, and the third insulating layer is formed by a patterning process. The third insulating layer is formed with a plurality of vias.

[0120] Fig.8D for Figure 6 Schematic diagram of a display substrate after forming a third insulating layer. In some examples, such as Fig.8D As shown, the vias opened in the third insulating layer of the first circuit area A21 may include: the first via V1 to the sixth via V6, the thirteenth via V13, the sixteenth via V16, and the seventeenth via V17 to the nineteenth via V19. The vias opened in the third insulating layer of the second circuit area A22 may include: the seventh via V7 to the twelfth via V12, the fourteenth via V14, the fifteenth via V15, and the twentieth via V20 to the twenty-second via V22.

[0121] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 to the sixth via hole V6 and the seventh via hole V7 to the twelfth via hole V12 can be removed to expose the surface of the semiconductor layer. The third insulating layer and the second insulating layer in the thirteenth via hole V13, the fourteenth via hole V14, the fifteenth via hole V15, and the sixteenth via hole V16 can be removed to expose the surface of the first conductive layer. The third insulating layer in the seventeenth via hole V17 to the nineteenth via hole V19 and the twentieth via hole V20 to the twenty-second via hole V22 can be removed to expose the surface of the second conductive layer.

[0122] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate forming the aforementioned structure, and the third conductive film is patterned by a patterning process to form a third conductive layer located on the third insulating layer.

[0123] Fig. 8E for Figure 6 Schematic diagram of a display substrate after forming a third conductive layer. In some examples, such as Fig. 8E As shown, the third conductive layer of the first circuit area A21 may include: a first connection electrode 301, a second connection electrode 302, a third connection electrode 303, a fourth connection electrode 304, a fifth connection electrode 305 and a sixth connection electrode 306. The third conductive layer of the second circuit area A22 may include: a seventh connection electrode 307, an eighth connection electrode 308, a ninth connection electrode 309, a tenth connection electrode 310, an eleventh connection electrode 311 and a twelfth connection electrode 312. The third conductive layer of the second display area may further include: a second scan line GL2(n).

[0124] In some examples, such as FIG. 8A to FIG. 8E As shown, the first connection electrode 301 can be electrically connected to the first area of ​​the active layer T10 of the first reset transistor T1 of the first pixel circuit through the first via hole V1, and can also be electrically connected to the first initial signal line INIT1 through the seventeenth via hole V17. The second connection electrode 302 can be electrically connected to the second area of ​​the active layer T10 of the first reset transistor T1 of the first pixel circuit through the second via hole V2, and can also be electrically connected to the gate of the driving transistor T3 through the thirteenth via hole V13. The third connection electrode 303 can be electrically connected to the first area of ​​the active layer T40 of the data writing transistor T4 of the first pixel circuit through the third via hole V3. The fourth connection electrode 304 can be electrically connected to the first area of ​​the active layer T50 of the first light emission control transistor T5 of the first pixel circuit through the fourth via hole V4, and can also be electrically connected to the second plate Cst1-2 of the storage capacitor Cst1 through the eighteenth via hole V18. The fifth connection electrode 305 can be electrically connected to the second area of ​​the active layer T60 of the second light emission control transistor T6 through the fifth via hole V5. The sixth connection electrode 306 may be electrically connected to the first region of the active layer T70 of the anode reset transistor T7 through the sixth via hole V6 , and may also be electrically connected to the second initial signal line INIT2 through the nineteenth via hole V19 .

[0125] In some examples, such as FIG. 8A to FIG. 8EAs shown, the seventh connection electrode 307 can be electrically connected to the first area of ​​the active layer M10 of the first reset transistor M1 of the second pixel circuit through the seventh via hole V7, and can also be electrically connected to the first initial signal line INIT1 through the twentieth via hole V20. The eighth connection electrode 308 can be electrically connected to the second area of ​​the active layer M10 of the first reset transistor M1 of the second pixel circuit through the eighth via hole V8, and can also be electrically connected to the gate of the driving transistor M3 through the fourteenth via hole V14. The ninth connection electrode 309 can be electrically connected to the first area of ​​the active layer M40 of the data writing transistor M4 of the second pixel circuit through the ninth via hole V9. The tenth connection electrode 310 can be electrically connected to the first area of ​​the active layer M50 of the first light emission control transistor M5 of the second pixel circuit through the tenth via hole V10, and can also be electrically connected to the second plate Cst2-2 of the storage capacitor Cst2 through the twenty-first via hole V21. The eleventh connection electrode 311 can be electrically connected to the second area of ​​the active layer M60 of the second light emission control transistor M6 through the eleventh via hole V11. The twelfth connection electrode 312 may be electrically connected to the second region of the active layer M70 of the anode reset transistor M7 of the second pixel circuit through the twelfth via hole V12 , and may also be electrically connected to the second initial signal line INIT2 through the twenty-second via hole V22 .

[0126] In some examples, such as FIG. 8A to FIG. 8E As shown, the second scan line GL2(n) may include a plurality of sub-segments along the first direction D1, one end of at least one sub-segment may be electrically connected to the gate T71 of the anode reset transistor T7 of the first pixel circuit through the fifteenth via hole V15, and one end of an adjacent sub-segment may be electrically connected to the gate T71 of the anode reset transistor T7 of the first pixel circuit through the sixteenth via hole V16. In this example, adjacent sub-segments of the second scan line GL2(n) may be electrically connected through the gate of the anode reset transistor T7 of the first pixel circuit, thereby realizing the transmission of the second scan signal along the first direction D1. The positive projection of the second scan line GL2(n) on the substrate may be located between the positive projection of the light emitting control line EML(n) and the second initial signal line INIT2 on the substrate. The arrangement of the second scan line in this example may save space.

[0127] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate on which the aforementioned structure is formed, and the fourth insulating layer is formed by a patterning process. The fourth insulating layer may be provided with a plurality of vias.

[0128] Fig.8F for Figure 6 Schematic diagram of a display substrate after forming a fourth insulating layer in FIG. Fig.8FAs shown, the fourth insulating layer of the first circuit area A21 may be provided with at least 31st to 33rd via holes V31 to V33. The fourth insulating layer of the second circuit area A22 may be provided with at least 34th to 36th via holes V34 to V36. The fourth insulating layer within the 31st to 36th via holes V31 to V36 may be removed to expose the surface of the third conductive layer.

[0129] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned structure, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the fourth insulating layer in the second display region.

[0130] In some examples, such as Figure 6 As shown, the fourth conductive layer of the second display area may include at least a plurality of data (e.g., data lines 421 and 422) and a plurality of first power lines (e.g., first power lines 411 and 412), and anode connection electrodes 401 and 402. The data line 421 may be electrically connected to the third connection electrode 303 through the thirty-first via hole V31, thereby realizing electrical connection with the data write transistor T4 of the first pixel circuit. The first power line 411 may be electrically connected to the fourth connection electrode 304 through the thirty-second via hole V32, thereby realizing electrical connection with the first light emission control transistor T5 and the storage capacitor Cst1 of the first pixel circuit. The data line 422 may be electrically connected to the ninth connection electrode 309 through the thirty-fourth via hole V34, thereby realizing electrical connection with the data write transistor M4 of the second pixel circuit. The first power line 412 may be electrically connected to the tenth connection electrode 310 through the thirty-fifth via hole V35, thereby realizing electrical connection with the first light emission control transistor T5 and the storage capacitor Cst2 of the second pixel circuit. The anode connection electrode 401 can be electrically connected to the fifth connection electrode 305 through the thirty-third via hole V33, thereby realizing electrical connection with the second light emission control transistor T6 and the anode reset transistor T7 of the first pixel circuit. The anode connection electrode 402 can be electrically connected to the eleventh connection electrode 311 through the thirty-sixth via hole V33, thereby realizing electrical connection with the second light emission control transistor M6 and the anode reset transistor M7 of the second pixel circuit.

[0131] In some examples, after forming the aforementioned structure, the first display area may include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on the substrate. Subsequently, at least one transparent conductive layer may be formed, and the transparent conductive layer may include a plurality of connecting lines. An insulating layer may be provided between adjacent transparent conductive layers. Subsequently, an anode film is deposited on the substrate on which the aforementioned pattern is formed, and the anode film is patterned by a patterning process to form an anode layer; the anode layer may include an anode of a first light-emitting element located in the first display area and an anode of a second light-emitting element located in the second display area. Subsequently, a pixel definition film is coated, and a pixel definition layer is formed by masking, exposure, and development processes. The pixel definition layer may be formed with a plurality of pixel openings exposing the anode layer. An organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0132] In some examples, the first insulating layer, the second insulating layer and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer, and the third insulating layer may be referred to as an interlayer insulating (ILD) layer. The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The fourth insulating layer may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology. The pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited to this.

[0133] The structure of the display substrate of this embodiment and its preparation process are only an exemplary description. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, can be well compatible with existing preparation processes, and has simple process implementation, easy implementation, high production efficiency, low production cost, and high yield rate.

[0134] The display substrate provided in this example controls the conduction of the data write transistor by a first scan signal, and controls the conduction of the anode reset transistor by a second scan signal, and the first scan signal is different from the second scan signal, so that when the data write transistor is turned on, the anode reset transistor can be disconnected, and there is no need to reset the anode of the first light-emitting element, thereby increasing the light-emitting time of the first light-emitting element and improving the darkening of the first display area.

[0135] Fig. 9 Schematic diagram of a method for providing a first scanning signal and a second scanning signal according to at least one embodiment of the present disclosure. Fig. 9 As shown, the peripheral area BB of the display substrate may be provided with a first scan driving circuit and a second scan driving circuit. The first scan driving circuit may be electrically connected to the first scan line GL1 and configured to provide a first scan signal to the first scan line GL1. The second scan driving circuit may be electrically connected to the second scan line GL2 and configured to provide a second scan signal to the second scan line GL2.

[0136] In some examples, the first scan drive circuit can generate a first scan signal to be provided to a plurality of first scan lines GL1 by a scan clock signal, a first scan start signal, etc. received from a timing controller. For example, the first scan drive circuit can sequentially provide a first scan signal having a conduction level pulse to the first scan line. In some examples, the first scan drive circuit can include a shift register, which can sequentially transmit the first scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the scan clock signal to generate the first scan signal. Similarly, the second scan drive circuit can generate a second scan signal to be provided to a plurality of second scan lines GL2 by a scan clock signal, a second scan start signal, etc. received from a timing controller. The structure of the second scan drive circuit is similar to that of the first scan drive circuit, so it will not be repeated here.

[0137] Fig.10 1 is a timing diagram of a first scan start signal and a second scan start signal of at least one embodiment of the present disclosure. Fig.10As shown, the first scanning start signal GSTVa sends an on-level pulse in each frame, and the second scanning start signal GSTVb sends an on-level pulse in the first frame period F1 of every two frames, and does not send an on-level pulse in the second frame period F2.

[0138] Fig.11 Schematic diagram of another method of providing the first scanning signal and the second scanning signal of at least one embodiment of the present disclosure. In some examples, such as Fig.11 As shown, a first scan drive circuit may be provided in the peripheral area BB of the display substrate. The first scan drive circuit may be electrically connected to the first scan line, and configured to provide a first scan signal to the first scan line. The first scan drive circuit may also be electrically connected to the second scan line through the control circuit 510, and configured to provide a second scan signal to the second scan line under the control of the control circuit 510. In some examples, the control circuit 510 may be located in the peripheral area, or the control circuit 510 may be located in the edge area of ​​the display area close to the peripheral area. However, this embodiment is not limited to this.

[0139] In some examples, such as Fig.11 As shown, the control circuit 510 may include a control transistor T11, the gate of the control transistor T11 is electrically connected to the control line CTL, the first electrode of the control transistor T11 is electrically connected to the first scan line GL1(n) and the output end of the first scan drive circuit, and the second electrode of the control transistor T11 is electrically connected to the second scan line GL2(n). The first scan drive circuit may include a plurality of cascaded sub-circuits, the output end of each sub-circuit is electrically connected to a first scan line, and is electrically connected to a second scan line through a control transistor. In this way, it is possible to provide the first scan signal and the second scan signal to each row of pixel circuits in the display area.

[0140] Fig.12 is a timing diagram of the operation of the control circuit of at least one embodiment of the present disclosure. Fig.12 As shown, the control transistor T11 is a P-type transistor as an example. In the first frame time period F1, the control signal Ctl provided by the control line CTL is a low-level signal, and the control transistor T11 is turned on, so that the first scan signal SCAN1 transmitted by the first scan line and the second scan signal SCAN2 transmitted by the second scan line are the same. In the second frame time period F2, the control signal Ctl provided by the control line is a high-level signal, and the control transistor T11 is turned off, so that the first scan signal SCAN1 and the second scan signal SCAN2 are different. Among them, the first scan signal SCAN1 is the same as the output signal of the first scan drive circuit, and the second scan signal SCAN2 is a continuous high-level signal. However, this embodiment is not limited to this. In other examples, the control circuit may include multiple transistors.

[0141] In some examples, the capacitor Cito at the anode connection node of the first pixel circuit causes the display of the first display area to be dark and have poor dark lines. In the low-frequency (e.g., less than or equal to 60Hz) display process, it can be improved by adjustable methods such as Gamma. In the high-frequency (e.g., greater than 60Hz, such as about 120Hz) display process, the capacitor Cito has a greater impact and cannot be improved by adjustable methods such as Gamma. Therefore, in a display substrate using a high-frequency display mode, by controlling the anode reset transistor and the data write transistor of the first pixel circuit with different scanning signals, the light emission time of the first light-emitting element can be effectively increased, and the darkening of the first display area can be improved.

[0142] An embodiment of the present disclosure further provides a display device, comprising the display substrate as described above.

[0143] Fig.13 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.13 As shown, this embodiment provides a display device, including: a display substrate 91 and an optical sensor 92 located on a non-display surface side of the display substrate 91. The orthographic projection of the optical sensor 92 on the display substrate 91 overlaps with the first display area A1.

[0144] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiments of the present disclosure are not limited thereto.

[0145] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to the usual design. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those of ordinary skill in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate having a first display area and a second display area located at at least one side of the first display area; A plurality of first light emitting elements, located in the first display area; a plurality of first pixel circuits, located in the second display area, at least one of the plurality of first pixel circuits being electrically connected to at least one of the plurality of first light-emitting elements, and configured to drive the at least one first light-emitting element to emit light; At least one first pixel circuit among the plurality of first pixel circuits comprises: a driving subcircuit, a data writing subcircuit and an anode resetting subcircuit; The driving subcircuit is connected between the data writing subcircuit and the anode resetting subcircuit, and the anode resetting subcircuit is electrically connected to the anode of the at least one first light emitting element; The data writing subcircuit is electrically connected to the first scan line, and is configured to provide a data signal to the driving subcircuit under the control of the first scan line; the anode resetting subcircuit is electrically connected to the second scan line, and is configured to reset the anode of the at least one first light-emitting element under the control of the second scan line; A period of the second scan signal provided by the second scan line is greater than a period of the first scan signal provided by the first scan line.

2. The display substrate according to claim 1, wherein: A period of the second scanning signal is twice a period of the first scanning signal.

3. The display substrate according to claim 1, characterized in that: The substrate further comprises: a peripheral area located at the periphery of the first display area and the second display area; the peripheral area is provided with a first scan driving circuit and a second scan driving circuit; The first scan driving circuit is electrically connected to the first scan line and configured to provide the first scan signal to the first scan line; the second scan driving circuit is electrically connected to the second scan line and configured to provide the second scan signal to the second scan line.

4. The display substrate according to claim 1, characterized in that: The substrate also includes: a peripheral area located outside the first display area and the second display area; a first scan drive circuit is arranged in the peripheral area, the first scan drive circuit is electrically connected to the first scan line, and is configured to provide the first scan signal to the first scan line; the first scan drive circuit is electrically connected to the second scan line through a control circuit, and is configured to provide the second scan signal to the second scan line under the control of the control circuit.

5. The display substrate according to claim 4, characterized in that: The control circuit includes: a control transistor; a gate of the control transistor is electrically connected to a control line, a first electrode of the control transistor is electrically connected to an output end of the first scan drive circuit and the first scan line, and a second electrode of the control transistor is electrically connected to the second scan line.

6. The display substrate according to claim 1, characterized in that: The driving subcircuit includes a driving transistor, the data writing subcircuit includes a data writing transistor, and the anode reset subcircuit includes an anode reset transistor; The first electrode of the driving transistor is electrically connected to the second electrode of the data writing transistor, the first electrode of the data writing transistor is electrically connected to the data line, and the gate of the data writing transistor is electrically connected to the first scanning line; the second electrode of the driving transistor is electrically connected to the second electrode of the anode reset transistor, the first electrode of the anode reset transistor is electrically connected to the second initial signal line, the gate of the anode reset transistor is electrically connected to the second scanning line, and the second electrode of the anode reset transistor is electrically connected to the anode of the at least one first light-emitting element.

7. The display substrate according to claim 6, characterized in that: The first pixel circuit further includes: a threshold compensation transistor, a first reset transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor; The gate of the threshold compensation transistor is electrically connected to the first scan line, the first electrode is electrically connected to the gate of the driving transistor, and the second electrode is electrically connected to the second electrode of the driving transistor; The gate of the first reset transistor is electrically connected to the reset control line, the first electrode is electrically connected to the first initial signal line, and the second electrode is electrically connected to the gate of the driving transistor; The gate of the first light emitting control transistor is electrically connected to the light emitting control line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the first electrode of the driving transistor; The gate of the second light emitting control transistor is electrically connected to the light emitting control line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the second electrode of the anode reset transistor; The first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the first power line.

8. The display substrate according to claim 7, characterized in that: The orthographic projection of the second scanning line on the substrate is located between the orthographic projection of the second initial signal line and the orthographic projection of the light emitting control line on the substrate.

9. The display substrate according to claim 6, characterized in that: The gate of the anode reset transistor and the second scan line are located in different film layers; the gate of the data write transistor and the first scan line are an integrated structure.

10. The display substrate according to claim 6, characterized in that: In the second display area, the second scan line is located at a side of the first scan line away from the substrate.

11. The display substrate according to claim 10, characterized in that: In a direction perpendicular to the display substrate, the display substrate of the second display area at least comprises: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer arranged on the substrate; The second scan line is located in the third conductive layer, and the first scan line is located in the first conductive layer.

12. The display substrate according to claim 11, characterized in that: The display substrate of the second display area further comprises: a fourth conductive layer located on a side of the third conductive layer away from the substrate; The fourth conductive layer at least includes: the data line.

13. The display substrate according to claim 6, characterized in that: A frame period of the first pixel circuit includes: a reset phase, a data writing phase and a light emitting phase; in the reset phase, the gate of the driving transistor is reset; in the data writing phase, a data signal is provided to the driving transistor through the data writing transistor; in the light emitting phase, the first light emitting element is driven to emit light; Taking two adjacent frame time periods as a group of time periods, the data write transistor is turned on under the control of the first scanning signal during the data writing phase of the first frame time period and the data writing phase of the second frame time period in a group of time periods; the anode reset transistor is turned on under the control of the second scanning signal during the data writing phase of the first frame time period in a group of time periods, and is turned off under the control of the second scanning signal during the data writing phase of the second frame time period in the group of time periods.

14. The display substrate according to claim 1, characterized in that: The display substrate further comprises: a plurality of second light emitting elements and a plurality of second pixel circuits located in the second display area, at least one second pixel circuit of the plurality of second pixel circuits being electrically connected to at least one second light emitting element of the plurality of second light emitting elements and configured to drive the at least one second light emitting element to emit light; The second pixel circuit includes at least a driving transistor, a data writing transistor and an anode reset transistor, the first electrode of the driving transistor is electrically connected to the data writing transistor, the second electrode of the driving transistor is electrically connected to the anode reset transistor; the gate of the anode reset transistor and the gate of the data writing transistor are both electrically connected to the first scanning line.

15. A display device, characterized in that: It comprises a display substrate and an optical sensor as claimed in any one of claims 1 to 14, wherein the optical sensor is located on a non-display surface side of the display substrate, and an orthographic projection of the optical sensor on the display substrate overlaps with the first display area.

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