Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a bottom dielectric layer, comprising a first dielectric layer and a second dielectric layer located on the first dielectric layer, a plurality of interconnection layers are formed in the first dielectric layer, comprising spaced first and second interconnection layers, a conductive plug is formed in the second dielectric layer and in contact with the first interconnection layer; a top dielectric layer located on the bottom dielectric layer; a first metal line penetrating through the top dielectric layer and in contact with the conductive plug, the first metal line serving as a signal line; a second metal line penetrating through the second dielectric layer and the top dielectric layer and in contact with the second interconnection layer, the second metal line serving as a power supply line, so that the power supply line and the second interconnection layer are electrically connected without the conductive plug, which is conducive to preventing the influence of the resistance of the conductive plug on the electrical connection performance between the power supply line and the second interconnection layer, optimizing the electrical connection performance between the power supply line and the second interconnection layer, reducing the IR drop, and improving the power supply efficiency of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the requirements of interconnects after the critical size reduction, the conduction between different metal layers or between a metal layer and a substrate is currently achieved through interconnect structures. As technology nodes advance, the size of interconnect structures is becoming smaller and smaller; correspondingly, the process of forming interconnect structures is becoming more and more difficult. The formation quality of interconnect structures has a significant impact on the back end of line (BEOL) electrical performance and device reliability, and in severe cases, it can affect the normal operation of semiconductor devices.

[0004] Metal wires typically include signal lines for transmitting signals and power lines for supplying power to the components within the chip.

[0005] However, the current power supply efficiency of the devices is relatively low. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the power supply efficiency of the device.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a bottom dielectric layer, the bottom dielectric layer including a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer having a plurality of interconnect layers formed therein, including a first interconnect layer and a second interconnect layer spaced apart, a conductive plug being formed in the second dielectric layer above the first interconnect layer and in contact with the first interconnect layer; a top dielectric layer located on the bottom dielectric layer; a first metal wire penetrating the top dielectric layer above the conductive plug and in contact with the conductive plug, the first metal wire serving as a signal line; and a second metal wire penetrating the second dielectric layer above the second interconnect layer and the top dielectric layer, and in contact with the second interconnect layer, the second metal wire serving as a power supply line.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a bottom dielectric layer, the bottom dielectric layer including a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer having a plurality of interconnect layers formed therein, including a first interconnect layer and a second interconnect layer spaced apart, a conductive plug being formed in the second dielectric layer at the top of the first interconnect layer in contact with the first interconnect layer; forming a top dielectric layer on the bottom dielectric layer; forming a first interconnect trench penetrating the top of the conductive plug in the top dielectric layer, and a second interconnect trench penetrating the second dielectric layer at the top of the second interconnect layer and the top dielectric layer, the first interconnect trench exposing the conductive plug, and the second interconnect trench exposing the second interconnect layer; filling the first interconnect trench and the second interconnect trench with conductive material to form a first metal wire and a second metal wire respectively, the first metal wire being in contact with the conductive plug and used as a signal line, and the second metal wire being in contact with the second interconnect layer and used as a power supply line.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] The semiconductor structure provided in this embodiment of the invention has a first metal line in contact with the conductive plug and used as a signal line, and a second metal line in contact with the second interconnect layer and used as a power supply line. Thus, the power supply line and the second interconnect layer do not need to be electrically connected through the conductive plug, which helps to prevent the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnect layer, optimizes the electrical connection performance between the power supply line and the second interconnect layer, reduces IR drop, and improves the power supply efficiency of the device.

[0011] In the semiconductor structure formation method provided by this invention, in the step of forming a first interconnect trench and a second interconnect trench, the first interconnect trench penetrates the top dielectric layer on the conductive plug, and the second interconnect trench penetrates the second dielectric layer and the top dielectric layer on the top of the second interconnect layer, and the second interconnect trench exposes the second interconnect layer. That is, the depth of the second interconnect trench is greater than that of the first interconnect trench. In the step of filling the first interconnect trench and the second interconnect trench with conductive material to form a first metal line and a second metal line respectively, the first metal line contacts the conductive plug and is used as a signal line, and the second metal line contacts the second interconnect layer and is used as a power supply line. Thus, the power supply line and the second interconnect layer do not need to be electrically connected through the conductive plug, which helps to prevent the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnect layer, optimizes the electrical connection performance between the power supply line and the second interconnect layer, reduces IR drop, and improves the power supply efficiency of the device. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a semiconductor structure.

[0013] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 3 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] As is known from the background technology, the power supply efficiency of current devices is relatively low. This paper analyzes the reasons for the low power supply efficiency of devices using a specific semiconductor structure. Figure 1 This is a schematic diagram of a semiconductor structure.

[0016] refer to Figure 1 The semiconductor structure includes: a substrate 10, comprising a base (not shown), a gate structure (not shown) on the substrate, source / drain doped regions 11 on both sides of the gate structure, and a first dielectric layer 12 on the substrate covering the source / drain doped regions 11. The first dielectric layer 12 has a plurality of source / drain interconnect layers in contact with the source / drain doped regions 11, including a first source / drain interconnect layer 13 and a second source / drain interconnect layer 14; a second dielectric layer 15, located on the first dielectric layer 12 and covering the source / drain interconnect layers; and a conductive plug located in the second dielectric layer 15 and connected to the source / drain interconnect layers. The conductive plugs are in contact with each other, including a first conductive plug 16 in contact with the first source-drain interconnect layer 13 and a second conductive plug 17 in contact with the second source-drain interconnect layer 14; a third dielectric layer 18 is located on the second dielectric layer 15 and covers the conductive plugs; a plurality of metal lines are located in the third dielectric layer 18, including a signal line 19(1) in contact with the first conductive plug 16 and a power supply line 19(2) in contact with the second conductive plug 17, wherein the line width of the power supply line 19(2) is greater than the line width of the signal line 19(1).

[0017] In the semiconductor structure, the power supply line 19(2) has a larger linewidth than the signal line 19(1) in order to reduce the resistance of the power supply line 19(2) and thus reduce the IR drop. Moreover, the power supply line 19(2) and the signal line 19(1) are formed in the same process step, and both the power supply line 19(2) and the signal line 19(1) need to be electrically connected to the corresponding source-drain interconnect layer through conductive plugs.

[0018] However, the power supply line 19(2) is used to supply power to the source-drain doped region 11 through the source-drain interconnect layer. The power supply line 19(2) and the source-drain interconnect layer are electrically connected through conductive plugs. The resistance of the conductive plugs will reduce the power supply efficiency of the device.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a bottom dielectric layer, the bottom dielectric layer including a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer having a plurality of interconnect layers formed therein, including a first interconnect layer and a second interconnect layer spaced apart, a conductive plug being formed in the second dielectric layer above the first interconnect layer and in contact with the first interconnect layer; a top dielectric layer located on the bottom dielectric layer; a first metal wire penetrating the top dielectric layer above the conductive plug and in contact with the conductive plug, the first metal wire serving as a signal line; and a second metal wire penetrating the second dielectric layer above the second interconnect layer and the top dielectric layer, and in contact with the second interconnect layer, the second metal wire serving as a power supply line.

[0020] The semiconductor structure provided in this embodiment of the invention has a first metal line in contact with the conductive plug and used as a signal line, and a second metal line in contact with the second interconnect layer and used as a power supply line. Thus, the power supply line and the second interconnect layer do not need to be electrically connected through the conductive plug, which helps to prevent the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnect layer, optimizes the electrical connection performance between the power supply line and the second interconnect layer, reduces IR drop, and improves the power supply efficiency of the device.

[0021] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 2 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0022] like Figure 2As shown, in this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 including a bottom dielectric layer 101, the bottom dielectric layer 101 including a first dielectric layer 130 and a second dielectric layer 150 located on the first dielectric layer 130, the first dielectric layer 130 having a plurality of interconnect layers, including a first interconnect layer 170 and a second interconnect layer 180 spaced apart, the second dielectric layer 150 at the top of the first interconnect layer 170 having a conductive plug 160 in contact with the first interconnect layer 170; a top dielectric layer 102 located on the bottom dielectric layer 101; a first metal line 210 penetrating the top of the conductive plug 160 in the top dielectric layer 102 and in contact with the conductive plug 160, the first metal line 210 being used as a signal line; and a second metal line 220 penetrating the second dielectric layer 150 and the top dielectric layer 102 at the top of the second interconnect layer 180 and in contact with the second interconnect layer 180, the second metal line 220 being used as a power rail.

[0023] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0024] Depending on the actual process, the substrate 100 includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field-effect transistors, resistive structures, conductive structures, etc.

[0025] Specifically, in this embodiment, the substrate 100 further includes a substrate (not shown), a gate structure (not shown) on the substrate, and source / drain doped regions 140 located on both sides of the gate structure. The gate structure and the source / drain doped regions 140 located on both sides of the gate structure are used to form a MOS transistor.

[0026] The substrate provides a process platform for transistor fabrication. The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0027] The gate structure is used to enable and disable the conductive channel of a transistor. The material of the gate structure includes any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0028] In this embodiment, the substrate 100 further includes a gate dielectric layer (not shown) located between the gate structure and the channel structure 110. The gate dielectric layer is used to achieve electrical isolation between the gate structure and the channel structure.

[0029] In this embodiment, the material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0030] The source / drain doped region 140 is used as the source or drain of a transistor. As an example, when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions, and the stress layer material is Si or SiGe; when forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions, and the stress layer material is Si or SiC.

[0031] As an embodiment, the substrate 100 further includes a protrusion 105 discrete on the substrate, a channel structure 110 located on the protrusion 105, and an isolation layer 115 located on the substrate and surrounding the protrusion 105; the gate structure is located on the isolation layer 115 and spans the channel structure 110; the source / drain doped regions 140 are located within the channel structures 110 on both sides of the gate structure.

[0032] The channel structure 110 is used to provide a conductive channel for the field-effect transistor. The materials of the protrusion 105 and the channel structure 110 include one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0033] In this embodiment, the channel structure 110 is a fin, and the gate structure correspondingly spans the fin and covers part of the top and part of the sidewall of the fin. Specifically, the fin is connected to the protrusion 105. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the channel structure layer includes one or more channel layers arranged at intervals in sequence, and the gate structure correspondingly spans the channel structure layer and surrounds the channel layer.

[0034] The isolation layer 115 is used to isolate adjacent protrusions 105 and also to isolate the substrate from the gate structure. The isolation layer 115 exposes the channel structure 110. The material of the isolation layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0035] In this embodiment, the bottom dielectric layer 101 is located above the substrate and covers the source / drain doped regions 140. Specifically, in this embodiment, the bottom dielectric layer 101 is located on the isolation layer 115.

[0036] The bottom dielectric layer 101 can be a multilayer structure or a single-layer structure. In this embodiment, the bottom dielectric layer 101 is a multilayer structure as an example for illustration.

[0037] In the bottom dielectric layer 101, the first dielectric layer 130 is used to achieve electrical isolation between interconnect layers, and the second dielectric layer 150 is used to achieve electrical isolation between conductive plugs 160.

[0038] Both the first dielectric layer 130 and the second dielectric layer 150 are made of dielectric materials, such as one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. As an example, the first dielectric layer 130 is made of silicon oxide. As an example, the second dielectric layer 180 is made of silicon hydroxide.

[0039] The interconnect layers are used to realize electrical connections between functional structures within the substrate 100 and external circuits or other interconnect structures. There are multiple interconnect layers, thereby enabling electrical connections between multiple functional structures within the substrate 100 and external circuits or other interconnect structures.

[0040] The interconnect layer is made of a conductive material, including one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN. As an example, the interconnect layer is made of Cu. Cu has low resistivity, which helps reduce RC delay in subsequent processes, and Cu also has excellent electromigration resistance.

[0041] In one embodiment, the interconnect layer is located in the first dielectric layer 130 on top of the source / drain doped region 140 and is in contact with the source / drain doped region 140. That is, the interconnect layer serves as a source / drain interconnect layer to realize the electrical connection between the source / drain doped region 140 and external circuits or interconnect structures.

[0042] In other implementations, depending on the actual process requirements, the interconnect layer may also be other types of interconnect layers used to realize electrical connections between other components and external circuits or interconnect structures.

[0043] In this embodiment, for ease of illustration and explanation, only two device regions in the substrate 100 are shown. Each device region has a corresponding MOS transistor. Accordingly, the first interconnect layer 170 and the second interconnect layer 180 are used to realize the electrical connection between the source and drain doped regions 140 of the two device regions and external circuits or other interconnect structures.

[0044] The conductive plug 160 is used to enable electrical connection between the interconnect layer and external circuits or other interconnect structures. Specifically, in this embodiment, the conductive plug 160 is used to enable electrical connection between the first interconnect layer 170 and external circuits or other interconnect structures.

[0045] The conductive plug 160 is made of a conductive material. The material of the conductive plug 160 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0046] The top dielectric layer 102 is used to achieve electrical isolation between the metal wires. The top dielectric layer 102 covers the conductive plug 160.

[0047] The top dielectric layer 102 is made of a dielectric material. The material of the top dielectric layer 102 may include one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. Specifically, the material of the top dielectric layer 102 may be a low-k dielectric material or an ultra-low-k dielectric material, thereby effectively reducing the capacitance between metal lines and thus reducing the RC delay of the device. As an example, the material of the top dielectric layer 102 is silicon hydroxide.

[0048] The first metal line 210 is in contact with the conductive plug 160, and the conductive plug 160 is in contact with the first interconnect layer 170. Therefore, the first metal line 210 is used to realize the electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. In this embodiment, the first metal line 210 is used as a signal line to realize the signal connection between the source / drain doped region 140 and external circuits or other interconnect structures.

[0049] The second metal line 220 is in contact with the second interconnect layer 180, and the second interconnect layer 180 is in contact with the source / drain doped region 140. Therefore, the second metal line 220 is used to realize the electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. Specifically, in this embodiment, the second metal line 220 is used as a power supply line, that is, the second metal line 220 is used to supply power to the source / drain doped region 140.

[0050] The second metal line 220 is in contact with the second interconnect layer 180 and is used as a power supply line, so that the power supply line and the second interconnect layer 180 do not need to be electrically connected through the conductive plug 160. This helps to prevent the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnect layer 180, optimizes the electrical connection performance between the power supply line and the second interconnect layer 180, reduces IR drop, and improves the power supply efficiency of the device.

[0051] Moreover, in this embodiment, the linewidth of the second metal line 220 is greater than that of the first metal line 210. That is, the linewidth of the power supply line is larger than that of the signal line, which is beneficial to reduce the resistance of the power supply line, reduce IR drop, and further improve the power supply efficiency of the device.

[0052] Both the first metal wire 210 and the second metal wire 220 are made of conductive materials. As an example, the material of the first metal wire 210 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; the material of the second metal wire 220 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0053] The first metal line 210 may include a first anti-diffusion barrier layer (not shown) located on the sidewall and bottom of the first interconnect trench 230, and a first metal layer (not shown) located on the first anti-diffusion barrier layer and filling the first interconnect trench; the second metal line 220 may include a second anti-diffusion barrier layer (not shown) located on the sidewall and bottom of the second interconnect trench 240, and a second metal layer (not shown) located on the second anti-diffusion barrier layer and filling the second interconnect trench.

[0054] In this embodiment, the first metal wire 210 and the second metal wire 220 are formed in the same step. Therefore, the structure of the first metal wire 210 and the structure of the second metal wire 220 are the same, and the material of the first metal wire 210 and the material of the second metal wire 220 are the same.

[0055] Specifically, in this embodiment, the material of the first anti-diffusion barrier layer is the same as the material of the second anti-diffusion barrier layer, and the materials of the first metal layer and the second metal layer are the same.

[0056] As an example, the materials of the first anti-diffusion barrier layer and the second anti-diffusion barrier layer are both TiN; the materials of the first metal layer and the second metal layer are both Cu. Cu has a low resistivity, which is beneficial to reduce RC delay in the subsequent process, and Cu has excellent anti-electromigration ability.

[0057] The number of the first metal lines 210 can be one or more. The number of the second metal lines 220 can be one or more. It should be noted that in actual processes, when there are multiple second metal lines 220, based on the actual pattern of the interconnect layer and the metal lines, some of the second metal lines 220 may not be in contact with the second interconnect layer 180.

[0058] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0059] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0060] refer to Figure 3 A substrate 100 is provided, the substrate 100 including a bottom dielectric layer 101, the bottom dielectric layer 101 including a first dielectric layer 130 and a second dielectric layer 150 located on the first dielectric layer 130, a plurality of interconnect layers are formed in the first dielectric layer 130, including a first interconnect layer 170 and a second interconnect layer 180 spaced apart, and a conductive plug 160 in contact with the first interconnect layer 170 is formed in the second dielectric layer 180 on top of the first interconnect layer 170.

[0061] Substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0062] Depending on the actual process, the substrate 100 includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field-effect transistors, resistive structures, conductive structures, etc.

[0063] Specifically, in this embodiment, the substrate 100 further includes a substrate (not shown), a gate structure (not shown) on the substrate, and source / drain doped regions 140 located on both sides of the gate structure. The gate structure and the source / drain doped regions 140 located on both sides of the gate structure are used to form a MOS transistor.

[0064] The substrate provides a process platform for transistor fabrication. The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0065] The gate structure is used to enable and disable the conductive channel of a transistor. The material of the gate structure includes any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0066] In this embodiment, the substrate 100 further includes a gate dielectric layer (not shown) located between the gate structure and the channel structure 110. The gate dielectric layer is used to achieve electrical isolation between the gate structure and the channel structure.

[0067] The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0068] The source / drain doped region 140 is used as the source or drain of a transistor. As an example, when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions, and the stress layer material is Si or SiGe; when forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions, and the stress layer material is Si or SiC.

[0069] As an embodiment, the substrate 100 further includes a protrusion 105 discrete on the substrate, a channel structure 110 located on the protrusion 105, and an isolation layer 115 located on the substrate and surrounding the protrusion 105; the gate structure is located on the isolation layer 115 and spans the channel structure 110; the source / drain doped regions 140 are located within the channel structures 110 on both sides of the gate structure.

[0070] The channel structure 110 is used to provide a conductive channel for the field-effect transistor. The materials of the protrusion 105 and the channel structure 110 include one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0071] In this embodiment, the channel structure 110 is a fin, and the gate structure correspondingly spans the fin and covers part of the top and part of the sidewall of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the channel structure layer includes one or more channel layers arranged at intervals in sequence, and the gate structure correspondingly spans the channel structure layer and surrounds the channel layer.

[0072] The isolation layer 115 is used to isolate adjacent protrusions 105 and also to isolate the substrate from the gate structure. The isolation layer 115 exposes the channel structure 110. The material of the isolation layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0073] In this embodiment, the bottom dielectric layer 101 is located above the substrate and covers the source / drain doped regions 140. Specifically, in this embodiment, the bottom dielectric layer 101 is located on the isolation layer 115.

[0074] The bottom dielectric layer 101 can be a multilayer structure or a single-layer structure. In this embodiment, the bottom dielectric layer 101 is a multilayer structure as an example for illustration.

[0075] In the bottom dielectric layer 101, the first dielectric layer 130 is used to achieve electrical isolation between interconnect layers, and the second dielectric layer 150 is used to achieve electrical isolation between conductive plugs 160.

[0076] Both the first dielectric layer 130 and the second dielectric layer 150 are made of dielectric materials, such as one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. As an example, the first dielectric layer 130 is made of silicon oxide. As an example, the second dielectric layer 180 is made of silicon hydroxide.

[0077] The interconnect layers are used to realize electrical connections between functional structures within the substrate 100 and external circuits or other interconnect structures. There are multiple interconnect layers, thereby enabling electrical connections between multiple functional structures within the substrate 100 and external circuits or other interconnect structures.

[0078] The interconnect layer is made of a conductive material, including one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN. As an example, the interconnect layer is made of Cu. Cu has low resistivity, which helps reduce RC delay in subsequent processes, and Cu also has excellent electromigration resistance.

[0079] In one embodiment, the interconnect layer is located in the first dielectric layer 130 on top of the source / drain doped region 140 and is in contact with the source / drain doped region 140. That is, the interconnect layer serves as a source / drain interconnect layer to realize the electrical connection between the source / drain doped region 140 and external circuits or interconnect structures.

[0080] In other implementations, depending on the actual process requirements, the interconnect layer may also be other types of interconnect layers used to realize electrical connections between other components and external circuits or interconnect structures.

[0081] In this embodiment, for ease of illustration and explanation, only two device regions in the substrate 100 are shown. Each device region has a corresponding MOS transistor. Accordingly, the first interconnect layer 170 and the second interconnect layer 180 are used to realize the electrical connection between the source and drain doped regions 140 of the two device regions and external circuits or other interconnect structures.

[0082] The conductive plug 160 is used to enable electrical connection between the interconnect layer and external circuits or other interconnect structures. Specifically, in this embodiment, the conductive plug 160 is used to enable electrical connection between the first interconnect layer 170 and external circuits or other interconnect structures.

[0083] The conductive plug 160 is made of a conductive material. The material of the conductive plug 160 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0084] Continue to refer to Figure 3 A top dielectric layer 102 is formed on the bottom dielectric layer 101. The top dielectric layer 102 covers the conductive plug 160.

[0085] Subsequently, multiple metal lines are formed in the top dielectric layer 102, which is used to achieve electrical isolation between the metal lines.

[0086] The material of the top dielectric layer 102 is a dielectric material. The material of the top dielectric layer 102 may include one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG. Specifically, the material of the top dielectric layer 102 may be a low-k dielectric material or an ultra-low-k dielectric material, thereby effectively reducing the capacitance between metal lines and thus reducing the RC delay of the device. As an example, the material of the top dielectric layer 102 is silicon hydroxide.

[0087] refer to Figures 4 to 8 A first interconnect trench 230 is formed through the top dielectric layer 102 of the conductive plug 160, and a second interconnect trench 240 is formed through the second dielectric layer 150 and the top dielectric layer 102 of the second interconnect layer 180 (e.g., Figure 7 As shown), the first interconnect trench 230 exposes the conductive plug 160, and the second interconnect trench 240 exposes the second interconnect layer 180.

[0088] The first interconnecting groove 230 is used to provide spatial location for forming the first metal wire.

[0089] The first interconnect groove 230 penetrates the top dielectric layer 102 of the top of the conductive plug 160 and exposes the conductive plug 160 so that the subsequent first metal wire can contact the conductive plug 160.

[0090] The second interconnecting groove 240 is used to provide space for forming the second metal wire.

[0091] The second interconnect trench 240 penetrates the second dielectric layer 150 and the top dielectric layer 102 on the top of the second interconnect layer 180 and exposes the second interconnect layer 180 so that the subsequent second metal line can contact the second interconnect layer 180.

[0092] Furthermore, in this embodiment, the first metal wire is used as a signal line, the second metal wire is used as a power supply line, and the second interconnect trench 240 penetrates the second dielectric layer 150 and the top dielectric layer 102 on the top of the second interconnect layer 180, and exposes the second interconnect layer 180. Thus, the subsequent power supply line is in direct contact with the second interconnect layer 180, and there is no need to achieve electrical connection between the power supply line and the second interconnect layer 180 through conductive plugs. This helps to prevent the resistance of the conductive plugs from affecting the electrical connection performance between the power supply line and the second interconnect layer 180, optimizes the electrical connection performance between the power supply line and the second interconnect layer 180, reduces IR drop, and improves the power supply efficiency of the device.

[0093] In this embodiment, the opening linewidth of the second interconnect trench 240 is greater than the opening linewidth of the first interconnect trench 230. Correspondingly, after the first metal line is formed in the first interconnect trench 230 and the second metal line is formed in the second interconnect trench 240, the linewidth of the second metal line is greater than the linewidth of the first metal line. That is to say, the linewidth of the power supply line is larger than that of the signal line, which is beneficial to reduce the resistance of the power supply line, reduce IR drop, and thus improve the power supply efficiency of the device.

[0094] The number of the first interconnect slots 230 can be one or more. The number of the second interconnect slots 240 can be one or more. It should be noted that in actual manufacturing processes, when there are multiple second interconnect slots 240, based on the actual pattern of the interconnect layer and interconnect slots, some of the second interconnect slots 240 may not expose the second interconnect layer 180.

[0095] The steps for forming the first interconnecting slot 230 and the second interconnecting slot 240 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0096] refer to Figure 4 Multiple trenches are formed through the top dielectric layer 102, including a first interconnect trench 230 located on top of the conductive plug 160 and exposing the conductive plug 160, and a first initial trench 260 located above the second interconnect layer 180, the first initial trench 260 exposing the second dielectric layer 102.

[0097] In this embodiment, the opening linewidth of the first initial trench 260 is greater than the opening linewidth of the first interconnect trench 230, so as to form a second initial trench that penetrates the bottom of the second dielectric layer 102. The opening linewidth of the second interconnect trench formed by the second initial trench and the first initial trench 260 is larger, which correspondingly makes the linewidth of the second metal line subsequently formed in the second interconnect trench larger.

[0098] Specifically, in this embodiment, the step of forming multiple trenches penetrating the top dielectric layer 102 includes: forming a hard mask layer 250 on the top dielectric layer 102, wherein a plurality of mask openings (not shown) are formed in the hard mask layer 250; using the hard mask layer 250 as a mask, etching the top dielectric layer 102 along the mask openings to form a plurality of trenches penetrating the top dielectric layer 102.

[0099] The hard mask layer 250 is used as an etching mask to form the trench. The mask openings are used to define the size, shape, and location of the trench.

[0100] The hard mask layer 250 is made of a material that has etching selectivity with the materials of the top dielectric layer 102 and the bottom dielectric layer 101, so as to ensure that the hard mask layer 250 can play the role of an etching mask.

[0101] As one embodiment, the material of the hard mask layer 250 is titanium nitride.

[0102] In this embodiment, using the hard mask layer 250 as a mask, an anisotropic etching process is employed to etch the top dielectric layer 102 along the mask opening, forming multiple trenches. The anisotropic etching process is beneficial for providing the accuracy of pattern transfer, thereby improving the profile control of the trenches and the dimensional accuracy of the trenches. Specifically, the anisotropic etching process can be anisotropic dry etching.

[0103] refer to Figures 5 to 8 A second initial trench 270 is formed through the bottom of the second dielectric layer 102 of the first initial trench 260, the second initial trench 270 exposes the second interconnect layer 180, and the second initial trench 270 and the first initial trench 260 are used to form the second interconnect trench 240.

[0104] A second initial trench 270 is formed, thereby increasing the depth of the second interconnect trench so that the second interconnect trench can expose the second interconnect layer 180.

[0105] As one embodiment, the step of forming the second initial trench 270 includes:

[0106] like Figure 5 As shown, a sacrificial layer 245 is formed on the bottom and sidewall of the trench, and the sacrificial layer 245 located on the sidewall of the first interconnect trench 230 is in contact with the first interconnect trench 230, filling the first interconnect trench 230, while the sidewall of the sacrificial layer 245 located on the sidewall of the first initial trench 260 is separate.

[0107] The sacrificial layer 245 is used to form a shielding layer in the first interconnect trench 230 through subsequent etching processes, so that the shielding layer can shield and protect the second dielectric layer 150 at the bottom of the first interconnect trench 230 during the subsequent etching of the second dielectric layer 150 at the bottom of the first initial trench 260.

[0108] In this embodiment, the sacrificial layer 245 fills the first interconnect trench 230, and the sidewalls of the sacrificial layer 245 located on the sidewalls of the first initial trench 260 are separate. That is, the sacrificial layer 245 located on the sidewalls of the first initial trench 260 is thinner in the direction perpendicular to the sidewalls or bottom of the first initial trench 260, while the sacrificial layer 245 in the first interconnect trench 230 is thicker in the direction perpendicular to the bottom of the first interconnect trench 230 because they are in contact with each other. This is so that during the subsequent etching process of the sacrificial layer 245, while removing the sacrificial layer in the first initial trench 260, the sacrificial layer 245 in the first interconnect trench 230 can still retain a portion of its thickness to serve as the shielding layer.

[0109] In this embodiment, since the opening linewidth of the first initial trench 260 is greater than the opening linewidth of the first interconnect trench 230, during the formation of the sacrificial layer 245, as the thickness of the sacrificial layer 245 material on the bottom and sidewalls of the trench gradually increases, the sacrificial layer 245 material on the opposite sidewalls of the first interconnect trench 230 gradually comes into contact. Furthermore, by controlling the thickness of the sacrificial layer 245 to be less than 0.5 times the opening linewidth of the first initial trench 260, the sidewalls of the sacrificial layer 245 on the opposite sidewalls of the first initial trench 260 remain separate from each other.

[0110] In this embodiment, the sacrificial layer 245 is also formed on the top and sidewalls of the hard mask layer 250.

[0111] The sacrificial layer 245 is made of a material that is etchable selective to the top dielectric layer 102 and the bottom dielectric layer 101, so that after the sacrificial layer 245 is etched to form the shielding layer, the shielding layer can protect and shield the second dielectric layer 150 at the bottom of the first interconnect trench 230.

[0112] In addition, after the second initial trench is formed, the sacrificial layer 245 needs to be removed. The sacrificial layer 245 is made of a material that is easy to remove, so as to reduce the difficulty of removing the sacrificial layer 245, improve process compatibility, and reduce the probability of the process of removing the sacrificial layer 245 causing damage to other film structures (e.g., top dielectric layer, bottom dielectric layer).

[0113] In this embodiment, the material of the sacrificial layer 245 includes amorphous carbon or amorphous germanium.

[0114] As an example, the sacrificial layer 245 is made of amorphous carbon. Amorphous carbon is an readily available material, which helps reduce the process cost of forming the sacrificial layer 245. Moreover, amorphous carbon can be removed by an oxidation process, which helps reduce the difficulty of the subsequent removal of the sacrificial layer 245, simplifies the process flow, improves the manufacturing efficiency, and also helps reduce the impact of the sacrificial layer 245 on subsequent process steps and semiconductor structures.

[0115] In this embodiment, the sacrificial layer 245 is formed using a chemical vapor deposition (CVD) process. CVD offers good coverage, strong process compatibility, and low cost.

[0116] In other embodiments, depending on the material of the sacrificial layer and the actual process requirements, other processes may be used to form the sacrificial layer 245.

[0117] like Figure 6 As shown, the sacrificial layer 245 is etched to remove the sacrificial layer 245 located on the sidewall and bottom of the first initial trench 260, and the remaining sacrificial layer 245 filling the first interconnect trench 230 is used as a shielding layer 265.

[0118] During the subsequent etching of the second dielectric layer 150 at the bottom of the first initial trench 260, the shielding layer 265 serves to shield and protect the second dielectric layer 150 at the bottom of the first interconnect trench 230.

[0119] In this embodiment, an isotropic etching process is used to etch the sacrificial layer 245.

[0120] The isotropic etching process possesses the characteristics of isotropic etching, enabling the etching of the sacrificial layer 245 located on the sidewalls and bottom of the first initial trench 260. Furthermore, in this embodiment, since the sacrificial layers 245 located on the sidewalls of the first initial trench 260 are mutually independent, and the sacrificial layer 245 located in the first interconnect trench 230 completely fills the first interconnect trench 230, the isotropic etching process removes the sacrificial layer 245 located in the first initial trench 260 while retaining a portion of its thickness in the first interconnect trench 230 to serve as the shielding layer 265.

[0121] Moreover, in this embodiment, no photomask or mask is needed during the formation of the shielding layer 265, which helps to save process costs and simplify the process flow.

[0122] Specifically, the isotropic etching process can be one or both of isotropic dry etching and wet etching processes.

[0123] like Figure 7 As shown, using the shielding layer 265 as a mask, the second dielectric layer 150 at the bottom of the first initial trench 260 is etched, forming a second initial trench 270 below the first initial trench 260, exposing the second interconnect layer 180. The second initial trench 270 and the first initial trench 260 constitute the second interconnect trench 240. The second initial trench 270 is connected to the first initial trench 260.

[0124] In this embodiment, the process of etching the second dielectric layer 150 at the bottom of the first initial trench 260 includes an anisotropic etching process. Anisotropic etching improves the accuracy of pattern transfer, thereby enhancing the cross-sectional morphology quality and dimensional accuracy of the second initial trench 270.

[0125] like Figure 8 As shown, after forming the second initial trench 270 and before filling the first interconnect trench 230 and the second interconnect trench 240 with conductive material, the method of forming the semiconductor structure further includes removing the shielding layer 265.

[0126] Remove the shielding layer 265 to expose the space of the first interconnect trench 230 so that conductive material can be subsequently filled into the first interconnect trench 230.

[0127] In this embodiment, the shielding layer 265 is made of amorphous carbon, and the sacrificial layer 124 is removed using an oxidation process. The oxygen-containing gas in the oxidation process reacts with the amorphous carbon material to generate carbon dioxide gas, which is then discharged from the reaction chamber. This removal process is simple, highly compatible, and has few side effects, thus reducing process costs and increasing production capacity.

[0128] In other embodiments, when the sacrificial layer is made of amorphous germanium, a wet etching process is used to remove the sacrificial layer. Specifically, HCl vapor is used for the wet etching process. In other embodiments, when the sacrificial layer is made of other materials, a suitable process is used to remove the sacrificial layer accordingly.

[0129] In this embodiment, after forming the second initial trench 270, the formation of the semiconductor structure further includes removing the hard mask layer 250. Removing the hard mask layer 250 reduces the thickness that subsequent conductive materials need to fill, thereby reducing the difficulty of filling subsequent conductive materials.

[0130] It should be noted that the steps for forming the second initial trench 270 described above are merely an example. The steps for forming the second initial trench 270 are not limited to this. For example, in other embodiments, the steps for forming the second initial trench include: forming a patterned layer on the top dielectric layer, the patterned layer filling the first interconnect layer and exposing the first initial trench; and using the patterned layer as a mask, etching the second dielectric layer at the bottom of the first initial trench.

[0131] It should also be noted that, in this embodiment, the second interconnecting trench is constructed by forming a first interconnecting trench and a first initial trench, and then connecting the second initial trench to the first initial trench. That is, in this embodiment, the first interconnecting trench and the second interconnecting trench are formed in different steps. The process steps for forming the first interconnecting trench and the second interconnecting trench are not limited to this.

[0132] In other embodiments, depending on the actual process, the first interconnect trench and the second interconnect trench can also be formed in the same step.

[0133] refer to Figure 9 Conductive material is filled into the first interconnect groove 230 and the second interconnect groove 240 to form a first metal line 210 and a second metal line 220, respectively. The first metal line 210 is in contact with the conductive plug 160 and is used as a signal line, and the second metal line 220 is in contact with the second interconnect layer 180 and is used as a power rail.

[0134] The first metal line 210 is in contact with the conductive plug 160, and the conductive plug 160 is in contact with the first interconnect layer 170. Therefore, the first metal line 210 is used to realize the electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. In this embodiment, the first metal line 210 is used as a signal line to realize the signal connection between the source / drain doped region 140 and external circuits or other interconnect structures.

[0135] The second metal line 220 is in contact with the second interconnect layer 180, and the second interconnect layer 180 is in contact with the source / drain doped region 140. Therefore, the second metal line 220 is used to realize the electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. Specifically, in this embodiment, the second metal line 220 is used as a power supply line, that is, the second metal line 220 is used to supply power to the source / drain doped region 140.

[0136] The second metal line 220 is in contact with the second interconnect layer 180 and is used as a power supply line, so that the power supply line and the second interconnect layer 180 do not need to be electrically connected through the conductive plug 160. This helps to prevent the resistance of the conductive plug from affecting the electrical connection performance between the power supply line and the second interconnect layer 180, optimizes the electrical connection performance between the power supply line and the second interconnect layer 180, reduces IR drop, and improves the power supply efficiency of the device.

[0137] Moreover, in this embodiment, the opening linewidth of the second interconnect trench 240 is greater than the opening linewidth of the first interconnect trench 230. Correspondingly, the linewidth of the second metal line 220 is greater than the linewidth of the first metal line 210. In other words, the linewidth of the power supply line is larger than that of the signal line, which is beneficial to reduce the resistance of the power supply line, reduce IR drop, and further improve the power supply efficiency of the device.

[0138] Both the first metal wire 210 and the second metal wire 220 are conductive materials. As an example, the material of the first metal wire 210 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; the material of the second metal wire 220 includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0139] The first metal line 210 may include a first anti-diffusion barrier layer (not shown) located on the sidewall and bottom of the first interconnect trench 230, and a first metal layer (not shown) located on the first anti-diffusion barrier layer and filling the first interconnect trench; the second metal line 220 may include a second anti-diffusion barrier layer (not shown) located on the sidewall and bottom of the second interconnect trench 240, and a second metal layer (not shown) located on the second anti-diffusion barrier layer and filling the second interconnect trench.

[0140] In this embodiment, the first metal wire 210 and the second metal wire 220 are formed in the same step. Therefore, the structure of the first metal wire 210 and the structure of the second metal wire 220 are the same, and the material of the first metal wire 210 and the material of the second metal wire 220 are the same.

[0141] Specifically, in this embodiment, the material of the first anti-diffusion barrier layer is the same as the material of the second anti-diffusion barrier layer, and the materials of the first metal layer and the second metal layer are the same.

[0142] As an example, the materials of the first anti-diffusion barrier layer and the second anti-diffusion barrier layer are both TiN; the materials of the first metal layer and the second metal layer are both Cu. Cu has a low resistivity, which is beneficial to reduce RC delay in the subsequent process, and Cu has excellent anti-electromigration ability.

[0143] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a bottom dielectric layer, which is a stacked structure. The bottom dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer. A plurality of interconnect layers are formed in the first dielectric layer, including a first interconnect layer and a second interconnect layer spaced apart. A conductive plug in contact with the first interconnect layer is formed in the second dielectric layer on top of the first interconnect layer. A top dielectric layer is located on top of the bottom dielectric layer; A first metal wire penetrates the top dielectric layer at the top of the conductive plug and is in contact with the conductive plug; the first metal wire is used as a signal wire. The second metal wire passes through the second dielectric layer and the top dielectric layer at the top of the second interconnect layer and is in contact with the second interconnect layer. The second metal wire is used as a power supply line.

2. The semiconductor structure as described in claim 1, characterized in that, The line width of the second metal wire is greater than that of the first metal wire.

3. The semiconductor structure as described in claim 1, characterized in that, The interconnect layer is made of one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; the conductive plug is made of one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

4. The semiconductor structure as described in claim 1, characterized in that, The material of the first metal wire includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; the material of the second metal wire includes one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the bottom dielectric layer includes one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG; the material of the top dielectric layer includes one or more of SiOCH, SiOC, SiO2, FSG, BSG, PSG, and BPSG.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a substrate, a gate structure located on the substrate, and source / drain doped regions located on both sides of the gate structure; The bottom dielectric layer is located above the substrate and covers the source / drain doped regions; The interconnect layer is located in the first dielectric layer on top of the source / drain doped region and is in contact with the source / drain doped region.

7. The semiconductor structure as described in claim 6, characterized in that, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the gate structure includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

8. The semiconductor structure as described in claim 6, characterized in that, The substrate further includes a gate dielectric layer located between the gate structure and the channel structure; the material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a bottom dielectric layer, the bottom dielectric layer having a stacked structure, the bottom dielectric layer including a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer having a plurality of interconnect layers formed therein, including a first interconnect layer and a second interconnect layer spaced apart, and a conductive plug in contact with the first interconnect layer being formed in the second dielectric layer on top of the first interconnect layer; A top dielectric layer is formed on the bottom dielectric layer; A first interconnect trench is formed through the top dielectric layer of the conductive plug, and a second interconnect trench is formed through the second dielectric layer and the top dielectric layer of the second interconnect layer. The first interconnect trench exposes the conductive plug, and the second interconnect trench exposes the second interconnect layer. Conductive material is filled into the first interconnect trench and the second interconnect trench to form a first metal wire and a second metal wire, respectively. The first metal wire is in contact with the conductive plug and is used as a signal line, and the second metal wire is in contact with the second interconnect layer and is used as a power supply line.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The opening linewidth of the second interconnecting slot is greater than that of the opening linewidth of the first interconnecting slot.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The steps of forming the first interconnect trench and the second interconnect trench include: forming a plurality of trenches penetrating the top dielectric layer, including a first interconnect trench located on top of the conductive plug and exposing the conductive plug, and a first initial trench located above the second interconnect layer, the first initial trench exposing the second dielectric layer; A second initial trench is formed through the bottom of the first initial trench, forming a second dielectric layer. The second initial trench exposes the second interconnect layer, and the second initial trench and the first initial trench are used to form the second interconnect trench.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The opening linewidth of the first initial trench is greater than the opening linewidth of the first interconnect trench; The step of forming the second initial trench includes: forming a sacrificial layer on the bottom and sidewall of the trench, with the sacrificial layer located on the sidewall of the first interconnect trench in contact with each other, filling the first interconnect trench, and the sidewall of the sacrificial layer located on the sidewall of the first initial trench being separate; The sacrificial layer is etched to remove the sacrificial layer located on the sidewalls and bottom of the first initial trench, and the remaining sacrificial layer filling the first interconnect trench is used as a shielding layer. Using the shielding layer as a mask, the second dielectric layer at the bottom of the first initial trench is etched to form the second initial trench below the first initial trench.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the second initial trench includes: forming a patterned layer on the top dielectric layer, the patterned layer filling the first interconnect trench and exposing the first initial trench; and etching a second dielectric layer at the bottom of the first initial trench using the patterned layer as a mask.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the second initial trench and before filling the first interconnect trench and the second interconnect trench with conductive material, the method of forming the semiconductor structure further includes removing the shielding layer.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, The formation of the sacrificial layer includes a chemical vapor deposition process.

16. The method for forming a semiconductor structure as described in claim 12, characterized in that, The sacrificial layer is etched using an isotropic etching process.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process of etching the second dielectric layer at the bottom of the first initial trench includes anisotropic etching processes.

18. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the sacrificial layer includes amorphous carbon or amorphous germanium.

19. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming multiple trenches penetrating the top dielectric layer includes: forming a hard mask layer on the top dielectric layer, wherein a plurality of mask openings are formed in the hard mask layer; Using the hard mask layer as a mask, the top dielectric layer is etched along the opening of the mask to form multiple trenches penetrating the top dielectric layer; In the step of forming the sacrificial layer, the sacrificial layer is also formed on the top and sidewalls of the hard mask layer.

20. The method for forming a semiconductor structure according to any one of claims 9-19, characterized in that, The substrate further includes a substrate, a gate structure located on the substrate, and source / drain doped regions located on both sides of the gate structure; The bottom dielectric layer is located above the substrate and covers the source / drain doped regions; the interconnect layer is located in the first dielectric layer on top of the source / drain doped regions and is in contact with the source / drain doped regions.

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