Display Substrate, Preparation Method Thereof, and Display Device

Abstract

The present disclosure provides a display substrate, a preparation method thereof, and a display device. The display substrate includes a plurality of first pixel defining structures, second pixel defining structures, and third pixel defining structures; the first pixel defining structures have a long strip shape extending along a first direction and are arranged in sequence along a second direction; the second pixel defining structures are arranged at intervals between the first pixel defining structures, and at least one third pixel defining structure is arranged between the first pixel defining structures and the second pixel defining structures; the height of the third pixel defining structure is less than the height of the second pixel defining structure. By providing the third pixel defining structure, the third pixel defining structure can achieve a flow guiding function in the edge region of the first pixel defining structure, effectively reducing the thickness of the organic light emitting layer in the edge region of the first pixel defining structure, effectively reducing the brightness in the edge region of the first pixel defining structure, improving the display uniformity, and improving the display quality.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is an active light-emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, bendability, and low cost. With the continuous development of display technologies, a display device using an OLED as a light-emitting device and controlled by a thin film transistor (TFT) has become the mainstream product in the current display field.

[0003] Currently, existing OLED display devices have problems of poor display uniformity. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0005] The technical problem to be solved by the exemplary embodiments of the present disclosure is to provide a display substrate, a method for manufacturing the same, and a display device to solve the problem of poor display uniformity in existing structures.

[0006] To solve the above technical problem, an exemplary embodiment of the present disclosure provides a display substrate, including a substrate and a pixel definition layer disposed on the substrate; the pixel definition layer includes a plurality of first pixel definition structures, a plurality of second pixel definition structures, and a plurality of third pixel definition structures; the first pixel definition structure has a long strip shape extending along a first direction, and a plurality of first pixel definition structures are arranged in sequence along a second direction, and the first direction intersects with the second direction; the second pixel definition structure has a long strip shape extending along the second direction, and a plurality of second pixel definition structures are spaced apart and disposed between adjacent first pixel definition structures; at least one third pixel definition structure is disposed between the first pixel definition structure and the second pixel definition structure; in a direction perpendicular to the substrate, the height of the third pixel definition structure is less than the height of the second pixel definition structure.

[0007] In an exemplary embodiment, in a direction perpendicular to the substrate, the height of the second pixel definition structure is less than the height of the first pixel definition structure.

[0008] In an exemplary embodiment, in a direction perpendicular to the substrate, the height of the first pixel definition structure is 1.0 μm to 2.0 μm.

[0009] In an exemplary embodiment, in a direction perpendicular to the substrate, the height of the second pixel defining structure is from 0.3 μm to 0.8 μm.

[0010] In an exemplary embodiment, in a direction perpendicular to the substrate, the height of the third pixel defining structure is from 0.1 μm to 0.3 μm.

[0011] In an exemplary embodiment, there is a first distance between an edge of the first pixel defining structure adjacent to the second pixel defining structure and an end face of the second pixel defining structure adjacent to the first pixel defining structure, and the first distance is greater than or equal to 2 μm.

[0012] In an exemplary embodiment, in a plane perpendicular to the first direction, the cross-sectional shape of the first pixel defining structure is a first trapezoid, the width of the upper base of the first trapezoid is greater than or equal to 15 μm, and the first slope angle of the side of the first trapezoid is from 30° to 70°; in a plane perpendicular to the second direction, the cross-sectional shape of the second pixel defining structure is a second trapezoid, the width of the upper base of the second trapezoid is greater than or equal to 3 μm, and the second slope angle of the side of the second trapezoid is from 30° to 90°.

[0013] In an exemplary embodiment, the first pixel defining structure has stronger liquid repellency than the second pixel defining structure, and the second pixel defining structure has stronger liquid repellency than the third pixel defining structure.

[0014] In an exemplary embodiment, the material of the third pixel defining structure includes a liquidophilic inorganic material or a liquidophilic organic material.

[0015] In an exemplary embodiment, there is a first overlapping region between the orthographic projection of the first pixel defining structure on the substrate and the orthographic projection of the third pixel defining structure on the substrate, and in the second direction, the first overlapping width of the first overlapping region is from 1 μm to 3 μm.

[0016] In an exemplary embodiment, there is a second overlapping region between the orthographic projection of the second pixel defining structure on the substrate and the orthographic projection of the third pixel defining structure on the substrate, and in the second direction, the second overlapping width of the second overlapping region is from 1 μm to 3 μm.

[0017] In an exemplary embodiment, the first pixel defining structure and the third pixel defining structure are an integrally connected structure.

[0018] In an exemplary embodiment, a first side of the first pixel defining structure, which is away from the second pixel defining structure, has a first slope angle, and a third side of the first pixel defining structure, which is away from the first side, has a third slope angle, and the first slope angle is greater than the third slope angle.

[0019] In an exemplary embodiment, the second pixel defining structure and the third pixel defining structure are an integrally connected structure.

[0020] In an exemplary embodiment, the third pixel defining structure includes at least two mutually isolated sub-defining structures, and the at least two sub-defining structures are arranged in sequence along the first direction.

[0021] In an exemplary embodiment, the positive projection of at least one sub-defining structure on the substrate overlaps at least partially with the positive projection of the first pixel defining structure on the substrate, and / or the positive projection of at least one sub-defining structure on the substrate overlaps at least partially with the positive projection of the second pixel defining structure on the substrate.

[0022] In an exemplary embodiment, the positive projection of at least one sub-defining structure on the substrate does not overlap with the positive projection of the first pixel defining structure on the substrate, and / or the positive projection of at least one sub-defining structure on the substrate does not overlap with the positive projection of the second pixel defining structure on the substrate.

[0023] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer, the organic light-emitting layer is disposed in an opening region defined by the first pixel defining structure and the second pixel defining structure, and the organic light-emitting layer covers the third pixel defining structure.

[0024] An exemplary embodiment of the present disclosure further provides a display device, including the above-mentioned display substrate.

[0025] To solve the above technical problems, an exemplary embodiment of the present disclosure provides a method for manufacturing a display substrate, including:

[0026] Forming a pixel defining layer on a substrate; the pixel defining layer includes a plurality of first pixel defining structures, a plurality of second pixel defining structures, and a plurality of third pixel defining structures; the first pixel defining structure has a long strip shape extending along a first direction, and the plurality of first pixel defining structures are arranged in sequence along a second direction, and the first direction intersects the second direction; the second pixel defining structure has a long strip shape extending along the second direction, and the plurality of second pixel defining structures are spaced apart and disposed between adjacent first pixel defining structures; at least one third pixel defining structure is disposed between the first pixel defining structure and the second pixel defining structure; in a direction perpendicular to the substrate, the height of the third pixel defining structure is less than the height of the second pixel defining structure.

[0027] Exemplary embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device. By providing a third pixel definition structure, the third pixel definition structure can achieve a diversion function in the edge region of the first pixel definition structure, effectively reducing the thickness of the organic light-emitting layer in the edge region of the first pixel definition structure, effectively reducing the brightness in the edge region of the first pixel definition structure, improving the display uniformity, and improving the display quality.

[0028] Of course, when implementing any product or method of the present invention, it is not necessarily required to achieve all the above advantages simultaneously. Other features and advantages of the present invention will be described in the subsequent embodiments of the specification, and some of them will become obvious from the embodiments of the specification, or can be understood by implementing the present invention. The objectives and other advantages of the exemplary embodiments of the present disclosure can be achieved and obtained through the structures specifically pointed out in the specification, claims, and drawings.

[0029] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0030] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0031] Figure 1 It is a schematic structural diagram of a display device;

[0032] Figure 2 It is a schematic plan view of a display substrate;

[0033] Figure 3 It is a schematic cross-sectional view of a display substrate;

[0034] Figure 4 It is an equivalent circuit schematic diagram of a pixel driving circuit;

[0035] Figure 5 It is a timing diagram of the operation of a pixel driving circuit;

[0036] Figure 6a 、 Figure 6b and Figure 6c They are schematic plan views of the display substrate according to the exemplary embodiments of the present disclosure;

[0037] Figure 7 is Figure 6c a cross-sectional view taken along the line A-A in

[0038] Figure 8 isFigure 6c Cross-sectional view along the BB direction;

[0039] Figure 9 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a driving circuit layer pattern;

[0040] Figure 10 A schematic diagram of an exemplary embodiment of the present disclosure after an anode pattern is formed;

[0041] Figure 11a , Figure 11b and Figure 11c A schematic diagram of the present invention after forming a third pixel definition layer pattern;

[0042] Figure 12a , Figure 12b and Figure 12c A schematic diagram of the present invention after forming a second pixel definition layer pattern;

[0043] Figure 13a , Figure 13b and Figure 13c A schematic diagram of the present invention after forming a first pixel definition layer pattern;

[0044] Figure 14 It is a schematic diagram of an exemplary embodiment of the present disclosure after ink is sprayed;

[0045] Figure 15 A schematic diagram of an initial stage of ink drying in an exemplary embodiment of the present disclosure;

[0046] Figure 16 This is a schematic diagram of an exemplary embodiment of the present disclosure after the ink is dried to form an organic light-emitting layer pattern;

[0047] Figure 17 Another structure of a pixel definition layer according to an exemplary embodiment of the present disclosure;

[0048] Figure 18 A structure of another pixel definition layer according to an exemplary embodiment of the present disclosure;

[0049] Figure 19 A structure of another pixel definition layer according to an exemplary embodiment of the present disclosure;

[0050] Figure 20 A structure of another pixel definition layer according to an exemplary embodiment of the present disclosure;

[0051] Figure 21 A structure of another pixel definition layer according to an exemplary embodiment of the present disclosure;

[0052] Figure 22 A structure of another pixel definition layer according to an exemplary embodiment of the present disclosure;

[0053] Figure 23It is a display effect diagram after the display substrate light-emitting device is lit;

[0054] Figure 24 This is the display effect diagram after the display substrate light-emitting device of the exemplary embodiment of the present disclosure is lit.

[0055] Explanation of reference numerals:

[0056] 10 - First pixel definition structure; 20 - Second pixel definition structure; 30 - Third pixel definition structure;

[0057] 31 - Sub-definition structure; 40 - Light-emitting region; 101 - Substrate;

[0058] 101A - Transistor; 102B - Storage capacitor; 102 - Driving circuit layer;

[0059] 103 - Light-emitting structure layer; 104 - Encapsulation layer; 200 - Pixel definition layer;

[0060] 301 - Anode; 302 - Pixel definition layer; 303 - Organic light-emitting layer;

[0061] 304 - Cathode; 401 - First encapsulation layer; 402 - Second encapsulation layer;

[0062] 403 - Third encapsulation layer. Detailed implementation manners

[0063] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted. The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design

[0064] The drawing ratios in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams, and one manner of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0065] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0066] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of components changes appropriately according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be replaced appropriately according to the circumstances.

[0067] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0068] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0069] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other.

[0070] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0071] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes an angle state of more than 85° and less than 95°.

[0072] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0073] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, chamfers, arc edges, and deformations, etc.

[0074] "About" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement error ranges.

[0075] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that a scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that an emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, where o may be a natural number.

[0076] Figure 2 is a schematic plan view of a display substrate. As Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, and a third sub-pixel P3 that emits third-color light. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the respective sub-pixels, and the light-emitting devices are configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuits of the respective sub-pixels.

[0077] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, diamond-shaped, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular (pin) arrangement. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or square arrangement, which is not limited in the present disclosure.

[0078] Figure 3 It is a schematic cross-sectional structure diagram of a display substrate, showing the structures of three sub-pixels of an OLED display substrate. As Figure 3 shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 provided on a substrate 101, a light-emitting structure layer 103 provided on a side of the driving circuit layer 102 away from the substrate 101, and a packaging layer 104 provided on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display substrate may include other film layers, such as spacer columns, etc., which is not limited in the present disclosure.

[0079] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors that constitute the pixel driving circuit. Figure 3Only one transistor 101A and one storage capacitor 101B are taken as examples. The light-emitting structure layer 103 may include an anode 301, a pixel defining layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 101A through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0080] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 4 It is an equivalent circuit diagram of a pixel driving circuit. As Figure 4 shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0081] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5. The second node N2 is respectively connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C. The third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6.

[0082] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0083] The control electrode of the first transistor T1 is connected to the second scan signal line S2. The first electrode of the first transistor T1 is connected to the initial signal line INIT. The second electrode of the first transistor is connected to the second node N2. When a conduction-level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount on the control electrode of the third transistor T3.

[0084] The control electrode of the second transistor T2 is connected to the first scan signal line S1. The first electrode of the second transistor T2 is connected to the second node N2. The second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0085] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1. The second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0086] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1. The first electrode of the fourth transistor T4 is connected to the data signal line D. The second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D into the pixel driving circuit.

[0087] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E. The first electrode of the fifth transistor T5 is connected to the first power supply line VDD. The second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E. The first electrode of the sixth transistor T6 is connected to the third node N3. The second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0088] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1. The first electrode of the seventh transistor T7 is connected to the initial signal line INIT. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transfers an initialization voltage to the first electrode of the light-emitting device to initialize the electric charge accumulated in the first electrode of the light-emitting device or to release the electric charge accumulated in the first electrode of the light-emitting device.

[0089] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0090] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0091] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light-emitting signal line E, and the initial signal line INIT extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0092] In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0093] Figure 5 It is a timing diagram of the operation of a pixel driving circuit. The following Figure 4 illustrates the exemplary embodiments of the present disclosure through the operation process of the exemplary pixel driving circuit. Figure 4The pixel driving circuit therein includes seven transistors (a first transistor T1 to a sixth transistor T7), one storage capacitor C, and seven signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS). All the seven transistors are P-type transistors.

[0094] In an exemplary embodiment, the working process of the pixel driving circuit may include:

[0095] A first stage A1, called a reset stage, in which the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high-level signals. The low-level signal of the second scan signal line S2 turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The high-level signals of the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. In this stage, the OLED does not emit light.

[0096] A second stage A2, called a data writing stage or a threshold compensation stage, in which the signal of the first scan signal line S1 is a low-level signal, and the signals of the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal of the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first pole of the OLED to initialize (reset) the first pole of the OLED, empty the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light. The high-level signal of the second scan signal line S2 turns off the first transistor T1. The high-level signal of the light-emitting signal line E turns off the fifth transistor T5 and the sixth transistor T6.

[0097] The third stage A3, called the light-emitting stage, has a low-level signal on the light-emitting signal line E and high-level signals on the first scanning signal line S1 and the second scanning signal line S2. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0098] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0099] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * [(Vdd - Vd] 2

[0100] Where I is the driving current flowing through the third transistor T3, which is also the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output from the data signal line D, and Vdd is the power supply voltage output from the first power supply line VDD.

[0101] Currently, the film-forming methods of the organic light-emitting layer in the light-emitting structure layer mainly include evaporation process or solution process. The evaporation process is relatively mature and has been applied to the mass production of small-size OLEDs. However, due to the high production cost and large process difficulty of the evaporation process, solution processes are usually used for large-size OLEDs. Solution processes mainly include inkjet printing, nozzle coating, spin coating, screen printing, etc. Among them, the inkjet printing process is considered an important way to achieve mass production of large-size OLEDs due to its high production efficiency, low material cost, and ability to achieve large sizes. The inkjet printing process sprays the ink of the organic light-emitting material into the pixel openings defined by the pixel definition layer, and then dries and cures to form the organic light-emitting layer. During this process, due to the influence of the coffee ring effect, the printed ink often has a problem of climbing in the pixel openings, ultimately affecting the uniformity of the organic light-emitting layer film formation, reducing the display uniformity, and degrading the display quality of the OLED product.

[0102] The exemplary embodiments of the present disclosure provide a display substrate, including a substrate and a pixel defining layer disposed on the substrate; the pixel defining layer includes a plurality of first pixel defining structures, a plurality of second pixel defining structures, and a plurality of third pixel defining structures; the first pixel defining structure has an elongated shape extending along a first direction, and a plurality of first pixel defining structures are arranged in sequence along a second direction, and the first direction intersects with the second direction; the second pixel defining structure has an elongated shape extending along the second direction, and a plurality of second pixel defining structures are spaced between adjacent first pixel defining structures; at least one third pixel defining structure is disposed between the first pixel defining structure and the second pixel defining structure; in a direction perpendicular to the substrate, the height of the third pixel defining structure may be less than the height of the second pixel defining structure.

[0103] In an exemplary embodiment, at least one third pixel defining structure and the first pixel defining structure and the second pixel defining structure form an ink channel for the ink to flow in the first direction.

[0104] In an exemplary embodiment, the first pixel defining structure may be configured to store the ink for forming the organic light-emitting layer, the second pixel defining structure may be configured to define the opening region of the sub-pixel, and the third pixel defining structure may be configured to divert the flow at the edge region of the first pixel defining structure to reduce the thickness of the organic light-emitting layer in the edge region of the first pixel defining structure and reduce the brightness in the edge region of the first pixel defining structure.

[0105] In an exemplary embodiment, in a direction perpendicular to the substrate, the height of the second pixel defining structure may be less than the height of the first pixel defining structure.

[0106] In an exemplary embodiment, there is a first distance between the side surface of the first pixel defining structure close to the second pixel defining structure and the end surface of the second pixel defining structure close to the first pixel defining structure, and the first distance may be greater than or equal to 2 μm.

[0107] In an exemplary embodiment, there may be a first overlapping region between the orthographic projection of the first pixel defining structure on the substrate and the orthographic projection of the third pixel defining structure on the substrate, and in the second direction, the first overlapping width of the first overlapping region may be about 1 μm to 3 μm.

[0108] In an exemplary embodiment, there may be a second overlapping region between the orthographic projection of the second pixel defining structure on the substrate and the orthographic projection of the third pixel defining structure on the substrate, and in the second direction, the second overlapping width of the second overlapping region may be about 1 μm to 3 μm.

[0109] In an exemplary embodiment, the first pixel definition structure and the third pixel definition structure may be an integrated structure connected to each other and formed simultaneously by a same patterning process.

[0110] In an exemplary embodiment, the second pixel definition structure and the third pixel definition structure may be an integrated structure connected to each other and formed simultaneously by a same patterning process.

[0111] In an exemplary embodiment, the second pixel definition structure and the third pixel definition structure may be simultaneously formed using a same patterning process.

[0112] In an exemplary embodiment, the third pixel definition structure may include at least two sub-definition structures isolated from each other, and the at least two sub-definition structures are sequentially arranged along the first direction.

[0113] In an exemplary embodiment, the orthographic projection of at least one sub-definition structure on the substrate may at least partially overlap with the orthographic projection of the first pixel definition structure on the substrate, and / or the orthographic projection of at least one sub-definition structure on the substrate may at least partially overlap with the orthographic projection of the second pixel definition structure on the substrate.

[0114] In an exemplary embodiment, the orthographic projection of at least one sub-definition structure on the substrate may not overlap with the orthographic projection of the first pixel definition structure on the substrate, and / or the orthographic projection of at least one sub-definition structure on the substrate may not overlap with the orthographic projection of the second pixel definition structure on the substrate.

[0115] In an exemplary embodiment, the display substrate may include an organic light emitting layer disposed in an opening region defined by the first pixel definition structure and the second pixel definition structure, and the organic light emitting layer covers the third pixel definition structure.

[0116] Figure 6a , Figure 6b and Figure 6c FIG. 1 is a schematic diagram showing a planar structure of a substrate according to an exemplary embodiment of the present disclosure. Figure 6a To display the structure of the pixel definition layer on the substrate, Figure 6b for Figure 6a The structure of the pixel definition layer in the middle sub-pixel, Figure 6c for Figure 6b The structure of the pixel definition layer in a sub-pixel. Figure 6a , Figure 6b and Figure 6cAs shown, the display substrate may include a substrate 101 and a pixel defining layer 200 disposed on the substrate 101. A first edge structure 200-1 is provided at an edge of the pixel defining layer 200 in a first direction D1, and a second edge structure 200-2 is provided at an edge of the pixel defining layer 200 in a second direction D2. The first edge structure 200-1 may extend along the second direction D2, and the second edge structure 200-2 may extend along the first direction D1. The first edge structure 200-1 and the second edge structure 200-2 are connected in sequence to form an annular structure surrounding the pixel defining layer 200. Among them, the first direction D1 intersects the second direction D2.

[0117] In an exemplary embodiment, the pixel defining layer 200 may include a plurality of first pixel defining structures 10, a plurality of second pixel defining structures 20, and a plurality of third pixel defining structures 30. The first pixel defining structure 10 has a long strip shape extending along the first direction D1, and the plurality of first pixel defining structures 10 are arranged in sequence along the second direction D2. The second pixel defining structure 20 has a long strip shape extending along the second direction D2, and the plurality of second pixel defining structures 20 are arranged in sequence along the first direction D1 between adjacent first pixel defining structures 10. At least one third pixel defining structure 30 may be disposed on one side of the first pixel defining structure 10 in the second direction D2 and on the opposite side of the first pixel defining structure 10 in the second direction D2. Alternatively, at least one third pixel defining structure 30 may be disposed on one side of the second pixel defining structure 20 in the second direction D2 and on the opposite side of the second pixel defining structure 20 in the second direction D2.

[0118] In an exemplary embodiment, the height of the third pixel defining structure 30 may be less than the height of the second pixel defining structure 20, and the height of the second pixel defining structure 20 may be less than the height of the first pixel defining structure 10. The height is the dimension in a direction perpendicular to the substrate (third direction D3), such that the first pixel defining structure 10, the second pixel defining structure 20, and the third pixel defining structure 30 together form an ink channel through which ink can flow in the first direction D1.

[0119] Figure 7 and Figure 8 is a structure of a pixel defining layer according to an exemplary embodiment of the present disclosure. Figure 7 is Figure 6c a cross-sectional view taken along line A-A in Figure 8 is Figure 6c a cross-sectional view taken along line B-B in. As shown in Figure 6c 、 Figure 7 and Figure 8As shown, the pixel definition layer in a sub-pixel may include a first pixel definition structure 10, a second pixel definition structure 20, and a third pixel definition structure 30. The first pixel definition structure 10 and the third pixel definition structure 30 extend along a first direction D1. The third pixel definition structure 30 is respectively disposed on one side of the first pixel definition structure 10 in a second direction D2 and on the other side of the first pixel definition structure 10 in the opposite direction of the second direction D2. The second pixel definition structure 20 extends along the second direction D2 and is disposed between two adjacent first pixel definition structures 10 in the second direction D2.

[0120] In an exemplary embodiment, the mutually intersecting first pixel definition structure 10 and second pixel definition structure 20 form an opening area of the sub-pixel, and the mutually intersecting second pixel definition structure 20 and third pixel definition structure 30 form a light-emitting area 40 of the sub-pixel. Among them, the opening area of the sub-pixel refers to the area where the organic light-emitting layer is located in the sub-pixel, and the light-emitting area of the sub-pixel refers to the area where the organic light-emitting layer can emit light in the opening area of the sub-pixel, that is, the area where the organic light-emitting layer contacts the anode. The area of the light-emitting area is smaller than the area of the opening area, and the orthographic projection of the light-emitting area on the substrate is located within the range of the orthographic projection of the opening area on the substrate.

[0121] In an exemplary embodiment, in the second direction D2, there is a first distance L1 between the edge of the first pixel definition structure 10 close to the second pixel definition structure 20 and the end face of the second pixel definition structure 20 close to the first pixel definition structure 10. The first distance L1 can be used as the width of the ink channel for the ink to flow in the first direction D1. In an exemplary embodiment, the third pixel definition structure 30 extending along the first direction D1 is disposed at the bottom of the ink channel. In this way, the edge of the first pixel definition structure 10, the end of the second pixel definition structure 20, and the surface of the third pixel definition structure 30 far from the substrate together form an ink channel for the ink to flow in the first direction D1.

[0122] In an exemplary embodiment, the first distance L1 may be greater than or equal to 2 μm. For example, the first distance L1 may be about 2 μm to 4 μm, so that the ink has good fluidity in the ink channel.

[0123] In an exemplary embodiment, the third pixel definition structure 30 and the first pixel definition structure 10 may at least partially overlap. The first pixel definition structure 10 is arranged on the edge of the third pixel definition structure 30 close to the first pixel definition structure 10, and there is a first overlapping area between the orthographic projection of the third pixel definition structure 30 on the substrate and the orthographic projection of the first pixel definition structure 10 on the substrate.

[0124] In an exemplary embodiment, the third pixel defining structure 30 and the second pixel defining structure 20 may at least partially overlap. The second pixel defining structure 20 is disposed on an edge of the third pixel defining structure 30 away from the first pixel defining structure 10, and there is a second overlapping region between the orthographic projection of the third pixel defining structure 30 on the substrate and the orthographic projection of the second pixel defining structure 20 on the substrate.

[0125] In an exemplary embodiment, the first overlapping width K1 of the first overlapping region may be about 1 μm to 3 μm, and the second overlapping width K2 of the second overlapping region may be about 1 μm to 3 μm. The first overlapping width and the second overlapping width are dimensions in the second direction D2.

[0126] In an exemplary embodiment, in a plane perpendicular to the extending direction of the first pixel defining structure 10, that is, in a plane perpendicular to the first direction D1, the cross-sectional shape of the first pixel defining structure 10 may be a first trapezoid. The first trapezoid has a first lower base close to the substrate, a first upper base away from the substrate, and two first side edges respectively connecting the first lower base and the first upper base.

[0127] In an exemplary embodiment, the first width B1 of the first upper base may be greater than or equal to 15 μm, and the first slope angle β1 of the first side edge may be about 30° to 70°. The first width is a dimension in the second direction D2.

[0128] In an exemplary embodiment, the first height H1 of the first pixel defining structure 10 may be about 1.0 μm to 2.0 μm. The first height is a dimension in the third direction D3 (the direction perpendicular to the substrate).

[0129] In an exemplary embodiment, in a plane perpendicular to the extending direction of the second pixel defining structure 20, that is, in a plane perpendicular to the second direction D2, the cross-sectional shape of the second pixel defining structure 20 may be a second trapezoid. The second trapezoid has a second lower base close to the substrate, a second upper base away from the substrate, and two second side edges respectively connecting the second lower base and the second upper base.

[0130] In an exemplary embodiment, the second width K2 of the second upper base may be greater than or equal to 3 μm, and the second slope angle β2 of the second side edge may be about 30° to 90°. The second width is a dimension in the first direction D1.

[0131] In an exemplary embodiment, the second height H2 of the second pixel defining structure 20 may be about 0.3 μm to 0.8 μm. The second height is a dimension in the third direction D3 (the direction perpendicular to the substrate).

[0132] In an exemplary embodiment, in a plane perpendicular to the extending direction of the third pixel defining structure 30, that is, in a plane perpendicular to the first direction D1, the cross-sectional shape of the third pixel defining structure 30 may be a rectangle or a trapezoid.

[0133] In an exemplary embodiment, the third height H3 of the third pixel defining structure 30 may be approximately 0.1 μm to 0.3 μm, and the third height is a dimension in the third direction D3 (the direction perpendicular to the substrate).

[0134] In an exemplary embodiment, in the second direction D2, the distance between adjacent first pixel defining structures 10 may be determined according to factors such as pixel size and the minimum diameter of ink droplets, and the distance between adjacent first pixel defining structures 10 is greater than the minimum diameter of ink droplets. For example, the distance between adjacent first pixel defining structures 10 may be greater than or equal to 12 μm. In the first direction D1, the distance between adjacent second pixel defining structures 20 may be determined according to factors such as pixel size, and the present disclosure does not make a limitation herein.

[0135] An exemplary illustration is given below through the preparation process of the display substrate. The "patterning process" as mentioned in the present disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping, and for organic materials, includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not make a limitation. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as mentioned in the present disclosure means that A and B are simultaneously formed by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0136] In an exemplary embodiment, the preparation process of the display substrate in this exemplary embodiment may include the following operations.

[0137] (11) Form a base pattern. In an exemplary embodiment, the base may be a rigid base or a flexible base. The rigid base may be glass or quartz, and the flexible base may be a single-layer structure or a laminated structure.

[0138] In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic layer, a second flexible material layer, and a second inorganic layer stacked on a glass carrier. In an exemplary embodiment, the materials of the first flexible layer and the second flexible layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic layer and the second inorganic layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc. The first inorganic layer and the second inorganic layer may be referred to as a barrier layer or a buffer layer.

[0139] (12) Form a driving circuit layer pattern on the base. In an exemplary embodiment, the driving circuit layer may include transistors and storage capacitors constituting a pixel driving circuit. In an exemplary embodiment, forming the driving circuit layer pattern may include:

[0140] Deposit a semiconductor thin film on the base, pattern the semiconductor thin film through a patterning process, and form a semiconductor layer pattern on the base. The semiconductor layer pattern includes at least an active layer.

[0141] Subsequently, deposit a first insulating thin film and a first metal thin film in sequence, pattern the first metal thin film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first metal layer pattern disposed on the first insulating layer. The first metal layer pattern includes at least a gate electrode and a first capacitor electrode.

[0142] Subsequently, deposit a second insulating thin film and a second metal thin film in sequence, pattern the second metal thin film through a patterning process to form a second insulating layer covering the first metal layer pattern, and a second metal layer pattern disposed on the second insulating layer. The second metal layer pattern includes at least a second capacitor electrode, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.

[0143] Subsequently, deposit a third insulating thin film, pattern the third insulating thin film through a patterning process to form a third insulating layer covering the second metal layer pattern. At least one active via is formed on the third insulating layer, and the third insulating layer, the second insulating layer, and the first insulating layer within the active via are etched away to expose the surface of the active layer.

[0144] Subsequently, a third metal thin film is deposited, and the third metal thin film is patterned through a patterning process to form a third metal layer pattern on the third insulating layer. The third metal layer pattern includes at least a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer through active vias.

[0145] Subsequently, a planar thin film is deposited, and the planar thin film is patterned through a patterning process to form a planar layer covering the third metal layer pattern. At least one anode via pattern is formed on the planar layer, and the anode via exposes the surface of the drain electrode.

[0146] Thus far, the pattern of the driving circuit layer 102 disposed on the substrate 101 is fabricated, as Figure 9 shown, Figure 9 which schematically shows the structure of a sub-pixel of the display substrate. The pixel driving circuit in the sub-pixel takes a transistor 101A and a storage capacitor 101B as an example. In an exemplary embodiment, the active layer, the gate electrode, the source electrode, and the drain electrode form the transistor 101A, and the first capacitor electrode and the second capacitor electrode form the storage capacitor 101B. In an exemplary embodiment, the transistor may be a driving transistor in the pixel driving circuit.

[0147] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer and the second insulating layer are referred to as the (GI) layer, and the third insulating layer is referred to as the interlayer dielectric (ILD) layer. The planar thin film may be made of an organic material, such as a polysiloxane-based material, an acrylic-based material, a polyimide-based material, or a resin. The first metal thin film, the second metal thin film, and the third metal thin film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc. The active layer thin film may be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0148] In an exemplary embodiment, the driving circuit layer 102 may include a fourth insulating layer, and the fourth insulating layer may cover the third metal layer pattern. The planar layer is disposed on the fourth insulating layer, and the fourth insulating layer is referred to as the passivation (PVX) layer.

[0149] (13) Form an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the conductive thin film through a patterning process to form the anode 301 pattern, and the anode 301 is connected to the drain electrode of the transistor through an anode via, as Figure 10 shown.

[0150] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the anode 301 may be any one or more of the following: square, rectangle, pentagon, hexagon, circle, and ellipse.

[0151] In an exemplary embodiment, the conductive thin film may be made of a metal material or a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the conductive thin film may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0152] (14) Form a third pixel definition layer pattern. In an exemplary embodiment, forming the third pixel definition layer pattern may include: depositing or coating a third pixel definition thin film on the substrate on which the aforementioned pattern is formed, patterning the third pixel definition thin film through a patterning process to form the third pixel definition layer pattern, as Figure 11a , Figure 11b and Figure 11c shown, Figure 11a is a plan view of a sub-pixel in the display substrate, Figure 11b is Figure 11a a cross-sectional view taken along the A-A direction in Figure 11c is Figure 11a a cross-sectional view taken along the B-B direction in

[0153] In an exemplary embodiment, the third pixel definition layer pattern may at least include two third pixel definition structures 30. The two third pixel definition structures 30 are in the shape of long strips extending along the first direction D1, and the two third pixel definition structures 30 are respectively disposed on both sides of the anode 301 in the second direction D2. The orthographic projection of the third pixel definition structure 30 on the substrate overlaps at least partially with the orthographic projection of the anode 301 on the substrate.

[0154] In an exemplary embodiment, in a plane perpendicular to the first direction D1 (i.e., the D2-D3 plane), the cross-sectional shape of the third pixel definition structure 30 may be a rectangle or a trapezoid. In an exemplary embodiment, the cross-sectional shape of the third pixel definition structure 30 may be other regular shapes, which are not limited herein in the present disclosure.

[0155] In an exemplary embodiment, the third height H3 of the third pixel defining structure 30 may be approximately 0.1 μm to 0.3 μm.

[0156] In an exemplary embodiment, the third pixel definition film may be coated by a nano-imprinting process, and then a third pixel definition layer pattern may be formed by a patterning process.

[0157] In an exemplary embodiment, the orthographic projection of the anode via in the driving circuit layer 102 on the substrate can be located within the range of the orthographic projection of the third pixel definition structure 30 on the substrate, so that the area where the anode via is located is covered by the third pixel definition structure 30, which can ensure the flatness of the anode.

[0158] (15) Forming a second pixel definition layer pattern. In an exemplary embodiment, forming the second pixel definition layer pattern may include: coating a second pixel definition film on the substrate formed with the aforementioned pattern, patterning the second pixel definition film through a patterning process, and forming the second pixel definition layer pattern, such as Figure 12a , Figure 12b and Figure 12c As shown, Figure 12b for Figure 12a Sectional view along AA direction, Figure 12c for Figure 12a Cross-sectional view along the BB axis.

[0159] In an exemplary embodiment, the second pixel definition layer pattern may include at least two second pixel definition structures 20, the two second pixel definition structures 20 are in the shape of long strips extending along the second direction D2, the two second pixel definition structures 20 are respectively arranged on both sides of the anode 301 in the first direction D1, and the orthographic projection of the second pixel definition structure 20 on the substrate at least partially overlaps with the orthographic projection of the anode 301 on the substrate.

[0160] In an exemplary embodiment, in the second direction D2, two ends of the second pixel definition structure 20 are respectively placed on two third pixel definition structures 30, and the orthographic projection of the second pixel definition structure 20 on the substrate and the orthographic projection of the third pixel definition structure 30 on the substrate have a second overlapping area.

[0161] In an exemplary embodiment, in the second direction D2, the second overlap width K2 of the second overlap region may be approximately 1 μm to 3 μm.

[0162] In an exemplary embodiment, in a plane perpendicular to the second direction D2 (i.e., the D1-D3 plane), the cross-sectional shape of the second pixel definition structure 20 may be a second trapezoidal trapezoid. The second trapezoid has a second lower base close to one side of the substrate, a second upper base away from one side of the substrate, and two second side edges respectively connecting the second lower base and the second upper base, the second slope angle β2 of the second side edge may be approximately 30° to 90°, and the second width B2 of the second upper base may be greater than or equal to 3 μm, so as to be able to effectively wrap the anode.

[0163] In an exemplary embodiment, the second height H2 of the second pixel defining structure 20 may be greater than the third height H3 of the third pixel defining structure 30 .

[0164] In an exemplary embodiment, the second height H2 of the second pixel defining structure 20 may be approximately 0.3 μm to 0.8 μm.

[0165] In an exemplary embodiment, the distance between adjacent second pixel definition structures 20 may be determined according to factors such as pixel size, which is not limited in the present disclosure.

[0166] In an exemplary embodiment, the orthographic projection of the anode via in the driving circuit layer 102 on the substrate can be located within the range of the orthographic projection of the second pixel definition structure 20 on the substrate, so that the area where the anode via is located is covered by the second pixel definition structure 20, which can ensure the flatness of the anode.

[0167] (16) Forming a first pixel definition layer pattern. In an exemplary embodiment, forming the first pixel definition layer pattern may include: coating a first pixel definition film on the substrate formed with the aforementioned pattern, patterning the first pixel definition film through a patterning process, and forming the first pixel definition layer pattern, such as Figure 13a , Figure 13b and Figure 13c As shown, Figure 13b for Figure 13a Sectional view along AA direction, Figure 13c for Figure 13a Cross-sectional view along the BB axis.

[0168] In an exemplary embodiment, the first pixel definition layer pattern may include at least two first pixel definition structures 10, the two first pixel definition structures 10 are in the shape of long strips extending along the first direction D1, and the two first pixel definition structures 10 are respectively arranged on both sides of the anode 301 in the second direction D2, and the orthographic projection of the first pixel definition structure 10 on the substrate at least partially overlaps with the orthographic projection of the anode 301 on the substrate.

[0169] In an exemplary embodiment, in the second direction D2, one side of the first pixel defining structure 10 close to the anode 301 is laid on the third pixel defining structure 30, and there is a first overlapping region between the orthographic projection of the first pixel defining structure 10 on the substrate and the orthographic projection of the third pixel defining structure 30 on the substrate.

[0170] In an exemplary embodiment, in the second direction D2, the first overlapping width K1 of the first overlapping region can be approximately 1 μm to 3 μm.

[0171] In an exemplary embodiment, in the second direction D2, there is a first distance L1 between the first edge of the first pixel defining structure 10 close to one side of the first pixel defining structure 10 and the first end face of the second pixel defining structure 20 close to the first pixel defining structure 10, forming an ink channel through which ink can flow in the first direction D1. In an exemplary embodiment, the first distance L1 can be greater than or equal to 2 μm. For example, the first distance L1 can be approximately 2 μm to 4 μm, so that the ink has good fluidity in the ink channel.

[0172] In an exemplary embodiment, in a plane perpendicular to the first direction D1 (i.e., the D2-D3 plane), the cross-sectional shape of the first pixel defining structure 10 can be a first trapezoid in the shape of a trapezoid. The first trapezoid has a first lower base close to the substrate, a first upper base far from the substrate, and two first side edges respectively connecting the first lower base and the first upper base. The first width B1 of the first upper base can be greater than or equal to 15 μm, and the first slope angle β1 of the first side edge can be approximately 30° to 70°.

[0173] In an exemplary embodiment, the first height H1 of the first pixel defining structure 10 can be greater than the second height H2 of the second pixel defining structure 20.

[0174] In an exemplary embodiment, the first height H1 of the first pixel defining structure 10 can be approximately 1.0 μm to 2.0 μm.

[0175] In an exemplary embodiment, in the second direction D2, the distance between adjacent first pixel defining structures 10 can be determined according to factors such as pixel size and the minimum diameter of ink droplets, and the distance between adjacent first pixel defining structures 10 is greater than the minimum diameter of ink droplets. For example, the distance between adjacent first pixel defining structures 10 can be greater than or equal to 12 μm.

[0176] In an exemplary embodiment, the orthographic projection of the anode via hole in the driving circuit layer 102 on the substrate can be located within the range of the orthographic projection of the first pixel defining structure 10 on the substrate, so that the region where the anode via hole is located is covered by the first pixel defining structure 10, which can ensure the flatness of the anode.

[0177] Thus, the preparation of the pixel definition structure of the exemplary embodiment of the present disclosure is completed. The pixel definition structure includes three layers of pixel definition structures, namely, a first pixel definition structure 10, a second pixel definition structure 20, and a third pixel definition structure 30. An ink storage space is formed between adjacent first pixel definition structures 10. An opening area of a sub-pixel is formed by the intersecting first pixel definition structure 10 and second pixel definition structure 20. A light-emitting area of a sub-pixel exposing the anode 301 is formed by the intersecting second pixel definition structure 20 and third pixel definition structure 30. The surface of the third pixel definition structure 30 on the side away from the anode located on the anode 301, the first pixel definition structure 10 on one side of the third pixel definition structure 30, and the second pixel definition structure 20 on the other side of the third pixel definition structure 30 constitute an ink channel for ink flow, so that ink can flow between the opening areas of sub-pixels adjacent in the first direction D1.

[0178] In an exemplary embodiment, the materials of the first pixel definition structure, the second pixel definition structure, and the third pixel definition structure may be liquid-repellent organic materials. The liquid repellency of the first pixel definition structure may be stronger than that of the second pixel definition structure, and the liquid repellency of the second pixel definition structure may be stronger than that of the third pixel definition structure.

[0179] In an exemplary embodiment, the liquid-repellent organic material may be a hydrophobic and lipophilic material, such as polyimide, polysiloxane, polymethyl methacrylate, polybutyl methacrylate, polycyclohexyl methacrylate, or polystyrene, etc. Alternatively, the liquid-repellent organic material may be a hydrophobic and oleophobic material, such as polyhexafluoropropylene, fluorinated parylene, fluorinated polysiloxane ether, fluorinated polyimide, or fluorinated polyamide, etc. The present disclosure does not make a limitation herein.

[0180] In an exemplary embodiment, the material of the third pixel definition structure may be a liquid-philic inorganic material or a liquid-philic organic material. For example, the liquid-philic inorganic material may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0181] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the sub-pixel light-emitting area defined by the second pixel definition structure 20 and the third pixel definition structure 30 may be triangular, rectangular, polygonal, circular, or elliptical, etc. The present disclosure does not make a limitation herein.

[0182] In an exemplary embodiment, during the process of forming the first pixel definition structure pattern, a spacer pattern may be formed. The present disclosure does not make a limitation herein.

[0183] (17)Form an organic light-emitting layer pattern. In an exemplary embodiment, forming the organic light-emitting layer pattern may include:

[0184] A. On the substrate on which the foregoing pattern is formed, ink 303' of an organic light-emitting material is inkjet-printed so that the ink 303' fills between adjacent first pixel defining structures 10, as Figure 14 shown.

[0185] In an exemplary embodiment, between adjacent first pixel defining structures 10, the surface of the ink 303' away from the substrate is arched, and the ink 303' completely covers the second pixel defining structure 20 and the third pixel defining structure 30, that is, the second pixel defining structure 20 and the third pixel defining structure 30 are below the upper surface of the ink 303'.

[0186] In an exemplary embodiment, the arch height GH of the arched ink is related to the amount of ink and the liquid repellency of the first pixel defining structure. The more the amount of ink, the higher the arch height GH, and the stronger the liquid repellency of the first pixel defining structure, the higher the arch height. In an exemplary embodiment, the arch height GH may be less than or equal to half of the first pitch GL, and the first pitch GL is the pitch between adjacent first pixel defining structures in the second direction D2.

[0187] In an exemplary embodiment, the liquid repellency of the surface of the first pixel defining structure 10 away from the substrate is slightly weaker, and the ink 303' can have a certain extension on the surface of the first pixel defining structure 10 away from the substrate.

[0188] B. The ink is dried through a drying process so that the ink is gradually dried. In the initial stage of ink drying, the surface of the ink away from the substrate gradually changes from an arched shape to a flat shape, forming semi-dry ink 303", and the semi-dry ink 303" still completely covers the second pixel defining structure 20 and the third pixel defining structure 30, as Figure 15 shown. In the later stage of ink drying, since the ink in the area where the second pixel defining structure 20 is located has support, while the ink in the area between the first pixel defining structure 10 and the second pixel defining structure 20 has no support, a columnar protrusion is formed on the second pixel defining structure 20 during the further drying of the ink, making the second pixel defining structure 20 easily exposed. Finally, the ink is completely dried to form the organic light-emitting layer 303, and the second pixel defining structure 20 separates the ink in the adjacent sub-pixel light-emitting areas, as Figure 16 shown.

[0189] In an exemplary embodiment, the organic light-emitting layer 303 covers the third pixel defining structure 30, that is, the third pixel defining structure 30 is below the upper surface (the surface away from the substrate) of the organic light-emitting layer 303.

[0190] In an exemplary embodiment, since the pixel defining structure forms an ink channel for ink flow, during the drying process of the ink, the force direction of the ink is towards the ink channel direction, improving the phenomenon of ink climbing. Although there is still a certain amount of climbing around the first pixel defining structure 10 during the ink drying process, such that the thickness of the organic light-emitting layer 303 in the edge region close to the first pixel defining structure 10 is greater than the thickness of the organic light-emitting layer 303 in the middle region far from the first pixel defining structure 10, since the organic light-emitting layer 303 in the edge region is formed on the third pixel defining structure 30, the organic light-emitting layer 303 in the edge region of the first pixel defining structure 10 does not contact the anode, and the organic light-emitting layer 303 in this edge region does not emit light. Therefore, the thicker organic light-emitting layer 303 in the edge region does not affect the display effect after the light-emitting device is lit, avoiding the problem of uneven display brightness caused by different film thicknesses.

[0191] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (Hole Injection Layer, abbreviated as HIL), hole transport layer (Hole Transport Layer, abbreviated as HTL), electron blocking layer (Electron Block Layer, abbreviated as EBL), emitting layer (Emitting Layer, abbreviated as EML), hole blocking layer (Hole Block Layer, abbreviated as HBL), electron transport layer (Electron Transport Layer, abbreviated as ETL), and electron injection layer (Electron Injection Layer, abbreviated as EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0192] The subsequent manufacturing process may include forming structures such as a cathode and a packaging layer, which are not limited herein in the present disclosure.

[0193] Figure 17 This is another structure of the pixel defining layer in an exemplary embodiment of the present disclosure. Figure 17 is Figure 6c a cross-sectional view taken along the A-A direction in Figure 7 and Figure 8The structures shown are similar. The pixel definition layer in a sub-pixel may include a first pixel definition structure 10, a second pixel definition structure 20, and a third pixel definition structure 30. The intersecting first pixel definition structure 10 and second pixel definition structure 20 form an opening area of the sub-pixel, and the intersecting second pixel definition structure 20 and third pixel definition structure 30 form a light-emitting area of the sub-pixel. The difference is that the second pixel definition structure 20 and the third pixel definition structure 30 in this exemplary embodiment are an integrally connected structure and are formed simultaneously through the same patterning process, as Figure 17 shown.

[0194] In the exemplary embodiment, the structures of the first pixel definition structure 10, the second pixel definition structure 20, and the third pixel definition structure 30 may be similar to those of the previous embodiment, and related parameters such as the first distance L1, the first overlap width K1, the first width B1, the first height H1, the second height H2, and the third height H3 may be similar to those of the previous embodiment. The difference is that the second pixel definition structure 20 and the third pixel definition structure 30 are connected as a whole, and there is no second overlap area in the previous embodiment.

[0195] In the exemplary embodiment, the third pixel definition structure 30 and the first pixel definition structure 10 may at least partially overlap, and there is a first overlap area between the orthographic projection of the third pixel definition structure 30 on the substrate and the orthographic projection of the first pixel definition structure 10 on the substrate. In the exemplary embodiment, the height change between the second pixel definition structure 20 and the third pixel definition structure 30 may be a stepped structure with a sudden height change. In the second direction D2, there is a height change boundary line between the second pixel definition structure 20 with the second height H2 and the third pixel definition structure 30 with the third height H3, and there is a first distance L1 between the first edge of the first pixel definition structure 10 close to the second pixel definition structure 20 and the height change boundary line.

[0196] In the exemplary embodiment, the preparation process of the display substrate in this exemplary embodiment may include the following operations.

[0197] (21) to (23) The processes of forming the substrate, the driving circuit layer, and the anode pattern are similar to the processes of the preparation process (11) to (13) of the previous embodiment, and will not be elaborated here.

[0198] (24) Form the second pixel definition structure and the third pixel definition structure patterns. In an exemplary embodiment, forming the second pixel definition structure and the third pixel definition structure patterns may include: coating a pixel definition thin film on the substrate where the foregoing patterns are formed, patterning the pixel definition thin film by a patterning process using a halftone or gray tone mask, to form the second pixel definition structure and the third pixel definition structure patterns. The second pixel definition structure 20 has an elongated shape extending along the second direction D2, and a plurality of second pixel definition structures 20 are arranged in sequence along the first direction D1. The third pixel definition structure 30 has an elongated shape extending along the first direction D1, and is respectively disposed on both sides of the second pixel definition structure 20 along the second direction D2. The intersecting second pixel definition structure 20 and third pixel definition structure 30 form the light-emitting region of the sub-pixel.

[0199] In an exemplary embodiment, this process may include a surface treatment process. By treating the surface of the second pixel definition structure and / or the surface of the third pixel definition structure, the liquid repellency of the second pixel definition structure is made stronger than that of the third pixel definition structure, or the surface of the second pixel definition structure has liquid repellency while the surface of the third pixel definition structure has hydrophilicity.

[0200] (25) to (26) Form the first pixel definition structure and the organic light-emitting layer patterns, which may be similar to the processes of the foregoing embodiment preparation procedures (16) to (17), and will not be elaborated here.

[0201] The pixel definition structure of this exemplary embodiment improves the ink climbing phenomenon by forming ink channels for ink flow, and avoids the problem of uneven display brightness caused by different film thicknesses. By using the same patterning process to simultaneously form the second pixel definition structure and the third pixel definition structure in this exemplary embodiment, the process is simplified, the process time is shortened, and the production cost can be effectively reduced.

[0202] Figure 18 This is the structure of another pixel definition layer of an exemplary embodiment of the present disclosure. Figure 18 is Figure 6c a cross-sectional view taken along the A-A direction in. In an exemplary embodiment, the main structure of the pixel definition layer of this exemplary embodiment is the same as that of Figure 7 and Figure 8The structures shown are similar. The pixel definition layer in a sub-pixel may include a first pixel definition structure 10, a second pixel definition structure 20, and a third pixel definition structure 30. The intersecting first pixel definition structure 10 and second pixel definition structure 20 form an opening area of the sub-pixel, and the intersecting second pixel definition structure 20 and third pixel definition structure 30 form a light-emitting area of the sub-pixel. The difference is that the first pixel definition structure 10 and the third pixel definition structure 30 in this exemplary embodiment are an integrally connected structure and are formed simultaneously through the same patterning process, as Figure 18 shown.

[0203] In an exemplary embodiment, the structures of the first pixel definition structure 10, the second pixel definition structure 20, and the third pixel definition structure 30 may be similar to those of the foregoing embodiment, and related parameters such as the first distance L1, the second overlap width K2, the first width B1, the first height H1, the second height H2, and the third height H3 may be similar to those of the foregoing embodiment. The difference is that the first pixel definition structure 10 and the third pixel definition structure 30 are connected into one body, and there is no first overlap area in the foregoing embodiment.

[0204] In an exemplary embodiment, the third pixel definition structure 30 and the second pixel definition structure 20 may at least partially overlap, and there is a second overlap area between the orthographic projection of the third pixel definition structure 30 on the substrate and the orthographic projection of the second pixel definition structure 20 on the substrate. In an exemplary embodiment, the height change between the first pixel definition structure 10 and the third pixel definition structure 30 may be a stepped structure with a sudden height change. In the second direction D2, there is a height change boundary line between the first pixel definition structure 10 with the first height H1 and the third pixel definition structure 30 with the third height H3, and there is a first distance L1 between the height change boundary line and the first end face of the second pixel definition structure 20 close to the first pixel definition structure 10.

[0205] In an exemplary embodiment, the preparation process of the display substrate in this exemplary embodiment may include the following operations.

[0206] (31) to (33) The processes of forming the substrate, the driving circuit layer, and the anode pattern are similar to those of the foregoing embodiment (11) to (13), and will not be described in detail here.

[0207] (34) Form the patterns of the first pixel definition structure and the third pixel definition structure. In an exemplary embodiment, forming the patterns of the first pixel definition structure and the third pixel definition structure may include: coating a pixel definition thin film on the substrate on which the foregoing patterns are formed, and patterning the pixel definition thin film using a halftone or graytone mask plate patterning process to form the patterns of the first pixel definition structure and the third pixel definition structure pattern,

[0208] Both the first pixel defining structure 10 and the third pixel defining structure 30 have an elongated shape extending along the first direction D1, and the third pixel defining structure 30 is disposed on one or both sides of the first pixel defining structure 10 in the second direction D2.

[0209] In an exemplary embodiment, the present process may include a surface treatment process. By treating the surface of the first pixel defining structure and / or the surface of the third pixel defining structure, the hydrophobicity of the first pixel defining structure is made stronger than that of the third pixel defining structure, or the surface of the first pixel defining structure has hydrophobicity while the surface of the third pixel defining structure has hydrophilicity.

[0210] (35) to (36) Form the second pixel defining structure and the organic light emitting layer pattern. Forming the second pixel defining structure may be similar to the process of the foregoing embodiment preparation process (15), and forming the organic light emitting layer pattern may be similar to the process of the foregoing embodiment preparation process (17), which will not be elaborated here.

[0211] The pixel defining structure of the present exemplary embodiment improves the ink climbing phenomenon by forming an ink channel for ink flow, and avoids the problem of uneven display brightness caused by different film thicknesses. The present exemplary embodiment simplifies the process and shortens the process time by forming the first pixel defining structure and the third pixel defining structure simultaneously using the same patterning process, and can effectively reduce the production cost.

[0212] Figure 19 This is another structure of the pixel defining layer according to an exemplary embodiment of the present disclosure. Figure 19 For Figure 6c is a cross-sectional view taken along the A-A direction in Figure 18 shown in the structure. In an exemplary embodiment, the main structure of the pixel defining layer of the present exemplary embodiment is similar to the Figure 19 shown.

[0213] In an exemplary embodiment, the first side of the first pixel defining structure 10 away from the second pixel defining structure 20 has a first slope angle β1, and the third side of the third pixel defining structure 30 away from the first side has a third slope angle β3, and the first slope angle β1 may be greater than the third slope angle β3.

[0214] Figure 20 This is another structure of the pixel defining layer according to an exemplary embodiment of the present disclosure. Figure 20 For Figure 6c is a cross-sectional view taken along the A-A direction in Figure 18The structures shown are similar. The difference is that the height change between the first pixel definition structure 10 and the third pixel definition structure 30 in this exemplary embodiment is a gently varying ramp structure, and the side of the first pixel definition structure 10 facing the second pixel definition structure 20 is an arc, as Figure 20 shown.

[0215] In an exemplary embodiment, the side of the first pixel definition structure 10 facing the second pixel definition structure 20 can be a plurality of connected broken lines arranged in sequence.

[0216] Figure 21 This is another structure of the pixel definition layer in an exemplary embodiment of the present disclosure. In an exemplary embodiment, the main structure of the pixel definition layer in this exemplary embodiment is similar to the structure shown in Figure 7 and Figure 8 shown. The pixel definition layer in a sub-pixel can include a first pixel definition structure 10, a second pixel definition structure 20, and a third pixel definition structure 30. The difference is that the third pixel definition structure 30 in this exemplary embodiment includes at least two mutually isolated sub-definition structures 31 arranged in sequence along the first direction X, as Figure 21 shown.

[0217] In an exemplary embodiment, the structures and related parameters of the first pixel definition structure 10 and the second pixel definition structure 20 can be similar to those of the foregoing embodiments. The positive projection of each sub-definition structure 31 on the substrate and the positive projection of the first pixel definition structure 10 on the substrate have a first overlapping area, and the positive projection of each sub-definition structure 31 on the substrate and the positive projection of the second pixel definition structure 20 on the substrate have a second overlapping area.

[0218] The pixel definition structure of this exemplary embodiment improves the phenomenon of ink climbing by forming an ink channel for ink flow, and avoids the problem of uneven display brightness caused by different film thicknesses. By setting the third pixel definition structure as mutually isolated sub-definition structures in this exemplary embodiment, the area of the light-emitting region of the sub-pixel can be increased, and the aperture ratio can be improved.

[0219] Figure 22 This is another structure of the pixel definition layer in an exemplary embodiment of the present disclosure. In an exemplary embodiment, the main structure of the pixel definition layer in this exemplary embodiment is similar to the structure shown in Figure 21 shown. The pixel definition layer in a sub-pixel can include a first pixel definition structure 10, a second pixel definition structure 20, and a third pixel definition structure 30. The difference is that the third pixel definition structure 30 in this exemplary embodiment includes three mutually isolated sub-definition structures 31 arranged in sequence along the first direction X, as Figure 22 shown.

[0220] In an exemplary embodiment, the structures and related parameters of the first pixel defining structure 10 and the second pixel defining structure 20 may be similar to those of the foregoing embodiments. The positive projections of the first sub-defining structure 31-1 on the substrate respectively have a first overlapping region and a second overlapping region with the positive projections of the first pixel defining structure 10 and the second pixel defining structure 20 on the substrate. The positive projections of the second sub-defining structure 31-2 on the substrate respectively have a first overlapping region and a second overlapping region with the positive projections of the first pixel defining structure 10 and the second pixel defining structure 20 on the substrate. The first sub-defining structure 31-1 is located on one side of the second sub-defining structure 31-2 in the first direction D1.

[0221] In an exemplary embodiment, the third sub-defining structure 31-3 is located between the first sub-defining structure 31-1 and the second sub-defining structure 31-2, and the positive projection of the third sub-defining structure 31-3 on the substrate does not overlap with the positive projection of the second pixel defining structure 20 on the substrate.

[0222] In an exemplary embodiment, the positive projection of the third sub-defining structure 31-3 on the substrate may have an overlapping region with the positive projection of the first pixel defining structure 10 on the substrate, or the positive projection of the third sub-defining structure 31-3 on the substrate may not overlap with the positive projection of the first pixel defining structure 10 on the substrate.

[0223] Figure 23 It is a display effect diagram after the display substrate light-emitting device is lit. Figure 24 This is the display effect diagram after the display substrate light-emitting device of the exemplary embodiment of the present disclosure is lit. In a display substrate, the pixel defining structure is composed of a first pixel defining structure and a second pixel defining structure, and the second pixel defining structure separates the organic light-emitting layers of adjacent sub-pixel opening regions. Since there is a climbing phenomenon at the edges of the first pixel defining structure and the second pixel defining structure during the ink drying process, the thickness of the organic light-emitting layer formed after drying is different. The thickness of the organic light-emitting layer in the edge regions near the first pixel defining structure and the second pixel defining structure is significantly greater than that in other positions. The difference in the film thickness of the organic light-emitting layer at different positions will ultimately be reflected in the display effect after the light-emitting device is lit, making the brightness in the edge region of the pixel defining structure greater than that in other positions, especially the brightness in the edge region of the first pixel defining structure is greater than that in other positions, as shown in Figure 17 the ink abnormal aggregation region in.

[0224] In the exemplary embodiments of the present disclosure, by providing a third pixel defining structure, and using the third pixel defining structure, the first pixel defining structure, and the second pixel defining structure to form a channel for ink flow, the third pixel defining structure can not only achieve a diversion function in the edge region of the first pixel defining structure, effectively reducing the thickness of the organic light-emitting layer in the edge region of the first pixel defining structure, but also achieve isolation between the organic light-emitting layer and the anode in the edge region of the first pixel defining structure, effectively eliminating the influence of the organic light-emitting layer in the edge region of the first pixel defining structure on the light-emitting effect. After the light-emitting device is lit, the brightness in the edge region of the first pixel defining structure is significantly reduced. Compared with the existing structure, the exemplary embodiments of the present disclosure effectively reduce the brightness in the edge region of the pixel defining structure, improve the display uniformity, and improve the display quality. The exemplary embodiments of the present disclosure do not require changing the existing process flow or process equipment when preparing the display substrate, have good process compatibility, high process feasibility, strong practicability, a simple method, obvious effects, and have good application prospects.

[0225] The structure shown in the present disclosure and its preparation process are only an exemplary illustration. In the exemplary embodiments, the corresponding structure can be changed according to actual needs, and the patterning process can be increased or decreased. For example, the first pixel defining structure and the second pixel defining structure can be formed simultaneously by a single patterning process, followed by a hydrophobic treatment. For another example, the third pixel defining structure and the first pixel defining structure may not overlap, and the third pixel defining structure and the second pixel defining structure may not overlap. For yet another example, other electrodes or leads may be provided in the driving structure layer and the light-emitting structure layer, which are not limited in the present disclosure.

[0226] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which are not limited in the present disclosure.

[0227] The exemplary embodiments of the present disclosure also provide a method for preparing a display substrate. In the exemplary embodiments, the method for preparing a display substrate may include:

[0228] A pixel defining layer is formed on a substrate; the pixel defining layer includes a plurality of first pixel defining structures, a plurality of second pixel defining structures, and a plurality of third pixel defining structures; the first pixel defining structures have a strip shape extending along a first direction, and a plurality of first pixel defining structures are arranged in sequence along a second direction, the first direction intersecting the second direction; the second pixel defining structures have a strip shape extending along the second direction, and a plurality of second pixel defining structures are arranged at intervals between adjacent first pixel defining structures; at least one third pixel defining structure is arranged between the first pixel defining structures and the second pixel defining structures; in a direction perpendicular to the substrate, the height of the third pixel defining structure is less than the height of the second pixel defining structure.

[0229] An exemplary embodiment of the present disclosure further provides a display device, including the foregoing display substrate. The display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0230] Although the disclosed embodiments of the present invention are as above, the above content is only an embodiment adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, It includes a substrate and a pixel definition layer disposed on the substrate; the pixel definition layer includes a plurality of first pixel definition structures, a plurality of second pixel definition structures, and a plurality of third pixel definition structures; the first pixel definition structure has an elongated shape extending along a first direction, and a plurality of first pixel definition structures are arranged in sequence along a second direction, with the first direction intersecting the second direction. The second pixel definition structure has an elongated shape extending along the second direction, and a plurality of second pixel definition structures are spaced between adjacent first pixel definition structures; there is a first distance between the edge of the first pixel definition structure close to the second pixel definition structure and the end face of the second pixel definition structure close to the first pixel definition structure; at least one third pixel definition structure is disposed between the first pixel definition structure and the second pixel definition structure; in the direction perpendicular to the substrate, the height of the third pixel definition structure is less than the height of the second pixel definition structure. The hydrophobicity of the first pixel definition structure is stronger than that of the third pixel definition structure; in a plane perpendicular to the first direction, the cross-sectional shape of the first pixel definition structure is a first trapezoid, and the first slope angle of at least part of the side of the first trapezoid is 30° to 70°; in a plane perpendicular to the second direction, the cross-sectional shape of the second pixel definition structure is a second trapezoid, and the second slope angle of at least part of the side of the second trapezoid is 30° to 90°.

2. The display substrate according to claim 1, wherein In the direction perpendicular to the substrate, the height of the second pixel definition structure is less than the height of the first pixel definition structure.

3. The display substrate according to claim 1, wherein In the direction perpendicular to the substrate, the height of the first pixel definition structure is 1.0 μm to 2.0 μm.

4. The display substrate according to claim 1, wherein In the direction perpendicular to the substrate, the height of the second pixel definition structure is 0.3 μm to 0.8 μm.

5. The display substrate according to claim 1, wherein In the direction perpendicular to the substrate, the height of the third pixel definition structure is 0.1 μm to 0.3 μm.

6. The display substrate according to claim 1, wherein The first distance is greater than or equal to 2 μm.

7. The display substrate according to claim 1, characterized in that, The width of the upper base of the first trapezoid is greater than or equal to 15 μm, and the width of the upper base of the second trapezoid is greater than or equal to 3 μm.

8. The display substrate according to claim 1, wherein The hydrophobicity of the first pixel definition structure is stronger than that of the second pixel definition structure, and the hydrophobicity of the second pixel definition structure is stronger than that of the third pixel definition structure.

9. The display substrate according to claim 1, wherein The material of the third pixel definition structure includes a hydrophilic inorganic material or a hydrophilic organic material.

10. The display substrate according to any one of claims 1 to 9, characterized in that, There is a first overlapping area between the orthographic projection of the first pixel definition structure on the substrate and the orthographic projection of the third pixel definition structure on the substrate, and in the second direction, the first overlapping width of the first overlapping area is 1 μm to 3 μm.

11. The display substrate according to any one of claims 1 to 9, characterized in that, There is a second overlapping area between the orthographic projection of the second pixel definition structure on the substrate and the orthographic projection of the third pixel definition structure on the substrate, and in the second direction, the second overlapping width of the second overlapping area is 1 μm to 3 μm.

12. The display substrate according to any one of claims 1 to 9, characterized in that, The first pixel definition structure and the third pixel definition structure are an integrally connected structure.

13. The display substrate according to claim 12, characterized in that, A first side of the first pixel defining structure, which is away from the second pixel defining structure, has a first slope angle, and a third side of the first pixel defining structure, which is away from the first side, has a third slope angle, and the first slope angle is greater than the third slope angle.

14. The display substrate according to any one of claims 1 to 9, characterized in that, The second pixel defining structure and the third pixel defining structure are an integrally connected structure.

15. The display substrate according to any one of claims 1 to 9, characterized in that, The third pixel defining structure includes at least two mutually isolated sub-defining structures, and the at least two sub-defining structures are arranged in sequence along the first direction.

16. The display substrate according to claim 15, wherein The positive projection of at least one sub-defining structure on the substrate overlaps at least partially with the positive projection of the first pixel defining structure on the substrate, and / or the positive projection of at least one sub-defining structure on the substrate overlaps at least partially with the positive projection of the second pixel defining structure on the substrate.

17. The display substrate according to claim 15, wherein The positive projection of at least one sub-defining structure on the substrate does not overlap with the positive projection of the first pixel defining structure on the substrate, and / or the positive projection of at least one sub-defining structure on the substrate does not overlap with the positive projection of the second pixel defining structure on the substrate.

18. The display substrate according to any one of claims 1 to 9, characterized in that, The display substrate further includes an organic light emitting layer, the organic light emitting layer is disposed in an opening region defined by the first pixel defining structure and the second pixel defining structure, and the organic light emitting layer covers the third pixel defining structure.

19. A display device, characterized in that, Including the display substrate according to any one of claims 1 to 18.

20. A method for preparing a display substrate, characterized in that, Including: Forming a pixel defining layer on a substrate; The pixel defining layer includes a plurality of first pixel defining structures, a plurality of second pixel defining structures, and a plurality of third pixel defining structures; The first pixel defining structure has an elongated shape extending along a first direction, and a plurality of first pixel defining structures are arranged in sequence along a second direction, and the first direction intersects with the second direction; The second pixel defining structure has an elongated shape extending along the second direction, and a plurality of second pixel defining structures are arranged at intervals between adjacent first pixel defining structures; there is a first distance between an edge of the first pixel defining structure close to the second pixel defining structure and an end face of the second pixel defining structure close to the first pixel defining structure; at least one third pixel defining structure is disposed between the first pixel defining structure and the second pixel defining structure; in a direction perpendicular to the substrate, the height of the third pixel defining structure is less than the height of the second pixel defining structure; The first pixel defining structure has stronger liquid repellency than the third pixel defining structure; in a plane perpendicular to the first direction, the cross-sectional shape of the first pixel defining structure is a first trapezoid, and the first slope angle of at least part of the side of the first trapezoid is 30° to 70°; in a plane perpendicular to the second direction, the cross-sectional shape of the second pixel defining structure is a second trapezoid, and the second slope angle of at least part of the side of the second trapezoid is 30° to 90°.

Images