Multi-main grid back contact heterojunction solar cell and manufacturing method thereof

Abstract

The present application relates to a multi-main-grid back contact heterojunction solar cell, which comprises a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions arranged alternately on a first main surface of the semiconductor substrate, an isolation groove arranged between each first semiconductor region and second semiconductor region, a first insulating layer array arranged horizontally on each first semiconductor region, a second insulating layer array arranged horizontally on each second semiconductor region, a first solderable main grid line arranged in correspondence with the same horizontal position of each second insulating layer array, and a second solderable main grid line arranged in correspondence with the same horizontal position of each first insulating layer array; the first insulating layer array and the second insulating layer array are staggered from top to bottom. The purpose of the present application is to provide a multi-main-grid back contact heterojunction solar cell, which realizes a multi-main-grid structure while significantly reducing the conductivity requirement of the fine grid lines and reducing the production cost.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a multi-busbar back-contact heterojunction solar cell and its fabrication method. Background Technology

[0002] In recent years, advancements in solar cell manufacturing technology have led to declining production costs and increasing conversion efficiency. Solar cell power generation is becoming increasingly widespread and is a crucial energy source for electricity supply. High-efficiency solar cells represent the future industry trend, increasing wattage per unit area while simultaneously reducing costs, thereby enhancing the added value of solar cell power generation modules.

[0003] Back-contact solar cells, one type of high-efficiency solar cell, move all the electrodes from the light-receiving surface to the back, maximizing the area of ​​the light-receiving surface and thus improving the cell's conversion efficiency. A representative example is SUN POWER from the United States.

[0004] However, high-efficiency battery technologies currently all suffer from high manufacturing costs. For example, the copper plating technology used in back-contact batteries presents challenges related to copper-containing wastewater treatment and environmental protection, and requires substantial production space, hindering large-scale mass production. Therefore, it is necessary to develop a low-cost metal electrode structure suitable for back-contact batteries to promote the large-scale production of high-efficiency back-contact batteries. Summary of the Invention

[0005] One of the objectives of this invention is to provide a multi-busbar back-contact heterojunction solar cell that significantly reduces the conductivity requirements of fine grid lines while achieving a multi-busbar structure and reducing production costs.

[0006] One of the objectives of this invention is to provide a method for manufacturing multi-busbar back-contact heterojunction solar cells, which can greatly reduce metallization costs, avoid complex wet copper electroplating schemes, and is more conducive to the production and application of back-contact heterojunction solar cell technology.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] A multi-busbar back-contact heterojunction solar cell includes a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions disposed on a first main surface of the semiconductor substrate and alternately arranged from left to right, an isolation trench disposed between each of the first semiconductor regions and the second semiconductor regions, a column or more of first insulating layer arrays horizontally disposed on each of the first semiconductor regions, a column or more of second insulating layer arrays horizontally disposed on each of the second semiconductor regions, a column or more of first solderable main grid lines electrically connected to each of the first semiconductor regions and corresponding to each of the second insulating layer arrays at the same horizontal position, and a column or more of second solderable main grid lines electrically connected to each of the second semiconductor regions and corresponding to each of the first insulating layer arrays at the same horizontal position; the first insulating layer arrays and the second insulating layer arrays are staggered from top to bottom.

[0009] A method for fabricating a multi-busbar back-contact heterojunction solar cell includes the following steps:

[0010] Step A: A first semiconductor region and a second semiconductor region are alternately disposed from left to right on the first main surface of the semiconductor substrate, and an isolation trench is disposed between the first semiconductor region and the second semiconductor region.

[0011] Step B involves two or more rows of insulating segments staggered from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are formed; each row of insulating segments is only provided in the first semiconductor region or the second semiconductor region, and the first semiconductor region and the second semiconductor region are each provided with one or more rows of insulating segments, and each first semiconductor region and each second semiconductor region are provided with insulating segments; a row of insulating segments provided at the same horizontal position in the first semiconductor region is a first insulating layer array, and a row of insulating segments provided at the same horizontal position in the second semiconductor region is a second insulating layer array;

[0012] Step C: At the same horizontal position in each of the second insulating layer arrays, a first solderable main gate line electrically connected to each of the first semiconductor regions is set, and at the same horizontal position in each of the first insulating layer arrays, a second solderable main gate line electrically connected to each of the second semiconductor regions is set.

[0013] Compared with the prior art, the advantages of the present invention are as follows:

[0014] (1) The first semiconductor region and the second semiconductor region are alternately set. The insulating layer array and the solderable main grid line are staggered in the corresponding semiconductor region. The insulating layer array separates and insulates different semiconductor regions at the same horizontal position, ensuring that the solderable main grid line is only electrically connected to the semiconductor region of the same conductivity type, effectively avoiding short circuits, realizing the multi-main grid structure of back contact heterojunction solar cell, significantly reducing the conductivity requirements of the solar cell for the fine grid line, and at the same time, it is very convenient for cell testing and sorting and cell stringing during module manufacturing.

[0015] (2) A deposited metal conductive layer is used as a fine grid electrode. The metal conductive layer and the transparent conductive film are deposited at the same time, eliminating the need for copper electroplating. At the same time, the fine grid electrode does not require expensive low-temperature silver paste, thus greatly simplifying the cell production process and reducing production costs, making it very suitable for mass production. Attached Figure Description

[0016] Figure 1 The following are the steps for manufacturing a solar cell according to Embodiment 1 of the present invention;

[0017] Figure 2 A cross-sectional view of an n-type silicon wafer with a passivation layer formed on the front and an anti-reflection layer formed therewith, and a first semiconductor region, an isolation region, and a second semiconductor region formed in a cross arrangement on the back, provided in Embodiment 1 of the present invention;

[0018] Figure 3 This is a cross-sectional view of the transparent conductive film layer and the metal conductive film layer deposited on the back of a silicon wafer according to Embodiment 1 of the present invention;

[0019] Figure 4 This is a cross-sectional view of the protective ink printed on the surface of the isolation area on the back of a silicon wafer according to Embodiment 1 of the present invention;

[0020] Figure 5 This is a schematic diagram of the structure of the protective ink printed on the back of a silicon wafer according to Embodiment 1 of the present invention;

[0021] Figure 6 This is a cross-sectional view of the isolation groove formed in Embodiment 1 of the present invention;

[0022] Figure 7 This is a schematic diagram of the structure of a silicon wafer after cleaning and protecting the ink on the back side according to Embodiment 1 of the present invention;

[0023] Figure 8 This is a cross-sectional view of an alternating insulating layer formed on the back side of a silicon wafer according to Embodiment 1 of the present invention;

[0024] Figure 9 This is a schematic diagram of the structure of an alternating insulating layer formed on the back side of a silicon wafer according to Embodiment 1 of the present invention;

[0025] Figure 10 This is a cross-sectional view of a silicon wafer with solderable main gate lines formed on the back side, according to Embodiment 1 of the present invention.

[0026] Figure 11 This is a schematic diagram of the structure of forming a solderable main gate line on the back of a silicon wafer according to Embodiment 1 of the present invention;

[0027] Figure 12 This is a schematic diagram of the structure of a silicon wafer after string bonding according to Embodiment 1 of the present invention;

[0028] Figure 13 The following are the steps for manufacturing a solar cell according to Embodiment 2 of the present invention;

[0029] Figure 14 A cross-sectional view of an n-type silicon wafer with a passivation layer formed on the front and an anti-reflection layer formed therewith, and a first semiconductor region, an isolation region, and a second semiconductor region formed in a cross arrangement on the back, provided in Embodiment 2 of the present invention;

[0030] Figure 15 This is a cross-sectional view of the transparent conductive film deposited on the back of the battery in Embodiment 2 of the present invention;

[0031] Figure 16 This is a cross-sectional view of the isolation groove pattern formed on the back of the battery according to Embodiment 2 of the present invention;

[0032] Figure 17 This is a cross-sectional view of the isolation groove formed on the back of the battery in Embodiment 2 of the present invention;

[0033] Figure 18 This is a schematic diagram of the structure of the battery back side forming an isolation groove according to Embodiment 2 of the present invention;

[0034] Figure 19 This is a cross-sectional view of the alternating insulating layers formed on the back of the battery according to Embodiment 2 of the present invention;

[0035] Figure 20 This is a schematic diagram of the structure of the battery back side with alternating insulating layers according to Embodiment 2 of the present invention;

[0036] Figure 21 This is a cross-sectional view of the alternating metal grid lines formed on the back of the battery according to Embodiment 2 of the present invention;

[0037] Figure 22 This is a schematic diagram of the alternating metal grid lines formed on the back of the battery according to Embodiment 2 of the present invention;

[0038] Figure 23 This is a schematic diagram of the structure of the battery after the welding strips are connected in series on the back side in Embodiment 2 of the present invention;

[0039] Figure 24 This is another structural schematic diagram of alternating metal grid lines formed on the back of the battery according to Embodiment 2 of the present invention. Detailed Implementation

[0040] A multi-busbar back-contact heterojunction solar cell includes a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions disposed on a first main surface of the semiconductor substrate and alternately arranged from left to right, an isolation trench disposed between each of the first semiconductor regions and the second semiconductor regions, a column or more of first insulating layer arrays horizontally disposed on each of the first semiconductor regions, a column or more of second insulating layer arrays horizontally disposed on each of the second semiconductor regions, a column or more of first solderable main grid lines electrically connected to each of the first semiconductor regions and corresponding to each of the second insulating layer arrays at the same horizontal position, and a column or more of second solderable main grid lines electrically connected to each of the second semiconductor regions and corresponding to each of the first insulating layer arrays at the same horizontal position; the first insulating layer arrays and the second insulating layer arrays are staggered from top to bottom.

[0041] The first insulating layer array covers the first semiconductor region and the isolation trench at the same horizontal position, so that the second solderable main gate line can only form electrical contact with the second semiconductor region; the second insulating layer array covers the second semiconductor region and the isolation trench at the same horizontal position, so that the first solderable main gate line can only form electrical contact with the first semiconductor region.

[0042] An isolation region is provided between the first semiconductor region and the second semiconductor region, and the isolation trench is disposed on the isolation region.

[0043] The first semiconductor region includes a first type semiconductor film layer and a first conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The second semiconductor region includes a second type semiconductor film layer and a second conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation region includes a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation trench divides the isolation conductive film layer into left and right parts.

[0044] The first type of semiconductor film layer includes a first passivation layer and a first semiconductor layer formed sequentially from bottom to top on a first main surface of a semiconductor substrate; the second type of semiconductor film layer includes a second passivation layer and a second semiconductor layer formed sequentially from bottom to top on a first main surface of a semiconductor substrate; the first conductive film layer, the second conductive film layer, and the isolation conductive film layer include transparent conductive layers formed on the respective semiconductor layers as substrates; the isolation film layer includes an isolation insulating layer formed on the first semiconductor layer as substrate in the isolation region.

[0045] Each first semiconductor region between two adjacent first insulating layer arrays has multiple first fine gates electrically connected to a first solderable main gate line, and each second semiconductor region between two adjacent second insulating layer arrays has multiple second fine gates electrically connected to a second solderable main gate line; the thickness of the first and second fine gates is 5-30 μm, and the length is 10-40 mm. In a preferred embodiment, the first conductive film layer, the second conductive film layer, and the insulating conductive film layer include a metal conductive layer formed on a transparent conductive layer substrate, replacing the first and second fine gates.

[0046] The first passivation layer and the second passivation layer respectively include an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0047] The first semiconductor layer and the second semiconductor layer include an N-type doped amorphous silicon / microcrystalline silicon layer or a P-type doped amorphous silicon / microcrystalline silicon layer. When the first semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer. When the first semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer. The isolation film layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon carbide layer.

[0048] The transparent conductive layer is at least one of indium tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, zinc-doped indium oxide, and tungsten-doped indium oxide, with a total thickness of 50-100 nm and a total sheet resistance of 20-100 Ω / □; the metallic conductive layer is at least one of copper, aluminum, nickel, nickel alloy, and indium tin oxide, with a total thickness of 200-600 nm and a total sheet resistance of 0.02-0.5 Ω / □.

[0049] The width of the isolation groove is 10-150um, and the resistance between the metal conductive layers on both sides of the isolation groove is greater than 1KΩ.

[0050] The first solderable main gate line and the first solderable main gate line are solderable low-temperature silver paste layers, solderable silver-coated copper paste layers, or solderable nickel paste layers, with a thickness of 5-30 μm and a width of 0.04-10 mm. In a preferred embodiment, the width of the first solderable main gate line or the second solderable main gate line in the area not in contact with the first semiconductor region or the second semiconductor region is 0.04-1 mm, and the width of the first solderable main gate line or the second solderable main gate line in the area in contact with the first semiconductor region or the second semiconductor region is 1-10 mm.

[0051] The first and second solder ribbon insulating layer arrays are insulating varnish or insulating ink layers with a thickness of 3-25 μm and a width of 0.3-1 mm. Both arrays are made of transparent material.

[0052] A method for fabricating a multi-busbar back-contact heterojunction solar cell includes the following steps:

[0053] Step A: A first semiconductor region and a second semiconductor region are alternately disposed from left to right on the first main surface of the semiconductor substrate, and an isolation trench is disposed between the first semiconductor region and the second semiconductor region.

[0054] Step B involves two or more rows of insulating segments staggered from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are formed; each row of insulating segments is only provided in the first semiconductor region or the second semiconductor region, and the first semiconductor region and the second semiconductor region are each provided with one or more rows of insulating segments, and each first semiconductor region and each second semiconductor region are provided with insulating segments; a row of insulating segments provided at the same horizontal position in the first semiconductor region is a first insulating layer array, and a row of insulating segments provided at the same horizontal position in the second semiconductor region is a second insulating layer array;

[0055] Step C: At the same horizontal position in each of the second insulating layer arrays, a first solderable main gate line electrically connected to each of the first semiconductor regions is set, and at the same horizontal position in each of the first insulating layer arrays, a second solderable main gate line electrically connected to each of the second semiconductor regions is set.

[0056] The specific method of step A is as follows: the first semiconductor region and the second semiconductor region are alternately disposed on the first main surface of the semiconductor substrate from left to right, an isolation region is disposed between the first semiconductor region and the second semiconductor region, and an isolation trench is disposed on the isolation region.

[0057] The first semiconductor region forms a first type semiconductor film layer and a first conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The second semiconductor region forms a second type semiconductor film layer and a second conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation region forms a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. An isolation groove is formed on the isolation region to divide the isolation conductive film layer into left and right parts.

[0058] The isolation groove is formed on the surface of the isolation area using laser etching or chemical etching techniques; the width of the isolation groove is 10-150 μm. The laser etching technique has a etching speed of 3-50 m / s and a pulse energy between 10 μJ and 1000 μJ. The chemical etching technique can form the isolation groove by printing protective ink followed by etching with a chemical solution, or by baking and etching with etching ink.

[0059] The first type of semiconductor film layer is mainly composed of a first passivation layer and a first semiconductor layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate; the second type of semiconductor film layer is mainly composed of a second passivation layer and a second semiconductor layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate; the first conductive film layer, the second conductive film layer, and the isolation conductive film layer are mainly composed of a transparent conductive layer and a metal conductive layer formed sequentially from bottom to top on the corresponding semiconductor layer; the isolation film layer is mainly composed of an isolation insulating layer formed on the first semiconductor layer in the isolation region; an isolation trench is formed on the isolation region to separate the transparent conductive layer and the metal conductive layer into left and right parts. In a preferred embodiment, if the first conductive film layer, the second conductive film layer, and the isolation conductive film layer do not contain a metal conductive layer, step C further includes forming a first fine gate electrically connected to a first main gate on each first semiconductor region between two adjacent first insulating layer arrays, and forming a second fine gate electrically connected to a second solderable main gate line on each second semiconductor region between two adjacent second insulating layer arrays.

[0060] The first passivation layer and the second passivation layer are at least one of intrinsic amorphous silicon and intrinsic microcrystalline silicon. The first semiconductor layer and the second semiconductor layer are either N-type doped amorphous silicon / microcrystalline silicon layers or P-type doped amorphous silicon / microcrystalline silicon layers. When the first semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer; when the first semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer. The insulating layer is at least one of silicon nitride, silicon oxide, and silicon carbide.

[0061] The transparent conductive layer and the metallic conductive layer are deposited using physical vapor deposition (PVD) or reactive plasma deposition (RPD) techniques. The transparent conductive film is at least one of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc-doped indium oxide (IZO), and tungsten-doped indium oxide (IWO), with a thickness of 50-100 nm and a sheet resistance of 20-100 Ω / □. The metallic conductive film is at least one of copper (Cu), aluminum (Al), nickel (Ni), nickel alloys, and indium tin oxide (ITO), with a thickness of 200-600 nm and a sheet resistance of 0.02-0.5 Ω / □.

[0062] The resistance between the metal conductive layers on both sides of the isolation groove is greater than 1KΩ.

[0063] The specific method of step B is as follows: A first insulating layer array and a second insulating layer array are staggered from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are located, using roller coating, pad printing, screen printing, or printing technology; two or more of each of the first and second insulating layer arrays are provided. The first and second solder ribbon insulating layer arrays are made of transparent material.

[0064] The first and second insulating layer arrays are formed by coating, pad printing, screen printing, or printing insulating ink and then curing it at 130-200℃ for 5-30 minutes. The thickness is 3-25µm and the width is 0.3-1mm. When the insulating ink thickness is 10µm, the resistance is greater than 1 megohm / cm. 2 In another preferred embodiment, an insulating varnish is used to fabricate the first and second insulating layer arrays.

[0065] The specific method of step C is to form a second solderable main grid line or a first solderable main grid line at a horizontal position corresponding to the first insulating layer array or the second insulating layer array using roller coating, pad printing, screen printing or printing technology.

[0066] The first and second solderable main gate lines are formed by coating, pad printing, screen printing or printing with solderable low-temperature silver paste, solderable silver-coated copper paste or solderable nickel paste, and then baking at 150-230℃ for 5-40 minutes to cure. The width of the first or second solderable main gate line in the area not in contact with the first or second semiconductor region is 0.04-1mm, and the width of the first or second solderable main gate line in the area in contact with the first or second semiconductor region is 1-10mm.

[0067] On the second main surface of the semiconductor substrate, a fourth passivation layer and an antireflection layer are sequentially formed from bottom to top, with the semiconductor substrate as the base. The fourth passivation layer is at least one of intrinsic amorphous silicon, intrinsic microcrystalline silicon, N-type doped amorphous silicon, and N-type doped microcrystalline silicon; the antireflection layer is at least one of silicon nitride, silicon oxide, silicon carbide, and a transparent conductive film.

[0068] The semiconductor substrate is a cast monocrystalline silicon wafer, a monocrystalline silicon wafer, or a polycrystalline silicon wafer.

[0069] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0070] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0071] Example 1:

[0072] like Figures 1 to 12 The diagram shown is an embodiment of a method for fabricating a multi-busbar back-contact heterojunction solar cell provided by the present invention.

[0073] This embodiment can be implemented using the following methods:

[0074] S1. An n-type silicon wafer 10 is provided with a passivation layer 30 and an anti-reflection layer 31 formed on the front side, and a first semiconductor region 42, an isolation region 44, and a second semiconductor region 43 arranged in a cross pattern on the back side.

[0075] S2. A transparent conductive film layer 50 and a metal conductive film layer 51 are deposited on the back side of the silicon wafer 10 by physical vapor deposition (PVD) technology.

[0076] S3. A protective ink 52 is printed on the back of the silicon wafer 10 to form an isolation groove pattern using printing technology;

[0077] S4. After being corroded and cleaned with a chemical solution, an isolation groove 53 is formed on the surface of the isolation zone 44;

[0078] S5. An insulating layer 60 / 61 is simultaneously formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by screen printing technology;

[0079] S6. Solderable main gate lines 70B / 71B are formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by screen printing technology.

[0080] like Figure 2The diagram shows a cross-sectional view of the n-type silicon wafer 10 provided in S1. The passivation layer 30 formed on the front side of the silicon wafer 10 is intrinsically oxygen-doped microcrystalline silicon with a thickness of 5-15 nm, and the antireflection layer 31 is silicon nitride with a thickness of 80-150 nm, formed by plasma-enhanced chemical vapor deposition (PECVD). The first semiconductor region 42 has a first passivated amorphous silicon layer 20 and an N-type doped amorphous silicon and microcrystalline silicon composite layer 21 sequentially disposed on the surface of the silicon wafer 10. The second semiconductor region 43 has a second passivated amorphous layer 40 and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 sequentially disposed on the surface of the silicon wafer 10. The isolation region 44 has, sequentially disposed on the surface of the silicon wafer 10, a first passivated amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, a silicon nitride isolation layer 22, a second passivated amorphous layer 40, and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41. The thicknesses of the first passivated amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the second passivated amorphous layer 40, and the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are 5-15 nm, and the thickness of the silicon nitride isolation layer 22 is 80-150 nm. All of these layers are formed by PECVD deposition. The silicon wafer 10 can be a cast monocrystalline silicon wafer or a monocrystalline silicon wafer.

[0081] like Figure 3 The image shows a cross-sectional view of a transparent conductive film layer 50 and a metal conductive film layer 51 deposited on the back side of silicon wafer 10 in S2. The transparent conductive film layer 50 is indium tin oxide (ITO) with a thickness of 80-100 nm and a sheet resistance of 30-40 Ω / □. The metal conductive film layer is a composite layer of copper (Cu) and indium tin oxide (ITO), wherein the copper layer has a thickness of 300 nm, the indium tin oxide (ITO) layer has a thickness of 20-50 nm, and the sheet resistance is 0.05-0.1 Ω / □.

[0082] like Figure 4-5 As shown, the back of silicon wafer 10 in S3 is printed with protective ink 52 to form an isolation groove 53 pattern. The spacing between the protective inks 52 is 50-150um. The baking temperature of the protective inks 52 is 150℃ and the baking time is 10 minutes.

[0083] like Figure 6-7 As shown, in S4, the silicon wafer 10 is etched for 3 minutes using a mixed solution of 5% FeCl3 and 5% HCl to clean the metal conductive layer 51 and transparent conductive film layer 50 outside the protective ink 52 area. The protective ink 52 is then cleaned with a 5% NaOH solution to form an isolation groove 53. The resistance between the metal conductive layers 51 on both sides of the isolation groove 53 is greater than 1KΩ.

[0084] like Figure 8-9 As shown, in S5, insulating layers 60 / 61 are simultaneously formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 using screen printing technology on the back side of the silicon wafer 10. The insulating layers 60 / 61 have a thickness of 3-25um and a width of 0.5-0.8mm. After printing, they are dried by baking at 180℃ for 5 minutes. The insulating layers 60 on the surface of the first semiconductor region 42 and the insulating layers 61 on the surface of the second semiconductor region 43 are arranged alternately.

[0085] like Figure 10-11 As shown, in S6, low-temperature solderable silver-coated copper paste is printed on the back of silicon wafer 10 using screen printing technology to form solderable main gate lines 70B / 71B. The thickness of the solderable main gate lines 70B / 71B is 10-15um. After printing, they are cured by baking at 180℃ for 30 minutes. There are 10-20 columns of main gate lines. Each column of main gate lines is independently connected to the first semiconductor region 42 or the second semiconductor region 43. The width of the main gate lines 70B / 71B is 0.06mm. In order to reduce the contact resistance between the main gate lines 70B / 71B and the metal conductive layer 51, the area in direct contact between the main gate lines 70B / 71B and the metal conductive layer 51 can be widened to 3mm.

[0086] During the sorting test, only the main gate line 70B on the surface of the first semiconductor region 42 and the main gate line 71B on the surface of the second semiconductor region 43 need to be led out to collect IV data. For example... Figure 12 As shown, during the component manufacturing process, when the silicon wafers 10 are connected in series, it is only necessary to alternately solder the main gate line 70B on the surface of the first semiconductor region 42 and the main gate line 71B on the surface of the second semiconductor region 43 on the back of two adjacent silicon wafers 10 together with solder ribbons 80 to achieve the series connection between the silicon wafers 10.

[0087] This invention, employing the above technical solutions, enables a multi-busbar structure for back-contact heterojunction solar cells. This significantly reduces the conductivity requirements of the fine grid lines on the solar cells. Furthermore, by using a physical vapor deposition (PVD) metal conductive layer as the fine grid electrode, and by employing conventionally used low-temperature silver paste only for the main grid lines, the silver paste consumption per G1 silicon wafer is reduced to 50-100 mg, far lower than the approximately 200 mg consumption of conventional heterojunction cells and also far lower than the approximately 400 mg consumption of multi-busbar silicon-based homojunction back-contact cells. Simultaneously, it avoids the use of large-scale wet copper plating equipment, eliminating concerns about copper-containing wastewater treatment, environmental protection, large production sites, and high operating costs. Therefore, it greatly simplifies the cell manufacturing process, reduces production costs, and significantly facilitates cell testing, sorting, and string bonding during module fabrication. This greatly benefits the mass production and promotion of high-efficiency back-contact heterojunction solar cells.

[0088] Example 2:

[0089] like Figures 13 to 24The diagram shown is an embodiment of a method for fabricating a multi-busbar back-contact heterojunction solar cell provided by the present invention.

[0090] This embodiment can be implemented using the following methods:

[0091] S1. An n-type silicon wafer 10 is provided with a passivation layer 30 and an anti-reflection layer 31 formed on the front side, and a first semiconductor region 42, an isolation region 44, and a second semiconductor region 43 arranged in a cross pattern on the back side.

[0092] S2. A transparent conductive film layer 50 is deposited on the back side of silicon wafer 10 using physical vapor deposition (PVD) technology.

[0093] S3. Form an isolation groove pattern 52 on the back of the battery using screen printing technology;

[0094] S4. An isolation groove 53 is formed on the surface of the isolation area 44 by wet chemical etching and ink removal technology;

[0095] S5. An insulating layer 60 and 61 are formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by screen printing technology.

[0096] S6. Metal gate lines 70 / 71, which are alternately arranged with insulating layers 60 / 61, are formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 by screen printing technology.

[0097] like Figure 14The diagram shows a cross-sectional view of the n-type silicon wafer 10 provided in S1. The passivation layer 30 formed on the front side of the silicon wafer 10 is intrinsically oxygen-doped microcrystalline silicon with a thickness of 5-15 nm, and the antireflection layer 31 is silicon nitride with a thickness of 80-150 nm, formed by plasma-enhanced chemical vapor deposition (PECVD). The first semiconductor region 42 has a first passivated amorphous silicon layer 20 and an N-type doped amorphous silicon and microcrystalline silicon composite layer 21 sequentially disposed on the surface of the silicon wafer 10. The second semiconductor region 43 has a second passivated amorphous layer 40 and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 sequentially disposed on the surface of the silicon wafer 10. The isolation region 44 has, sequentially disposed on the surface of the silicon wafer 10, a first passivated amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, a silicon nitride isolation layer 22, a second passivated amorphous layer 40, and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41. The thicknesses of the first passivated amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the second passivated amorphous layer 40, and the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are 5-15 nm, and the thickness of the silicon nitride isolation layer 22 is 80-150 nm. All of these layers are formed by PECVD deposition. The silicon wafer 10 can be a cast monocrystalline cell or a monocrystalline cell.

[0098] like Figure 15 The image shows a cross-sectional view of a transparent conductive film layer 50 deposited on the back side of silicon wafer 10 in S2. The transparent conductive film layer 50 is indium tin oxide (ITO), with a thickness of 80-100 nm and a sheet resistance of 30-40 Ω / □.

[0099] like Figure 16 The image shown is a cross-sectional view of the isolation groove pattern formed by screen printing protective ink 52 on the back side of the S3 silicon wafer 10. The width of the isolation groove is 30-100 μm, the baking temperature of the protective ink is 150°C, and the baking time is 5-10 minutes.

[0100] like Figure 17-18 As shown, Figure 17 This is a cross-sectional view of the isolation trench 53 formed on the surface of the isolation region 44 on the back side of the S4 silicon wafer 10 by wet chemical etching and ink removal technology. Figure 18 This is a schematic diagram of the structure in which an isolation trench 53 is formed on the surface of the isolation area 44 on the back side of the S4 silicon wafer 10 using a wet chemical etching and ink removal technique. After the protective ink 52 is baked, the transparent conductive film layer 50 outside the protective ink 52 area is etched clean with a 2-10% hydrochloric acid solution. Then, the protective ink 52 is removed and cleaned with a 2-10% potassium hydroxide solution. After etching and ink removal, the resistance between the transparent conductive film layers 50 on both sides of the isolation trench 53 is greater than 1KΩ.

[0101] like Figures 19-20 The diagram shows a cross-sectional view and a schematic diagram of the alternating insulating layers 60 and 61 formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 using screen printing technology in step S5. The insulating layers 60 and 61 are made of insulating ink, with a thickness of 3-25 μm, a length of 5-15 mm, and a width of 0.5-0.8 mm. The printing process involves baking at 150°C for 5-10 minutes to cure the ink. Insulating layer 60 covers the first semiconductor region 42 and the isolation trench 53 at the same horizontal position; insulating layer 61 covers the second semiconductor region 43 and the isolation trench 53 at the same horizontal position.

[0102] like Figure 21-22 The diagram shows a cross-sectional view and structural schematic of metal gate lines 70 / 71 alternating with insulating layers 60 / 61 formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 using screen printing technology. The metal gate lines comprise two parts: fine gate lines 70F / 71F and main gate lines 70B / 71B. There are 10-20 columns of metal gate lines 70 / 71, made of either low-temperature silver paste or solderable silver-coated copper paste. The fine gate lines 70F / 71F and the main gate lines 70B / 71B are screen printed simultaneously, with a thickness of 5-30 μm and a length of 10-40 mm. After screen printing, they are cured by baking at 180°C for 30 minutes. The metal gate lines 70 / 71 are arranged alternately on the surfaces of the first semiconductor region 42 and the second semiconductor region 42. The metal gate lines 70 / 71 between the first semiconductor region 42 and the second semiconductor region 42 are mutually insulated, with an insulation resistance greater than 1 kΩ. In a preferred embodiment, as shown... Figure 24 As shown, the area where the main gate line 70B / 71B directly contacts the first semiconductor region 42 or the second semiconductor region 42 can be widened.

[0103] The difference between this embodiment and embodiment 2 is that: S2 only performs transparent conductive film deposition; S6 forms metal gate lines, including solderable main gate lines and fine gate lines.

[0104] This embodiment employs the above technical solution, achieving a bifacial power generation rate of over 80% for back-contact heterojunction solar cells. This allows for higher power generation when the back-contact heterojunction solar cells are installed in locations with good back-side reflection. Furthermore, it greatly facilitates series welding during cell module fabrication. Figure 23The diagram shows the structure after the cell half-cells are cut and connected in series with the solder ribbon 80 to form the metal grid lines 70 / 71. The solder ribbon 80 connects the metal main grid lines 70B of the first semiconductor region 42 and the metal main grid lines 71B of the second semiconductor region 43 of adjacent cells in series to form a cell string. This technical solution can also avoid the use of large-scale wet copper electroplating equipment, and eliminates the need to consider problems such as copper-containing wastewater treatment, environmental protection, large production sites, and high operating costs. Therefore, it greatly simplifies the cell manufacturing process, reduces production costs, and is very conducive to the mass production and promotion of high-conversion-efficiency back-contact heterojunction solar cells.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-busbar back-contact heterojunction solar cell, characterized in that: It includes a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions disposed on a first main surface of the semiconductor substrate and alternately arranged from left to right, an isolation trench disposed between each of the first semiconductor regions and the second semiconductor regions, one or more rows of first insulating layer arrays horizontally disposed on each of the first semiconductor regions, one or more rows of second insulating layer arrays horizontally disposed on each of the second semiconductor regions, one or more rows of first solderable main gate lines electrically connected to each of the first semiconductor regions and corresponding to each of the second insulating layer arrays at the same horizontal position, and one or more rows of first solderable main gate lines electrically connected to each of the second semiconductor regions and corresponding to each of the first insulating layer arrays at the same horizontal position. The first and second insulating layer arrays are staggered from top to bottom. The surface structure layers of the first and second semiconductor regions are a transparent conductive film layer and a metal conductive layer arranged sequentially from the inside to the outside, with the metal conductive layer serving as a fine gate electrode. The metal conductive layer is at least one of copper, aluminum, nickel, and nickel alloy layers, with a total thickness of 200-600 nm and a total sheet resistance of 0.02-0.5 Ω / □. The first and second solderable main gate lines are solderable low-temperature silver paste layers, solderable silver-coated copper paste layers, or solderable nickel paste layers, with a thickness of 5-30 μm and a width of 0.04-10 mm.

2. The multi-busbar back-contact heterojunction solar cell according to claim 1, characterized in that: The width of the first solderable main gate line or the second solderable main gate line in the area not in contact with the first semiconductor region or the second semiconductor region is 0.04-1mm, and the width of the first solderable main gate line or the second solderable main gate line in the area in contact with the first semiconductor region or the second semiconductor region is 1-10mm.

3. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 1 or 2, characterized in that: It includes the following steps: Step A: A first semiconductor region and a second semiconductor region are alternately disposed from left to right on the first main surface of the semiconductor substrate, and an isolation trench is disposed between the first semiconductor region and the second semiconductor region. Step B involves two or more rows of insulating segments staggered from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are formed; each row of insulating segments is only provided in the first semiconductor region or the second semiconductor region, and the first semiconductor region and the second semiconductor region are each provided with one or more rows of insulating segments, and each first semiconductor region and each second semiconductor region are provided with insulating segments; a row of insulating segments provided at the same horizontal position in the first semiconductor region is a first insulating layer array, and a row of insulating segments provided at the same horizontal position in the second semiconductor region is a second insulating layer array; Step C: At the same horizontal position in each of the second insulating layer arrays, a first solderable main gate line electrically connected to each of the first semiconductor regions is set, and at the same horizontal position in each of the first insulating layer arrays, a second solderable main gate line electrically connected to each of the second semiconductor regions is set.

4. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 3, characterized in that: The specific method of step A is as follows: the first semiconductor region and the second semiconductor region are alternately disposed on the first main surface of the semiconductor substrate from left to right, an isolation region is disposed between the first semiconductor region and the second semiconductor region, and an isolation trench is disposed on the isolation region.

5. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 4, characterized in that: The first semiconductor region forms a first type semiconductor film layer and a first conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The second semiconductor region forms a second type semiconductor film layer and a second conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation region forms a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. An isolation groove is formed on the isolation region to divide the isolation conductive film layer into left and right parts.

6. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 4, characterized in that: The isolation groove is formed on the surface of the isolation area by laser etching or chemical etching technology; the width of the isolation groove is 10-150um.

7. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 5, characterized in that: The first conductive film layer, the second conductive film layer, and the isolation conductive film layer are mainly composed of transparent conductive layers formed on the corresponding conductive film layers as substrates; the isolation film layer is mainly composed of an isolation insulating layer formed on the first semiconductor layer as substrate in the isolation region; and an isolation groove is formed on the isolation region to separate the transparent conductive layer and the metal conductive layer into left and right parts.

8. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 7, characterized in that: The first conductive film layer, the second conductive film layer, and the isolation conductive film layer further include a metal conductive layer formed on the basis of the corresponding transparent conductive layer.

9. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 3, characterized in that: The specific method of step B is to use roller coating, pad printing, screen printing or printing technology to set a first insulating layer array and a second insulating layer array from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are set; there are two or more of the first insulating layer array and the second insulating layer array.

10. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 9, characterized in that: The first insulating layer array and the second insulating layer array are formed by coating, pad printing, screen printing or printing insulating ink and then baking at 130-200℃ for 5-30 minutes to cure it. The thickness is 3-25um and the width is 0.3-1mm. When the thickness of the insulating ink is 10um, the resistance value is greater than 1 megohm / cm2.

11. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to any one of claims 4-10, characterized in that: The specific method of step C is to form a second solderable main grid line or a first solderable main grid line at a horizontal position corresponding to the first insulating layer array or the second insulating layer array using roller coating, pad printing, screen printing or printing technology.

12. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 11, characterized in that: The first and second solderable main gate lines are formed by coating, pad printing, screen printing or printing with solderable low-temperature silver paste, solderable silver-coated copper paste or solderable nickel paste, and then baking at 150-230℃ for 5-40 minutes to cure. The width of the first or second solderable main gate line in the area not in contact with the first or second semiconductor region is 0.04-1mm, and the width of the first or second solderable main gate line in the area in contact with the first or second semiconductor region is 1-10mm.

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