High-speed random number generator based on conservative chaotic system and method for generating the same

Abstract

The application provides a high-speed random number generator based on a conservative chaotic system and a generation method thereof. The generated random number is subjected to two commonly used random number test standards, namely, a test suite NIST SP800-22 of The National Institute of Standards and Technology and another test suite TestU01, and experimental test results can prove that the generated random bit sequence passes the randomness test. The throughput of the high-speed random number generator can reach 19 Gbps.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of communication information security, and relates to a high-speed random number generator based on a conservative chaotic system and a generation method thereof. BACKGROUND

[0002] In current digital communication, a password is embodied in the form of randomly distributed 0 and 1 bits, and a stable and fast random number generator can effectively guarantee the password. A nonlinear system is a potential object for random number generation. If it is intended to know the past and future information of a known system, a mathematical model with calculus is the best method for reproducing system information. In this case, a chaotic system that is both dynamic and random is more suitable. Chaos theory, as an important part of nonlinear science, has attracted widespread attention and research. However, although a large number of chaotic and hyperchaotic systems have been proposed, the development of various research directions is uneven, and most of the systems are dissipative chaotic systems, and conservative chaotic systems are very rare. In order to generate random numbers with high throughput for application, there are mainly two implementation methods of analog circuit and digital circuit. Because the analog circuit has its inherent shortcomings, such as poor security and weak anti-interference ability, the electric signal will be disturbed by various noises in the outside world and the internal communication system during transmission along the line, and it is difficult to separate the noise and the signal after mixing, thereby reducing the accuracy of the system calculation result. In recent years, researchers have increasingly used programmable logic devices FPGA to implement chaotic systems, so that the calculation result of the chaotic system is more stable, the rate of generating random numbers is faster, and the throughput is larger. SUMMARY

[0003] The purpose of the present application is to solve the problems existing in the prior art, and provide a high-speed random number generator based on a conservative chaotic system and a generation method thereof, which have stable calculation results, fast random number generation rate and large throughput.

[0004] To this end, the present application adopts the following technical solutions:

[0005] The high-speed random number generator based on a conservative chaotic system comprises:

[0006] An input module, which is used for inputting an initial value;

[0007] An N-K4 iteration module, which comprises a four-dimensional conservative chaotic system calculation unit and an iteration unit, and is used for calculating a four-dimensional value by using a four-dimensional conservative chaotic system equation and iterating the four-dimensional value according to the initial value input by the input module;

[0008] A post-processing module that can convert the four-dimensional numerical values after iteration into 180-bit random bits in binary form, with 30 bits output for each dimension, for a total of 180 bits of random bits.

[0009] Further, the four-dimensional conservative chaotic system calculation unit includes an x input register, a y input register, a z input register, and a u input register. Specifically;

[0010] The x input register is respectively connected to a first shifter and a first inverter. The first shifter is connected to a ∂y output register. The first inverter is connected to a first adder that can perform an increment-by-1 operation. The first adder is connected to a second shifter, which is connected to a second adder. The second adder is connected to a ∂u output register;

[0011] The y input register is connected to a second inverter, which is connected to a third adder that can perform an increment-by-1 operation. The third adder is connected to a third shifter, which is connected to a fourth adder. The fourth adder is connected to a ∂x output register;

[0012] The z input register is respectively connected to a fourth shifter, a fifth shifter, and a third inverter. The fourth shifter is connected to a fifth adder that can perform an increment-by-20 operation. The fifth adder is connected to a sixth shifter, which is connected to a multiplexer. The multiplexer is connected to the second adder. The fifth shifter is connected to a sixth adder that can perform an increment-by -20 operation. The sixth adder is connected to the multiplexer. The third inverter is connected to a seventh adder that can perform an increment-by-1 operation. The seventh adder is connected to a seventh shifter, which is connected to the multiplexer;

[0013] The u input register is connected to a fourth adder. The u input register is also connected to an eighth inverter, which is connected to an eighth adder that can perform an increment-by-1 operation. The eighth adder is connected to an eighth shifter, which is connected to a ∂z output register.

[0014] Further, the logical operation rule of the multiplexer is to output 16*z - 20 when z > 1, -4z when -1 < z < 1, and 16*z + 20 when z < -1.

[0015] Further, the iteration unit is used to iterate the four-dimensional numerical values calculated by the four-dimensional conservative chaotic system equation.

[0016] Furthermore, the iterative unit iterates once per clock cycle through a parallel pipelined computation structure.

[0017] This invention also provides a high-speed random number generation method based on a conservative chaotic system, employing the high-speed random number generator based on a conservative chaotic system described in any one of the above-mentioned methods, and comprising the following steps:

[0018] (1) Input initial values ​​(x0, y0, z0, u0);

[0019] (2) Substitute the initial values ​​into the four-dimensional conservative chaotic system equations, and calculate the four-dimensional values ​​of (k1, k2, k3, k4) in the fourth-order K-value method: (xk1, xk2, xk3, xk4), (yk1, yk2, yk3, yk4), (zk1, zk2, zk3, zk4), and (uk1, uk2, uk3, uk4). The four-dimensional conservative chaotic system equations are as follows:

[0020]

[0021] In the formula

[0022] g(z)=1.25*(∣z-1∣-∣z+1∣);

[0023] (3) Iterate the four-dimensional values ​​according to the following formula to obtain the values ​​S of the four dimensions. n+1 :

[0024]

[0025] In the formula

[0026] ;

[0027] (4) Iterate the S from the chaotic system n+1 The initial values ​​(x0, y0, z0, u0) are fed back into step (2) as initial values ​​and simultaneously applied to S. n+1 After post-processing, it is converted into a six-dimensional random bit number in binary form, with 30 bits output for each dimension, for a total of 180 random bits.

[0028] Furthermore, the post-processing in step (4) includes the following steps:

[0029] a. Use the 37-bit number of each dimension of the four-dimensional chaotic system generated by the fourth-order K-value method as the input terminal;

[0030] b. Extract the last 30 bits from the 37 bits of each of the four values ​​in step 1;

[0031] c. Convert the input 30-bit number to decimal using the following formula.

[0032]

[0033] In the formula, i represents the binary bits of the current value;

[0034] d. Perform mod 2 processing on each dimension's 30-bit decimal random number to convert the value of each dimension into a 30-bit number;

[0035] e. Using the XOR method, the 30 bits of the four dimensions x, y, z, u are XORed bit by bit in pairs, that is, x^y, x^z, x^u, y^z, y^u, z^u respectively.

[0036] The beneficial effects of this invention are as follows:

[0037] (1) A new four-dimensional conservative chaotic system: The chaotic system designed in this invention has four dimensions. Compared with the existing four-dimensional continuous chaotic system, this system has five linear terms and one nonlinear function term. The analysis of the Lyapunov exponent spectrum, phase diagram, equilibrium point eigenvalues, initial value sensitivity comparison diagram, spatial ergodicity, and bifurcation diagram of the system by Matlab software confirms that the system exhibits good wide parameter characteristics, large spatial ergodicity, strong intrinsic randomness and initial value sensitivity, thus making it possible to use chaotic signals to generate high-speed random numbers.

[0038] (2) Optimization of FPGA resources (multiplier usage is 0): In order to make the FPGA implementation of the chaotic system occupy less resources and power consumption, the present invention adjusts the parameters of all linear terms of the system to positive and negative integer multiples of 2, that is, turns all multipliers into shifters. Taking advantage of the wide parameter of the conservative system, the processing of the nonlinear function of the chaotic system is optimized into a combination of data selector, shifter and adder. In the entire FPGA algorithm design, no multiplier is used, which saves resources to a great extent.

[0039] (3) New method for iterative output calculation of chaotic system: It effectively improves the rate of random number generation in FPGA. Based on the original fourth-order Runge-Kutta method RK4, a new fourth-order K-value method N-K4 is proposed, which shortens the timing implementation of FPGA by 3 clock cycles compared with RK4, and is more conducive to the generation of high-speed random numbers.

[0040] (4) Parallel pipeline structure (generating a batch of random numbers using only one clock): Abandoning the idea of ​​serial operation, the parallel pipeline digital circuit structure of FPGA is used, combined with the characteristic that the four-dimensional conservative chaotic system has a strong initial value sensitivity, to realize the system output value iterating once per clock cycle and generating a batch of random bits.

[0041] (5) New post-processing method: In order to enhance the randomness of random numbers and improve throughput, this invention creates a new post-processing method, which transforms the original four-dimensional random bit number output per iteration into a six-dimensional random bit number output per iteration, with each dimension outputting 30 bits, that is, 180 bits of random number can be output in one clock cycle. The FPGA model used in this design is Xilinx Kintex-7 series xc7k325tffg900-2, and the clock frequency used is 106MHz. Finally, the throughput of random numbers generated by this invention is 19Gbps. The random numbers generated by this invention can pass all randomness statistical tests of the current mainstream random number test suites NIST SP800-22 and TestU01. Attached Figure Description

[0042] Figure 1 This is a structural framework diagram of the present invention;

[0043] Figure 2 This is a logic circuit diagram of the computational unit of the four-dimensional conservative chaotic system of the present invention;

[0044] Figure 3 This is a logic circuit diagram of the iteration unit in the N-K4 iteration module of the present invention;

[0045] Figure 4 This is the two-dimensional phase diagram output by the N-K4 method in an FPGA for a four-dimensional conservative chaotic system in this invention.

[0046] Figure 5 This is a framework diagram of the post-processing module of the present invention;

[0047] Figure 6 Timing diagram for iteration unit N-K4;

[0048] Figure 7 The timing diagram for the existing classic fourth-order Runge-Kutta method RK4;

[0049] Figure 8 This is a schematic diagram of the parallel pipeline structure of the iterative unit in this invention.

[0050] Figure 9 This is a timing diagram of the parallel pipeline structure for iterative units;

[0051] Figure 10 A diagram showing the number of bits distributed for fixed-point arithmetic operations;

[0052] Figure 11 A four-dimensional random number plot generated by a Matlab simulation;

[0053] Figure 12 A four-dimensional random number graph generated from a simulation of the Vivado chaos algorithm;

[0054] Figure 13 To verify the real random number plot observed by ILA on the FPGA board;

[0055] Figure 14 A diagram illustrating the bit-by-bit conversion of decimal numbers using mod2;

[0056] Figure 15 This is a diagram showing the resource usage on the FPGA side.

[0057] Figure 16 The image shows the test results of NIST random numbers with a capacity of 100Mb.

[0058] Figure 17 Tested with 1000Mb NIST random numbers;

[0059] Figure 18 The image shows the test results for TestU01.

[0060] Figure 19 Lyapunov index (LE) plot;

[0061] Figure 20 The distribution of the eigenvalues ​​λ of the equilibrium points R1, R2, and R3 in the complex plane;

[0062] Figure 21 All two-dimensional planar phase diagrams obtained from the simulation of the four-dimensional conservative chaotic system equations;

[0063] Figure 22 All three-dimensional planar phase diagrams obtained from the simulation of the four-dimensional conservative chaotic system equations;

[0064] Figure 23 A comparison chart of waveforms with different initial values ​​selected for the four dimensions x, y, z, and u;

[0065] Figure 24 A comparison of the waveforms in the x-dimensional and y-dimensional dimensions after 500,000 iterations;

[0066] Figure 25 For the histograms of numerical distributions in the x and y dimensions;

[0067] Figure 26 This is a bifurcation diagram and LE diagram of a chaotic system as parameters change. Detailed Implementation

[0068] The present invention will be described in detail below with reference to embodiments:

[0069] First, this invention proposes a four-dimensional conservative chaotic system equation formula as follows:

[0070]

[0071] Where (x, y, z, u) are the state variables of the system, and g(z) is a piecewise linear function, the formula of which is as follows:

[0072] g(z)=1.25*(∣z-1∣-∣z+1∣);

[0073] The software simulation platform used is Matlab 2021b. Initially, a fourth-order Runge-Kutta method was employed, with a step size of 1 / 64 selected to calculate the ordinary differential equations. The step size h determines the resolution and accuracy of the calculation results. Smaller step sizes provide greater resolution and higher accuracy, but also increase computational load and system runtime.

[0074] The following analysis examines the dynamic characteristics of a four-dimensional conservative chaotic system based on its equations:

[0075] The Lyapunov exponent (LE) can characterize the motion of a system. The maximum LE determines the speed of the entire attractor, while the minimum LE determines the speed of orbital convergence. The sum of all LEs can roughly characterize the speed of average orbital divergence or convergence. The formula for calculating LE is as follows:

[0076]

[0077] The initial values ​​of the four dimensions of the system are set to (1, 1, 1, 1). The formulas yield LE1 = 0.6708, LE2 = 0.0079, LE3 = -0.0072, and LE4 = -0.6714. The LE graph is shown below. Figure 19 As shown, from Figure 19 It can be seen that there is a state with a significantly greater than 0 LE in x-dimensional space. A positive LE means that in the phase space of the system, no matter how small the initial distance between the two trajectories is, their difference will increase exponentially with time, eventually reaching an unpredictable state of motion. Therefore, it can be determined that the system has entered a chaotic state of motion.

[0078] The rate of increase or decrease in the volume of the phase space system is characterized by the following formula:

[0079]

[0080] From this formula, we can derive...

[0081]

[0082] It can be proven that the changes in this system are bounded, when It is obvious that when the value is less than 0, the system's spatial volume is continuously decreasing, indicating a dissipative nature, while the equations of a four-dimensional conservative chaotic system... The value is very close to 0, indicating that the growth rate and decrease rate of the phase space volume in the four-dimensional conservative chaotic system equation are both 0. It is neither a dissipative nor a growing type, but a conservative chaotic system.

[0083] Stability analysis of the system's equilibrium point:

[0084] When performing equilibrium point analysis on a mathematical system model with differentials, all differential terms in the system equations need to be set to 0. At this point, the system's velocity is 0, and the equilibrium state equation of the system can be obtained as follows:

[0085]

[0086] Solving this system of equations yields three real equilibrium points: R1 = (0,0,1.25,0), R2 = (0,0,0,0), and R3 = (0,0,-1.25,0). The Jacobian matrix of this system is:

[0087]

[0088] Linearizing the equations of the four-dimensional conservative chaotic system at the equilibrium point R1, the corresponding Jacobi matrix is:

[0089]

[0090] Linearizing the equations of the four-dimensional conservative chaotic system at the equilibrium point R2, the corresponding Jacobi matrix is:

[0091]

[0092] Linearizing the equations of the four-dimensional conservative chaotic system at the equilibrium point R3, the corresponding Jacobi matrix is:

[0093]

[0094] The traditional methods for finding eigenvalues ​​and eigenvectors are as follows:

[0095]

[0096] Since the Jscobi matrices of R1 and R3 are the same, substituting formula (1) into the eigenvalue formula (4), we can obtain the four eigenvalues ​​corresponding to the equilibrium points R1 and R3 as (8.6139i, -8.6139i, 3.7149i, -3.7149i). Substituting formula (2) into the eigenvalue formula (4), we can obtain the four eigenvalues ​​corresponding to the equilibrium point R2 as (-3.5345, 4.5269i, -4.5269i, 3.5345). Their complex plane diagrams can be drawn as follows. Figure 20 As shown, from Figure 20It can be seen that the eigenvalues ​​of equilibrium point R2 are two purely imaginary numbers and two purely real numbers, one positive and one negative. Therefore, it can be determined that equilibrium point R2 has one unstable eigenvalue (positive real number) and eigenvector, and one stable eigenvalue (negative real number) and eigenvector. The solution trajectory in the phase plane will have a divergent and a convergent trend, and this equilibrium point is called a saddle point. The eigenvalues ​​of equilibrium points R1 and R3 are both distributed on the imaginary axis, with a real part of 0. Therefore, the solution trajectory of the system will be a circle centered at the origin. Thus, it can be determined that these two equilibrium points are central equilibrium points of the system, further proving that the phase space motion of the four-dimensional conservative chaotic system equations has neither dissipation nor an increasing trend. This characteristic mostly exists in conservative systems. Table 1 can be summarized from the above calculation results and explanations.

[0097] Table 1 shows the stability analysis of the system equilibrium point.

[0098]

[0099] Phase diagram analysis of the system

[0100] In the experiment of drawing phase diagrams, the parameter step size h of the four-dimensional conservative chaotic system equations was chosen to be 1 / 64, and the initial value of the system was set to (1, 1, 1, 1). All the two-dimensional planar phase diagrams obtained from the simulation of the four-dimensional conservative chaotic system equations are as follows: Figure 21 As shown, all three-dimensional plane phase diagrams of the equations for a four-dimensional conservative chaotic system are as follows: Figure 22 As shown, from Figure 21 to Figure 22 It can be seen that the equations of the four-dimensional conservative chaotic system are significantly different from those of ordinary continuous dissipative chaotic systems or hyperchaotic continuous dissipative systems. This system lacks a significant chaotic attractor and traverses most coordinate points within a given volume of motion space. Compared to ordinary continuous chaotic systems and four-dimensional or five-dimensional hyperchaotic systems, the four-dimensional continuous conservative chaotic system exhibits a more uniform shape. Its phase diagram does not show the common sparse-inside-dense-outside distribution found in the former. The three-dimensional phase diagrams of the four-dimensional conservative chaotic system equations are mostly spherical or ellipsoidal in shape, indicating that the numerical distribution within the chaotic space is uniform and the system makes excellent use of space. This lays a solid foundation for the strong randomness of this random number generator.

[0101] Initial value sensitivity analysis of the system

[0102] Initial value sensitivity is one of the most important characteristics of chaotic systems. It refers to the ability of even small changes in parameters across different dimensions under initial conditions to trigger a large, long-term chain reaction in the entire system, potentially deviating entirely from the original trend, such as the butterfly effect. This paper analyzes the initial value sensitivity of a four-dimensional conservative chaotic system. The first initial value (x0, y0, z0, u0) is set to (1, 1, 1, 1). To maximize the initial value sensitivity, the second initial value is set to a very small change (one ten-thousandth), specifically altering the x-axis. The second initial value is set to (x0, y0, z0, u0) as (1.0001, 1, 1, 1), with a step size h of 1 / 64. Waveforms with different initial values ​​in the x, y, z, and u dimensions are compared. Figure 23 As shown, from Figure 23 It can be seen that with the initial value remaining constant in other dimensions, only a one ten-thousandth change occurs in the x-dimensional dimension. After t=10, the numerical waveforms of the system show increasingly larger differences. The number of iterations of the system is t / h, therefore, it can be known that after 640 iterations, the waveforms of the system's four dimensions changing with time have already shown significant differences.

[0103] To obtain more information about the initial value sensitivity of the four-dimensional conservative chaotic system equations, the number of iterations was increased sufficiently to observe changes in the trajectory. The waveforms of the x-dimensional and y-dimensional systems after 500,000 iterations under the aforementioned initial conditions are compared below. Figure 24 As shown, from Figure 24 It can be seen that after 500,000 iterations, the waveforms in the y-dimensional and z-dimensional dimensions show almost no correlation. This experiment demonstrates that even if the initial value in one direction changes by one ten-thousandth, as long as the number of iterations is sufficient, the original chaotic system will transform into two uncorrelated systems. This proves that the four-dimensional conservative chaotic system equations have good initial value sensitivity.

[0104] Spatial ergodicity analysis of the system

[0105] The phase diagram macroscopically shows that the four-dimensional conservative chaotic system equations have good space utilization. To more intuitively analyze the spatial ergodicity of the system, the system parameter step size h was selected as 1 / 64, and the total time length was 1000. That is, after 64,000 system iterations, the numerical distribution of each dimension was analyzed. The above system was calculated using Matlab 2021b software, and the numerical statistics of partitioning according to the boundaries of each dimension are shown in Tables 2 to 4.

[0106] Table 2. Statistical table of numerical distribution in x and y dimensions

[0107]

[0108] Table 3. Statistical table of z-dimensional numerical distribution

[0109]

[0110] Table 4. Statistical table of u-dimensional numerical distribution

[0111]

[0112] Based on the statistical distribution of values ​​for each dimension in Tables 2 to 4, a histogram can be drawn, such as... Figure 25 As shown in the histograms of the numerical distribution of the system in the four dimensions, the four-dimensional conservative chaotic system equations do not exhibit the typical pattern of large values ​​at both ends and small values ​​in the middle, unlike classical continuous chaotic systems such as Lorenz. The numerical distribution of the four-dimensional conservative chaotic system equations is relatively uniform across all dimensions. Figure 25 It can be seen that the numerical distribution of the system in the histogram statistics of the y-dimensional and z-dimensional dimensions is very uniform. In the distribution of numerical intervals in the x-dimensional and u-dimensional dimensions, there is no case where the total number of one interval is greater than a positive integer multiple of the total number of another interval. This proves that the spatial ergodicity of the four-dimensional conservative chaotic system equation is superior to that of other continuous chaotic systems.

[0113] Bifurcation diagram and LE spectrum analysis of the system as parameters change

[0114] The bifurcation diagram and LE plot drawn by the changes in the three parameters b, d, and e are as follows: Figure 26 As shown, from Figure 26 It can be seen that the changes in the LE diagram and the bifurcation diagram are consistent. No two line segments in the LE diagram show a significant value greater than 0, indicating that the system has not entered a hyperchaotic state, proving that the system is a conservative system. Because the newly established four-dimensional conservative chaotic system has strong initial value sensitivity and large spatial ergodicity, it can be used to implement a random number generator.

[0115] High-speed random number generator based on conservative chaotic systems (such as...) Figure 1 As shown in the figure, it is implemented using FPGA hardware. The relevant modules are configured on the FPGA, specifically including:

[0116] The input module is used for inputting initial values;

[0117] The N-K4 iteration module includes a four-dimensional conservative chaotic system computation unit and an iteration unit. Specifically, the four-dimensional conservative chaotic system computation unit is used to calculate the four-dimensional value from the initial value input by the input module using the fourth-order K-value method. The four-dimensional conservative chaotic system computation unit specifically includes (e.g.) Figure 2As shown in the figure: x input register a1, y input register a2, z input register a3, and u input register a4. The x input register a1 is respectively connected to a first shifter b1 and a first inverter c1. The first shifter b1 is connected to a ∂y output register d1. The first shifter b1 can perform a left shift operation of 2 bits. The first inverter c1 is connected to a first adder e1. The first adder e1 can perform an addition operation of 1. The first adder e1 is connected to a second shifter b2. The second shifter b2 can perform a left shift operation of 3 bits. The second shifter b2 is connected to a second adder e2. The second adder e2 is connected to a ∂u output register d2;

[0118] The y input register a2 is connected to a second inverter c2. The second inverter c2 is connected to a third adder e3. The third adder e3 can perform an addition operation of 1. The third adder e3 is connected to a third shifter b3. The third shifter b3 can perform a left shift operation of 2 bits. The third shifter b3 is connected to a fourth adder e4. The fourth adder e4 is connected to a ∂x output register d3;

[0119] The z input register a3 is respectively connected to a fourth shifter b4, a fifth shifter b5, and a third inverter c3. The fourth shifter b4 is connected to a fifth adder e5. The fifth adder e5 can perform an addition operation of 20. The fifth adder e5 is connected to a sixth shifter b6. The sixth shifter b6 is connected to a three - way selector f. The three - way selector f is connected to the second adder e2. The fifth shifter b5 is connected to a sixth adder e6. The sixth adder e6 can perform an addition operation of - 20. The sixth adder e6 is connected to the three - way selector f. The third inverter c3 is connected to a seventh adder e7. The seventh adder e7 can perform an addition operation of 1. The seventh adder e7 is connected to a seventh shifter b7. The seventh shifter b7 is connected to the three - way selector f;

[0120] The u input register a4 is connected to the fourth adder e4. The u input register a4 is also connected to a fourth inverter c4. The fourth inverter c4 is connected to an eighth adder e8. The eighth adder e8 can perform an addition operation of 1. The eighth adder e8 is connected to an eighth shifter b8. The eighth shifter b8 is connected to a ∂z output register d4.

[0121] The logical operation rule of the three - way selector f is that when z > 1, it outputs 16*z - 20; when - 1 < z < 1, it outputs - 4z; when z < - 1, it outputs 16*z + 20.

[0122] Compared with the existing conventional circuits, the logic circuit of the four - dimensional conservative chaotic computing unit of the present invention uses shifters instead of multipliers, reducing the multiplier resources to zero. Instead, shifters and inversion operations are used, greatly reducing the utilization rate of the resources within the FPGA board.

[0123] The four-dimensional conservative chaotic system equations proposed in this invention can be realized through the above logic circuit:

[0124]

[0125] This equation enables the calculation of various numerical values ​​(k1, k2, k3, k4) in four dimensions using the fourth-order K-value method.

[0126] The iteration unit is used to iterate over four-dimensional values. Specifically, the logic circuit of the iteration unit is as follows: Figure 3 As shown in the diagram, the Timing Control Unit is a state machine with only two states. State T0 controls the output values ​​of k1, k2, k3, and k4, occupying 16 registers, denoted as (xk1, xk2, xk3, xk4), (yk1, yk2, yk3, yk4), (zk1, zk2, zk3, zk4), and (uk1, uk2, uk3, uk4). State T1 controls the output values ​​of the four dimensions of Sn, occupying 4 registers, namely (xk1, xk2, xk3, xk4), (yk1, yk2, yk3, yk4), (zk1, zk2, zk3, zk4), and (uk1, uk2, uk3, uk4). n y n , z n u n The following iterative formula can be implemented using this combinational logic circuit:

[0127]

[0128] In the formula

[0129] ;

[0130] from Figure 3 It can be seen that a multiplier is used to multiply h in the iterative unit. 2 In this embodiment, the value of h is 1 / 64, so the multiplier can be replaced by a shifter (<<12). That is, the combinational logic circuit of the new fourth-order K-value method N-K4 does not use a multiplier, effectively saving resources.

[0131] This invention utilizes a Xilinx Kintex-7 FPGA, specifically the chip model xc7k325tffg900-2. The aforementioned sequential combinational logic circuit is implemented using Verilog. After successful onboard program download, the system begins execution. The value of Sn for each system iteration is output to a text file (.txt) on the computer via serial port. After 20,000 iterations, Matlab 2021b software reads the text document. The Matlab program iterates through the text data and places it into a matrix consisting of four dimensions (x, y, z, u), i.e., four columns and n rows (n=20000). Then, the data in each column is paired and plotted as a phase diagram from top to bottom. This yields all the two-dimensional phase diagrams of the FPGA-implemented four-dimensional conservative chaotic system. The FPGA uses the N-K4 method to implement the various two-dimensional phase diagrams plotted for the four-dimensional conservative chaotic calculation, as shown below. Figure 4 As shown in the figure, the phase diagram of the system implemented by N-K4 is quite similar to that of the classic fourth-order Runge-Kutta method RK4. In the sequential logic implemented on FPGA, N-K4 can shorten the clock cycle by 3 clock cycles compared to RK4, which is more conducive to the invention of a faster random number generator. The above algorithm realizes the design of generating a batch of random bits in two clock cycles.

[0132] The post-processing module, to enhance the randomness of the generated random numbers, needs to post-process the values ​​of the four dimensions obtained by the N-K4 iteration of the chaotic system. The post-processing module can convert the iterated four-dimensional values ​​into six-dimensional random bits in binary form, with each dimension outputting 30 bits. The framework of the post-processing module is as follows: Figure 5 As shown, the post-processing module uses a Xilinx Kintex-7 series FPGA product, with the chip model being xc7k325tffg900-2, and the clock frequency is set to 106MHz.

[0133] This invention also provides a high-speed random number generation method based on a conservative chaotic system, employing the aforementioned high-speed random number generator based on a conservative chaotic system, and comprising the following steps:

[0134] (1) Input the initial value S0 through the input module. Specifically, S0 is (x0, y0, z0, u0) and transmit the initial value to the four-dimensional conservative chaotic calculation unit.

[0135] (2) The initial values ​​are substituted into the system differential equations through the chaos calculation module. Specifically, the differential equations are as follows:

[0136]

[0137] In the formula

[0138] g(z)=1.25*(∣z-1∣-∣z+1∣)

[0139] The values ​​F(S) of (k1, k2, k3, k4) in the four dimensions are calculated using the formula. n ), F(S n Specifically, (xk1, xk2, xk3, xk4), (yk1, yk2, yk3, yk4), (zk1, zk2, zk3, zk4), and (uk1, uk2, uk3, uk4).

[0140] (3) Iterate the four-dimensional values ​​according to the following formula to obtain the values ​​S of the four dimensions. n+1

[0141]

[0142] In the formula

[0143]

[0144] Then obtain S n+1 The four-dimensional numerical input is fed into the post-processing module and simultaneously fed back to the four-dimensional conservative chaotic calculation unit as the initial value for the next iteration.

[0145] As can be seen from the above formulas, the solution method for the new fourth-order K-value method N-K4 proposed in this invention, from k1 to k4, starts from S. n Modify the values ​​of each dimension and then substitute them into F(S) n The advantage of this is that (k1, k2, k3, k4) no longer have a correlation with preceding and following times; they are all only related to S. n Relatedly, the timing diagram of N-K4 can be drawn, as shown in the following figure. Figure 6 As shown, the new fourth-order K-value method N-K4 proposed in this invention requires only one clock cycle for each system iteration.

[0146] The existing classical fourth-order Runge-Kutta method RK4 calculation formula is as follows:

[0147]

[0148] In the formula

[0149]

[0150] The formula shows that k1, k2, k3, k4, and S n+1 The relationship exists (k1) k2 k3 k4 S nThe correlation between the preceding and following times can be used to draw a classic RK4 timing diagram (e.g.) Figure 7 As shown in the figure, by comparison, it can be seen that the present invention shortens the clock cycle by 3 clock cycles compared with the existing classic fourth-order Runge-Kutta method RK4.

[0151] The following describes how this invention shortens the iteration cycle of a chaotic system to only one clock cycle. When implementing the new fourth-order K-value method N-K4 using an FPGA, if a state machine is used, the state machine requires two states, i.e., two clock cycles, to iterate once, because (k1, k2, k3, k4) represents a total of 16 registers. Figure 3 The process only operates once in state T1, while data is retained in state T0, failing to save sufficient time. Therefore, this invention abandons the serial approach and discards the state machine timing structure in Verilog. Utilizing the parallel computing advantages unique to FPGAs, all registers are assigned values ​​and iterated once in each cycle without reducing the randomness of the random numbers. Since the initial value sensitivity of four-dimensional conservative chaotic systems is very high, different initial values ​​will result in two different systems. Therefore, this invention adopts a parallel pipeline structure in the iteration unit, such as... Figure 8 As shown in the figure, S is used. n Representative (x) n y n , z n u n Four registers, k1 represents (xk1, xk2, xk3, xk4), k2 represents (yk1, yk2, yk3, yk4), k3 represents (zk1, zk2, zk3, zk4), and k4 represents (uk1, uk2, uk3, uk4). n+1 Representative (x) n+1 y n+1 , z n+1 u n+1 Four registers, S0 and P0 are two different initial values ​​for the four-dimensional conservative chaotic system. Figure 8 The upper-middle line indicates that it is one clock cycle ahead of the lower-middle line. The first few clock cycles of the system are described as follows:

[0152] The first clock: S0 and P0 represent two different initial values ​​(1, 1, 1, 1) and (0.8, 0.4, 0.6, 0.9) respectively. The upper side line S0 of the first clock after the system reset ends is first input to the input terminal of the next layer N-K4.

[0153] Second clock: P0 is input to the input of the next layer N-K4 via the lower side line.

[0154] The third clock: Since N-K4 only needs two clock cycles to get the result of one iteration, S0, as the initial input, has already obtained the result S1 of the first iteration. Then, S1 is fed back to the input of N-K4 through the red line.

[0155] At the fourth clock cycle: P0 is used as the initial input to obtain the result P1 of the second iteration. P1 is then fed back to the input of N-K4 via the lower wire.

[0156] In the fifth clock cycle: S1, as the input of N-K4, has obtained the result S2 of the third iteration. S2 is then fed back to the input of N-K4 through the upper line, and so on for more clock cycles of subsequent system operation steps.

[0157] Based on the initial 5 clock cycles of the above system, the pipeline timing diagram can be derived as follows: Figure 9 As shown, from Figure 9 As can be seen, the 16 registers represented by (k1, k2, k3, k4) are processed and assigned values ​​every clock cycle, thus not wasting a single clock cycle. The previous clock cycle calculates the k value for the S system, and the next clock cycle continues to calculate the k value for the P system. The value of the register represented by Sn is also assigned once every clock cycle. The previous clock cycle calculates the output value of the S system, the next clock cycle calculates the output value of the P system, and so on. The above system design realizes a method to generate a random number once per clock cycle iteration.

[0158] Because there are no truly meaningful decimals in actual digital circuit structures, this invention uses signed fixed-point arithmetic, setting each value to 36 bits, with the distribution of positive and decimal numbers as follows: Figure 10 As shown in the figure, all numerical operations in the four-dimensional conservative chaotic system equations are performed with a bit width of 37 bits. Bits 0-29 are selected as decimals, bits 30-36 as integers, and the last bit 37 is used as the sign bit.

[0159] Generated using Matlab simulation (x) n y n , z n u n Four-dimensional random numbers, such as Figure 11 As shown, in Figure 11 In the image, the first column on the left (1, 2, 3, 4) represents (x... n y n , z n u nThe data is as follows: the second column represents the values ​​of the four dimensions of S0, the third column represents the values ​​of the four dimensions of P0, the fourth column represents the values ​​of the four dimensions of S1, the fifth column represents the values ​​of the four dimensions of P1, and so on. Through Matlab software simulation, this invention has initially realized the parallel pipeline structure at the software simulation level.

[0160] Implement the algorithm for chaotic systems and parallel pipelines using Verilog, and run the testbench file on Vivado 2018.3 software to obtain (x n y n , z n u n Four-dimensional random numbers, such as Figure 12 As shown in the figure, lb_clk is the master clock set in the testbench file. FPGA software simulation demonstrates that a parallel pipeline structure that outputs a random number once per clock iteration has been implemented in the FPGA program. The Verilog program for the designed pipeline structure of the four-dimensional conservative chaotic system is generated into bitstreams, downloaded to the FPGA development board, connected to a computer, and verified on the FPGA board using the ILA (Integrated Logic Analyzer). The actual data displayed by the ILA trigger is as follows... Figure 13 As shown, in Figure 11 to Figure 13 In this case, because the lower 30 bits of the data in the fixed-point arithmetic operations on the FPGA development board are decimals, the entire value is magnified by a factor of 2^30 compared to the ideal data. To facilitate comparison with Matlab simulation data, Figure 10 The Matlab simulation data in the figure is magnified by 2^30 times. The actual ILA running state on the board shows that the new parallel pipeline structure truly achieves the goal of generating a batch of random numbers in one clock iteration. In other words, this invention, from Matlab chaotic algorithm simulation to FPGA simulation and actual FPGA board ILA verification, demonstrates the four dimensions (x, y, z) of the system in the three figures. n y n , z n u n The output data of each iteration is exactly the same and there is no error, which proves that the present invention has completed the specific implementation of the four-dimensional conservative chaotic system from software simulation to hardware design.

[0161] (4) To enhance the randomness of the generated random numbers, it is necessary to post-process the values ​​of the four dimensions obtained by the N-K4 iteration of the chaotic system. To this end, a new post-processing method is proposed, which is carried out according to the following steps (in combination with...). Figure 5 (Detailed explanation follows)

[0162] a. Use the 37-bit number of each dimension of the four-dimensional chaotic system generated by N-K4 iteration as the input.

[0163] b. Extract the last 30 bits from each of the four 37-bit values.

[0164] c. Convert the input 30-bit number to decimal using the following formula.

[0165]

[0166] In the formula, i represents the binary digit of the current value. In basic mathematical principles, the value always carries from the least significant bit to the most significant bit. The higher the number of bits in the value, the greater the time correlation between the higher bits. Therefore, the higher 15 bits of the 30 bits are added to the corresponding lower bits, and then the number of bits is added. The lower 15 bits are added to the number of bits of the value itself. In this way, each bit number is converted into a decimal number, and each dimension produces a 30-bit decimal number.

[0167] d. Perform modulo 2 processing on each dimension of the 30-bit decimal random number (e.g., Figure 14 As shown in the figure, this converts the value of each dimension into 30 bits. The correlation between the value processed by mod2 and the original value has been reduced, and the output value can be directly used as a number of bits, saving computing resources.

[0168] e. In order to completely disrupt the correlation of values, an XOR method is adopted. The 30-bit numbers of the four dimensions x, y, z, u are XORed bit by bit in pairs, that is, x^y, x^z, x^u, y^z, y^u, z^u respectively. Using this method, a six-dimensional random number can be output in one clock cycle. Each dimension outputs a 30-bit number, so the six dimensions can output a 180-bit random number in one clock cycle.

[0169] This invention uses a Xilinx Kintex-7 series FPGA, specifically the XC7K325TFFG900-2 chip, with a clock frequency of 106MHz. The random number generator designed in this invention can output 180 bits per clock cycle, resulting in a random number generation throughput of 19080Mbps, or 19Gb / s. The FPGA resource usage is as follows: Figure 15 As shown, the estimated power consumption of this random number generator is 2.36W@19Gbps.

[0170] The most important metric for a random number generator is the randomness of the generated numbers. Currently, most tests use the NIST SP800-22 and the TestU01 test suite. Both of these test suites can test .txt or .bin files composed of bits. This invention inputs the random numbers generated on the FPGA board to a host computer via a serial port for testing. First, a 100Mb bit file is generated for NIST testing. The test results are as follows... Figure 16 As shown, in NIST's test report, P-VALUE displays the P-value, and PROPORTION displays the pass rate. If the P-VALUE value is greater than 0.01 and the PROPORTION is greater than 96%, the test is considered successful.

[0171] from Figure 16 It can also be seen that the P-VALUE values ​​of the 100Mb bit files output by this invention are all greater than 0.01 and the PROPORTION is greater than 960 / 1000, thus proving that the 100Mb bit files have passed the NIST test.

[0172] To verify the randomness of generating more random numbers, this invention uses an FPGA to output a 1000Mb bit file for testing. The test results are as follows: Figure 17 As shown, from Figure 17 As can be seen, the P-VALUE values ​​of the test results obtained when generating 1000Mb of bits are all greater than 0.01, and the pass rate PROPORTION is greater than 96%. Therefore, it can be proved that the random number generator has successfully passed the randomness statistics test of the NIST800.22 test suite.

[0173] The TestU01 test suite tests bit files in 32-bit units. Therefore, the number of bits output by the FPGA should be a multiple of 32. When 268,435,456 bits are output, the test result is as follows. Figure 18 As shown, from Figure 18 As can be seen, after a total test time of 125 seconds, all the random numbers in bit form generated by the random number generator of the present invention passed the randomness statistics test of Rabbit and Alphabit in the TestU01 test suite.

Claims

1. A high-speed random number generator based on conservative chaotic systems, characterized in that, Comprising: An input module for inputting initial values; An N-K4 iteration module, which includes a four-dimensional conservative chaotic system calculation unit and an iteration unit. The N-K4 iteration module is used to calculate four-dimensional values using the four-dimensional conservative chaotic system equation for the initial values input by the input module and perform iteration on the four-dimensional values. The four-dimensional conservative chaotic system calculation unit includes an x input register, a y input register, a z input register, and a u input register. Specifically; The x input register is respectively connected to a first shifter and a first inverter. The first shifter is connected to a ∂y output register. The first inverter is connected to a first adder, which can perform an add-1 operation. The first adder is connected to a second shifter, the second shifter is connected to a second adder, and the second adder is connected to a ∂u output register; The y input register is connected to a second inverter, the second inverter is connected to a third adder, which can perform an add-1 operation. The third adder is connected to a third shifter, the third shifter is connected to a fourth adder, and the fourth adder is connected to a ∂x output register; The z input register is respectively connected to a fourth shifter, a fifth shifter, and a third inverter. The fourth shifter is connected to a fifth adder, which can perform an add-20 operation. The fifth adder is connected to a sixth shifter, the sixth shifter is connected to a multiplexer, and the multiplexer is connected to the second adder. The fifth shifter is connected to a sixth adder, which can perform an add -20 operation, and the sixth adder is connected to the multiplexer. The third inverter is connected to a seventh adder, which can perform an add-1 operation. The seventh adder is connected to a seventh shifter, and the seventh shifter is connected to the multiplexer; The u input register is connected to the fourth adder, and the u input register is also connected to an eighth inverter. The eighth inverter is connected to an eighth adder, which can perform an add-1 operation. The eighth adder is connected to an eighth shifter, and the eighth shifter is connected to a ∂z output register; A post-processing module, which can convert the iterated four-dimensional values into six-dimensional random bit numbers in binary form, with 30 bits output for each dimension, and a total of 180 bits of random bit numbers are output.

2. The high-speed random number generator based on a conservative chaotic system according to claim 1, characterized in that, The logical operation rule of the multiplexer is to output 16*z - 20 when z > 1, output -4z when -1 < z < 1, and output 16*z + 20 when z < -1.

3. The high-speed random number generator based on a conservative chaotic system according to claim 1, characterized in that, The iteration unit is used to perform iteration on the four-dimensional values calculated by the four-dimensional conservative chaotic system equation.

4. The high-speed random number generator based on a conservative chaotic system according to claim 3, characterized in that, The iteration unit iterates once every clock cycle through a parallel pipelined operation structure.

5. A high-speed random number generation method based on conservative chaotic systems, employing the high-speed random number generator based on conservative chaotic systems as described in any one of claims 1-4, characterized in that, Including the following steps: (1) Input the initial values (x0, y0, z0, u0); (2) Substitute the initial values ​​into the four-dimensional conservative chaotic system equations, and calculate the four-dimensional values ​​of (k1, k2, k3, k4) in the fourth-order K-value method: (xk1, xk2, xk3, xk4), (yk1, yk2, yk3, yk4), (zk1, zk2, zk3, zk4), and (uk1, uk2, uk3, uk4). The four-dimensional conservative chaotic system equations are as follows: In the formula g(z)=1.25*(∣z-1∣-∣z+1∣); (3) Iterate the four-dimensional values ​​according to the following formula to obtain the values ​​S of the four dimensions. n+1 : In the formula ； (4) Iterate the S from the chaotic system n+1 The initial values ​​(x0, y0, z0, u0) are fed back into step (2) as initial values ​​and simultaneously applied to S. n+1 After post-processing, it is converted into a six-dimensional random bit number in binary form, with 30 bits output for each dimension, for a total of 180 random bits.

6. The high-speed random number generation method based on conservative chaotic systems according to claim 5, characterized in that, The post-processing in step (4) includes the following steps: a. Use the 37-bit number of each dimension of the four-dimensional chaotic system generated by the fourth-order K-value method as the input terminal; b. Extract the last 30 bits from each of the four 37-bit values ​​in step a; c. Convert the input 30-bit number to decimal using the following formula. In the formula, i represents the binary bits of the current value; d. Perform mod 2 processing on each dimension's 30-bit decimal random number to convert the value of each dimension into a 30-bit number; e. Using the XOR method, each of the 30 bits of the four dimensions x, y, z, u is XORed with each other bit by bit to achieve x^y, x^z, x^u, y^z, y^u, z^u respectively.

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