Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, wherein the array substrate comprises: a substrate; a first conductive layer, located at one side of the substrate, the first conductive layer comprising a first power line; a second conductive layer, located at a side of the first conductive layer away from the substrate, the second conductive layer comprising a first signal line, a second signal line and a second power line located between the first signal line and the second signal line, wherein the first power line, the first signal line, the second signal line and the second power line are all extended and formed along the second direction, and the first power line and the second power line are connected by via holes. In the present application, the first power line and the second power line are connected by via holes, which can increase the distribution area of ​​the power line, thereby reducing the resistance of the power line, improving the influence of insufficient driving voltage on the display panel, and thereby improving the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] Organic Light-Emitting Diode (OLED) is an active light-emitting device. Compared with the traditional liquid crystal display (LCD) display method, OLED display technology does not require a backlight and has the characteristic of self-luminescence. OLED uses a thinner organic material film layer and a glass substrate. When an electric current passes through, the organic material will emit light. Therefore, OLED display panels can significantly save electricity, can be made lighter and thinner, can withstand a wider range of temperature changes than LCD display panels, and have a larger viewing angle. OLED display panels are expected to become the next generation of flat-panel display technology after LCD, and are one of the most popular technologies in flat-panel display technology.

[0003] The OLED display panel includes an array substrate and a display substrate. The array substrate includes a power line and a pixel circuit. The power line sends a driving signal to the pixel circuit, which drives the display substrate to emit light. If the power line resistance is too large, the driving voltage will be insufficient, which will affect the display effect of the display panel. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel, aiming to improve the display effect of the display panel.

[0005] An embodiment of the first aspect of the present application provides an array substrate, comprising: a substrate; a first conductive layer, located on one side of the substrate, the first conductive layer comprising a first power line; a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a first signal line, a second signal line and a second power line located between the first signal line and the second signal line, wherein the first power line, the first signal line, the second signal line and the second power line are all extended and formed along the second direction, and the first power line and the second power line are connected by vias.

[0006] According to an implementation of the first aspect of the present application, the second power line includes a plurality of power blocks spaced apart along the second direction and a connecting line connected between two adjacent power blocks, wherein the width of the connecting line in the first direction is smaller than the width of the power block in the first direction.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the second conductive layer further includes:

[0008] A first connecting portion connected to the first signal line and located between the first signal line and the second signal line;

[0009] A second connection portion connected to the second signal line and located between the first signal line and the second signal line;

[0010] Among the two connecting lines located on both sides of the same power block in the second direction and connected thereto, one is a first connecting line and the other is a second connecting line. The first connecting line is extended between the first connecting portion and the second signal line, and the second connecting line is extended between the second connecting portion and the first signal line.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the first connecting line is connected to a side of the power block facing the second signal line, and the second connecting line is connected to a side of the power block facing the first signal line.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the plurality of second power lines are spaced apart along the first direction, the power block of at least one second power line includes a functional block and an auxiliary block, the connection line of the second power line further includes a third connection line, the auxiliary block and the functional block are spaced apart in the second direction and connected to each other through the third connection line, and a first via portion is provided between the auxiliary block and the functional block;

[0013] The array substrate also includes a third conductive layer and a fourth conductive layer, which are arranged on both sides of the second conductive layer. The third conductive layer includes a third signal line, and the fourth conductive layer includes a pixel electrode, which is connected to the third signal line through a first via portion.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, of the two second power lines adjacent to each other along the first direction, one is a first sub-power line, and the other is a second sub-power line, the first sub-power line includes a functional block but does not include an auxiliary block, the second sub-power line includes a functional block and an auxiliary block, a second via portion is provided between the power block of the first sub-power line and the first connecting portion and / or the second connecting portion, and the pixel electrode is interconnected with the third signal line through the second via portion.

[0015] According to any of the aforementioned implementations of the first aspect of the present application, further comprising:

[0016] The fourth conductive layer is located on the side of the second conductive layer away from the substrate. The fourth conductive layer includes a pixel electrode. The orthographic projection of the pixel electrode along the thickness direction of the array substrate at least partially overlaps with the orthographic projection of the second power line along the thickness direction.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of each power block along the thickness direction at least partially overlaps with the orthographic projection of each pixel electrode along the thickness direction.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the power block along the thickness direction is arranged symmetrically with respect to the center of the orthographic projection of the pixel electrode along the thickness direction.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the power block along the thickness direction is located within the orthographic projection of the pixel electrode along the thickness direction.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, the areas of at least two pixel electrodes are different, the areas of at least two power blocks are different, and the area of ​​a power block is positively correlated with the area of ​​the corresponding pixel electrode.

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate.

[0022] According to any of the aforementioned implementations of the first aspect of the present application, the array substrate further comprises a plurality of pixel circuits disposed on one side of the substrate, and the plurality of pixel circuits are arranged in a row along the second direction;

[0023] The first signal line is a first data line, the second signal line is a second data line, and the first data line and the second data line are used to provide data signals to a plurality of pixel circuits in the same column arranged along the second direction.

[0024] According to any of the aforementioned embodiments of the first aspect of the present application, in two adjacent pixel circuits in the second direction, the data signal of one pixel circuit is provided by the first data line, and the data signal of the other pixel circuit is provided by the second data line.

[0025] An embodiment of a second aspect of the present application provides a display panel, comprising an array substrate of any one of the above-mentioned embodiments of the first aspect.

[0026] In the array substrate provided in the embodiment of the present application, the array substrate includes a substrate and a first conductive layer and a second conductive layer arranged on the substrate, a first power line is arranged in the first conductive layer, a first signal line, a second signal line and a second power line located between the first signal line and the second signal line are arranged in the second conductive layer, and the first power line and the second power line are connected by via holes, which can increase the distribution area of ​​the power line, thereby reducing the resistance of the power line, improving the influence of insufficient driving voltage on the display panel, and thereby improving the display effect of the display panel. In addition, the second conductive layer is also provided with the first signal line and the second signal line arranged side by side with the second power line along the first direction, which can enrich the function of the second conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0028] Figure 1 is a top view of an array substrate provided by an embodiment of the present application;

[0029] Figure 2 yes Figure 1 A partial cross-sectional view of

[0030] Figure 3 is a top view of an array substrate provided in another embodiment of the present application;

[0031] Figure 4 This is a schematic diagram of a pixel circuit structure of an array substrate provided by an embodiment of the present application;

[0032] Figure 5 yes Figure 1 Schematic diagram of the local enlarged structure.

[0033] Description of reference numerals:

[0034] 01. Substrate;

[0035] 02, first conductive layer; 210, first power line;

[0036] 03, second conductive layer; 310, first signal line; 320, second signal line; 330, second power line; 330a, first sub-power line; 330b, second sub-power line; 331, power block; 331a, functional block; 331b, auxiliary block; 332, connection line; 332a, first connection line; 332b, second connection line; 332c, third connection line; 340, first connection part; 350, second connection part; 360, first via part; 370, second via part;

[0037] 04, third conductive layer; 410, third signal line;

[0038] 05, fourth conductive layer; 510, pixel electrode;

[0039] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0040] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0041] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0042] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0043] The embodiments of the present application provide an array substrate and a method for manufacturing the same. The embodiments of the array substrate and the method for manufacturing the same are described below in conjunction with the accompanying drawings.

[0044] An embodiment of the present application provides an array substrate, which can be used for a display panel. The display panel can be an organic light emitting diode (OLED) display panel.

[0045] See also Figure 1 and Figure 2 , Figure 1 A top view of a partial layer structure of an array substrate provided by an embodiment of the present application is shown. Figure 2 yes Figure 1 A partial cross-sectional view of .

[0046] like Figure 1 and Figure 2 As shown, an embodiment of the first aspect of the present application provides an array substrate, the array substrate comprising a substrate 01, a first conductive layer 02 and a second conductive layer 03; the first conductive layer 02 is located on one side of the substrate 01, and the first conductive layer 02 comprises a first power line 210; the second conductive layer 03 is located on the side of the first conductive layer 02 away from the substrate 01, and the second conductive layer 03 comprises a first signal line 310, a second signal line 320 arranged at intervals along a first direction X, and a second power line 330 located between the first signal line 310 and the second signal line 320, wherein the first power line 210, the first signal line 310, the second signal line 320 and the second power line 330 are all extended and formed along the second direction Y, and the first power line 210 and the second power line 330 are connected by vias.

[0047] In the array substrate provided in the embodiment of the present application, the array substrate includes a substrate 01 and a first conductive layer 02 and a second conductive layer 03 arranged on the substrate 01, a first power line 210 is arranged in the first conductive layer 02, a first signal line 310, a second signal line 320 and a second power line 330 located between the first signal line 310 and the second signal line 320 are arranged in the second conductive layer 03, and the first power line 210 and the second power line 330 are connected by via holes, which can increase the distribution area of ​​the power line, thereby reducing the resistance of the power line, improving the influence of insufficient driving voltage on the display panel, and thereby improving the display effect of the display panel. In addition, the second conductive layer 03 is also provided with the first signal line 310 and the second signal line 320 arranged side by side with the second power line 330 along the first direction X, which can enrich the function of the second conductive layer 03.

[0048] Please also read Figures 1 to 3 , Figure 3 is an enlarged structural schematic diagram of an array substrate provided in another embodiment of the present application, Figure 3 and Figure 1 The difference is that a conductive layer including a pixel electrode 510 is added to the array substrate.

[0049] Optionally, the display panel includes an array substrate and a light emitting layer on the array substrate, the light emitting layer includes a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer and an electron injection layer stacked in sequence. The pixel electrode 510 may be an anode or a cathode.

[0050] The second power line 330 is located between the first signal line 310 and the second signal line 320. The orthographic projection of the second power line 330 along the thickness direction Z of the array substrate overlaps with the orthographic projection of the pixel electrode 510 located thereon along the thickness direction Z of the array substrate. Therefore, the shape of the second power line 330 can be adjusted to improve the flatness of the pixel electrode 510, thereby improving the color deviation problem caused by the pixel electrode 510 reflecting the light emitted by the light-emitting layer in all directions, thereby better improving the display effect of the display panel.

[0051] Optionally, an insulating layer is provided between the first conductive layer 02 and the second conductive layer 03 to avoid short circuit connection between the first conductive layer 02 and the second conductive layer 03. In the embodiment of the present application, an insulating layer is provided between two adjacent conductive layers to avoid short circuit connection, which will not be repeated here.

[0052] The substrate 01 may be a flexible substrate or a rigid substrate. For example, the material of the substrate 01 may include a flexible material such as polyimide, or the material of the substrate 01 may include a rigid material such as glass. Other film layers may be provided between the first conductive layer 02 and the substrate 01, as long as the first conductive layer 02 is located on one side of the substrate 01. The material of the first conductive layer 02 may include a metal material, so that the first power line 210 has good electrical conductivity. The material of the second conductive layer 03 may include a metal material, so that the first signal line 310, the second signal line 320, and the second power line 330 have good electrical conductivity.

[0053] There are many ways to set the first signal line 310 and the second signal line 320. In some optional embodiments, the first signal line 310 is a first data line, and the second signal line 320 is a second data line. The array substrate also includes a plurality of pixel circuits arranged on one side of the substrate 01, and the plurality of pixel circuits are arranged in columns along the second direction Y. The first data line and the second data line are used to provide data signals to the plurality of pixel circuits arranged in the same column along the second direction Y.

[0054] like Figure 4 As shown, the data line data is used to send a data signal to the pixel circuit. In an optional specific embodiment, in two adjacent pixel circuits in the same column, the data signal of one pixel circuit is provided by the first data line, and the data signal of the other pixel circuit is provided by the second data line. Then, the number of pixel circuits that need to be driven by the same data line is reduced, which can reduce the transmission time of the data signal on the data signal line, reduce the delay, and increase the power supply time of a single sub-pixel.

[0055] In these optional embodiments, a plurality of pixel circuits in the same column may transmit data signals via two data lines, namely a first data line and a second data line, which can extend the charging time of a single pixel circuit and improve the display effect of the display panel.

[0056] In some optional embodiments, the array substrate further includes a fourth conductive layer 05 , the fourth conductive layer 05 is located on a side of the second conductive layer 03 facing away from the substrate 01 , and the fourth conductive layer 05 includes a pixel electrode 510 .

[0057] The first data line and the second data line correspond to the same column of pixel circuits, so the first data line and the second data line can correspond to the same column of pixel electrodes 510, and the orthographic projection of the second power line 330 located between the first data line and the second data line along the thickness direction Z is at least partially overlapped with the orthographic projection of the pixel electrode 510 along the thickness direction Z. The distribution of the second power line 330 affects the surface shape of the insulating layer located thereon, and further affects the flatness of the pixel electrode 510. Therefore, by reasonably setting the distribution of the second power line 330, the flatness of the pixel electrode 510 can be improved, which is conducive to improving the display effect. For example, improving the flatness of the pixel electrode 510 can improve the display effect of the display panel caused by excessive dispersion of light emitted by the reflective light-emitting layer of the pixel electrode 510 due to the unevenness of the pixel electrode 510.

[0058] In these optional embodiments, the distance between the second conductive layer 03 and the fourth conductive layer 05 is closer. For example, when the pixel electrode 510 is continuously prepared after the insulating layer is prepared on the second conductive layer 03, the flatness of the second conductive layer 03 toward the surface of the insulating layer will affect the flatness of the surface of the pixel electrode 510 on the insulating layer, and the distribution of the first signal line 310, the second signal line 320 and the second power line 330 will also affect the flatness of the surface of the insulating layer, thereby causing the distribution of the first signal line 310, the second signal line 320 and the second power line 330 to indirectly affect the flatness of the pixel electrode 510. The orthographic projections of the pixel electrode 510 and the second power line 330 are at least partially overlapped, so that the second power line 330 can improve the problem of uneven pixel electrode 510.

[0059] In addition, by arranging the first signal line 310 and the second signal line 320 in a conductive layer closer to the pixel electrode 510, the distance between the first signal line 310 and the second signal line 320 and other signal lines in the array substrate along the thickness direction Z can be increased, and the parasitic circuit generated by the overlap of the first signal line 310 and the second signal line 320 with other signal lines can be reduced, thereby ensuring the stability of signal transmission.

[0060] There are many ways to arrange the second power lines 330. Optionally, the second power lines 330 may extend along the second direction Y and be arranged with equal width.

[0061] In some other optional embodiments, such as Figure 3As shown, the second power line 330 includes a plurality of power blocks 331 spaced apart along the second direction Y and a connecting line 332 connected between two adjacent power blocks 331, wherein the extension width of the connecting line 332 in the first direction X is smaller than the width of the power block 331 in the first direction X.

[0062] In these optional embodiments, the second power line 330 includes a power block 331 and a connecting line 332. The power block 331 is relatively wide, which can increase the distribution area of ​​the second power line 330, reduce the resistance of the second power line 330, and thereby increase the driving voltage, thereby improving the display effect of the display panel.

[0063] In addition, by properly setting the positions of the power block 331 and the connection line 332, the orthographic projection of the power block 331 along the thickness direction Z of the array substrate can overlap with the orthographic projection of the pixel electrode 510 along the thickness direction Z of the array substrate. Since the orthographic projection area of ​​the power block 331 along the thickness direction Z of the array substrate is large, the overlapping area of ​​the orthographic projection of the power block 331 along the thickness direction Z and the orthographic projection of the pixel electrode 510 along the thickness direction Z can be increased. By properly setting the shape of the power block 331, the flatness of the pixel electrode 510 can be indirectly affected, thereby better improving the problem of uneven pixel electrode 510. By properly setting the position of the connection line 332, the problem of short circuit connection between the second power line 330 and the first signal line 310 and the second signal line 320 can also be improved.

[0064] There are many ways to set the shape of the power block 331. The orthographic projection of the power block 331 on the substrate 01 can be circular, semicircular, polygonal or irregular. Optionally, the orthographic projection of the power block 331 on the substrate 01 is a quadrilateral such as a rectangle, square, or rhombus. The shape of the orthographic projection of the power block 331 on the substrate 01 is not limited here, and can be set according to actual needs.

[0065] When the second power line 330 includes a connection line 332 and a power block 331 , an orthographic projection of the connection line 332 and / or the power block 331 along the thickness direction Z at least partially overlaps an orthographic projection of the pixel electrode 510 along the thickness direction Z.

[0066] Optionally, the orthographic projection of each power block 331 along the thickness direction Z at least partially overlaps with the orthographic projection of each pixel electrode 510 along the thickness direction Z. The distribution area of ​​the power block 331 is larger, and the overlap of the power block 331 and the pixel electrode 510 can better improve the unevenness of the pixel electrode 510.

[0067] Optionally, the orthographic projection of the power block 331 along the thickness direction Z is centrally symmetrically arranged about the center of the orthographic projection of the pixel electrode 510 along the thickness direction Z. The center of the orthographic projection of the pixel electrode 510 along the thickness direction Z may be the geometric center of the orthographic projection of the pixel electrode 510 along the thickness direction Z. The orthographic projection of the power block 331 along the thickness direction Z is centrally symmetrically arranged about the geometric center, so that the flatness of different positions on the central circumference of the pixel electrode 510 is close, and the influence of the unevenness of the pixel electrode 510 on the display effect is better improved.

[0068] Optionally, at least a portion of the power block 331 satisfies: the orthographic projection of the power block 331 along the thickness direction Z is located within the orthographic projection of the pixel electrode 510 along the thickness direction Z, so that the power block 331 can better improve the impact of the unevenness of the pixel electrode 510 on the display effect.

[0069] For example, the orthographic projection center of the power block 331 along the thickness direction Z overlaps with the orthographic projection center of the pixel electrode 510 along the thickness direction Z, so that the power block 331 can better improve the influence of the unevenness of the pixel electrode 510 on the display effect.

[0070] The array substrate includes a plurality of pixel electrodes 510, and the area sizes of the pixel electrodes 510 may be the same or different. For example, when the array substrate is used for a display panel, and the display panel includes a plurality of sub-pixels, the distribution areas of the plurality of sub-pixels may be the same or different. For example, in some embodiments, the sub-pixels of the display panel include red sub-pixels, blue sub-pixels, and green sub-pixels, and the distribution area of ​​the blue sub-pixels may be larger, while the distribution area of ​​the green sub-pixels may be smaller. Correspondingly, the orthographic projection area of ​​the pixel electrode 510 of the blue sub-pixel along the thickness direction Z is larger than the orthographic projection area of ​​the pixel electrode 510 of the green sub-pixel along the thickness direction Z.

[0071] When the orthographic projection areas of the two pixel electrodes 510 along the thickness direction Z are inconsistent, the orthographic projection areas of the power blocks 331 corresponding to the two pixel electrodes 510 along the thickness direction Z may be the same or different.

[0072] In some optional embodiments, the areas of at least two pixel electrodes 510 are different, the areas of at least two power blocks 331 are different, and the area of ​​the power block 331 is positively correlated with the area of ​​the corresponding pixel electrode 510. For example, the pixel electrode 510 includes a first pixel electrode and a second pixel electrode, the power block 331 includes a first power block and a second power block, the orthographic projection of the first power block along the thickness direction Z is at least partially overlapped with the orthographic projection of the first pixel electrode along the thickness direction Z, and the orthographic projection of the second power block along the thickness direction Z is at least partially overlapped with the orthographic projection of the second pixel electrode along the thickness direction Z, that is, the first power block corresponds to the first pixel electrode, and the second power block corresponds to the second pixel electrode. When the orthographic projection area of ​​the first pixel electrode along the thickness direction Z is greater than the orthographic projection area of ​​the second pixel electrode along the thickness direction Z, the orthographic projection area of ​​the first power block along the thickness direction Z is greater than the orthographic projection area of ​​the second power block along the thickness direction Z.

[0073] In these optional embodiments, pixel electrodes 510 of different areas correspond to power blocks 331 of different areas, and the area of ​​the power block 331 is positively correlated with the area of ​​the corresponding pixel electrode 510, which can better and more specifically improve the flatness of the pixel electrode 510 corresponding to the power block 331 and better improve the display effect of the display panel.

[0074] Please also read Figures 1 to 4 , Figure 5 yes Figure 1 Schematic diagram of the local enlarged structure.

[0075] In some optional embodiments, such as Figures 1 to 5 As shown, the second conductive layer 03 further includes a first connection portion 340 and a second connection portion 350, wherein the first connection portion 340 is connected to the first signal line 310 and is located between the first signal line 310 and the second signal line 320; the second connection portion 350 is connected to the second signal line 320 and is located between the first signal line 310 and the second signal line 320; and of the two connection lines 332 located on both sides of the same power block 331 in the second direction Y and connected thereto, one is a first connection line 332a and the other is a second connection line 332b, wherein the first connection line 332a is extended between the first connection portion 340 and the second signal line 320, and the second connection line 332b is extended between the second connection portion 350 and the first signal line 310. When the first signal line 310 is a first data line, and the first data line is used to transmit a data signal to a pixel circuit, the first connection portion 340 is used, for example, to connect the first signal line 310 and a pixel circuit driven by the first signal line 310. Likewise, when the second signal line 320 is a second data line and the second data line is used to transmit a data signal to a pixel circuit, the second connection portion 350 may be used to connect the second signal line 320 and the pixel circuit driven by the second signal line 320 .

[0076] In these optional embodiments, the second conductive layer 03 includes a first connection portion 340 and a second connection portion 350. The first connection portion 340 is connected to the first signal line 310 and is located between the first signal line 310 and the second signal line 320, that is, there is a first gap between the first connection portion 340 and the second signal line 320; the second connection portion 350 is connected to the second signal line 320 and is located between the first signal line 310 and the second signal line 320, that is, there is a second gap between the first connection portion 340 and the first signal line 310. Since the first connection portion 340 is connected to the first signal line 310, the first gap is arranged closer to the second signal line 320, and similarly, the second gap is arranged closer to the first signal line 310. A first connecting line 332a and a second connecting line 332b are arranged on both sides of the same power block 331. The first connecting line 332a is extended between the first connecting portion 340 and the second signal line 320, that is, the first connecting line 332a extends through the first gap, and the second connecting line 332b is arranged between the second connecting portion 350 and the second signal line 320. The second connecting line 332b extends through the second gap, which can better ensure the insulation between the second power line 330 and the first signal line 310 and the second signal line 320.

[0077] There are many ways to set the connection positions of the first connection line 332a and the second connection line 332b to the power block 331. For example, the first connection line 332a and the second connection line 332b can be connected to the same side of the power block 331 in the first direction X.

[0078] In some other optional embodiments, the first connection line 332 a is connected to a side of the power block 331 facing the second signal line 320 , and the second connection line 332 b is connected to a side of the power block 331 facing the first signal line 310 .

[0079] In these optional embodiments, on the one hand, when the first connection line 332a is located on the side of the power block 331 facing the second signal line 320, the first connection line 332a can pass between the second signal line 320 and the first connection portion 340 along a relatively straight extension path, which can simplify the shape of the first connection line 332a. Similarly, the second connection line 332b is connected to the side of the power block 331 facing the first signal line 310, which can also simplify the shape of the second connection line 332b and facilitate the preparation of the first connection line 332a and the second connection line 332b. On the other hand, the first connection line 332a and the second connection line 332b are connected to the diagonal sides of the power block 331, and the first connection line 332a and the second connection line 332b are relatively symmetrically arranged relative to the power block 331, which can better improve the unevenness of the pixel electrode 510.

[0080] In some optional embodiments, such as Figures 1 to 5 As shown, a plurality of second power lines 330 are spaced apart along the first direction X, and a power block 331 of at least one second power line 330 includes a functional block 331a and an auxiliary block 331b. Optionally, the orthographic projection of the functional block 331a along the thickness direction Z and the orthographic projection of the pixel electrode 510 along the thickness direction Z are at least partially overlapped, and the distribution area and position of the functional block 331a will indirectly affect the flatness of the pixel electrode 510, that is, the functional block 331a has the function of adjusting the flatness of the pixel electrode 510. The auxiliary block 331b is used to assist in increasing the distribution area of ​​the power block 331, so as to increase the distribution area of ​​the second power line 330 and reduce the resistance of the second power line 330. The connection line 332 of the second power line 330 also includes a third connection line 332c, and the auxiliary block 331b and the functional block 331a are spaced apart in the second direction Y and are connected to each other through the third connection line 332c. The third connection line 332 c may be located closer to the second signal line 320 of the first signal line 310 and the second signal line 320 , or the third connection line 332 c may be located closer to the first signal line 310 of the first signal line 310 and the second signal line 320 .

[0081] A power block 331 may include one or more functional blocks 331a, and / or, a power block 331 may include one or more auxiliary blocks 331b. If the auxiliary block 331b and the functional block 331a of a power block 331 need to be connected through multiple third connection lines 332c, then the multiple third connection lines 332c may be located on the same side. Specifically, compared to the second signal line 320, the multiple third connection lines 332c are all located closer to the first signal line 310; or, compared to the first signal line 310, the multiple third connection lines 332c are all located closer to the second signal line 320. In addition, the multiple third connection lines 332c may also be located on different sides, for example, a portion of the third connection lines 332c are located closer to the first signal line 310, and another portion of the third connection lines 332c are located closer to the second signal line 320.

[0082] The second conductive layer 03 may further include a first via portion 360 disposed between the auxiliary block 331b and the functional block 331a; the array substrate further includes a third conductive layer 04 and the fourth conductive layer 05 as described above, the third conductive layer 04 and the fourth conductive layer 05 are disposed on both sides of the second conductive layer 03, that is, the third conductive layer 04 is located on the side of the second conductive layer 03 facing the substrate 01, and the fourth conductive layer 05 is located on the side of the second conductive layer 03 facing away from the substrate 01. The third conductive layer 04 includes a third signal line 410, and at least one pixel electrode 510 of the fourth conductive layer 05 is connected to the third signal line 410 through the first via portion 360.

[0083] There are many ways to set the third signal line 410. For example, the transistor TFT in the pixel circuit of the array substrate includes a semiconductor portion, a gate, a source and a drain, and the third signal line 410 can be one of the source and the drain. Alternatively, the third signal line 410 is a bridge line for connecting the pixel electrode 510 with the source or the drain.

[0084] There are many ways to set the relative position of the third conductive layer 04 and the first conductive layer 02. The third conductive layer 04 can be located on the side of the first conductive layer 02 facing the substrate 01, or the third conductive layer 04 can be located between the first conductive layer 02 and the second conductive layer 03, or the third conductive layer 04 and the first conductive layer 02 can be reused.

[0085] In these optional embodiments, the power block 331 is divided into an auxiliary block 331b and a functional block 331a, the auxiliary block 331b and the functional block 331a are connected to each other through a third connection line 332c, and a first via portion 360 is provided between the auxiliary block 331b and the functional block 331a, that is, the power block 331 is provided in the functional block 331a and the auxiliary block 331b to provide a space for the first via portion 360. The pixel electrode 510 can be connected to the third signal line 410 through the first via portion 360.

[0086] There are many ways to arrange the second power lines 330. For example, the second power lines 330 arranged side by side and spaced apart along the first direction X may have the same shape and arrangement.

[0087] In some other optional embodiments, such as Figure 5 As shown, the shapes of the two second power lines 330 adjacent to each other along the first direction X are different. For example, of the two second power lines 330 adjacent to each other along the first direction X, one is a first sub-power line 330a, and the other is a second sub-power line 330b, the first sub-power line 330a includes the above-mentioned functional block 331a but does not include the auxiliary block 331b, and the second sub-power line 330b includes the above-mentioned functional block 331a and the auxiliary block 331b. That is, of the two adjacent second power lines 330, the power block 331 of one is integrally arranged, and the power block 331 of the other is divided into the functional block 331a and the auxiliary block 331b. In the first sub-power line 330a not including the auxiliary block 331b, a second via portion 370 is arranged between the power block 331 and the first connecting portion 340 and / or the second connecting portion 350, the pixel electrode 510 is connected to the third signal line 410 through the second via portion 370, and the second via portion 370 is located in the second conductive layer 03.

[0088] From the above content, it can be seen that the first via portion 360 and the second via portion 370 are both used to connect the pixel electrode 510 to the third signal line 410. The difference between the two is that the first via portion 360 and the second via portion 370 are arranged at different positions. The first via portion 360 is arranged in the column where the second sub-power line 330b is located, and the second via portion 370 is arranged in the column where the first sub-power line 330a is located. Therefore, the first via portion 360 is used to connect the pixel electrode 510 in the column where the second sub-power line 330b is located to the third signal line 410, and the second via portion 370 is used to connect the pixel electrode 510 in the column where the first sub-power line 330a is located to the third signal line 410. In these optional embodiments, the shapes of the two second power lines 330 adjacent to each other along the first direction X are different, and the corresponding pixel electrodes 510 are connected to the third signal line 410 at different positions. Continue to refer to Figure 3 and Figure 5 In the example shown, the pixel electrode 510 includes a first pixel electrode 510a and a second pixel electrode 510b adjacent to each other along the first direction X, the orthographic projection of the first pixel electrode 510a along the thickness direction Z is at least partially overlapped with the orthographic projection of the power block 331 of the first sub-power line 330a along the thickness direction Z, and the second pixel electrode 510b is at least partially overlapped with the orthographic projection of the functional block 331a of the second sub-power line 330b along the thickness direction Z. The first pixel electrode 510a and the second pixel electrode 510b are connected to different third signal lines 410, the first pixel electrode 510a is connected to the third signal line 410 through the second via portion 370, and the second pixel electrode 510b is connected to the third signal line 410 through the first via portion 360. The reasonable arrangement of the positions of the first connection portion 340, the second connection portion 350, the first via portion 360, the second via portion 370, the first sub-power line 330a and the second sub-power line 330b facilitates the realization of various functions.

[0089] In the above embodiment, the second power line 330 may include first sub-power lines 330a and second sub-power lines 330b arranged alternately. In other embodiments, the second power line 330 may include only first sub-power lines 330a. In still other embodiments, the second power line 330 may include only second sub-power lines 330b.

[0090] Optionally, the orthographic projection area of ​​a power block 331 of the first sub-power line 330a along the thickness direction Z is larger than the orthographic projection area of ​​a functional block 331a of the second sub-power line 330b along the thickness direction Z, and the orthographic projection area of ​​a first pixel electrode 510 along the thickness direction Z is larger than the orthographic projection area of ​​a second pixel electrode 510 along the thickness direction Z, that is, for pixel electrodes 510 of different sizes, different size designs are performed for the power blocks 331 of the first sub-power line 330a and the second sub-power line 330b, which can better improve the unevenness problem of the first pixel electrode 510 and the second pixel electrode 510.

[0091] In some optional embodiments, the orthographic projection of the first power line 210 on the substrate 01 overlaps at least partially with the orthographic projection of the second power line 330 on the substrate 01. In this way, the distance between each first power line 210 and each second power line 330 can be ensured to be close, which facilitates the mutual connection of the first power line 210 and the second power line 330. In any of the above embodiments, there are many ways to set the shape of the first connecting line 332a and the second connecting line 332b, as long as the first connecting line 332a and the second connecting line 332b can both connect the adjacent power blocks 331.

[0092] For example, in the first sub-power line 330a, the first connection line 332a and the second connection line 332b can be extended along a straight path, the first connection line 332a is located on the side of the power block 331 of the first sub-power line 330a close to the second signal line 320, and the second connection line 332b is located on the side of the power block 331 of the first sub-power line 330a close to the first signal line 310. The first connection line 332a and the second connection line 332b are extended along a straight path to simplify the shapes of the first connection line 332a and the second connection line 332b, and facilitate the preparation of the first connection line 332a and the second connection line 332b.

[0093] Optionally, there are multiple second vias 370, and the second vias 370 may be located between the power block 331 of the first sub-power line 330a and the first connection portion 340 and / or the second connection portion 350. Optionally, the number of the second vias 370 is the same as the number of the power blocks 331 in the first sub-power line 330a, and each power block 331 is provided with a second via 370 on one side of the second direction Y to increase the connection area between the first power line 210 and the first sub-power line 330a.

[0094] Optionally, in the second sub-power line 330b, the shape of the third connection line 332c can be set in various ways. For example, the third connection line 332c can be extended along a straight path to simplify the shape of the third connection line 332c.

[0095] Optionally, the areas of the functional block 331a and the auxiliary block 331b may be the same or different. For example, the orthographic projection area of ​​the functional block 331a along the thickness direction Z is larger than the orthographic projection area of ​​the auxiliary block 331b along the thickness direction Z. The functional block 331a is overlapped with the pixel electrode 510. The larger area of ​​the functional block 331a can better improve the unevenness of the pixel electrode 510.

[0096] Optionally, the first connection line 332a and / or the second connection line 332b are used to connect the functional block 331a of one of the two adjacent power blocks 331 with the auxiliary block 331b of the other. There are many ways to set the shapes of the first connection line 332a and the second connection line 332b. For example, the auxiliary block 331b and the edge of the power block 331 facing the second signal line 320 are aligned along the second direction Y, and the first connection line 332a can extend along a straight line to connect the functional block 331a of one of the two adjacent power blocks 331 with the auxiliary block 331b of the other, which can simplify the shape of the first connection line 332a. Alternatively, when the auxiliary block 331b and the edge of the power block 331 facing the first signal line 310 are staggered along the second direction Y, the second connection line 332b extends along a bending path to connect the functional block 331a of one of the two adjacent power blocks 331 with the auxiliary block 331b of the other.

[0097] Optionally, in the second sub-power line 330 b , the first connection line 332 a and the third connection line 332 c are aligned along the second direction Y to simplify the shape of the connection line 332 .

[0098] The embodiment of the second aspect of the present application also provides a display panel, including the array substrate of any one of the above-mentioned first aspect embodiments. Since the display panel provided by the embodiment of the second aspect of the present application includes the above-mentioned array substrate, the display panel provided by the embodiment of the second aspect of the present application has the beneficial effects of the above-mentioned array substrate, which will not be repeated here.

[0099] The display panel provided in the embodiment of the present application may be at least one of an organic light emitting diode display panel, a liquid crystal display panel, and a micro light emitting diode display panel.

[0100] The embodiment of the third aspect of the present application also provides a display device, including the display panel of any of the first aspect embodiments. Since the display device provided by the embodiment of the third aspect of the present application includes the display panel of any of the first aspect embodiments, the display device provided by the embodiment of the third aspect of the present application has the beneficial effects of the display panel of any of the second aspect embodiments, which will not be described in detail here.

[0101] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0102] According to the embodiments described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer, located on one side of the substrate, wherein the first conductive layer comprises a first power line; a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a first signal line, a second signal line and a second power line between the first signal line and the second signal line, arranged in a first direction at intervals; The first power line, the first signal line, the second signal line and the second power line are all extended along the second direction, and the first power line and the second power line are connected by via holes; the second power line includes a plurality of power blocks spaced apart along the second direction and a connecting line connected between two adjacent power blocks, wherein the width of the connecting line in the first direction is smaller than the width of the power block in the first direction; The second conductive layer further comprises: A first connecting portion connected to the first signal line and located between the first signal line and the second signal line; a second connection portion connected to the second signal line and located between the first signal line and the second signal line; Of the two connecting wires located on both sides of the same power block in the second direction and connected thereto, one is a first connecting wire and the other is a second connecting wire, the first connecting wire is extended between the first connecting portion and the second signal wire, and the second connecting wire is extended between the second connecting portion and the first signal wire; The first connection line is connected to a side of the power block facing the second signal line, and the second connection line is connected to a side of the power block facing the first signal line.

2. The array substrate according to claim 1, characterized in that: A plurality of the second power lines are spaced apart along the first direction, the power block of at least one of the second power lines comprises a functional block and an auxiliary block, the connection line of the second power line further comprises a third connection line, the auxiliary block and the functional block are spaced apart in the second direction and are connected to each other through the third connection line, and a first via portion is provided between the auxiliary block and the functional block; The array substrate also includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer and the fourth conductive layer are respectively arranged on both sides of the second conductive layer, the third conductive layer includes a third signal line, and the fourth conductive layer includes a pixel electrode, and the pixel electrode is connected to the third signal line through the first via portion.

3. The array substrate according to claim 2, characterized in that: Of the two second power lines adjacent to each other along the first direction, one is a first sub-power line and the other is a second sub-power line, the first sub-power line includes the functional block but does not include the auxiliary block, the second sub-power line includes the functional block and the auxiliary block, a second via portion is provided between the power block of the first sub-power line and the first connecting portion and / or the second connecting portion, and the pixel electrode is interconnected with the third signal line through the second via portion.

4. The array substrate according to any one of claims 1 to 3, characterized in that: Also includes: The fourth conductive layer is located on a side of the second conductive layer away from the substrate, and the fourth conductive layer includes a pixel electrode, and the orthographic projection of the pixel electrode along the thickness direction of the array substrate is at least partially overlapped with the orthographic projection of the second power line along the thickness direction.

5. The array substrate according to claim 4, characterized in that: An orthographic projection of each of the power blocks along the thickness direction at least partially overlaps with an orthographic projection of each of the pixel electrodes along the thickness direction.

6. The array substrate according to claim 4, characterized in that: The orthographic projection of the power supply block along the thickness direction is centrally symmetrically arranged with respect to the center of the orthographic projection of the pixel electrode along the thickness direction.

7. The array substrate according to claim 4, characterized in that: An orthographic projection of the power block along the thickness direction is located within an orthographic projection of the pixel electrode along the thickness direction.

8. The array substrate according to claim 4, characterized in that: At least two of the pixel electrodes have different areas, at least two of the power blocks have different areas, and the area of ​​the power block is positively correlated with the area of ​​the corresponding pixel electrode.

9. The array substrate according to any one of claims 1 to 3, characterized in that: An orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the second power line on the substrate.

10. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate further comprises a plurality of pixel circuits disposed on one side of the substrate, and the plurality of pixel circuits are arranged in a row along the second direction; The first signal line is a first data line, the second signal line is a second data line, and the first data line and the second data line are used to provide data signals to a plurality of pixel circuits in the same column arranged along the second direction.

11. The array substrate according to claim 10, characterized in that: Of the two pixel circuits adjacent to each other in the second direction, a data signal of one of the pixel circuits is provided by the first data line, and a data signal of the other pixel circuit is provided by the second data line.

12. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 11.

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