Display panel and display device

Abstract

The present application discloses a display panel and a display device, and relates to the field of display technology. In the display panel, a first control line is electrically connected to a first gate of a first transistor in a first overlapping region that at least partially overlaps, and a second control line is electrically connected to a second gate of a second transistor in a second overlapping region that at least partially overlaps. Thus, not only can the control of the first transistor and the second transistor be realized, but also the first control line and the second control line can be prevented from occupying too much layout space in the second direction, so as to facilitate the realization of a narrow frame of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light emitting diode (OLED) display panels have been widely used due to their self-luminescence, low driving voltage, fast response and other characteristics.

[0003] In the related art, multiple testing steps are usually set up during the production process of the display panel to ensure the quality of the display panel and improve production efficiency. At present, a lighting test circuit can be designed in the peripheral area of ​​the display panel, and the lighting test circuit can be used to perform a lighting test on the display panel to check for poor display of the display panel.

[0004] However, since the lighting test circuit needs to occupy a large space in the peripheral area, the screen-to-body ratio of the display panel is low, which affects the narrow frame of the display panel. Summary of the invention

[0005] The present application provides a display panel and a display device, which can solve the problem of low screen-to-body ratio of display panels in related technologies, which affects the narrow frame of the display panels. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel having a display area and a peripheral area surrounding the display area, comprising: a substrate, a plurality of sub-pixels located on one side of the substrate, and a plurality of test circuit groups; the plurality of sub-pixels are located in the display area; the plurality of test circuit groups are located in the peripheral area and arranged along the extension direction of the boundary of the display area; the test circuit group includes at least one first test circuit, each of the first test circuits includes:

[0007] a first transistor, the first transistor comprising a first gate;

[0008] a first control line, the first control line extending in a first direction, an orthographic projection of the first control line on the substrate and an orthographic projection of the first gate on the substrate having a first overlapping region formed by at least partial overlap, and the first control line and the first gate are electrically connected in the first overlapping region, the first control line is used to provide a first control signal to the first gate, and the first transistor is turned on or off under the control of the first control signal provided by the first control line;

[0009] a second transistor, the second transistor comprising a second gate;

[0010] and a second control line, wherein the second control line extends along the first direction, an orthographic projection of the second control line on the substrate and an orthographic projection of the second gate on the substrate have a second overlapping area formed by at least partial overlap, and the second control line is electrically connected to the second gate in the second overlapping area, and the second control line is used to provide a second control signal to the second gate, and the second transistor is turned on or off under the control of the second control signal provided by the second control line.

[0011] Optionally, the display panel includes: an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third insulating layer, a first source-drain electrode layer, a fourth insulating layer and a second source-drain electrode layer sequentially stacked on the base substrate; the active layer includes an active pattern; the first gate layer includes at least a first gate pattern and a second gate pattern arranged along the second direction, the first gate pattern and the active pattern overlapped portion constitute the first gate, and the second gate pattern and the active pattern overlapped portion constitute the second gate;

[0012] Among them, the first control line and the second control line are located in the first source and drain layer, the first control line and the first gate pattern are electrically connected through the first via holes in the second insulating layer and the third insulating layer, and the second control line and the second gate pattern are electrically connected through the second via holes in the second insulating layer and the third insulating layer.

[0013] Optionally, each of the first test circuits further includes: a first signal input line, a second signal input line and a first signal output line; the first transistor further includes a first source and a first drain, and the second transistor further includes a second source and a second drain;

[0014] The first signal input line and the second signal input line both extend along the first direction, the first signal input line is electrically connected to the first source or the second source, and is used to provide a first input signal to the first source and the second source, and the second signal input line is electrically connected to the first source or the second source, and is used to provide a second input signal to the second source;

[0015] The first signal output line extends along a second direction intersecting the first direction, the first signal output line is electrically connected to the first drain and the second drain, and the first signal output line is also connected to the plurality of sub-pixels, and when the first control line controls the first transistor to turn on and the second control line controls the second transistor to turn off, the first signal output line is used to transmit the input signal received from the first drain to the plurality of sub-pixels, and when the first control line controls the first transistor to turn off and the second control line controls the second transistor (M2) to turn on, the first signal output line is also used to transmit the input signal received from the second drain to the plurality of sub-pixels.

[0016] Optionally, the first signal input line and the second signal input line are located in the second source-drain layer; the first signal output line is located in the second gate layer; the first source-drain layer at least includes a first source-drain pattern, a second source-drain pattern and a third source-drain pattern arranged along the second direction; the first control line is located between the first source-drain pattern and the second source-drain pattern, and the second control line is located between the second source-drain pattern and the third source-drain pattern;

[0017] The orthographic projection of the first source-drain pattern on the base substrate at least partially overlaps with the orthographic projection of the first signal input line on the base substrate, and the first source-drain pattern is electrically connected to the first signal input line through a third via hole in the fourth insulating layer, and the first source-drain pattern is a first source of the first transistor;

[0018] The orthographic projection of the second source-drain pattern on the base substrate at least partially overlaps with the orthographic projection of the first signal output line on the base substrate, and the second source-drain pattern is electrically connected to the first signal output line through a fourth via hole in the third insulating layer, and the second source-drain pattern is a first drain of the first transistor and a second drain of the second transistor;

[0019] The orthographic projection of the third source-drain pattern on the substrate at least partially overlaps with the orthographic projection of the second signal input line on the substrate, and the third source-drain pattern is electrically connected to the second signal input line through a fifth via in the fourth insulating layer, and the third source-drain pattern is the second source of the second transistor.

[0020] Optionally, the orthographic projection of the first via hole on the base substrate and the orthographic projection of the second via hole on the base substrate are both located within the orthographic projection of the active pattern on the base substrate;

[0021] The orthographic projection of the first gate pattern on the base substrate covers the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the second gate pattern on the base substrate covers the orthographic projection of the second via hole on the base substrate.

[0022] Optionally, the orthographic projection of the first via hole on the base substrate and the orthographic projection of the second via hole on the base substrate do not overlap with the orthographic projection of the active pattern on the base substrate.

[0023] Optionally, the second insulating layer and the third insulating layer include at least two first vias and two second vias; the active pattern includes a first portion and two second portions located on both sides of the first portion, the orthographic projection of the first portion on the base substrate partially overlaps with the orthographic projection of the first gate pattern on the base substrate and the orthographic projection of the second gate pattern on the base substrate, the orthographic projection of one of the second portions on the base substrate partially overlaps with the orthographic projection of the first source-drain pattern on the base substrate, and the orthographic projection of the other second portion on the base substrate partially overlaps with the orthographic projection of the second source-drain pattern on the base substrate;

[0024] At least two of the first vias are arranged along the first direction with the first portion, and at least two of the first vias are located on both sides of the first portion, a length of the first gate pattern along the first direction is greater than a length of the first portion along the first direction, the first gate pattern includes a first region and a second region that do not overlap with the first portion and are arranged along the first direction, and the first control line and the first gate pattern are electrically connected in the first region and the second region respectively through at least one of the first vias;

[0025] At least two of the second vias are arranged along the first direction with the first part, and at least two of the second vias are located on both sides of the first part, the length of the second gate pattern along the first direction is greater than the length of the first part along the first direction, the second gate pattern includes a third area and a fourth area that do not overlap with the first part and are arranged along the first direction, and the second control line and the second gate pattern are electrically connected in the third area and the fourth area respectively through at least one of the second vias.

[0026] Optionally, the second insulating layer and the third insulating layer include at least two first vias and two second vias; the active pattern includes a first portion and two second portions located on both sides of the first portion, the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the first gate pattern on the substrate and the orthographic projection of the second gate pattern on the substrate, the orthographic projection of one of the second portions on the substrate overlaps with the first source portion of the first transistor, and the orthographic projection of the other second portion on the substrate overlaps with the second source portion of the second transistor;

[0027] At least two of the first vias are arranged along the first direction with the first portion and are both located on one side of the first portion, a length of the first gate pattern along the first direction is greater than a length of the first portion along the first direction, the first gate pattern includes a fifth region that does not overlap with the first portion, and the first control line and the first gate pattern are electrically connected in the fifth region through at least two of the first vias;

[0028] At least two of the second vias are arranged along the first direction with the first part and are both located on one side of the first part, the length of the second gate pattern along the first direction is greater than the length of the first part along the first direction, the second gate pattern includes a sixth area that does not overlap with the first part, and the second control line and the second gate pattern are electrically connected in the sixth area through at least two of the second vias.

[0029] Optionally, at least two of the first via holes are arranged along the first direction, or at least two of the first via holes are arranged along the second direction;

[0030] At least two of the second via holes are arranged along the first direction, or at least two of the second via holes are arranged along the second direction.

[0031] Optionally, the length of the first portion along the first direction is less than or equal to the length of the second portion along the first direction.

[0032] Optionally, for each of the first source-drain pattern, the second source-drain pattern and the third source-drain pattern, the orthographic projection of the source-drain pattern on the substrate at least partially overlaps with the orthographic projection of the active pattern on the substrate, and the source-drain pattern and the active pattern are electrically connected through a sixth via in the first insulating layer, the second insulating layer and the third insulating layer.

[0033] Optionally, the test circuit group includes two first test circuits arranged along the second direction; the two first test circuits share a first signal input line, or the two first test circuits share a second signal input line.

[0034] Optionally, the first signal output line in the first one of the first test circuits and the first signal output line in the second one of the first test circuits are respectively located on two sides of transistors included in the two first test circuits.

[0035] Optionally, the display panel further includes a plurality of second test circuits, the plurality of second test circuits are located in the peripheral area and arranged along the extension direction of the boundary of the display area; each of the second test circuits includes a second signal output line; the plurality of sub-pixels constitute a plurality of first pixel columns and a plurality of second pixel columns, each of the first pixel columns includes a plurality of first color sub-pixels and a plurality of second color sub-pixels, and each of the second pixel columns includes a plurality of third color sub-pixels;

[0036] The first signal output line of each first test circuit is connected to multiple first color sub-pixels and multiple second color sub-pixels of one first pixel column, and the second signal output line of each second test circuit is connected to multiple third color sub-pixels of one second pixel column.

[0037] On the other hand, a display device is provided, the display device comprising: a power supply component and the display panel as described in the above aspect;

[0038] The power supply component is used to supply power to the display panel.

[0039] The beneficial effects of the technical solution provided by this application include at least:

[0040] The present application provides a display panel and a display device, in which a first control line is electrically connected to a first gate of a first transistor in a first overlapping region that at least partially overlaps, and a second control line is electrically connected to a second gate of a second transistor in a second overlapping region that at least partially overlaps. Thus, not only can the control of the first transistor and the second transistor be achieved, but also the first control line and the second control line can be prevented from occupying too much layout space in the second direction, thereby facilitating the realization of a narrow frame of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a partial schematic diagram of a test circuit in the related art;

[0043] Figure 2 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0044] Figure 3 is a structural schematic diagram of a first test circuit provided in an embodiment of the present application;

[0045] Figure 4 yes Figure 3 A cross-sectional view of the first test circuit shown along the AA direction;

[0046] Figure 5 It is a schematic diagram of an electron microscope provided in an embodiment of the present application;

[0047] Figure 6 yes Figure 5 The cross-sectional view shown;

[0048] Figure 7 It is another electron microscope schematic diagram provided in the embodiment of the present application;

[0049] Figure 8 yes Figure 7 The cross-sectional view shown;

[0050] Fig. 9 is a partial schematic diagram of a test circuit group provided in an embodiment of the present application;

[0051] Fig.10 is a partial schematic diagram of another test circuit group provided in an embodiment of the present application;

[0052] Fig.11 is a partial schematic diagram of another test circuit group provided in an embodiment of the present application;

[0053] Fig.12 is a partial schematic diagram of another test circuit group provided in an embodiment of the present application;

[0054] Fig.13 is a partial schematic diagram of another test circuit group provided in an embodiment of the present application;

[0055] Fig.14 is an equivalent circuit diagram of a first test circuit and a second test circuit provided in an embodiment of the present application;

[0056] Fig.15 is a signal timing diagram provided by an embodiment of the present application;

[0057] Fig.16 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0058] Fig.17 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0060] Organic light emitting diode (OLED) is a new type of current-type semiconductor light-emitting device. The organic light-emitting diode realizes the display function by controlling the injection of carriers and simultaneously compound-exciting the organic material to emit light. Among them, the driving mode of the organic light-emitting diode can be divided into active driving and passive driving. Correspondingly, the display panel can be an active matrix display panel (active-matrix organic light-emitting diode, AMOLED) and a passive matrix display panel (passive matrix organic light-emitting diode, PMOLED). Compared with passive driving, active driving can equip each sub-pixel in the display panel with a thin film transistor (thin film transistor, TFT) and a charge storage capacitor, thereby improving the load driving capability, making it easy to achieve high resolution and high brightness, and having the advantages of high working efficiency and low power consumption. AMOLED display panel is easy to integrate into the display panel, and it is easier to improve the circuit integration to achieve large-area display. It is an ideal device for low-power large-size display devices.

[0061] However, AMOLED display panels still have obvious shortcomings in terms of structure. For example, the peripheral circuits of AMOLED display panels need to occupy a larger space in the layout, so the border width of the display panel is larger, which affects the narrow border of AMOLED display products.

[0062] In the related art, the display panel has a display area and a peripheral area surrounding the display area. The peripheral area includes a fanout bonding area located on one side of the display area, and a lighting test circuit (cell test) is located on the side of the bonding area away from the display area. Since the design space of the lighting test circuit in the pixel row direction of the display panel is limited, it is necessary to design two rows of lighting test circuits. Figure 1, taking a two-row lighting test circuit as an example, the related technology is briefly introduced. The two-row lighting test circuit includes two first control lines (CTSW21 and CTSW22), one second control line (CTSW3), two first signal input lines (CTDR1 and CTDR2) and two second signal input lines (CTDB1 and CTDB2).

[0063] The first control line (CTSW21), the second signal input line (CTDB1), the first signal input line (CTDR1), the second control line (CTSW3), the second signal input line (CTDB2), the first signal input line (CTDR2) and the first control line (CTSW22) are all extended along the pixel row direction and arranged in sequence along the pixel column direction. In addition, each lighting test circuit includes a first transistor and a second transistor. The first transistor and the second transistor of the first lighting test circuit are located between the first control line (CTSW21) and the second control line (CTSW3), and the first transistor and the second transistor of the second lighting test circuit are located between the second control line (CTSW3) and the first control line (CTSW22).

[0064] The first transistor includes a first gate, a first source and a first drain, and the second transistor includes a second gate, a second source and a second drain. The first control line (CTSW21) is connected to the first gate of the first transistor of a lighting test circuit by transferring to the vertical wiring of the first gate layer, and the first control line (CTSW22) is connected to the first gate of the first transistor of another lighting test circuit by transferring to the vertical wiring of the first gate layer. Both sides of the second control line (CTSW3) are connected to the second gates of the second transistors of the two lighting test circuits by transferring to the vertical wiring of the first gate layer.

[0065] The first signal input lines (CTDR1 and CTDR2) are used to write the data signal of the red sub-pixel, and the second signal input lines (CTDB1 and CTDB2) are used to write the data signal of the blue sub-pixel, which is usually a DC signal with a fixed voltage value. The first control lines (CTSW21 and CTSW22) are used to control the on or off of the first transistor. The second control line (CTSW3) is used to control the on or off of the second transistor.

[0066] The first transistor in each lighting test circuit can be turned on or off under the control of a control signal provided by a first control line (CTSW21 or CTSW22), and the second transistor in each lighting test circuit can be turned on or off under the control of a control signal provided by a second control line (CTSW3). The lighting test circuit also includes a first signal output line extending in the direction of the pixel column. When the first transistor is turned on and the second transistor is turned off, the first signal input line (CTDR1 or CTDR2) transmits a first input signal to the first signal output line through the first transistor. When the first transistor is turned off and the second transistor is turned on, the second signal input line (CTDB1 and CTDB2) transmits a second input signal to the first signal output line through the second transistor. The lighting test is thus achieved by alternately turning on the first transistor and the second transistor.

[0067] However, this solution causes these wirings to occupy more layout space in the direction of pixel columns, resulting in a wider width in the peripheral area, making it difficult to achieve a narrow frame of the display panel.

[0068] Figure 2 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 2 The display panel 10 may include: a base substrate 101, a plurality of sub-pixels 102 located on one side of the base substrate 101, and a plurality of test circuit groups 103. The display panel 10 may have a display area 10a and a peripheral area 10b surrounding the display area 10a. The plurality of sub-pixels 102 are located in the display area 10a, and the plurality of test circuit groups 103 are located in the peripheral area 10b and are arranged along the extension direction of the boundary of the display area 10a.

[0069] Figure 3 is a schematic diagram of the structure of a test circuit group provided in an embodiment of the present application. Figure 3 , the test circuit group 103 includes at least one first test circuit 1031 . Figure 3 A test circuit group 103 is shown in FIG. 1 , and the test circuit group 103 includes a first test circuit 1031. Figure 3 Each first test circuit 1031 may include: a first transistor M1, a first control line 10311, a second transistor M2, and a second control line 10312.

[0070] The first transistor M1 includes a first gate, and the second transistor M2 includes a second gate. The first control line 10311 and the second control line 10312 both extend along the first direction X.

[0071] In the embodiment of the present application, the orthographic projection of the first control line 10311 on the substrate 101 and the orthographic projection of the first gate of the first transistor M1 on the substrate 101 have a first overlapping region formed by at least partial overlap, and the first control line 10311 is electrically connected to the first gate in the first overlapping region. The first control line 10311 is used to provide a first control signal to the first gate. The first transistor M1 is turned on or off under the control of the first control signal provided by the first control line 10311 to the first gate.

[0072] The orthographic projection of the second control line 10312 on the substrate 101 and the orthographic projection of the second gate of the second transistor M2 on the substrate 101 have a second overlapping region formed by at least partial overlap, and the second control line 10312 is electrically connected to the second gate in the second overlapping region. The second control line 10312 is used to provide a second control signal to the second gate. The second transistor M2 is turned on or off under the control of the second control signal provided by the second control line 10312 to the second gate.

[0073] In summary, the embodiment of the present application provides a display panel, in which the first control line is electrically connected to the first gate of the first transistor in a first overlapping region that at least partially overlaps, and the second control line is electrically connected to the second gate of the second transistor in a second overlapping region that at least partially overlaps. Thus, not only can the control of the first transistor and the second transistor be achieved, but also the first control line and the second control line can be prevented from occupying too much layout space in the second direction, thereby facilitating the realization of a narrow frame of the display panel.

[0074] Optionally, through the design of the embodiment of the present application, the size of the display panel along the second direction Y of about 23 μm (micrometers) to 28 μm can be saved.

[0075] In the examples of this application, refer to Figure 3 , the first test circuit 1031 also includes a first signal input line 10313, a second signal input line 10314 and a first signal output line 10315. The first signal input line 10313, the second signal input line 10314 and the first signal output line 10315 all extend along the first direction X. Among them, the first signal input line 10313, the first control line 10313, the second control line 10316 and the second signal input line 10314 are arranged in sequence along the second direction Y. Among them, the second direction Y intersects with the first direction X, for example, the first direction X is the pixel row direction of the display panel, and the second direction Y is the pixel column direction of the display panel. In addition, the first transistor M1 may also include a first source and a first drain, and the second transistor M2 may also include a second source and a second drain.

[0076] The first signal input line 10313 is electrically connected to the first source of the first transistor M1 or the second source of the second transistor M2, and is used to provide a first input signal to the first source or the second source. The second signal input line 10314 is electrically connected to the first source of the first transistor M1 or the second source of the second transistor M2, and is used to provide a second input signal to the first source or the second source.

[0077] The first signal output line 10315 is electrically connected to the first drain and the second drain of the first transistor M1, and the first signal output line 10315 is also connected to a plurality of sub-pixels 102 located in the display area 10a. In the case where the first control line 10311 controls the first transistor M1 to turn on, and the second control line 10312 controls the second transistor M2 to turn off, the first signal output line 10315 is used to transmit the input signal received from the first drain to the plurality of sub-pixels 102. In the case where the first control line 10311 controls the first transistor M1 to turn off, and the second control line 10312 controls the second transistor M2 to turn on, the first signal output line 10315 is also used to transmit the input signal received from the second drain to the plurality of sub-pixels 102.

[0078] refer to Figure 4 , the display panel 10 may include: an active layer (poly) a1, a first insulating layer a2, a first gate layer (Gate1) a3, a second insulating layer a4, a second gate layer (Gate2) a5, a third insulating layer a6, a first source-drain layer (SD1) a7, a fourth insulating layer a8 and a second source-drain layer (SD2) a9 stacked in sequence on the base substrate 101. Optionally, the first insulating layer a2 may be a first gate insulating layer (gate insulator, GI). The second insulating layer a4 may be a second gate insulating layer. The third insulating layer a6 may be an inter level dielectric, ILD. The fourth insulating layer a8 may include a passivation layer (passivation layer, PVX) a81 and a planarization layer (planarization layer, PLN) a82.

[0079] The active layer a1 includes an active pattern a11. The first gate layer a3 includes at least a first gate pattern a31 and a second gate pattern a32 arranged along the second direction Y. The overlapping portion of the first gate pattern a31 and the active pattern a11 constitutes the first gate of the first transistor M1, and the overlapping portion of the second gate pattern a32 and the active pattern a11 constitutes the second gate of the second transistor M2. The first source-drain layer a7 includes at least a first source-drain pattern a71, a second source-drain pattern a72, and a third source-drain pattern a73 arranged along the second direction Y.

[0080] In the embodiment of the present application, the first control line 10311 and the second control line 10312 are both located in the first source-drain layer a7. The first control line 10311, the second control line 10312, the first source-drain pattern a71, the second source-drain pattern a72 and the third source-drain pattern a73 can be made of the same material and prepared by the same patterning process. Among them, the first control line 10311 is located between the first source-drain pattern a71 and the second source-drain pattern a72, and the second control line 10312 is located between the second source-drain pattern a72 and the third source-drain pattern a73. In addition, the first signal output line 10315 is located in the second gate layer a5.

[0081] The insulating film layer between the first control line 10311 and the first gate pattern a31 includes a second insulating layer a4 and a third insulating layer a6, and the second insulating layer a4 and the third insulating layer a6 may have a first via hole, and the first control line 10311 and the first gate pattern a31 may be electrically connected through the first via hole. Similarly, the insulating film layer between the second control line 10312 and the second gate pattern a32 also includes a second insulating layer a4 and a third insulating layer a6, and the second insulating layer a4 and the third insulating layer a6 may have a second via hole, and the second control line 10312 and the second gate pattern a32 may be electrically connected through the second via hole.

[0082] The orthographic projection of the first source-drain pattern a71 on the base substrate 101 at least partially overlaps with the orthographic projection of the first signal input line 10313 on the base substrate 101, and the first source-drain pattern a71 is electrically connected to the first signal input line 10313 through a third via hole in the fourth insulating layer a8. The first source-drain pattern a71 may be a first source of the first transistor M1.

[0083] The orthographic projection of the second source-drain pattern a72 on the base substrate 101 at least partially overlaps with the orthographic projection of the first signal output line 10315 on the base substrate 101, and the second source-drain pattern a72 is electrically connected to the first signal output line 10315 through the fourth via hole in the third insulating layer a6, and the second source-drain pattern a72 is the first drain of the first transistor M1 and the second drain of the second transistor M2. That is, the first drain of the first transistor M1 and the second drain of the second transistor M2 are shared.

[0084] The orthographic projection of the third source-drain pattern a73 on the substrate 101 at least partially overlaps with the orthographic projection of the second signal input line 10314 on the substrate 101, and the third source-drain pattern a73 is electrically connected to the second signal input line 10314 through a fifth via hole in the fourth insulating layer a8. The third source-drain pattern a73 may be the second source of the first transistor M1.

[0085] In addition, in the embodiment of the present application, for each of the first source-drain pattern a71, the second source-drain pattern a72, and the third source-drain pattern a73, the orthographic projection of the source-drain pattern on the base substrate 101 at least partially overlaps with the orthographic projection of the active pattern a11 on the base substrate 101. Moreover, the source-drain pattern and the active pattern a11 are electrically connected through the sixth via hole in the first insulating layer a2, the second insulating layer a4, and the third insulating layer a6.

[0086] As a first optional implementation, refer to Figure 3 and Fig. 9 , the orthographic projection of the first via hole on the base substrate 101 and the orthographic projection of the second via hole on the base substrate 101 are both located within the orthographic projection of the active pattern a11 on the base substrate 101. That is, the area where the first control line 10311 is electrically connected to the first gate pattern a31 and the area where the second control line 10312 is electrically connected to the second gate pattern a32 are both located within the orthographic projection of the active pattern a11 on the base substrate 101.

[0087] In this implementation, reference Figures 5 to 8 If the size of the first via hole (or the second via hole) is too large and exposes the boundary of the first gate pattern a31 (or the second gate pattern a32), the first control line 10311 (or the second control line 10312) will cover the side wall of the first gate pattern a31 (or the second gate pattern a32), and the first control line 10311 (or the second control line 10312) may be short-circuited with the active pattern a11 due to the close distance, and the first transistor M1 (or the second transistor M2) will fail.

[0088] Based on this, in order to avoid transistor failure, the orthographic projection of the first gate pattern a31 on the base substrate 101 can cover the orthographic projection of the first via hole on the base substrate 101, and the orthographic projection of the second gate pattern a32 on the base substrate 101 can cover the orthographic projection of the second via hole on the base substrate 101.

[0089] Optionally, the apertures of the first via hole and the second via hole range from 2 μm to 2.5 μm. In the original design, the length of the first gate pattern a31 along the second direction Y (i.e., the width of the first gate pattern a31) and the length of the second gate pattern a32 along the second direction Y (i.e., the width of the second gate pattern a32) range from about 3.2 μm to 4.5 μm. In order to avoid transistor failure, the width of the first gate pattern a31 and the width of the second gate pattern a32 can be made to range from 4.5 μm to 6.4 μm.

[0090] Without changing the width-to-length ratio of the channels of the first transistor M1 and the second transistor M2, since the width of the first gate pattern a31 and the width of the second gate pattern a32 are increased (equivalent to increasing the length of the channels of the first transistor M1 and the second transistor M2), it is necessary to appropriately increase the length of the active pattern a11 along the first direction X, so as to increase the length of the overlapping area of ​​the first gate pattern a31 and the active pattern a11 along the first direction X, and the length of the overlapping area of ​​the second gate pattern a32 and the active pattern a11 along the first direction X (equivalent to increasing the width of the channels of the first transistor M1 and the second transistor M2). Therefore, the range of the length of the active pattern a11 along the first direction X can be changed from the original 15μm to 17μm to 18μm to 20μm. In addition, the length of the first gate pattern a31 along the first direction X (ie, the length of the first gate pattern a31 ) and the length of the second gate pattern a32 along the first direction X (ie, the length of the second gate pattern a32 ) can be changed from the original 21 μm to 24 μm to 26 μm to 30 μm.

[0091] As a second optional implementation, the second insulating layer a4 and the third insulating layer a6 include at least two first vias and two second vias. The active pattern a11 includes a first portion a111 and two second portions a112 located on both sides of the first portion a111. The orthographic projection of the first portion a111 on the substrate 101 overlaps with the orthographic projection of the first gate pattern a31 on the substrate 101 and the orthographic projection of the second gate pattern a32 on the substrate 101. The orthographic projection of one of the second portions a112 on the substrate 101 overlaps with the orthographic projection of the first source and drain pattern a71 on the substrate 101, and the orthographic projection of the other second portion a112 on the substrate 101 overlaps with the orthographic projection of the second source and drain pattern a72 on the substrate 101.

[0092] The first option, refer to Fig.10 , at least two first vias are arranged with the first portion a111 along the first direction X, and at least two first vias are located on both sides of the first portion a111. The length of the first gate pattern a31 along the first direction X is greater than the length of the first portion a111 along the first direction X. The first gate pattern a31 includes a first region and a second region that are not overlapped with the first portion a111 and are arranged along the first direction X. The first control line 10311 and the first gate pattern a31 are electrically connected in the first region and the second region respectively through at least one first via. Fig.10 The second insulating layer a4 and the third insulating layer a6 include two first via holes.

[0093] And, reference Fig.10, at least two second vias are arranged with the first portion a111 along the first direction X, and at least two second vias are located on both sides of the first portion a111. The length of the second gate pattern a32 along the first direction X is greater than the length of the first portion a111 along the first direction X. The second gate pattern a32 includes a third region and a fourth region that do not overlap with the first portion a111 and are arranged along the first direction X. The second control line 10312 and the second gate pattern a32 are electrically connected in the third region and the fourth region respectively through at least one second via. Fig.10 The second insulating layer a4 and the third insulating layer a6 include two second via holes.

[0094] The second option, refer to Fig.11 , at least two first vias are arranged with the first portion a111 along the first direction X, and at least two first vias are located on one side of the first portion a111. The length of the first gate pattern a31 along the first direction X is greater than the length of the first portion a111 along the first direction X. The first gate pattern a31 includes a fifth region that does not overlap with the first portion a111 (the fifth region can be located on the left or right side of the first portion a111). The first control line 10311 and the first gate pattern a31 are electrically connected in the fifth region through at least two first vias. Fig.11 The second insulating layer a4 and the third insulating layer a6 include two first via holes.

[0095] And, reference Fig.11 , at least two second vias are arranged with the first part a111 along the first direction X, and at least two second vias are located on one side of the first part a111. The length of the second gate pattern a32 along the first direction X is greater than the length of the first part a111 along the first direction X. The second gate pattern a32 includes a sixth region that does not overlap with the first part a111 (the sixth region may be located on the left or right side of the first part a111, and the sixth region and the fifth region may be located on the same side of the first part a111, or may be located on both sides of the first part a111 respectively). The second control line 10312 and the second gate pattern a32 are electrically connected in the sixth region through at least two second vias. Fig.11 The second insulating layer a4 and the third insulating layer a6 include two second via holes.

[0096] Refer to the above Fig.11 , the two first via holes can be arranged along the first direction X, and the two second via holes can be arranged along the first direction X. Of course, referring to Fig.12 , the two first vias may also be arranged along the second direction Y, and the two second vias may also be arranged along the second direction Y. In addition, the two first vias may also be arranged along the first direction X, and the two second vias may be arranged along the second direction Y. Alternatively, the two first vias may be arranged along the second direction Y, and the two second vias may be arranged along the first direction X.

[0097] That is, in the embodiment of the present application, at least two first vias are arranged along the first direction X, or at least two first vias are arranged along the second direction Y. At least two second vias are arranged along the first direction X, or at least two second vias are arranged along the second direction Y.

[0098] In the embodiment of the present application, the length of the first portion a111 along the first direction X may be less than or equal to the length of the second portion a112 along the first direction X. Figures 9 to 12 , the length of the first portion a111 along the first direction X is equal to the length of the second portion a112 along the first direction X. In this solution, the length of the first gate pattern a31 along the first direction X and the length of the second gate pattern a32 along the first direction X need to be designed to be greater than the length of the second portion a112 along the first direction X. Of course, referring to Fig.13 , the length of the first portion a111 along the first direction X is less than the length of the second portion a112 along the first direction X. In this solution, the length of the first gate pattern a31 along the first direction X and the length of the second gate pattern a32 along the first direction X may be greater than or equal to the length of the second portion a112 along the first direction X. Optionally, the length of the first portion a111 along the first direction X ranges from 15 μm to 17 μm. The length of the second portion a112 along the first direction X ranges from 18 μm to 20 μm.

[0099] In the second implementation, since the orthographic projection of the first via hole on the base substrate 101 and the orthographic projection of the second via hole on the base substrate 101 do not overlap with the orthographic projection of the active pattern a11 on the base substrate 101, the electrical connection between the first control line 10311 and the first gate pattern a31, and the electrical connection between the second control line 10312 and the second gate pattern a32 will not affect the active pattern a11, thereby ensuring the performance of the first transistor M1 and the second transistor M2.

[0100] In the examples of this application, refer to Figures 9 to 13 The test circuit group 103 includes two first test circuits 1031 arranged along the second direction Y. The two first test circuits 1031 may share a first signal input line 10313 , or the two first test circuits 1031 may share a second signal input line 10314 .

[0101] If the two first test circuits 1031 share a first signal input line 10313, the first signal input line 10313 can provide a first input signal to the sources of the two transistors connected to the first signal input line 10312 in the two first test circuits 1031. If the two first test circuits 1031 share a second signal input line 10314, the second signal input line 10314 can provide a second input signal to the two transistors connected to the second signal input line 10314 in the two first test circuits 1031.

[0102] refer to Figures 9 to 13 It can be seen that the first signal output line 10315 in the first first test circuit 1031 and the first signal output line 10315 in the second first test circuit 1031 are respectively located on both sides of the transistors included in the two first test circuits 1031. This can improve the pattern uniformity of the layout design.

[0103] In the embodiment of the present application, the display panel 10 may further include a plurality of second test circuits (not shown in the figure), which may be located in the peripheral area 10b and arranged along the extension direction of the boundary of the display area 10a. For example, the plurality of second test circuits may be located on a side of the test circuit group 103 away from the display area 10a.

[0104] refer to Figures 9 to 13 Each second test circuit 104 includes a second signal output line 1041, which can extend along the second direction Y. Of course, the second signal output line 1041 can also be bent appropriately to adapt to the layout design. Of course, the second test circuit 104 can also include a third transistor M3 (described below) Fig.14 A third transistor is shown in FIG), a third signal input line, and a third control line ( Figures 9 to 13 The third transistor, the third signal input line, and the third control line are not shown in the figure. The third transistor includes a third gate, a third source and a third drain. The third control line is electrically connected to the third gate and is used to provide a third control signal to the third gate. The third transistor is turned on or off under the control of the third control signal provided by the third control line. The third signal input line is electrically connected to the third source and is used to provide a third input signal to the third source. The second signal output line is electrically connected to the third drain and is used to transmit the third input signal received from the third drain to multiple sub-pixels 102 when the third control line controls the third transistor to turn on.

[0105] In addition, refer to Fig.14, the plurality of sub-pixels 102 may constitute a plurality of first pixel columns 102a and a plurality of second pixel columns 102b. Each first pixel column 102a includes a plurality of first color sub-pixels and a plurality of second color sub-pixels. Each second pixel column 102b includes a plurality of third color sub-pixels. Optionally, the first color sub-pixel may be a red (red, R) sub-pixel, the second color sub-pixel may be a blue (blue, B) sub-pixel, and the third color sub-pixel may be a green (green, G) sub-pixel.

[0106] The first signal output line 10315 of each first test circuit 1031 is connected to a plurality of first color sub-pixels and a plurality of second color sub-pixels of a first pixel column 102a. The second signal output line of each second test circuit is connected to a plurality of third color sub-pixels of a second pixel column 102b.

[0107] Fig.14 CTSW1 is used to indicate the third control signal provided by the third control line, CTSW2 is used to indicate the first control signal provided by the first control line, and CTSW3 is used to indicate the second control signal provided by the second control line. CTDG is used to indicate the third input signal provided by the third signal input line, CTDR is used to indicate the first input signal provided by the first signal input line, and CTDB is used to indicate the second input signal provided by the second signal input line.

[0108] Fig.15 is a signal timing diagram provided by an embodiment of the present application. Fig.15 , when the display panel 10 displays a white screen, the potential of the first control signal CTSW2 provided by the first control line 10311 and the potential of the second control signal CTSW3 provided by the second control line 10312 are alternately the first potential L, and the first control signal CTSW2 and the second control signal CTSW3 can be AC ​​signals. The potential of the third control signal CTSW1 provided by the third control line is the first potential L, and the third control signal CTSW1 is a DC signal. Among them, the first potential L can be an effective potential, the second potential H can be an invalid potential, and the first potential L can be a low potential relative to the second potential H.

[0109] In addition, the first input signal CTDR provided by the first signal input line 10313, the second input signal CTDB provided by the second signal input line 10314, and the third input signal CTDG provided by the third signal input line are all fixed voltage signals. For example, the range of the fixed voltage signal is 0V (volts) to 8V. For example, if the fixed voltage signal received by the sub-pixel is 0V, the sub-pixel can emit light; if the fixed voltage signal received by the sub-pixel is 7V, the sub-pixel may not emit light.

[0110] During the lighting test of the display panel, the display screen of the display panel can be adjusted by controlling the magnitude of the fixed voltage signal inputted by each signal input line, thereby realizing the test.

[0111] Fig.16 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Fig.16 It can be seen that the display panel 10 may include a power driving circuit 105, a first power line 106 and a second power line 107. The power driving circuit 105 may be located in the peripheral area and on a side of the test circuit group 103 away from the display area 10a. For example, the power driving circuit 105 may be located at the lower side of the display area 10a.

[0112] The power driving circuit 105 can be connected to the first power line 106 and the second power line 107, and the power driving circuit is used to provide a first power signal (VSS signal) to the first power line 106, so that the first power line 106 provides the first power signal from the power driving circuit 105 to the cathodes of the plurality of sub-pixels 102. In addition, the power driving circuit 105 can also be used to provide a second power signal (VDD signal) to the second power line 107, so that the second power line 107 provides the second power signal from the power driving circuit 105 to the anodes of the plurality of sub-pixels 102.

[0113] For example, Fig.16 A first power line 106 is shown in FIG. 1 , and the first power line 106 may at least partially surround the display area 10a. Also, Fig.16 Two second power lines 107 are shown (one second power line 107 on the upper side and one on the lower side).

[0114] refer to Fig.16 The display panel 10 further includes a driver integrated circuit (IC) 108. The driver integrated circuit 108 may be located on a side of the test circuit group 103 and the second test circuit 104 away from the display area 10a. The driver integrated circuit 108 may be used to provide various input signals and control signals to the first test circuit 1031 and the second test circuit 104. The peripheral area 10b of the substrate 101 may include a fan-out binding area 101b1, and the first test circuit 1031 and the second test circuit 104 may be connected to a plurality of sub-pixels 102 in the display area 10a through the fan-out binding area 101b1.

[0115] refer to Fig.16The display panel 10 may further include a row driving circuit (gate driver on array, GOA) 109, a first reset (vinit) circuit 110 and a second reset circuit 111. The row driving circuit 109 may include a first sub-driving circuit and a second sub-driving circuit located on both sides of the display area 10a. The first reset circuit 110 may include a first sub-reset circuit and a second sub-reset circuit located on both sides of the display area 10a. The second reset circuit 111 may include a third sub-reset circuit and a fourth sub-reset circuit located on both sides of the display area 10a.

[0116] Optionally, the display panel 10 further includes a plurality of power connection lines 112 extending along the second direction. The power connection lines 112 may be connected to the second power line 107 and a column of sub-pixels in the display area 10a. The power connection lines 112 may transmit the second power signal provided by the second power line 107 to the column of sub-pixels.

[0117] In addition, the display panel 10 may further include a plurality of row drive signal lines 113, a plurality of first reset signal lines 114, and a plurality of second reset signal lines 115. The two ends of each row drive signal line 113 are respectively connected to the first sub-drive circuit and the second sub-drive circuit included in the row drive circuit 109, and each row drive signal line 113 is also connected to a row of sub-pixels in the display area 10a, and is used to provide a row drive signal for a row of sub-pixels. The two ends of each first reset signal line 114 are respectively connected to the two first sub-reset circuits and the second sub-reset circuit included in the first reset circuit 110, and each first reset signal line 114 is also connected to a row of sub-pixels in the display area 10a, and is used to provide a first reset signal for a row of sub-pixels. The two ends of each second reset signal line 115 are respectively connected to the two third sub-reset circuits and the fourth sub-reset circuit included in the second reset circuit 111, and each second reset signal line 115 is also connected to a row of sub-pixels in the display area 10a, and is used to provide a second reset signal for a row of sub-pixels.

[0118] In summary, the embodiment of the present application provides a display panel, in which the first control line is electrically connected to the first gate of the first transistor in a first overlapping region that at least partially overlaps, and the second control line is electrically connected to the second gate of the second transistor in a second overlapping region that at least partially overlaps. Thus, not only can the control of the first transistor and the second transistor be achieved, but also the first control line and the second control line can be prevented from occupying too much layout space in the second direction, thereby facilitating the realization of a narrow frame of the display panel.

[0119] Fig.17 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.17The display device may include a power supply component 20 and a display panel 10 as provided in the above embodiment. The power supply component 20 may be used to supply power to the display panel 10.

[0120] Optionally, the display device can be: a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, electronic paper, a low-temperature polysilicon (LTPS) display, a low-temperature polycrystalline oxide (LTPO) display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0121] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0122] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, comprising a display area (10a) and a peripheral area (10b) surrounding the display area (10a), characterized in that: include: A base substrate (101), a plurality of sub-pixels (102) and a plurality of test circuit groups (103) located on one side of the base substrate (101); the plurality of sub-pixels (102) are located in the display area (10a); the plurality of test circuit groups (103) are located in the peripheral area (10b) and are arranged along the extension direction of the boundary of the display area (10a); the test circuit group (103) comprises at least one first test circuit (1031), and each of the first test circuits (1031) comprises: A first transistor (M1), wherein the first transistor (M1) comprises a first gate; a first control line (10311), the first control line (10311) extending along a first direction (X), an orthographic projection of the first control line (10311) on the substrate (101) and an orthographic projection of the first gate on the substrate (101) having a first overlapping region formed by at least partial overlap, and the first control line (10311) and the first gate are electrically connected in the first overlapping region, the first control line (10311) being used to provide a first control signal to the first gate, and the first transistor (M1) being turned on or off under the control of the first control signal provided by the first control line (10311); a second transistor (M2), the second transistor (M2) comprising a second gate; and a second control line (10312), wherein the second control line (10312) extends along the first direction (X), an orthographic projection of the second control line (10312) on the substrate (101) and an orthographic projection of the second gate on the substrate (101) having a second overlapping region formed by at least partial overlap, and the second control line (10312) and the second gate are electrically connected in the second overlapping region, the second control line (10312) is used to provide a second control signal to the second gate, and the second transistor (M2) is turned on or off under the control of the second control signal provided by the second control line (10312).

2. The display panel according to claim 1, characterized in that: The display panel comprises: an active layer (a1), a first insulating layer (a2), a first gate layer (a3), a second insulating layer (a4), a second gate layer (a5), a third insulating layer (a6), a first source-drain electrode layer (a7), a fourth insulating layer (a8) and a second source-drain electrode layer (a9) which are sequentially stacked on the base substrate (101); the active layer (a1) comprises an active pattern (a11); the first gate layer (a3) ​​comprises at least a first gate pattern (a31) and a second gate pattern (a32) arranged along a second direction (Y); the overlapping portion of the first gate pattern (a31) and the active pattern (a11) constitutes the first gate, and the overlapping portion of the second gate pattern (a32) and the active pattern (a11) constitutes the second gate; In which, the first control line (10311) and the second control line (10312) are located in the first source and drain layer (a7), the first control line (10311) and the first gate pattern (a31) are electrically connected through the first via holes in the second insulating layer (a4) and the third insulating layer (a6), and the second control line (10312) and the second gate pattern (a32) are electrically connected through the second via holes in the second insulating layer (a4) and the third insulating layer (a6).

3. The display panel according to claim 2, characterized in that: Each of the first test circuits (1031) further includes: a first signal input line (10313), a second signal input line (10314) and a first signal output line (10315); the first transistor (M1) further includes a first source and a first drain, and the second transistor (M2) further includes a second source and a second drain; The first signal input line (10313) and the second signal input line (10314) are both extended along the first direction (X), the first signal input line (10313) is electrically connected to the first source or the second source, and is used to provide a first input signal to the first source and the second source, and the second signal input line (10314) is electrically connected to the first source or the second source, and is used to provide a second input signal to the first source or the second source; The first signal output line (10315) extends along a second direction (Y), the second direction (Y) intersecting the first direction (X), the first signal output line (10315) being electrically connected to the first drain and the second drain, and the first signal output line (10315) being also connected to the plurality of sub-pixels (102), and when the first control line (10311) controls the first transistor (M1) to turn on, and the second control line (10312) controls the second transistor (M2) to turn off, the first signal output line (10315) being used to transmit an input signal received from the first drain to the plurality of sub-pixels (102), and when the first control line (10311) controls the first transistor (M1) to turn off, and the second control line (10312) controls the second transistor (M2) to turn on, the first signal output line (10315) being also used to transmit an input signal received from the second drain to the plurality of sub-pixels (102).

4. The display panel according to claim 3, characterized in that: The first signal input line (10313) and the second signal input line (10314) are located in the second source-drain layer (a9); the first signal output line (10315) is located in the second gate layer (a5); the first source-drain layer (a7) at least includes a first source-drain pattern (a71), a second source-drain pattern (a72) and a third source-drain pattern (a73) arranged along the second direction (Y); the first control line (10311) is located between the first source-drain pattern (a71) and the second source-drain pattern (a72), and the second control line (10312) is located between the second source-drain pattern (a72) and the third source-drain pattern (a73); The orthographic projection of the first source-drain pattern (a71) on the base substrate (101) at least partially overlaps with the orthographic projection of the first signal input line (10313) on the base substrate (101), and the first source-drain pattern (a71) and the first signal input line (10313) are electrically connected through a third via hole in the fourth insulating layer (a8), and the first source-drain pattern (a71) is a first source of the first transistor (M1); The orthographic projection of the second source-drain pattern (a72) on the base substrate (101) at least partially overlaps with the orthographic projection of the first signal output line (10315) on the base substrate (101), and the second source-drain pattern (a72) is electrically connected to the first signal output line (10315) through a fourth via hole in the third insulating layer (a6), and the second source-drain pattern (a72) is a first drain of the first transistor (M1) and a second drain of the second transistor (M2); The orthographic projection of the third source-drain pattern (a73) on the base substrate (101) at least partially overlaps with the orthographic projection of the second signal input line (10314) on the base substrate (101), and the third source-drain pattern (a73) and the second signal input line (10314) are electrically connected through a fifth via hole in the fourth insulating layer (a8), and the third source-drain pattern (a73) is the second source of the second transistor (M2).

5. The display panel according to claim 4, characterized in that: The orthographic projection of the first via hole on the base substrate (101) and the orthographic projection of the second via hole on the base substrate (101) are both located within the orthographic projection of the active pattern (a11) on the base substrate (101); The orthographic projection of the first gate pattern (a31) on the base substrate (101) covers the orthographic projection of the first via hole on the base substrate (101), and the orthographic projection of the second gate pattern (a32) on the base substrate (101) covers the orthographic projection of the second via hole on the base substrate (101).

6. The display panel according to claim 4, characterized in that: The orthographic projection of the first via hole on the base substrate (101) and the orthographic projection of the second via hole on the base substrate (101) do not overlap with the orthographic projection of the active pattern (a11) on the base substrate (101).

7. The display panel according to claim 6, characterized in that: The second insulating layer (a4) and the third insulating layer (a6) include at least two first via holes and two second via holes; the active pattern (a11) includes a first portion (a111) and two second portions (a112) located on both sides of the first portion (a111); the orthographic projection of the first portion (a111) on the substrate (101) partially overlaps with the orthographic projection of the first gate pattern (a31) on the substrate (101) and the orthographic projection of the second gate pattern (a32) on the substrate (101); the orthographic projection of one of the second portions (a112) on the substrate (101) partially overlaps with the orthographic projection of the first source-drain pattern (a71) on the substrate (101); and the orthographic projection of the other second portion (a112) on the substrate (101) partially overlaps with the orthographic projection of the second source-drain pattern (a72) on the substrate (101); At least two of the first via holes are arranged along the first direction (X) with the first portion (a111), and at least two of the first via holes are located on both sides of the first portion (a111); the length of the first gate pattern (a31) along the first direction (X) is greater than the length of the first portion (a111) along the first direction (X); the first gate pattern (a31) includes a first region and a second region which do not overlap with the first portion (a111) and are arranged along the first direction (X); the first control line (10311) and the first gate pattern (a31) are electrically connected in the first region and the second region respectively through at least one of the first via holes; At least two of the second vias are arranged along the first direction (X) with the first part (a111), and at least two of the second vias are located on both sides of the first part (a111), the length of the second gate pattern (a32) along the first direction (X) is greater than the length of the first part (a111) along the first direction (X), the second gate pattern (a32) includes a third area and a fourth area which do not overlap with the first part (a111) and are arranged along the first direction (X), and the second control line (10312) and the second gate pattern (a32) are electrically connected in the third area and the fourth area respectively through at least one of the second vias.

8. The display panel according to claim 6, characterized in that: The second insulating layer (a4) and the third insulating layer (a6) include at least two first via holes and two second via holes; the active pattern (a11) includes a first portion (a111) and two second portions (a112) located on both sides of the first portion (a111); the orthographic projection of the first portion (a111) on the base substrate (101) partially overlaps with the orthographic projection of the first gate pattern (a31) on the base substrate (101) and the orthographic projection of the second gate pattern (a32) on the base substrate (101); the orthographic projection of one of the second portions (a112) on the base substrate (101) overlaps with the first source portion of the first transistor (M1), and the orthographic projection of the other second portion (a112) on the base substrate (101) overlaps with the second source portion of the second transistor (M2); At least two of the first via holes are arranged along the first direction (X) with the first portion (a111), and are both located on one side of the first portion (a111); a length of the first gate pattern (a31) along the first direction (X) is greater than a length of the first portion (a111) along the first direction (X); the first gate pattern (a31) includes a fifth region that does not overlap with the first portion (a111); and the first control line (10311) and the first gate pattern (a31) are electrically connected in the fifth region through at least two of the first via holes; At least two of the second vias are arranged along the first direction (X) with the first part (a111), and are both located on one side of the first part (a111); the length of the second gate pattern (a32) along the first direction (X) is greater than the length of the first part (a111) along the first direction (X); the second gate pattern (a32) includes a sixth area that does not overlap with the first part (a111); and the second control line (10312) and the second gate pattern (a32) are electrically connected in the sixth area through at least two of the second vias.

9. The display panel according to claim 8, characterized in that: At least two of the first vias are arranged along the first direction (X), or at least two of the first vias are arranged along the second direction (Y); At least two of the second via holes are arranged along the first direction (X), or at least two of the second via holes are arranged along the second direction (Y).

10. The display panel according to any one of claims 7 to 9, characterized in that: The length of the first portion (a111) along the first direction (X) is less than or equal to the length of the second portion (a112) along the first direction (X).

11. The display panel according to any one of claims 4 to 9, characterized in that: For each of the first source-drain pattern (a71), the second source-drain pattern (a72) and the third source-drain pattern (a73), the orthographic projection of the source-drain pattern on the base substrate (101) at least partially overlaps with the orthographic projection of the active pattern (a11) on the base substrate (101), and the source-drain pattern and the active pattern (a11) are electrically connected through a sixth via hole in the first insulating layer (a2), the second insulating layer (a4) and the third insulating layer (a6).

12. The display panel according to any one of claims 1 to 9, characterized in that: The test circuit group (103) includes two first test circuits (1031) arranged along the second direction (Y); the two first test circuits (1031) share a first signal input line (10313), or the two first test circuits (1031) share a second signal input line (10314).

13. The display panel according to claim 12, characterized in that: The first signal output line (10315) in the first of the first test circuits (1031) and the first signal output line (10315) in the second of the first test circuits (1031) are respectively located on both sides of the transistors included in the two first test circuits (1031).

14. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further comprises a plurality of second test circuits, the plurality of second test circuits being located in the peripheral area (10b) and arranged along the extension direction of the boundary of the display area (10a); each of the second test circuits comprises a second signal output line; the plurality of sub-pixels (102) constitute a plurality of first pixel columns (102a) and a plurality of second pixel columns (102b), each of the first pixel columns (102a) comprising a plurality of first color sub-pixels and a plurality of second color sub-pixels, and each of the second pixel columns (102b) comprising a plurality of third color sub-pixels; The first signal output line (10315) of each of the first test circuits (1031) is connected to a plurality of first color sub-pixels and a plurality of second color sub-pixels of one of the first pixel columns (102a), and the second signal output line of each of the second test circuits is connected to a plurality of third color sub-pixels of one of the second pixel columns (102b).

15. A display device, characterized in that: The display device comprises: a power supply component (20) and a display panel (10) according to any one of claims 1 to 14; The power supply component (20) is used to supply power to the display panel (10).

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