A JTAG-based debugging system

Abstract

The application discloses a kind of based on JTAG's debugging system, including the debugging host computer, online simulator and processor internal debugging system connected in turn, the processor internal debugging system includes the debugging control module, data interaction control module and data interaction module connected in turn, control register for data interaction is configured in the data interaction control module, the debugging control module and the data interaction module are connected processor kernel or bus.The application adds data interaction control module and data interaction module in processor internal debugging system, utilizes standard JTAG signal and mainstream processor manufacturer newly added TCK_RET clock synchronization signal, in the case where chip pin is not increased, both meet the basic debugging operation of user, and provide a kind of efficient data interaction method, solve the problem that the interaction efficiency is not high when the existing processor debugging mode exists in batch data interaction.

Description

Technical Field

[0001] This invention relates to the field of JTAG debugging technology, and in particular to a JTAG-based debugging system. Background Technology

[0002] Remote cross-debugging of target processors using an in-circuit emulator based on the JTAG standard (IEEE 1149.1) has become an essential basic function for the vast majority of chips. The JTAG standard defines five basic signals—TCK, TRST, TMS, TDI, and TDO—for implementing debugging operations on the target processor.

[0003] However, as the clock speeds of target processors and in-circuit emulators continue to increase, the lack of necessary timing matching in the original JTAG standard signals leads to a decrease in stability and reliability between the in-circuit emulator and the target processor at higher frequencies. To address this, more and more processor manufacturers (ARM, TI, etc.) are adding a TCK_RET signal (the clock signal returned by the target processor to the in-circuit emulator) to the original JTAG standard signals to achieve clock adaptation between the target processor and the in-circuit emulator, thereby improving stability and reliability during debugging.

[0004] An online emulator conforming to the JTAG standard acts as the master device, driving the TAP state machine of the processor's internal debugging system via serial signals to fulfill different debugging requests from the host. The processor, acting as a slave device, passively receives serial signals from the online emulator. The processor's internal debugging system's TAP state machine switches between 16 standard states. In the Shift-DR state, TDI is input while TDO is output. Completing a single debugging operation requires the state machine to switch between multiple states, as shown in the attached diagram. Figure 1 As shown.

[0005] However, during debugging, the debugging host often needs to perform batch data interaction with the target processor through an online emulator, especially for computational processors such as digital signal processors (DSPs). During batch data read / write operations, the debugging host needs to continuously send the target address (and data) to the target processor via serial TCK, TMS, and TDI signals using the online emulator. Driven by the online emulator, the target processor continuously returns the execution results to the online emulator via TDO and TCK_RET signals. Throughout this process, the target processor is limited by the frequency of TCK and TCK_RET and the operation of the TAP state machine, resulting in low data interaction efficiency, especially low data export efficiency, which significantly impacts the user's development progress. Summary of the Invention

[0006] To address the shortcomings of existing processor debugging methods in batch data interaction, this invention proposes a JTAG-based debugging system.

[0007] A JTAG-based debugging system includes a debugging host, an online emulator, and a processor internal debugging system connected in sequence. The processor internal debugging system comprises a debugging control module, a data interaction control module, and a data interaction module connected in sequence. The data interaction control module is internally configured with a control register for data interaction. Both the debugging control module and the data interaction module are connected to the processor core or bus.

[0008] The debugging host is used to issue debugging commands or read / write data requests;

[0009] When the debugging host issues a debugging command or a single read / write data request, the online emulator and the processor's internal debugging system are in debug control mode. The online emulator converts the debugging command or single read / write data request into TDI, TMS, and TCK signals and sends them to the processor's internal debugging system. The debug control module returns the execution result to the online emulator via TDO and TCK_RET signals, and the online emulator then returns the execution result to the debugging host.

[0010] When the debugging host issues a batch read / write data request, the online emulator first configures the control register in the data interaction control module through the debugging control module. After the control register is configured, the TAP state machines of the online emulator and the processor internal debugging system are set to the initial state respectively. Then the data exchange module is enabled, and the online emulator and the processor internal debugging system switch to the data interaction mode.

[0011] In data interaction mode, the TMS signal remains high. The debug control module directly sends the received TCK and TDI signals to the data interaction module. The data interaction module returns the execution result to the online emulator through the TDO and TCK_RET signals. The online emulator then returns the execution result to the debug host until the data interaction operation is completed. When the data exchange module is turned off, the online emulator and the processor's internal debug system switch back to debug control mode.

[0012] Furthermore, the control registers used for data interaction include a start address register, a memory read / write length register, a read / write flag register, and a continuous read / write enable register; the data interaction module performs auto-incrementing addressing according to the configuration of the start address register and the memory read / write length register; and performs data interaction operations according to the configuration of the read / write flag register and the continuous read / write enable register.

[0013] Furthermore, during batch read operations, the data interaction module sends a read operation to the target address to the processor core or bus according to the configuration in the start address register and memory read / write length register. After obtaining the returned valid data, it returns the valid data to the online emulator via the TDO and TCK_RET signals. The online emulator then returns the valid data to the debugging host. During write operations, the data interaction module receives data from the online emulator via the TCK and TDI signals and writes the data to the target address according to the configuration of the control register.

[0014] Furthermore, in the data interaction mode, before and after reading and writing data, the online emulator and the processor's internal debugging system perform transmission start verification and transmission end verification respectively. The transmission start verification process is as follows: the online emulator sends a transmission start verification code to the processor's internal debugging system through TDI and TCK signals, and collects the TDO and TCK_RET signals output by the processor's internal debugging system until the collected data is the same as the transmission start verification code. The transmission end verification process is as follows: after the data read and write is completed, the data sender sends a transmission end verification code to the data receiver. After the data sender receives the transmission end verification code returned by the data receiver, the online emulator and the processor's internal debugging system switch back to the debugging control mode.

[0015] This invention adds a data interaction control module and a data interaction module to the processor's internal debugging system. By utilizing the standard JTAG signal and the TCK_RET clock synchronization signal added by mainstream processor manufacturers, it provides an efficient data interaction method without increasing the number of chip pins, thus solving the problem of low interaction efficiency in batch data interaction of existing processor debugging methods. Attached Figure Description

[0016] Figure 1 Timing diagram of JTAG signals in Shift-DR mode for debugging control;

[0017] Figure 2 This is a structural block diagram of the debugging system disclosed in this invention;

[0018] Figure 3 This is a timing diagram of the TCK, TDI, TDO, and TCK_RET signals in data interaction mode. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and design various embodiments with various modifications suitable for a particular purpose.

[0020] Example 1

[0021] A JTAG-based debugging system, such as Figure 2 As shown, the system includes a debug host, an online emulator, and a processor internal debug system connected in sequence. The processor internal debug system comprises a debug control module, a data interaction control module, and a data interaction module connected in sequence. Both the debug control module and the data interaction module are connected to the processor core or a bus (e.g., ...). Figure 2 (The AHB bus is shown in the image).

[0022] The debugging control module is an existing module in the existing processor internal debugging system. The data interaction control module and the data interaction module are new modules added by the present invention to meet the needs of batch data reading and writing. The core functions of the data interaction module include auto-incrementing addressing, data receiving and data sending, which are related to batch data reading and writing.

[0023] The data interaction control module is internally configured with a control register for data interaction. This control register can be configured according to the standard settings for batch read / write control. In this embodiment, the control register for data interaction includes a start address register, a memory read / write length register, a read / write flag register, and a continuous read / write enable register. The data interaction module performs auto-incrementing addressing based on the configuration of the start address register and the memory read / write length register; and executes data interaction operations based on the configuration of the read / write flag register and the continuous read / write enable register.

[0024] In this embodiment, both the online emulator and the processor's internal debugging system include two working modes: a basic debugging control mode and a newly added data interaction mode.

[0025] In debug control mode, the debug host sends different debug commands to the online emulator via USB or Ethernet. The online emulator converts the debug commands into TDI, TMS, and TCK signals and sends them to the processor's internal debug system. The debug control module returns the execution results to the online emulator via TDO and TCK_RET signals, and the online emulator then returns the execution results to the debug host. This is essentially consistent with existing debug methods.

[0026] In data interaction mode, the debugging host sends batch read / write data requests to the online emulator via USB or Ethernet. The online emulator recognizes the command as a data interaction operation, first configures the control register in the data interaction control module through the debugging control module, and after the control register is configured, sets the TAP state machines of the online emulator and the processor's internal debugging system to the initial state respectively, and then enables the data exchange module, and the online emulator and the processor's internal debugging system switch to data interaction mode.

[0027] In data interaction mode, the TMS signal remains high. The debug control module sends the received TCK and TDI signals directly to the data interaction module. The data interaction module returns the execution result to the online simulator through the TDO and TCK_RET signals. The online simulator then returns the execution result to the debug host until the data interaction operation is completed. When the data exchange module is turned off, the online simulator and the processor's internal debug system switch back to debug control mode.

[0028] Since both the online emulator and the processor's internal debugging system have switched to data interaction mode, there is no need to consider the operation of the TAP state machine in the debugging control module. The TCK and TCK_RET signals serve as the clock signals for data interaction, while the TDI and TDO signals serve as the data signals. Under normal circumstances, the frequency of the TCK and TCK_RET signals can be stably maintained at 50MHz during data transmission.

[0029] To ensure the reliability of data transmission, in the data interaction mode, before and after reading and writing data, the online simulator and the processor's internal debugging system respectively perform transmission start verification and transmission end verification.

[0030] The transmission start verification process is as follows: the online emulator sends a transmission start verification code (e.g., 0x5AA57BB7) to the processor's internal debugging system via TDI and TCK signals, and collects the TDO and TCK_RET signals output by the processor's internal debugging system until the collected data is the same as the transmission start verification code;

[0031] The transmission end verification process is as follows: After the data read and write is completed, the data sender sends a transmission end verification code (e.g., 0xA55AB77B) to the data receiver. After the data sender receives the transmission end verification code returned by the data receiver, the online simulator and the processor's internal debugging system switch back to the debugging control mode.

[0032] The processor's internal debugging system includes a debug control module, a data interaction control module, and a data interaction module. The debug control module is responsible for receiving all external JTAG signals and performing related operations. The data interaction control module mainly contains control registers for data interaction.

[0033] Data interaction operations are divided into batch read operations (the online emulator reads data from the processor memory in batches) and batch write operations (the online emulator writes data to the processor memory in batches). Figure 3 This is a timing diagram of the TCK, TDI, TDO, and TCK_RET signals in the data interaction mode. Data transmission is performed in units of data frames, each frame being 32 bits in size.

[0034] During the batch read operation, the data interaction module sends the read operation of the target address to the processor core or bus according to the configuration in the start address register and the memory read / write length register. After obtaining the returned valid data, the valid data is returned to the online emulator through the TDO and TCK_RET signals. The online emulator then returns the valid data to the debugging host.

[0035] During the write operation, the data interaction module receives data from the online emulator via TCK and TDI signals, and writes the data to the target address according to the configuration of the control register.

[0036] Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art and related fields based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.

Claims

1. A JTAG-based debugging system, comprising a debugging host, an online emulator, and a processor internal debugging system connected in sequence, characterized in that, The processor's internal debugging system includes a debugging control module, a data interaction control module, and a data interaction module connected in sequence. The data interaction control module is configured with a control register for data interaction. Both the debugging control module and the data interaction module are connected to the processor core or bus. The debugging host is used to issue debugging commands or read / write data requests; When the debugging host issues a debugging command or a single read / write data request, the online emulator and the processor's internal debugging system are in debugging control mode. The online emulator converts the debugging command or single read / write data request into TDI, TMS, and TCK signals and sends them to the processor's internal debugging system. The debugging control module returns the execution result to the online simulator via the TDO and TCK_RET signals, and the online simulator then returns the execution result to the debugging host. When the debugging host issues a batch read / write data request, the online emulator first configures the control register in the data interaction control module through the debugging control module. After the control register is configured, the TAP state machines of the online emulator and the processor internal debugging system are set to the initial state respectively. Then the data interaction module is enabled, and the online emulator and the processor internal debugging system switch to the data interaction mode. In data interaction mode, the TMS signal remains high. The debug control module directly sends the received TCK and TDI signals to the data interaction module. The data interaction module returns the execution result to the online emulator via the TDO and TCK_RET signals. The online emulator then returns the execution result to the debug host until the data interaction operation is completed. When the data interaction module is closed, the online emulator and the processor's internal debug system switch back to debug control mode. The control registers used for data interaction include the start address register, memory read / write length register, read / write flag register, and continuous read / write enable register; The data interaction module sends a read operation to the target address to the processor core or bus according to the configuration in the start address register and the memory read / write length register. After obtaining the returned valid data, it returns the valid data to the online emulator through the TDO and TCK_RET signals. The online emulator then returns the valid data to the debugging host. During the write operation, the data interaction module receives data from the online emulator via TCK and TDI signals, and writes the data to the target address according to the configuration of the control register.

2. The JTAG-based debugging system according to claim 1, characterized in that, The data interaction module performs auto-incrementing addressing based on the configuration of the start address register and the memory read / write length register; and performs data interaction operations based on the configuration of the read / write flag register and the continuous read / write enable register.

3. The JTAG-based debugging system according to claim 1, characterized in that, In the data interaction mode, before and after reading and writing data, the online simulator and the processor's internal debugging system respectively perform transmission start verification and transmission end verification.

4. The JTAG-based debugging system according to claim 3, characterized in that, The transmission start verification process is as follows: the online emulator sends a transmission start verification code to the processor's internal debugging system via TDI and TCK signals, and collects the TDO and TCK_RET signals output by the processor's internal debugging system until the collected data is the same as the transmission start verification code; The transmission end verification process is as follows: After the data read and write is completed, the data sender sends a transmission end verification code to the data receiver. After the data sender receives the transmission end verification code returned by the data receiver, the online simulator and the processor's internal debugging system switch back to the debugging control mode.

Images