Implementation method of spi transmission mode assignment structure

Abstract

The application relates to an implementation method of an SPI transmission mode assignment structure. An SPI controller loads data to be transmitted by a master-slave device when clock discontinuity occurs under a specific clock polarity and phase. The serial clock SCK of the SPI controller supports four kinds of timing, and the application is aimed at two kinds of timing conditions: low level when the clock is idle and rising edge sampling, and high level when the clock is idle and falling edge sampling. Under the two kinds of timing, when the transmission end first transmits data and when the clock is discontinuous, the application asynchronically loads the data to be transmitted into a transmission buffer through the structure when it is detected that a bus write control signal is valid and the SPI is not busy, so that continuous transmission of data is realized. The assignment structure of the SPI transmission end designed by the application supports all mainstream SPI transmission protocols at present, is simple in design, and meets the continuous and discontinuous data transmission of the SPI.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically a method for implementing an SPI transmit mode assignment structure. Background Technology

[0002] The Serial Peripheral Interface (SPI), developed by Motorola in 1979, is a commonly used short-range synchronous serial communication method. The SPI interface supports both half-duplex and full-duplex operation, offering the advantage of high-speed transmission at speeds up to tens of megahertz. It is typically used for high-speed connections between microcontroller systems and peripherals such as E2PROMs and ADCs.

[0003] In existing data transmission methods, when the serial clock SCK is discontinuous, the data transmission rate will decrease because the data to be transmitted cannot be preloaded quickly. Summary of the Invention

[0004] In the communication of the Serial Peripheral Interface (SPI), this invention proposes a method for asynchronously loading the data to be transmitted, i.e., an implementation method of an SPI transmission mode assignment structure, for two timing sequences: sampling data on the falling edge and transmitting data on the rising edge when the clock is high and sampling data on the rising edge and transmitting data on the falling edge when the clock is low, in the case of transmitting the first data or when the clock is discontinuous.

[0005] The SPI serial clock SCK is controlled by both clock polarity CPOL and clock phase CPHA, resulting in four possible timing relationships. CPOL set to "1" indicates SCK is high in the idle state, and set to "0" indicates SCK is low in the idle state. CPHA set to "1" indicates data is sampled and latched on the second edge of SCK, and CPHA set to "0" indicates data is sampled and latched on the first edge of SCK. When sampling and latching data on the first edge, in cases of clock discontinuity or when transmitting the first data, the data in the transmit buffer needs to be preloaded into the shift register via asynchronous setting to ensure continuous data transmission.

[0006] This invention adopts the following technical solution: The assignment structure for SPI transmission mode uses a register to load and transmit data based on an asynchronous set signal, wherein:

[0007] Reset Rstn is used to clear the shift register; it is active low.

[0008] The transmit buffer SPI_DR is used to store the next data to be transmitted;

[0009] The shift register Shift_Reg is used to shift and output the data to be sent under the control of the output edge of SCK;

[0010] Other Control Logic is used for logic control and includes control logic for CRC, DMA, and data bit width.

[0011] The shift register Shift_Reg is either shift register Shift_Reg_MTx or shift register Shift_Reg_STx;

[0012] The shift register Shift_Reg_MTx is used by the master device to shift and output the data to be sent under the control of the output edge of SCK;

[0013] The shift register Shift_Reg_STx is used to shift and output the data to be sent from the slave device under the control of the output edge of SCK;

[0014] The OtherControlLogic includes:

[0015] DFF data width, used for 8-bit or 16-bit data selection;

[0016] LSBFIRST frame format selection is used to control whether data is sent to the MSB or LSB first.

[0017] The TXE transmit buffer is empty, used for data and CRC loading control;

[0018] CRCNEXT_DMA, in DMA mode, is used to indicate that the next data to be sent is a CRC, and is used for CRC loading control;

[0019] CRCNEXT, in non-DMA mode, is used to indicate that the next data to be sent is a CRC, and is used for CRC loading control.

[0020] The asynchronous set signal includes:

[0021] The phase and polarity MO of the clock signal are used to sample data on the rising edge and transmit data on the falling edge when the clock is idle and at a low level.

[0022] The phase and polarity M3 of the clock signal are used to sample data on the falling edge when the clock is idle and high, and to send data on the rising edge.

[0023] cnt_sck_neg_s is a counter controlled by the falling edge of the device's SCK. It is cleared when it counts to 7 or 15, depending on the 8 or 16-bit width of the data.

[0024] cnt_sck_psg_s is a counter controlled by the rising edge of the SCK from the device. It is cleared when it counts to 7 or 15, depending on the data width of 8 or 16 bits.

[0025] SPI bus write signal SPI_DR_Wr;

[0026] The SPI busy signal BSY, a high level indicates that data transmission is in progress;

[0027] MSTR, when high, indicates the master device, and when low, it indicates the slave device. It is used to select the master or slave device.

[0028] The implementation method of the SPI transmit mode assignment structure for the master device includes the following steps:

[0029] When the master device sends data, it samples data on the falling edge and sends data on the rising edge when the clock is high during idle; and samples data on the rising edge and sends data on the falling edge when the clock is low during idle.

[0030] In the event of sending the first data or clock discontinuity, when a valid bus write signal is detected and the SPI is not busy, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_MTx, and then shifted and output under the control of SCK.

[0031] The implementation method of the SPI transmit mode assignment structure for slave devices includes the following steps:

[0032] When the device sends data, it samples data on the falling edge and sends data on the rising edge when the clock is high during idle; it samples data on the rising edge and sends data on the falling edge when the clock is low during idle.

[0033] When transmitting the first data or when the clock is discontinuous, if the bus write signal is detected to be valid and the values ​​of the slave device SCK rising edge counter cnt_sck_psg_s and the SCK falling edge counter cnt_sck_neg_s are both 0, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_STx, and then shifted and output under the control of SCK.

[0034] The present invention has the following beneficial effects and advantages:

[0035] 1. For SPI transmitting devices, since asynchronous setting is used, when transmitting the first data or when the clock is not continuous, the data to be transmitted in the transmit buffer can be loaded into the shift register in advance, and the data can be shifted and transmitted on the subsequent SCK transmit edge (data is transmitted on the falling edge when sampling on the rising edge, and data is transmitted on the rising edge when sampling on the falling edge).

[0036] 2. The assignment structure of the SPI transmitter designed in this invention supports all current mainstream SPI transmission protocols, is simple in design, and simultaneously satisfies both continuous and discontinuous data transmission in SPI. Attached Figure Description

[0037] Figure 1 A logic diagram of the master device transmitting data in MO and M3 modes according to the present invention;

[0038] Figure 2 This is a logic diagram illustrating the MO and M3 modes when sending data from the device. Detailed Implementation

[0039] The invention will be explained in detail below with reference to the accompanying drawings.

[0040] This invention relates to the loading of data to be transmitted by master and slave devices when the clock is discontinuous under specific clock polarity and phase of an SPI controller. The SPI controller's serial clock SCK supports four timing sequences, and this invention addresses two of these: low level with rising edge sampling during clock idle and high level with falling edge sampling during clock idle. Under these two timing sequences, in the two cases of the transmitting end transmitting data for the first time and transmitting data when the clock is discontinuous, when a valid bus write control signal is detected and the SPI is not busy, the structure asynchronously loads the data to be transmitted into the transmit buffer, thereby achieving continuous data transmission.

[0041] The assignment structure for the SPI transmission mode of this invention is an asynchronous set structure, including:

[0042] Reset Rstn, active low, is used to clear the shift register.

[0043] The transmit buffer SPI_DR is used to store the next data to be transmitted;

[0044] The shift register Shift_Reg_MTx is used by the master device to shift and output the data to be sent under the control of the output edge of SCK;

[0045] The shift register Shift_Reg_STx is used by the slave device to shift and output the data to be sent under the control of the output edge of SCK;

[0046] MSTR master or slave control;

[0047] The phase and polarity of the clock signal MO: when the clock is idle and low, data is sampled on the rising edge and transmitted on the falling edge;

[0048] The phase and polarity of the clock signal M3: when the clock is idle and at a high level, data is sampled on the falling edge and transmitted on the rising edge;

[0049] cnt_sck_neg_s is a counter controlled by the falling edge of the device's SCK. It is cleared when it counts to 7 or 15, depending on the 8-bit or 16-bit width of the data.

[0050] cnt_sck_psg_s is a counter controlled by the rising edge of the device's SCK. It is cleared when it counts to 7 or 15, depending on the data width of 8 or 16 bits.

[0051] SPI bus write signal SPI_DR_Wr;

[0052] The SPI busy signal BSY, a high level indicates that data transmission is in progress;

[0053] Other Control Logic includes Data Bit Width (DFF) for selecting 8-bit or 16-bit data; LSBFIRST frame format selection for controlling whether data is sent first (MSB or LSB); TXE transmit buffer empty flag for controlling data and CRC loading; CRCNEXT_DMA, used in DMA mode to indicate that the next data to be sent is a CRC, for CRC loading control; and CRCNEXT, used in non-DMA mode to indicate that the next data to be sent is a CRC, for CRC loading control.

[0054] The implementation steps of this invention are as follows:

[0055] When the master device transmits data, it samples data on the falling edge and transmits data on the rising edge when the clock is high during idle; it samples data on the rising edge and transmits data on the falling edge when the clock is low during idle. When transmitting the first data or when the clock is discontinuous, since there is no corresponding data transmission edge, this design employs... Figure 1 and Figure 2 The data loading method shown is such that when the bus write signal is detected to be valid and the SPI is not busy, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_MTx, and then shifted and output under the control of SCK.

[0056] When the device sends data, it samples data on the falling edge and sends data on the rising edge when the clock is high during idle; it samples data on the rising edge and sends data on the falling edge when the clock is low during idle. When sending the first data or when the clock is discontinuous, since there is no corresponding data transmission edge, this design uses... Figure 1 and Figure 2 The data loading method shown is as follows: when the bus write signal is detected to be valid and the values ​​of the rising edge counter cnt_sck_psg_s and the falling edge counter cnt_sck_neg_s of the slave device SCK are both 0, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_STx, and then shifted and output under the control of SCK.

[0057] The design concept of asynchronous setting of data to be sent at the master or slave device data sending end of this invention is as follows: Figure 1 and Figure 2The diagram shown illustrates the asynchronous setting structure of the master and slave device data transmitters. This is applicable when SPI operates in two modes (CPOL=1 or CPOL=0, CHPA=0) during the first clock edge sampling data:

[0058] When transmitting the first data or when the serial clock SCK is discontinuous, the SPI device loads the data to be transmitted from the transmit buffer into the shift register asynchronously before the sampling edge of the serial clock SCK arrives. The master device's condition is MSTR&&(M0||M3)&&SPI_DR_Wr&&! BSY: In master mode (MO or M3), when the SPI is not busy (during the first data write or when the SCK clock is discontinuous), the master loads the data to be transmitted from the transmit buffer into the shift register, thus transmitting the first bit of data (MSB or LSB). The remaining 7 or 15 bits of data are then shifted and output on the subsequent falling (or rising) edge (typically, SPI data format is 8 or 16 bits). The slave device's condition is... `MSTR&&SPI_DR_Wr(M0||M3)&&(cnt_sck_neg_s==5'd0)&&(cnt_sck_psg_s==5'd0)`: For slave devices in MO (or M3) mode, when the SPI is not busy (during the first data write or when the SCK clock is discontinuous, i.e., when both the rising and falling edge counters of SCK are 0), the data to be transmitted from the transmit buffer is loaded into the shift register, thus transmitting the first bit of data (MSB or LSB). The remaining 7 or 15 bits of data are then output on subsequent falling (or rising) edges. If CRC is used, when `CRCNEXT_DMA` or `CRCNEXT` is high, CRC data is transmitted after the last data transmission is complete.

Claims

1. An assignment structure for SPI transmission mode, characterized in that, A register is used to load and send data based on an asynchronous set signal, wherein: Reset Rstn is used to clear the shift register; it is active low. The transmit buffer SPI_DR is used to store the next data to be transmitted; The shift register Shift_Reg is used to shift and output the data to be sent under the control of the output edge of SCK; OtherControlLogic is used for logic control and includes control logic for CRC, DMA, and data bit width. The asynchronous set signal includes: The phase and polarity MO of the clock signal are used to sample data on the rising edge and transmit data on the falling edge when the clock is idle and at a low level. The phase and polarity M3 of the clock signal are used to sample data on the falling edge when the clock is idle and high, and to send data on the rising edge. cnt_sck_neg_s is a counter controlled by the falling edge of the device's SCK. It is cleared when it counts to 7 or 15, depending on the 8 or 16-bit width of the data. cnt_sck_psg_s is a counter controlled by the rising edge of the SCK from the device. It is cleared when it counts to 7 or 15, depending on the data width of 8 or 16 bits. SPI bus write signal SPI_DR_Wr; The SPI busy signal BSY, a high level indicates that data transmission is in progress; MSTR, when high, indicates a master device, and when low, it indicates a slave device. It is used to select the master or slave device. When the master device sends data, in MO or M3 mode; In the event of sending the first data or clock discontinuity, when a valid bus write signal is detected and SPI is not busy, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_MTx, and then shifted and output under the control of SCK; When sending data from the device, in MO or M3 mode; When transmitting the first data or when the clock is discontinuous, if the bus write signal is detected to be valid and the values ​​of the slave device SCK rising edge counter cnt_sck_psg_s and the SCK falling edge counter cnt_sck_neg_s are both 0, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_STx, and then shifted and output under the control of SCK.

2. The assignment structure for the SPI transmission mode according to claim 1, characterized in that, The shift register Shift_Reg is either shift register Shift_Reg_MTx or shift register Shift_Reg_STx; The shift register Shift_Reg_MTx is used by the master device to shift and output the data to be sent under the control of the output edge of SCK; The shift register Shift_Reg_STx is used to shift and output the data to be sent from the slave device under the control of the output edge of SCK.

3. The assignment structure for the SPI transmission mode according to claim 1, characterized in that, The OtherControlLogic includes: DFF data width, used for 8-bit or 16-bit data selection; LSBFIRST frame format selection is used to control whether data is sent to the MSB or LSB first. The TXE transmit buffer empty flag is used for data and CRC loading control; CRCNEXT_DMA, in DMA mode, is used to indicate that the next data to be sent is a CRC, and is used for CRC loading control; CRCNEXT, in non-DMA mode, is used to indicate that the next data to be sent is a CRC, and is used for CRC loading control.

4. A method for implementing the SPI transmission mode assignment structure, wherein the method is applied to the SPI transmission mode assignment structure described in claim 1, characterized in that, For use with the main device, the following steps are included: When the master device sends data, it samples data on the falling edge and sends data on the rising edge when the clock is high during idle; and samples data on the rising edge and sends data on the falling edge when the clock is low during idle. In the event of sending the first data or clock discontinuity, when a valid bus write signal is detected and the SPI is not busy, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_MTx, and then shifted and output under the control of SCK.

5. A method for implementing an SPI transmission mode assignment structure, wherein the method is applied to the SPI transmission mode assignment structure described in claim 1, characterized in that, For use with the device, the following steps are included: When sending data from the device, if the clock is high during idle time, data is sampled on the falling edge and sent on the rising edge; if the clock is low during idle time, data is sampled on the rising edge and sent on the falling edge. When transmitting the first data or when the clock is discontinuous, if the bus write signal is detected to be valid and the values ​​of the slave device SCK rising edge counter cnt_sck_psg_s and the SCK falling edge counter cnt_sck_neg_s are both 0, the data in the transmit buffer SPI_DR is asynchronously loaded into the shift register Shift_Reg_STx, and then shifted and output under the control of SCK.

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