Display device and data processing method thereof

Abstract

A display device includes: a display panel including a first surface containing a first pixel and a second surface containing a second pixel, the first surface contacting the second surface at its center; a first source integrated circuit (IC) sequentially latching first image data to be applied to the first surface at a panel edge of the first surface along a first direction facing the center of the panel; and a second source IC sequentially latching second image data to be applied to the second surface at a panel edge of the second surface along a second direction facing the center of the panel, wherein the first direction is opposite to the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0086961, filed on July 2, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device and a data processing method thereof. Background Technology

[0004] As the resolution and size of display devices increase, the amount of digital data transmitted from the timing controller to the source integrated circuit for image display also increases. With this increase in data transmission, existing display devices suffer from electromagnetic interference (EMI) and increased power consumption. Summary of the Invention

[0005] To overcome the aforementioned problems of the prior art, this disclosure provides a display device and its data processing method that reduces the bandwidth of data transmitted between a timing controller and a source integrated circuit, thereby minimizing EMI and power consumption.

[0006] To achieve these and other advantages, and for the purposes of this disclosure, as specifically implemented and broadly described herein, a display device includes: a display panel including a first surface containing a first pixel and a second surface containing a second pixel, the first surface contacting the second surface at its center; a first source integrated circuit (IC) sequentially latching first image data to be applied to the first surface at a panel edge on the first surface along a first direction facing the center of the panel; and a second source IC sequentially latching second image data to be applied to the second surface at a panel edge on the second surface along a second direction facing the center of the panel, wherein the first direction is opposite to the second direction.

[0007] In another aspect of this disclosure, a data processing method for a display device includes a display panel comprising a first surface containing a first pixel and a second surface containing a second pixel, the first surface contacting the second surface at its center, the method comprising sequentially latching first image data to be applied to the first surface at a panel edge of the first surface along a first direction facing the center of the panel, and sequentially latching second image data to be applied to the second surface at a panel edge of the second surface along a second direction facing the center of the panel, wherein the first direction is opposite to the second direction. Attached Figure Description

[0008] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and forming part of this application, illustrate (multiple) embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0009] Figure 1 This is a view illustrating a display device according to an embodiment of the present disclosure;

[0010] Figure 2 It is shown Figure 1 A view of the data transmission format between the timing controller and the source integrated circuit (IC) in a display device;

[0011] Figure 3 This is a view illustrating a source IC according to an embodiment of the present disclosure;

[0012] Figure 4 and Figure 5 It is used to describe in Figure 2 A view of the first latch operation performed in the source IC;

[0013] Figure 6 This is a view showing the first and second source ICs for surface-partitioned driving of the display panel, as well as the output delay and latching direction of each of the first and second source ICs;

[0014] Figure 7 It is a view used to describe a first latching operation on first image data to be applied to a first surface of a display panel;

[0015] Figure 8 It is a view used to describe the second latching operation and the first analog output operation of the first image data to be applied to the first surface of the display panel;

[0016] Figure 9 This is a view showing an example of performing normal latching operations on the first surface of the display panel without latching conflicts despite shortening the horizontal blank period;

[0017] Figure 10 It is a view used to describe the first latching operation of second image data to be applied to the second surface of the display panel;

[0018] Figure 11 It is a view used to describe a second latching operation and a second analog output operation of second image data to be applied to a second surface of a display panel;

[0019] Figure 12 This is a view showing an example of performing normal latching operations on the second surface of the display panel without latching conflicts despite shortening the horizontal blanking period;

[0020] Figure 13A This is a view illustrating an example of performing each of the second latch operation and the analog output operation simultaneously on multiple channels;

[0021] Figure 13B This is a view showing an example of performing each of the second latch operation and the analog output operation sequentially on multiple channels;

[0022] Figure 14 and Figure 15 This is a view illustrating the latch conflict (or latch error) operation that occurs when the horizontal blanking period is shortened in the comparative example of this embodiment;

[0023] Figure 16 This is a view showing an example of performing a first latching operation and a second latching operation according to this embodiment on each of the first and second surfaces in the same direction; and

[0024] Figure 17 This is a view illustrating an example of how, when the horizontal blanking period is shortened, the transmission frequency and bandwidth decrease as the high-period data enable signal increases. Detailed Implementation

[0025] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the disclosure to those skilled in the art.

[0026] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0027] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary and are not limited thereto. The same reference numerals always denote the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms “comprising,” “having,” “including,” etc., imply that additional parts may be added, unless the term “only” is used. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0028] Elements in the various embodiments of this disclosure should be interpreted as including error tolerances, even if not explicitly stated otherwise.

[0029] When describing positional relationships, for example, when the positional relationship between two parts is described as "on ~", "above ~", "below ~", and "next ~", one or more other parts may be positioned between the two parts unless "only" or "directly" is used.

[0030] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] In the following description, detailed descriptions of relevant known functions or configurations will be omitted where such descriptions would unnecessarily obscure important aspects of this disclosure. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a view illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A view of the data transmission format between the timing controller and the source integrated circuit (IC) in a display device.

[0033] This invention can be applied to flat panel display devices, such as liquid crystal display (LCD) devices, field emission display (FED) devices, plasma display panels (PDP), organic light-emitting diode (OLED) display devices, and inorganic light-emitting diode (OLED) display devices, but is not limited thereto. This invention can also be applied to bendable display devices, foldable display devices, rollable display devices, flexible display devices, etc. In the following description, organic light-emitting diode (OLED) display devices will be used as an example, but this invention is not limited to OLED display devices. Furthermore, this invention is not limited to the terminology used for the elements described in the claims. The various terms "circuit" described in the claims are not limited to hardware and can also refer to "logic" performing the corresponding function.

[0034] refer to Figure 1 The display device according to embodiments of this disclosure may include a display panel PNL, a timing controller TCON, a source integrated circuit (IC) SDIC, and a gate driver GDRV. The timing controller TCON and the source IC SDIC can be connected to each other via an embedded panel interface (EPI) device.

[0035] The display panel PNL may include a pixel array for displaying an input image. The pixel array may include multiple pixels arranged in a matrix type based on a cross structure of multiple data lines DL and multiple gate lines GL. Each of the multiple pixels may include a red (R) pixel, a green (G) pixel, and a blue (B) pixel for implementing the color, and may also include a white (W) pixel.

[0036] Each sub-pixel may include a light-emitting device, a driving element, a switching element, and a storage element. Internal and external compensation techniques can be applied to compensate for driving characteristic deviations between sub-pixels associated with the light-emitting device and / or driving element. Internal compensation techniques compensate for the driving current flowing in the light-emitting device by using compensation circuitry included in each sub-pixel, regardless of changes in the characteristics of the driving element. In external compensation techniques, sensing circuitry located outside the display panel PNL can sense changes in the driving characteristics of the light-emitting device and / or driving element of each sub-pixel, and the compensation circuitry can correct the image data to be applied to each sub-pixel to compensate for the sensed driving characteristic changes.

[0037] The pixel array may also include multiple touch sensors for implementing a touch user interface (UI). The touch sensors may be implemented as capacitive touch sensors that sense touch input based on changes in capacitance before and after a touch is applied to the touch sensor, but are not limited to this.

[0038] The timing controller TCON can receive digital image data and timing signals from the host system. These timing signals include a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal. The timing controller TCON can generate timing control signals based on these timing signals to control the operation timing of the source driver SDIC and the gate driver GDRV. The timing control signals can include source timing control signals for controlling the operation timing of the source driver SDIC and gate timing control signals for controlling the operation timing of the gate driver GDRV. The source timing control signals can include a source output enable signal (see...). Figure 3 SOE) and latch control signals (see Figure 6 LbR and DLYLR).

[0039] The timing controller TCON can be connected to the source driver SDIC via a clock embedding interface device based on a point-to-point encoding scheme, and can transmit data transmission packets including R, G, B, and W image data DATA to the source driver SDIC. In the clock embedding interface device, because the R, G, B, and W image data DATA and the clock are included in the data transmission packet and transmitted over a single transmission line, a separate clock transmission line can be omitted in high-resolution and large-size display devices, and the number of transmission lines can be easily reduced. In the data transmission packet, the clock may not be synchronized with the R, G, B, and W image data DATA, and may only contain conversion information for recovery by the receiving circuitry; therefore, in terms of transmission limitations, the clock embedding type may be superior to the clock separation type. The clock embedding interface device may include transmission circuitry, a transmission line, and receiving circuitry; the transmission circuitry can be embedded in the timing controller TCON, and the receiving circuitry can be embedded in the source driver SDIC.

[0040] The transmission circuit can encode the scrambled clock-embedded image data and clock-embedded blanking data, and can transmit data transmission packets encoded in serial data format to the receiving circuit through multiple transmission lines. The clock-embedded blanking data may include a clock training mode (CTP) corresponding to the blanking period.

[0041] Furthermore, the data transmission packet from the transmitting circuit to the receiving circuit may also include control packet data (CTR). The control packet data CTR can be allocated to a blanking period. The blanking period can be the logic low period of the data enable signal DE. The logic low period of the data enable signal DE can be the valid period to which the clock-embedded image data is allocated. The control packet data CTR may include a gate timing control signal for controlling the operating timing of the gate driver GDRV and a source timing control signal for controlling the operating timing of the source IC SDIC. The gate timing control signal and the source timing control signal can be recovered by the receiving circuit.

[0042] The source driver SDIC can recover R, G, B, and W image data DATA and source timing control signals SOE, LbR, and DLYLR. Based on the source timing control signals SOE, LbR, and DLYLR, it latches and gamma-compensates the R, G, B, and W image data DATA, and outputs the gamma-compensated image data to the data line DL. The data voltage output to the data line DL can be applied to the pixel synchronously with the scan signal provided through the gate line GL. The source driver SDIC can recover the gate timing control signal and can provide the recovered gate timing control signal to the gate driver GDRV via a separate signal line.

[0043] The gate driver GDRV can generate a scan signal that oscillates between a gate on-voltage and a gate off-voltage based on a gate timing control signal. The gate on-voltage can be the voltage used to turn on the switching element of each sub-pixel, and the gate off-voltage can be the voltage used to turn off the switching element of each sub-pixel. The gate driver GDRV can sequentially or non-sequentially output the scan signal to the gate line GL to select a sub-pixel, and the data voltage will be charged into the sub-pixel in units of horizontal rows.

[0044] The gate driver (GDRV) can be positioned in a non-display area outside the pixel array in the display panel (PNL). The GDRV can be designed based on a dual-row scheme to minimize RC delay deviation at each panel position corresponding to the same scan signal. According to the dual-row scheme, the GDRV can be positioned in two non-display areas with a pixel array between them.

[0045] Figure 3 This is a view illustrating a source IC SDIC according to an embodiment of the present disclosure. Figure 4 and Figure 5 It is used to describe in Figure 2 A view of the first latch operation performed in the source IC.

[0046] refer to Figures 3 to 5 The source IC SDIC may include a receiver circuit RX, a parallelization circuit S2P, a shift register SR, a first latch circuit LAT1, a second latch circuit LAT2, a digital-to-analog converter DAC, and an output circuit OTC.

[0047] The receiving circuit RX may include clock and data recovery (CDR) circuitry for recovering clock information from data transmission packets. The CDR circuitry receives data transmission packets via a transmission line and tracks the transition patterns of the data transmission packets to recover the clock information included in the data transmission packets. For this purpose, the CDR circuitry may use a phase-locked loop (PLL) or a delay-locked loop (DLL). The receiving circuitry RX may decode the data transmission packets based on the clock information recovered by the CDR circuitry and may descramble the decoded data to recover the R, G, B, and W image data DATA, as well as the source timing control signals SOE, LbR, and DLYLR.

[0048] The shift register SR can generate sampling reference clocks CLK1 to CLK192 based on predetermined internal clock timing signals CLK and SSP. The shift register SR can be implemented using D-type flip-flops, but is not limited to this.

[0049] The parallelization circuit S2P can sample the recovered R, G, B and W image data DATA based on the sampling reference clocks CLK1 to CLK192, and can convert each of the sampled R, G, B and W image data DATA into a parallel data format.

[0050] The first latch circuit LAT1 can sequentially store R, G, B, and W image data DATA, converted to parallel data format, into a data register based on the first latch control signal LbR (hereinafter referred to as the first latch operation). The first latch control signal LbR determines the direction of execution of the first latch operation. The first latch operation can be executed sequentially in a first direction from channel 1 to channel 768, or it can be executed sequentially in a second direction from channel 768 to channel 1. Figure 5 An example of performing a first latching operation along a first direction is shown.

[0051] The second latch circuit LAT2 can sequentially output the R, G, B, and W image data DATA stored in the data register to the digital-to-analog converter DAC based on the second latch control signal DLYLR and the source output enable signal SOE (hereinafter referred to as the second latch operation). The second latch control signal DLYLR determines the direction of execution of the second latch operation. The direction of execution of the second latch operation can be matched with the direction of increase of the output delay of the digital-to-analog converter DAC. The second latch operation can be executed sequentially in a first direction from channel 1 to channel 768, or sequentially in a second direction from channel 768 to channel 1.

[0052] A digital-to-analog converter (DAC) can map the R, G, B, and W image data (DATA) input from the data register to a gamma-compensated voltage (GMA) to generate the data voltage.

[0053] The output circuit OTC may include multiple output buffers, each corresponding to a data line. Each output buffer can be connected to the corresponding data line via a channel and can output the data voltage, which is the analog output of the digital-to-analog converter (DAC), to the corresponding data line based on the source output enable signal SOE. The output buffer can output the data voltage to the data line during the logic low period of the source output enable signal SOE. Moreover, the connection between the output buffer and the data line can be released during the logic low period of the source output enable signal SOE.

[0054] Figure 6 This is a view showing the first and second source ICs for surface-partitioned driving of the display panel, as well as the output delay and latching direction of each of the first and second source ICs.

[0055] refer to Figure 6The display panel may include a first surface having a first pixel and a second surface having a second pixel, wherein the first surface may contact the second surface at the center of the panel. The first surface may be positioned on the left side relative to the center of the panel, and the second surface may be positioned on the right side relative to the center of the panel.

[0056] The first source IC and the second source IC can drive the display panel in a surface-separated manner. The first source IC may include multiple left source ICs SDIC, which are disposed on the rear surface of the panel and drive the first surface, and the second source IC may include multiple right source ICs SDIC, which are disposed on the rear surface of the panel and drive the second surface.

[0057] The first source IC can sequentially latch first image data to be applied to the first surface along a first direction DIR1 from the edge of the first surface to the center of the first surface. The second source IC can sequentially latch second image data to be applied to the second surface along a second direction DIR2 from the edge of the second surface to the center of the second surface. Here, the first direction DIR1 may be the opposite of the second direction DIR2.

[0058] The output delay of the first source IC can be increased in the first direction DIR1, and the output delay of the second source IC can be increased in the second direction DIR2. The output delay of the source IC can be associated with the RC delay of the scan signal. The RC delay of the same scan signal in the first surface can be increased in the first direction DIR1, and the RC delay of the same scan signal in the second surface can be increased in the second direction DIR2.

[0059] In the first source IC, the first latch operation and the second latch operation can be executed on the first direction DIR1 with a specific time difference between them, thus preventing latch conflicts for the same channel. Specifically, based on the first latch control signal LbR with a high logic value H, the first latch operation can be sequentially executed on the first image data on the first direction DIR1, and then the second latch operation can begin with a specific time difference relative to the start timing of the first latch operation. Based on the second latch control signal DLYLR with a high logic value H, the second latch operation can be sequentially executed on the first image data on the first direction DIR1.

[0060] In the second source IC, the first latch operation and the second latch operation can be executed on the second direction DIR2 with a specific time difference between them, thus preventing latch conflicts for the same channel. Specifically, based on the first latch control signal LbR with a low logic value L, the first latch operation can be sequentially executed on the second image data on the second direction DIR2, and then the second latch operation can begin with a specific time difference relative to the start timing of the first latch operation. Based on the second latch control signal DLYLR with a low logic value L, the second latch operation can be sequentially executed on the second image data on the second direction DIR2.

[0061] Figure 7 It is a view used to describe the first latching operation of the first image data to be applied to the first surface of the display panel. Figure 8 It is a view used to describe the second latching operation and the first analog output operation of the first image data to be applied to the first surface of the display panel. Figure 9 This is a view showing an example of performing normal latching operations on the first surface of the display panel without latching conflicts despite shortening the horizontal blanking period.

[0062] refer to Figure 7 and 8 The first source IC can sequentially store the kth first image data of the kth horizontal row (where k is a natural number) to be applied to the first surface along the first direction in the first high period of the data enable signal DE into the first data register (kth first latch operation). Subsequently, the first source IC can sequentially store the (k+1)th first image data of the (k+1)th horizontal row to be applied to the first surface along the first direction in the second high period after the first high period of the data enable signal DE into the first data register (k+1st first latch operation).

[0063] Furthermore, the first source IC can sequentially output the kth first image data stored in the first data register to the first digital-to-analog converter (kth second latch operation) in the first direction during the low period between the first high period and the second high period when the data enable signal DE is arranged.

[0064] As described above, the first latch operation and the second latch operation performed by the first source IC can be performed along the same first direction from the first channel Ch1 to the nth channel Chn. In this case, because the first latch operation and the second latch operation are performed on the first image data to be applied to the same horizontal row in a manner with a specific time difference between them, normal latch operation can be performed without latch conflict.

[0065] In addition, such as Figure 9As shown, even when the horizontal blanking period H is shortened, normal latching operations can be performed because the first latching timing and the second latching timing applied to the first image data of the same horizontal row intersect each other about the same horizontal row. The horizontal blanking period H can be the low period of the data enable signal DE. When the horizontal blanking period H is shortened, it can be as follows: Figure 9 Adjust the source output enable signal SOE as described above. Here, the high period of the data enable signal DE can be the latch enable period, and the low period of the source output enable signal SOE can be the analog output enable period.

[0066] refer to Figure 9 At least a portion of the low period of the data enable signal DE can overlap with the high period of the source output enable signal SOE. In this case, during the low period of the source output enable signal SOE following the high period of the source output enable signal SOE, the first analog output of the first digital-to-analog converter (e.g., the first analog output of the kth first image data) can be executed sequentially in the first direction.

[0067] refer to Figure 9 The first source IC can also perform a second latch operation in some portions TX1 to TX2 of the first high period of the data enable signal DE approaching the low period of the data enable signal DE, and in the portion of the second high period of the data enable signal DE approaching the low period. That is, the first source IC can sequentially and further output the kth first image data stored in the first data register to the first digital-to-analog converter along a first direction in a portion of each of the first and second high periods.

[0068] In this scenario, during certain portions of the first peak time period (TX1 to TX2), a first latch operation that sequentially stores the kth first image data in the first data register and a second latch operation that sequentially outputs the kth first image data to the first digital-to-analog converter can be performed simultaneously without conflict. Furthermore, during the second peak time period, a first latch operation that sequentially stores the (k+1)th first image data in the first data register and a second latch operation that sequentially outputs the kth first image data to the first digital-to-analog converter can be performed simultaneously without conflict.

[0069] refer to Figures 7 to 9When the horizontal axis represents the panel position in the first direction and the vertical axis represents time, the first curve for timing the first latch operation at the panel position and the second curve for timing the second latch operation at the panel position can rise to the right and upward with time. This can be because the first and second latch operations are performed in the same first direction. In this case, because the high period of the source output enable signal SOE is shorter than the high period of the data enable signal DE, the slope of the first curve can be different from the slope of the second curve. This can be because the slope of the second curve is determined based on the slope of the "HiZ On" operation performed at each panel position during the high period of the source output enable signal SOE. The "HiZ On" operation can be performed sequentially in the first direction and can float the corresponding channel before the second latch operation.

[0070] Figure 10 It is a view used to describe the first latching operation of second image data to be applied to the second surface of the display panel. Figure 11 It is a view used to describe the second latching operation and the second analog output operation of the second image data to be applied to the second surface of the display panel. Figure 12 This is a view showing an example of performing normal latching operations on the second surface of the display panel without latching conflicts despite shortening the horizontal blanking period.

[0071] refer to Figure 10 and 11 The second source IC can sequentially store the kth second image data of the kth horizontal row (where k is a natural number) to be applied to the second surface along the second direction in the first high period of the data enable signal DE into the second data register (kth first latch operation). Subsequently, the second source IC can sequentially store the (k+1)th second image data of the (k+1)th horizontal row to be applied to the second surface along the second direction in the second high period after the first high period of the data enable signal DE into the second data register (k+1st first latch operation).

[0072] Furthermore, the second source IC can sequentially output the kth second image data stored in the second data register to the second digital-to-analog converter (kth second latch operation) in the second direction during the low period between the first high period and the second high period when the data enable signal DE is arranged.

[0073] As described above, the first latch operation and the second latch operation performed by the second source IC can be performed along the same second direction from the first channel Ch1 to the nth channel Chn. In this case, because the first latch operation and the second latch operation are performed on the second image data to be applied to the same horizontal row in a manner with a specific time difference between them, normal latch operation can be performed without latch conflict.

[0074] In addition, such as Figure 12 As shown, even when the horizontal blanking period H is shortened, normal latching operations can be performed because the first latching timing and the second latching timing applied to the second image data of the same horizontal row intersect each other about the same horizontal row. The horizontal blanking period H can be the low period of the data enable signal DE. When the horizontal blanking period H is shortened, it can be as follows: Figure 12 Adjust the source output enable signal SOE as described above. Here, the high period of the data enable signal DE can be the latch enable period, and the low period of the source output enable signal SOE can be the analog output enable period.

[0075] refer to Figure 12 At least a portion of the low period of the data enable signal DE can overlap with the high period of the source output enable signal SOE. In this case, during the low period of the source output enable signal SOE following the high period of the source output enable signal SOE, the second analog output of the second digital-to-analog converter (e.g., the second analog output of the kth second image data) can be executed sequentially in the second direction.

[0076] refer to Figure 12 The second source IC can also perform the kth second latch operation in some portions TX1 to TX2 of the first high period of the data enable signal DE approaching the low period of the data enable signal DE, and in the portion of the second high period of the data enable signal DE approaching the low period. That is, the second source IC can sequentially and further output the kth second image data stored in the second data register to the second digital-to-analog converter along the second direction in a portion of each of the first and second high periods.

[0077] In this scenario, during certain portions of the first peak time period (TX1 to TX2), a first latch operation that sequentially stores the kth second image data in the second data register and a second latch operation that sequentially outputs the kth second image data to the second digital-to-analog converter can be performed simultaneously without conflict. Furthermore, during the second peak time period, a first latch operation that sequentially stores the (k+1)th second image data in the second data register and a second latch operation that sequentially outputs the kth second image data to the second digital-to-analog converter can be performed simultaneously without conflict.

[0078] refer to Figures 10 to 12 When the horizontal axis represents the panel position in the second direction and the vertical axis represents time, the first curve for timing the first latch operation at the panel position and the second curve for timing the second latch operation at the panel position can rise to the left and upward with time. This can be because the first and second latch operations are performed along the same second direction. In this case, because the high period of the source output enable signal SOE is shorter than the high period of the data enable signal DE, the slope of the first curve can be different from the slope of the second curve. This can be because the slope of the second curve is determined based on the slope of the "HiZ On" operation performed at each panel position during the high period of the source output enable signal SOE. The "HiZ On" operation can be performed sequentially along the second direction and can float the corresponding channel before the second latch operation.

[0079] Figure 13A This is a view showing an example of performing each of the second latch operation and the analog output operation simultaneously on multiple channels. Figure 13B This is a view showing an example of performing each of the second latch operation and the analog output operation sequentially on multiple channels.

[0080] refer to Figure 13A The second latching operation and analog output operation described above can be performed simultaneously on multiple channels with a specific time difference between them. In this case, the peak EMI noise may increase.

[0081] On the other hand, in the embodiments of this disclosure, the following can be applied: Figure 13B A time-division scheme is used to reduce EMI peak noise.

[0082] refer to Figure 13B The second latching operation and analog output operation described above can be performed sequentially based on multiple channels with specific time differences between them. The second latching operation can be performed sequentially based on multiple channels with time intervals ranging from approximately tens to hundreds of nanoseconds. Furthermore, the analog output operation can be performed sequentially based on multiple channels with time intervals ranging from approximately tens to hundreds of nanoseconds. Therefore, EMI peak noise can be significantly reduced.

[0083] Figure 14 and Figure 15 This is a view illustrating a latch conflict (or latch error) operation that occurs when the horizontal blanking period is shortened in a comparative example of this embodiment.

[0084] exist Figure 14 and Figure 15In the comparative example, the first latch control signal LbR used to drive the first surface of the display panel and the first latch control signal LbR used to drive the second surface of the display panel can both be set to a low logic value L, the second latch control signal DLYLR used to drive the first surface of the display panel can be set to a high logic value H, and the second latch control signal DLYLR used to drive the second surface of the display panel can be set to a low logic value L.

[0085] Based on the first latch control signal LbR with a low logic value L, a first latch operation on the first image data of the first surface and a first latch operation on the second image data of the second surface can be sequentially executed along the second direction (from CHn to Ch1), and thus, the first curve of the timing of the first latch operation at the connection panel position can rise to the left and up in the first and second surfaces.

[0086] Based on the second latch control signal DLYLR with a high logic value H, a second latch operation on the first image data of the first surface can be sequentially performed along the first direction (from Ch1 to Chn), and therefore, the second timing curve of the second latch operation at the connection panel position can rise to the right and upward in the first surface. On the other hand, based on the second latch control signal DLYLR with a low logic value L, a second latch operation on the second image data of the second surface can be sequentially performed along the second direction, and therefore, the second timing curve of the second latch operation at the connection panel position can rise to the left and upward in the second surface.

[0087] For the purpose of providing a summary description, the first graph and the second graph may have slopes in opposite directions on the first surface and slopes in the same direction on the second surface.

[0088] When the horizontal blanking period H of the data enable signal DE is longer during its low-period phase, the bandwidth of the data transmitted between the timing controller and the source IC increases. This may be because image data is transmitted during the high-period phase of the data enable signal DE.

[0089] To reduce the bandwidth of transmitted data, the horizontal blanking period H should be shortened. However, when the horizontal blanking period H is shortened, latching conflicts may occur because the first curve and the second curve intersect on the first surface. Since the first latching time for the (k+1)th first image data in the same channel is before the second latching time for the kth first image data, latching conflicts may also occur. When a latching conflict occurs, the (k+1)th first image data may be output abnormally instead of the kth first image data.

[0090] As a result, Figure 14 and Figure 15In the comparative example, because the first curve and the second curve have slopes in opposite directions on the first surface, it may be difficult to shorten the horizontal blanking period H blanking.

[0091] Figure 16 This is a view showing an example of performing a first latching operation and a second latching operation according to this embodiment in the same direction on each of the first and second surfaces.

[0092] refer to Figure 16 The first latching operation and the second latching operation can be performed in the same direction on the first surface and the second surface of the display panel. For this purpose, the first latching control signal LbR and the second latching control signal DLYLR used to drive the first surface of the display panel can both be set to a high logic value H, and the first latching control signal LbR and the second latching control signal DLYLR used to drive the second surface of the display panel can both be set to a low logic value L.

[0093] Based on a first latch control signal LbR having a low logic value L, a first latch operation on the first image data of the first surface can be sequentially executed along a first direction (from Ch1 to Chn), and therefore, the first timing curve of the first latch operation at the connected panel location can rise to the right and upward. Furthermore, based on a second latch control signal DLYLR having a low logic value L, a second latch operation on the first image data of the first surface can be sequentially executed along the first direction, and therefore, the second timing curve of the second latch operation at the connected panel location can also rise to the right and upward on the second surface.

[0094] On the other hand, based on the first latch control signal LbR with a low logic value L, a first latch operation on the second image data of the second surface can be sequentially executed along the second direction (from CHn to Ch1), and therefore, the first timing curve of the first latch operation at the connection panel position can rise to the left and upward. Furthermore, based on the second latch control signal DLYLR with a low logic value L, a second latch operation on the second image data of the second surface can be sequentially executed along the second direction, and therefore, the second timing curve of the second latch operation at the connection panel position can also rise to the left and upward on the second surface.

[0095] For the purpose of providing a summary description, the first graph and the second graph may have slopes in the same direction on the first surface and may have slopes in the same direction on the second surface.

[0096] In this embodiment, even when the horizontal blanking period H is shortened for blanking, the first curve may not intersect with the second curve within the first surface, and the first curve may also not intersect with the second curve within the second surface. Therefore, in this embodiment, the latching conflict that occurred in the comparative example described above may not occur.

[0097] Figure 17 This is a view illustrating an example of how, when the horizontal blanking period is shortened, the transmission frequency and bandwidth decrease as the high-period data enable signal increases.

[0098] refer to Figure 17 In this embodiment, Case 2 can be applied to reduce the bandwidth of transmitted data. In this embodiment, the horizontal blanking period H can be shorter than in Case 1. As described above, even when Case 2 is applied, this embodiment can prevent latching errors.

[0099] In this embodiment, even when the amount of data transmitted between the timing controller and the source IC increases, the bandwidth of the transmitted data can be reduced without latching errors, thereby minimizing EMI and power consumption.

[0100] This embodiment can achieve the following effects.

[0101] In this embodiment, for multiple channels, the sequential execution direction of the first latch operation performed on the image data can be matched with the sequential execution direction of the second latch operation performed on the image data. Here, for the same channel, the first latch operation can be performed a specific time difference earlier than the second latch operation. Therefore, even when the horizontal blanking period is shortened, the first latch timing and the second latch timing applied to the first image data of the same horizontal row can be non-intersecting for the same channel, and thus, normal latching operations can be performed without latching errors. When the horizontal blanking period is shortened, the bandwidth of the data transmitted between the timing controller and the source IC can be reduced. As a result, in this embodiment, even when the amount of data transmitted between the timing controller and the source IC increases, the bandwidth of the transmitted data is reduced without latching errors, and therefore, EMI and power consumption can be minimized.

[0102] Furthermore, in this embodiment, the sequential execution direction of the first latch operation and the sequential execution direction of the second latch operation performed on the image data can be matched with the direction of the increase in the output delay of the source IC, and thus the data charging deviation at each panel position can be minimized.

[0103] Furthermore, in this embodiment, for multiple channels, the second latch operation can be performed sequentially based on a time-division scheme, and thus, the EMI peak noise can be reduced.

[0104] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0105] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A display device, comprising: The display panel has a first surface including a first pixel and a second surface including a second pixel, wherein the first surface contacts the second surface at the center of the panel. A first source integrated circuit (IC) sequentially latches first image data to be applied to the first surface at the edge of the panel along a first direction facing the center of the panel. as well as The second source IC sequentially latches the second image data to be applied to the second surface at the edge of the panel along a second direction facing the center of the panel. Wherein, the first direction is opposite to the second direction, and Among them, the first source IC During the first high-period of the data enable signal, along the first direction, the kth first image data of the kth horizontal row to be applied to the first surface is sequentially stored in the first data register, where k is a natural number. During the second high period following the first high period of the data enable signal, along the first direction, the (k+1)th first image data of the (k+1)th horizontal row to be applied to the first surface is sequentially stored in the first data register, and During the low period between the first high period and the second high period, the data enable signal is arranged along the first direction, and the kth first image data stored in the first data register is sequentially output to the first digital-to-analog converter.

2. The display device according to claim 1, wherein, The latching operation performed on the first source IC of the first image data includes a first latching operation and a second latching operation performed sequentially along the first direction, and The latching operation of the second source IC performed on the second image data includes a first latching operation and a second latching operation performed sequentially along the second direction.

3. The display device according to claim 1, wherein, The output delay of the first source IC increases along the first direction, and The output delay of the second source IC increases along the second direction.

4. The display device according to claim 1, wherein, The first source IC sequentially and further outputs the kth first image data stored in the first data register to the first digital-to-analog converter along the first direction during the portion of the first high period close to the low period and the portion of the second high period close to the low period.

5. The display device according to claim 4, wherein, During the first high-period segment, a first latch operation is performed simultaneously to sequentially store the kth first image data in the first data register and a second latch operation is performed to sequentially output the kth first image data to the first digital-to-analog converter.

6. The display device according to claim 4, wherein, During the second high-period segment, a first latch operation is performed simultaneously to sequentially store the (k+1)th first image data in the first data register and a second latch operation is performed to sequentially output the kth first image data to the first digital-to-analog converter.

7. The display device according to claim 5 or 6, wherein, When the horizontal axis represents the panel position along the first direction and the vertical axis represents time, the first curve for timing the first latch operation at the panel position and the second curve for timing the second latch operation at the panel position rise to the right and upward with time.

8. The display device according to claim 7, wherein, The slope of the first curve is different from the slope of the second curve.

9. The display device according to claim 1, wherein, The second source IC During the first high-period of the data enable signal, along the second direction, the kth second image data of the kth horizontal row to be applied to the second surface is sequentially stored in the second data register, where k is a natural number. During the second high period following the first high period of the data enable signal, along the second direction, the (k+1)th second image data of the (k+1)th horizontal row to be applied to the second surface is sequentially stored in the second data register, and During the low period between the first high period and the second high period, the data enable signal is arranged along the second direction, and the kth second image data stored in the second data register is sequentially output to the second digital-to-analog converter.

10. The display device according to claim 9, wherein, The second source IC sequentially and further outputs the kth second image data stored in the second data register to the second digital-to-analog converter along the second direction during the portion of the first high period close to the low period and the portion of the second high period close to the low period.

11. The display device according to claim 10, wherein, During the first high-period segment, a first latch operation is performed simultaneously to sequentially store the kth second image data in the second data register and a second latch operation is performed to sequentially output the kth second image data to the second digital-to-analog converter.

12. The display device according to claim 10, wherein, During the second high-period segment, a first latch operation is performed simultaneously to sequentially store the (k+1)th second image data in the second data register and a second latch operation is performed to sequentially output the kth second image data to the second digital-to-analog converter.

13. The display device according to claim 11 or 12, wherein, When the horizontal axis represents the panel position along the first direction and the vertical axis represents time, the first curve for timing the first latch operation at the panel position and the second curve for timing the second latch operation at the panel position rise to the left and upward with time.

14. The display device according to claim 13, wherein, The slope of the first curve is different from the slope of the second curve.

15. The display device according to claim 1 or 9, wherein, At least a portion of the low-period of the data enable signal overlaps with the high-period of the source output enable signal. During the low period of the source output enable signal following the high period of the source output enable signal, the first analog output of the first digital-to-analog converter is sequentially executed along the first direction, and During the low period of the source output enable signal, the second analog output of the second digital-to-analog converter is executed sequentially along the second direction.

16. The display device according to claim 15, wherein, The low-period of the data enable signal is shorter than the high-period of the source output enable signal.

17. A data processing method for a display device, the display device comprising a display panel, the display panel including a first surface containing a first pixel and a second surface containing a second pixel, the first surface contacting the second surface at its center, the data processing method comprising: First image data to be applied to the first surface is sequentially latched at the panel edge along a first direction facing the center of the panel, and The second image data to be applied to the second surface is sequentially locked at the panel edge along a second direction facing the center of the panel. Wherein, the first direction is opposite to the second direction. Specifically, during the first high-period of the data enable signal, along the first direction, the kth first image data of the kth horizontal row to be applied to the first surface is sequentially stored in the first data register, where k is a natural number. Specifically, during the second high-period following the first high-period of the data enable signal, along the first direction, the (k+1)th first image data of the (k+1)th horizontal row to be applied to the first surface is sequentially stored in the first data register, and... Specifically, during the low period between the first high period and the second high period, when the data enable signal is arranged along the first direction, the kth first image data stored in the first data register is sequentially output to the first digital-to-analog converter.

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