Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a driving transistor, a dual-gate transistor, a data writing module and a clamping module; the gate of the driving transistor and the first electrode of the dual-gate transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node; the dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a third node; the working process of the pixel circuit includes a non-luminous phase, and the non-luminous phase includes a first sub-phase; the clamping module is used to clamp the potential of the second node to the potential of the third node during at least part of the time period of the first sub-phase. In the present invention, the presence of the clamping module can reduce the voltage difference between the first node and the second node in different working phases of the pixel circuit, thereby improving the flickering phenomenon of the display panel and enhancing the display effect.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle and fast response speed, and has become one of the research hotspots in the current display field. Electronic display products will use different refresh rates for display in different application scenarios. For example, a higher refresh rate driving method is used to drive the display of dynamic images to ensure the smoothness of the display; a lower refresh rate driving method is used to drive the display of static images to reduce power consumption.

[0003] In the prior art, when a low frequency is set, the refresh rate of the light control signal is generally maintained and the refresh rate of the reset control signal or the data write control signal is reduced. This will result in differences in the rising speed of the brightness of the light-emitting element in different display stages, causing the screen to flicker. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device to improve the flicker phenomenon of the display panel and enhance the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit and a light-emitting element;

[0006] The pixel circuit includes a driving transistor, a dual-gate transistor, a data writing module and a clamping module;

[0007] The driving transistor is used to provide a driving current for the light emitting element;

[0008] The data writing module is used to provide a data signal for the driving transistor;

[0009] The gate of the driving transistor and the first electrode of the dual-gate transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node;

[0010] The dual-gate transistor includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a third node;

[0011] The working process of the pixel circuit includes a non-luminous phase, and the non-luminous phase includes a first sub-phase; in the first sub-phase, the first sub-transistor and the second sub-transistor are both turned off;

[0012] The clamping module is connected to the second node and the third node respectively, and is used to clamp the potential of the second node to the potential of the third node during at least a partial time period of the first sub-phase.

[0013] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect of the present invention.

[0014] In an embodiment of the present invention, the display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a driving transistor, a dual-gate transistor, a data writing module and a clamping module; the driving transistor is used to provide a driving current for the light-emitting element; the data writing module is used to provide a data signal for the driving transistor; the gate of the driving transistor and the first pole of the dual-gate transistor are connected to the first node, and the data writing module and the first pole of the driving transistor are connected to the second node; the dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a third node; the working process of the pixel circuit includes a non-luminous stage, and the non-luminous stage includes a first sub-stage; in the first sub-stage, the first sub-transistor and the second sub-transistor are both turned off; the clamping module is respectively connected to the second node and the third node, and the clamping module is used to clamp the potential of the second node to the potential of the third node in at least part of the time period of the first sub-stage. In the present invention, the existence of the clamping module makes the voltage difference between the first node and the second node closer before and after the signal is written, thereby better improving the flickering phenomenon of the display panel and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a pixel circuit in a display panel in the related art provided by an embodiment of the present invention;

[0016] Figure 2 A graph showing a change in luminance of a display panel in different display frames according to a related art provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of the structure of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention;

[0018] Figure 4 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0019] Figure 5 A schematic diagram of the structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0021] Figure 7 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0022] Figure 8 A schematic structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0023] Fig. 9 for Figure 8 The driving timing diagram of the pixel circuit shown;

[0024] Fig.10 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Fig.11 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0027] Figure 1 A schematic diagram of the structure of a pixel circuit in a display panel in the related art provided by an embodiment of the present invention, Figure 2 The luminance variation curve of the display panel in different display frames provided by the related art embodiment of the present invention is as follows: Figure 1 and Figure 2 As shown in , the first node N1 in the pixel circuit 1' is connected to the gate of the driving transistor T3 and one end of the first dual-gate transistor T1 respectively. The pixel circuit 1' may include a reset phase, a data writing phase and a light-emitting phase, wherein in the reset phase, the first dual-gate transistor T1 is turned on according to the reset control signal, and the reset signal Vref is transmitted to the first node N1, so that the first node N1, i.e., the gate of the driving transistor, is reset; in the data writing phase, the second dual-gate transistor T2 writes the data signal Vdata to the first node N1 and compensates the threshold voltage of the driving transistor T3 to the potential of the first node N1, and the potential stored in the first node N1 at the end of the data writing phase is Vdata-|Vth|, where Vth is the threshold voltage of the driving transistor T3; in the light-emitting phase, the light-emitting control signal controls the light-emitting control transistor T4 to be turned on, and the driving transistor T3 is turned on at the same time, and the first power supply voltage signal PVDD is input to the source of the driving transistor T3, and the driving transistor T3 generates a driving current based on the first power supply voltage signal PVDD at its source and the data signal Vdata-|Vth| stored in the first node N1 and compensated by the threshold value, and drives the light-emitting element 2' to emit light.

[0028] In the related art, when the display panel displays at a low frequency, the refresh rate of the data write control signal will be reduced, while the refresh rate of the light-emitting control signal will be maintained. For example, when the refresh rate of the light-emitting control signal is maintained at 60Hz and the refresh rate of the data write control signal is reduced to 15Hz, the display panel is driven to display at 15Hz. Under this setting, a frame of the display screen of the display panel may include a write frame A1 and a hold frame A2. In the write frame A1, the compensated data signal is normally written to the first node N1, and then in the hold frame A2, the light-emitting element 2' is driven by the voltage of the first node N1 written in the write frame A1, and no data is written in the hold frame A2. In the hold frame A2, the average light-emitting brightness of the display panel can be adjusted by adjusting the effective level duration (also called dimming length) of each light-emitting control signal.

[0029] The inventor has found that in the non-luminous phase of writing frame A1, such as the reset phase, the potential VN1 of the first node N1 is Vref, the second node N2 maintains the potential when the previous frame is luminous (close to the first power supply voltage signal PVDD), and the gate-source voltage difference Vgs1' of the driving transistor T3 is VN1-VN2≈Vref-PVDD. Generally, the reset signal Vref is about -3V, the first power supply voltage signal PVDD is about 3V, and Vgs1' is about -6V. In the non-luminous phase of keeping frame A2, since data is no longer written, the potential VN1 of the first node N1 is Vdata-|Vth|, and the second node N2 maintains the potential when the previous frame is luminous (close to the first power supply voltage signal PVDD). At this time, the gate-source voltage difference Vgs2' of the driving transistor T3 is VN1-VN2≈Vdata-|Vth|-PVDD. Taking Vdata-|Vth| as an example of about 3V, Vgs1' is about -1V. It can be seen that |VGS1'|>|VGS2'|, that is, the gate-source voltage difference VGS of the driving transistor T3 in the non-luminous stage of the writing frame A1 and the holding frame A2 is quite different. Since the gate-source voltage difference VGS2' in the holding frame A2 is relatively small, the luminous brightness of the light-emitting element 2' rises faster in the luminous stage of the holding frame A2; the gate-source voltage difference VGS1' in the writing frame A1 is relatively large, and the luminous brightness of the light-emitting element 2' rises slower in the luminous stage of the writing frame A1 (e.g. Figure 2 As shown in ), the display panel may flicker, which may affect the display effect of the display panel.

[0030] Based on the above defects of the prior art, the inventor proposes the technical solution in the present application. Specifically, the present application proposes a display panel, including a pixel circuit and a light-emitting element;

[0031] The pixel circuit includes a driving transistor, a dual-gate transistor, a data writing module and a clamping module;

[0032] The driving transistor is used to provide a driving current for the light emitting element;

[0033] The data writing module is used to provide a data signal to the driving transistor;

[0034] The gate of the driving transistor and the first electrode of the double-gate transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node;

[0035] The dual-gate transistor includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a third node;

[0036] The working process of the pixel circuit includes a non-luminous phase, and the non-luminous phase includes a first sub-phase; in the first sub-phase, the first sub-transistor and the second sub-transistor are both turned off;

[0037] The clamping module is connected to the second node and the third node respectively, and is used to clamp the potential of the second node to the potential of the third node during at least a partial time period of the first sub-phase.

[0038] In the present invention, the presence of the clamping module increases the voltage difference between the first node and the second node (the gate-source voltage difference of the driving transistor) in the first sub-stage, which is closer to the gate-source voltage difference of the driving transistor after data writing, thereby reducing the voltage difference between the first node and the second node in different working stages of the pixel circuit, thereby improving the flickering phenomenon of the display panel and enhancing the display effect of the display panel.

[0039] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Figure 3 A schematic diagram of a structure of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention, referring to Figure 3, the display panel includes a pixel circuit 1 and a light-emitting element 2; the pixel circuit 1 includes a driving transistor T3, a dual-gate transistor 3, a data writing module 8 and a clamping module 4; the driving transistor T3 is used to provide a driving current for the light-emitting element 2; the data writing module 8 is used to provide a data signal Vdata for the driving transistor T3; the gate of the driving transistor T3 and the first electrode of the dual-gate transistor 3 are connected to the first node N1, and the data writing module 8 and the first electrode of the driving transistor T3 are connected to the second node N2; the dual-gate transistor 3 includes a first sub-transistor 31 and a second sub-transistor 32, and the connection node between the first sub-transistor 31 and the second sub-transistor 32 is a third node N3; the working process of the pixel circuit 1 includes a non-light-emitting stage, and the non-light-emitting stage includes a first sub-stage; in the first sub-stage, the first sub-transistor 31 and the second sub-transistor 32 are both turned off; the clamping module 4 is respectively connected to the second node N2 and the third node N3, and the clamping module 4 is used to clamp the potential of the second node N2 to the potential of the third node N3 during at least a part of the time period of the first sub-stage.

[0041] Specifically, Figure 3 As shown in, in the present application, the display panel includes a pixel circuit 1 and a light-emitting element 2, and the pixel circuit 1 is used to drive the light-emitting element 2 to emit light to complete the display of the display panel. Among them, the pixel circuit 1 can be arranged in an array in the display panel, and the pixel circuit 1 is provided with a driving transistor T3, a dual-gate transistor 3, a data writing module 8 and a clamping module 4. The first electrode of the driving transistor is connected to the data writing module 8, and the connection point between the driving transistor and the data writing module 8 is the second node. In the data writing stage, the data writing control signal controls the data writing module 8 to be turned on, and the data signal Vdata is transmitted to the gate of the driving transistor T3, that is, the first node N1, through the data writing module 8, and then in the light-emitting stage, the driving transistor T3 provides a driving current to the light-emitting element 2 according to the data signal Vdata.

[0042] Continue to refer Figure 3 , the first node N1 is also connected to the first electrode of the dual-gate transistor 3. The dual-gate transistor 3 is composed of a first sub-transistor 31 and a second sub-transistor 32. The first sub-transistor 31 and the first sub-transistor 31 are connected through a third node N3. The gates of the first sub-transistor 31 and the second sub-transistor 32 are connected to the same scanning signal line and are controlled by the same scanning signal. The clamp module 4 is used to connect the second node N2 and the third node N3.

[0043] Those skilled in the art will know that, in addition to the driving transistor T3, the pixel circuit 1 is generally further provided with a reset module 5, a compensation module 6, a light-emitting control module 7, etc. The reset module 5 is turned on or off under the control of the reset control signal S1. In the reset stage, the reset module 5 transmits the reset signal Vref1 to the first node N1. The reset stage is generally before the data writing stage. The compensation module 6 is turned on or off under the control of the data writing control signal S2. In the threshold compensation stage, the compensation module 6 is turned on to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3. After the threshold compensation, the potential of the first node N1 is Vdata-|Vth|. In the time dimension, the threshold compensation stage can overlap with the data writing stage. The light-emitting control module 7 is turned on or off under the control of the light-emitting control signal EM. When the light-emitting control module EM is turned on, the driving transistor T3 generates a driving current and drives the light-emitting element 2 to emit light.

[0044] Figure 4 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention, referring to Figure 4 In the present application, the working process of the pixel circuit 1 can be divided into a light-emitting stage B1 and a non-light-emitting stage B2. The light-emitting stage B1 is the period when the light-emitting control module 7 is turned on and the driving current drives the light-emitting element 2 to emit light. The non-light-emitting stage B2 is any period except the light-emitting stage B1, such as the reset stage ta and the data writing stage (threshold compensation stage) tb. Among them, the non-light-emitting stage B2 also includes a first sub-stage B3. In the first sub-stage B3, the first sub-transistor 31 and the second sub-transistor 32 are both in the off state. Among them, the first sub-transistor 31 and the second sub-transistor 32 can be P-type transistors, and the scanning signal that controls the first sub-transistor 31 and the second sub-transistor 32 to be turned off is a high level. In the present application, the clamping module 4 can clamp the potential of the second node N2 to the potential of the third node N3 during at least part of the time period of the first sub-stage B3, that is, the potential of the third node N3 is charged into the second node N2. Since the third node N3 between the first sub-transistor 31 and the second sub-transistor 32 is pulled high by the high-level scanning signal, the clamping module 4 can charge a relatively high potential into the second node N2.

[0045] Among them, the first sub-stage B3 can be a partial period of time within the holding frame A2 mentioned in the above-mentioned related art. According to the description of the above-mentioned related art, if the clamping module 4 does not exist, the gate-source voltage difference of the driving transistor in the holding frame A2 and the writing frame A1 is large, and the light emitting brightness rising speed of the light emitting element in each light emitting stage is different. In the present application, in the first sub-stage B3, through the clamping module 4, the potential of the third node N3 can be charged into the second node N2, so that the potential of the second node N2 is increased. After the potential of the second node N2 is increased, the voltage difference between the first node N1 and the second node N2 (the gate-source voltage difference of the driving transistor) increases, and is closer to the gate-source voltage difference of the driving transistor in the writing frame A1, thereby better improving the flickering phenomenon of the display panel and improving the display effect of the display panel.

[0046] The embodiment of the present invention does not limit the specific position of the dual-gate transistor, and those skilled in the art may set it according to actual needs. Figure 3 FIG. 4 exemplarily shows that the compensation module 6 is configured as a dual-gate transistor 3. The actual configuration is not limited thereto.

[0047] The following is an example in which the compensation module 6 includes a dual-gate transistor 3 to illustrate the technical principle of the present invention. In the first sub-stage B3, the first sub-transistor 31 and the second sub-transistor 32 are turned off, and the data signal Vdata is not written to the first node N1. Normally, the scanning signal that controls the first sub-transistor 31 and the second sub-transistor 32 to turn off is a high-level signal VGH, and the potential of the third node N3 is pulled high. Under the action of the clamping module 4, the potential VN2 of the second node N2 becomes a voltage value close to the high-level signal VGH, and the potential VN1 of the first node N1 is still Vdata-|Vth|, and the value of VGH is generally around 8V. At this time, the gate-source voltage difference Vgs2≈Vdata-|Vth|-VGH≈-5V of the driving transistor T3. Except for the first sub-stage B3, when the data signal Vdata is written to the first node N1 in the non-luminous stage B2, the gate-source voltage difference Vgs1 of the driving transistor T3 is the same as Vgs1' in the related art, which is about -6V. Vgs1 is close to Vgs2, which can overcome the problem of different rising speeds of the brightness of the light-emitting element 2 in different luminous stages in the related art, avoid the occurrence of flickering to a large extent, and effectively improve the display effect of the display panel.

[0048] Optionally, the embodiment of the present invention does not limit the specific configuration of the clamping module 4, and those skilled in the art may configure it according to actual needs. Any specific design scheme for realizing the function of the clamping module 4 is within the scope of the technical solution protected by the present invention.

[0049] In the present invention, the presence of the clamping module increases the voltage difference between the first node and the second node (the gate-source voltage difference of the driving transistor) in the first sub-stage, and the voltage difference before and after the signal is written to the first node is closer, that is, the voltage difference between the first node and the second node when the signal is written to the first node is closer to the voltage difference between the first node and the second node when the signal is not written to the first node, thereby reducing the voltage difference between the first node and the second node in different working stages of the pixel circuit, thereby improving the flickering phenomenon of the display panel and enhancing the display effect of the display panel.

[0050] Optional, you can continue to refer to Figure 4 The non-luminous stage also includes a second sub-stage B4. In the second sub-stage B4, the first sub-transistor 31 and the second sub-transistor 32 are both turned on; the pixel circuit 1 also includes a reset module 5, the reset module 5 is used to provide a reset signal Vref1 for the first node N1 in the second sub-stage B4, and the reset module 5 includes a dual-gate transistor 3; or, the pixel circuit 1 also includes a compensation module 6, the compensation module 6 is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3 in the second sub-stage B4, and the compensation module 6 includes a dual-gate transistor 3.

[0051] Optionally, the non-luminous phase B2 may include a first sub-phase B3 and a second sub-phase B4, wherein the second sub-phase B4 is the period of writing the reset signal Vref1 or the data signal Vdata to the first node N1 in the above embodiment, which is also a part of the period of writing into the frame A1 in the related art. Figure 3 In the illustrated embodiment, the compensation module 6 is introduced as a dual-gate transistor 3. When the compensation module 6 is a dual-gate transistor 3, the second sub-stage B4 corresponds to the threshold compensation stage (data writing stage) tb. In the second sub-stage B4, the potential VN1 of the first node N1 is Vdata-|Vth|.

[0052] Figure 5 A schematic diagram of the structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention. Figure 5 In the illustrated embodiment, the reset module 5 may also include the above-mentioned dual-gate transistor 3. When the reset module 5 is the dual-gate transistor 3, the second sub-stage B4 may correspond to the reset stage ta. In the second sub-stage B4, the potential VN1 of the first node N1 is Vref-PVDD. When the reset module 5 is the dual-gate transistor 3, the working principle of the clamping module 4 is the same as in the above-mentioned embodiment, and no further explanation is given here.

[0053] Continue to refer Figure 3 to Figure 5The clamp module 4 may include a first transistor 41, two ends of the first transistor 41 are respectively connected to the second node N2 and the third node N3, and the control end of the first transistor 41 receives the clamp control signal S-RST; the first transistor 41 is used to be turned on in at least a partial time period of the first sub-stage B3 under the control of the clamp control signal S-RST.

[0054] As a possible embodiment, the function of the clamping module 4 can be realized by using a transistor. Specifically, a first transistor 41 can be provided in the clamping module 4, the first end of the first transistor 41 is connected to the second node N2, the second end of the first transistor 41 is connected to the third node N3, and the control end of the first transistor 41 is used to receive the clamping control signal S-RST. The clamping control signal S-RST controls the first transistor 41 to be in a conductive state at least part of the time in the first sub-stage B3. The first transistor 41 shown in the figure is a P-type transistor, and the actual setting method is not limited to this. When the first transistor 41 is a P-type transistor, the clamping control signal S-RST is at a low level in at least part of the time period of the first sub-stage B3 to control the first transistor 41 to be turned on. Among them, the pixel circuit 1 and the first transistor 41 can be in a one-to-one correspondence, that is, each pixel circuit 1 is provided with a first transistor 41, and the first transistor 41 can charge the potential of the third node N3 of the pixel circuit 1 into the second node N2 of the pixel circuit 1.

[0055] In addition, optionally, in an embodiment of the present invention, when the reset module 5 includes a dual-gate transistor 3, the first transistor 41 is also used to be turned off in the second sub-stage B4 under the control of the clamping control signal S-RST; when the compensation module 6 includes a dual-gate transistor 3, the first transistor 41 is also used to be turned off in the second sub-stage B4 under the control of the clamping control signal S-RST.

[0056] Specifically, when the reset module 5 is a dual-gate transistor 3 ( Figure 5 As shown in FIG. 1 , in the second sub-stage B4, i.e., the reset stage ta, the clamp control signal S-RST controls the first transistor 41 to be turned off, thereby preventing the first transistor 41 from charging the potential of the third node N3 into the second node N2, thereby ensuring the reset module 5 has a reset effect on the potential of the first node N1.

[0057] When the compensation module 6 is a dual-gate transistor 3 ( Figure 3), in the second sub-stage B4, i.e., the threshold compensation stage tb, the clamp control signal S-RST controls the first transistor 41 to be turned off, so as to prevent the first transistor 41 from charging the potential of the third node N3 into the second node N2, thereby ensuring the compensation effect of the compensation module 6 on the potential of the first node N1. Exemplarily, when the first transistor 41 is a P-type transistor, in the reset stage ta or the threshold compensation stage tb, the clamp control signal S-RST should be at a high level to control the first transistor 41 to be turned off.

[0058] Combine the following Figure 3 and Figure 4 , the driving timing of the pixel circuit in this embodiment is generally introduced. Among them, the second sub-stage B4 can be a threshold compensation stage tb (data writing stage). In the non-light-emitting stage B2, the light-emitting control signal EM is at a high level, and the light-emitting control module 7 is turned off. In the light-emitting stage B1, the light-emitting control signal EM is at a low level, and the light-emitting control module 7 is turned on. Figure 4 As shown in , the first sub-stage B3 and the second sub-stage B4 are both within the high level period of the light emitting control signal EM. First, the data writing control signal S2 becomes the effective level (low level), the data writing module 8 and the compensation module 6 are turned on, and the compensated data signal is written into the first node N1. After the data signal is written, the data writing control signal S2 jumps to a high level, the dual-gate transistor 3 is turned off, and the third node N3 between the first sub-transistor 31 and the second sub-transistor 32 is pulled to a high potential. In the above process, the clamping control signal S-RST is always an invalid level (high level). After the threshold compensation stage tb ends, the clamping control signal S-RST jumps to an effective level (low level), the first transistor 41 is turned on, and the high potential of the third node N3 is charged into the second node N2. The period during which the first transistor 41 is turned on is the first sub-stage B3. The first sub-stage B3 is located after the second sub-stage B4.

[0059] Optional, can still refer to Figure 3 to Figure 5The pixel circuit 1 may further include a data storage module 10; a reset module 5 is connected between the reset signal terminal Vref1 and the first node N1, a control terminal of the reset module 5 receives a reset control signal S1, and the reset module 5 is used to provide a reset signal Vref1 to the first node N1 under the control of the reset control signal S1; a data writing module 8 is connected between the data signal terminal Vdata and the first electrode of the driving transistor T3, and a control terminal of the data writing module 8 receives a data writing control signal S2; a compensation module 6 is connected between the second electrode of the driving transistor T3 and the first node N1; the data storage module 10 is connected between the first power supply voltage terminal PVDD and the first node N1; the data writing module 8 is used to write the data signal Vdata to the first node N1 through the driving transistor T3 and the compensation module 6 in sequence under the control of the data writing control signal S2, and the data storage module 10 is used to store the data signal written to the first node N1.

[0060] Among them, the data writing module 8, the reset module 5 and the compensation module 6 are mentioned in the above embodiments. The two ends of the reset module 5 can be specifically located between the reset signal end Vref1 and the first node N1. The control end of the reset module 5 receives the reset control signal S1, thereby resetting the first node N1. The data writing module 8 can be specifically located between the data signal end Vdata and the first end of the driving transistor T3. The control end of the data writing module 8 is used to receive the data writing control signal S2; the compensation module 6 can be specifically located between the second pole of the driving transistor T3 and the first node N1. The control end of the compensation module 6 can receive the same data writing control signal S2 as the data writing module 8. In the data writing stage tb, the data signal Vdata is written into the first node N1 after passing through the driving transistor T3 and the compensation module 6. The specific working principle of each stage can refer to the above embodiments and will not be repeated here.

[0061] In addition, a data storage module 10 is also provided in the pixel circuit 1 . The data storage module 10 is located between the first power supply voltage terminal PVDD and the first node N1 . The data signal Vdata written in the data writing phase tb can be stored in the data storage module 10 .

[0062] Among them, the reset module 5 can be a reset transistor, the data writing module 8 can be a data writing transistor, the compensation module 6 can be a compensation transistor, the light control module 7 can be a first light control transistor 71 and a second light control transistor 72, and the data storage module 10 can be a storage capacitor. The above transistors can all be P-type transistors, but are not limited to this.

[0063] Figure 6 A schematic diagram of a display panel provided by an embodiment of the present invention can be referred to Figure 3 and Figure 6In a possible embodiment, the display panel may include N rows of pixel circuits 1 and M cascaded first shift registers 11, wherein N and M are both positive integers greater than or equal to 1, and N<M; the first shift register 11 is used to provide a first scanning signal to the pixel circuit 1, and the first scanning signals provided by the first shift registers 11 of each stage are shifted by the same distance in sequence; in the pixel circuit 1 of the nth row, the first shift register 11 of the nth stage provides the first scanning signal as the reset control signal S1 to the control end of the reset module 5, and the first shift register 11 of the n+1th stage provides the first scanning signal as the data writing control signal S2 to the control end of the data writing module 8; wherein n is a positive integer greater than or equal to 1 and less than or equal to N.

[0064] Specifically, Figure 6 As shown in the figure, a total of N rows of pixel circuits 1 and M first shift registers 11 for providing the first scanning signal S1 to the pixel circuits 1 can be arranged in the display panel. The M first shift registers 11 are cascaded, that is, M cascaded first shift registers 11 can be arranged in the row direction where the pixel circuits 1 are located. Those skilled in the art can know the specific meaning of the cascade setting, which will not be described in detail here.

[0065] Wherein, both M and N should be positive integers greater than or equal to 1, and the number of first shift registers 11 is greater than the number of rows of pixel circuits 1. The M first shift registers 11 provide the first scanning signals required by each device in the pixel circuit 1 to the N pixel circuits 1. The direction from top to bottom shown in the figure is the first direction X. Along the first direction X, the first scanning signals provided by the first shift registers 11 of each stage are sequentially delayed by the same time, that is, after the first shift register 11 of the nth stage (n is a positive integer, and 1≤n≤N) sends out the first scanning signal, the first shift register 11 of the n+1th stage delays the preset time to send out the first scanning signal.

[0066] In this embodiment, for a certain row of pixel circuits 1, for example, the nth row of pixel circuits 1, the first scanning signal provided by the nth-stage first shift register 11 to the reset module 5 of the nth row of pixel circuits 1 is used as the reset control signal S1, which is used to control the on or off of the reset module 5; and the first scanning signal provided by the n+1th-stage first shift register 11 to its data writing module 8 is used as the data writing control signal S2, which is used to control the on or off of the data writing module 8. At the same time, the first scanning signal provided by the n+1th-stage first shift register 11 is also used as the reset control signal S1 of the reset module 5 in the n+1th row of pixel circuits 1. In simple terms, it can also be understood that the data writing control signal S2 received by the current row of pixel circuits 1 is also used as the reset control signal S1 of the next row of pixel circuits 1.

[0067] For example, Figure 7Another driving timing diagram of a pixel circuit provided by an embodiment of the present invention, combined with Figure 7 , which introduces the above driving process. Figure 7 , when n=1, the first scanning signal output by the first shift register 11 of the first stage is used as the reset control signal S1-1 to the pixel circuit 1 of the first row. After a delay of a preset time Δt, the first shift register 11 of the second stage outputs the first scanning signal, which is used as both the data writing control signal S2-1 of the pixel circuit 1 of the first row and the reset control signal S1-2 of the pixel circuit 1 of the second row. By analogy, the first scanning signal output by the first shift register 11 of the n+1th stage is used as both the reset control signal S1-(n+1) of the pixel circuit 1 of the n-1th row and the data writing control signal S2-n of the pixel circuit 1 of the nth row. It can be understood that the first scanning signal output by the first shift register 11 of the first stage is also used as a start signal to control the first shift registers 11 of each stage to start and transmit the first scanning signal after a delay of a preset time in sequence.

[0068] Optional, can still refer to Figure 6 The display panel also includes N cascaded second shift registers 12; the second shift register 12 is used to provide a second scanning signal to the pixel circuit, and the second scanning signals provided by the second shift registers 12 at each level are shifted by the same distance in sequence; the nth level second shift register 12 provides the second scanning signal to the first transistor in the pixel circuit of the nth row as a clamping control signal.

[0069] like Figure 6 As shown in , the display panel is also provided with N cascaded second shift registers 12, the number of the second shift registers 12 is the same as the number of rows of pixel circuits 1, and each level of the second shift register 12 provides a second scanning signal to the pixel circuit 1 of the corresponding row, and the second scanning signal can be used as the clamping control signal S-RST received by the first transistor 41 in each row of the pixel circuit. For example, the first-level second shift register 12 transmits the clamping control signal S-RST to the first-row pixel circuit. Along the first direction X, the second scanning signals provided by the second shift registers 12 of each level are sequentially delayed by the same time, that is, after the n-th level shift register sends the second scanning signal, the n+1-th level shift register 11 delays the preset time to send the second scanning signal.

[0070] The second shift register 12 is separately provided to provide the clamping control signal S-RST to the pixel circuits 1 of the corresponding rows, so as to improve the transmission accuracy of the clamping control signal S-RST and ensure that the clamping module 4 completes the clamping work normally.

[0071] You can continue to refer to Figure 6The display panel includes a display area AA, and a first shift register 11 and a second shift register 12 are respectively located on both sides of the display area 11 in a row direction.

[0072] It can be understood that the pixel circuit 1 is arranged in the display area AA of the display panel, and the shift register is generally arranged in the non-display area NA on both sides of the display area AA. In this embodiment, the first shift register 11 and the second shift register 12 can be respectively arranged in the non-display area NA on both sides of the display area AA. In this arrangement, the first shift register 11 and the second shift register 12 can both be unilaterally driven, thereby not increasing the occupied size of the shift register in the non-display area NA, and ensuring that the frame of the display panel is narrow.

[0073] Figure 6 Only the first shift register 11 and the second shift register 12 are shown exemplarily, and any shift register known to those skilled in the art may be provided in the display panel, such as a light emitting control shift register 13, etc., but not limited thereto.

[0074] Figure 8 A schematic diagram of the structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, Fig. 9 for Figure 8 The driving timing diagram of the pixel circuit shown in FIG. Figure 8 and Fig. 9 As shown in , the working process of the pixel circuit 1 also includes a dual-gate closing stage B5, in which the first sub-transistor 31 and the second sub-transistor 32 are both turned off; the first sub-stage B3 is located in the dual-gate closing stage B5; the clamping module 4 includes a potential grabbing unit 42 and a potential writing unit 43, the potential grabbing unit 42 is used to grab and store the potential of the third node N3 in the grabbing period t1; the potential writing unit 43 is used to write the potential of the third node N3 to the second node N2 in the writing period t2; wherein, in the time dimension, the grabbing period t1 and the writing period t2 are both located in the dual-gate closing stage B5, and the writing period t2 is located in the first sub-stage B3, and the writing period t2 is located after the grabbing period t1.

[0075] In this embodiment, in the time dimension, the period in which the first sub-transistor 31 and the second sub-transistor 32 are turned off at the same time is the dual-gate closing stage B5, and the first sub-stage B3 is located in the dual-gate closing stage B5. In this embodiment, the clamping module 4 can adopt another setting mode, and the clamping module 4 can be composed of a potential grabbing unit 42 and a potential writing unit 43. The potential grabbing unit 42 is connected to the third node N3 of the pixel circuit 1, and the potential grabbing unit 42 works in the grabbing period t1. In the grabbing period t1, the potential grabbing unit 42 grabs and stores the potential of the third node N3 in the pixel circuit 1. The potential writing unit 43 is respectively connected to the potential grabbing unit 42 and the second node N2 of the pixel circuit 1, and the potential writing unit 43 works in the writing period t2. In the writing period t2, the potential writing unit 43 writes the potential of the third node N3 grabbed by the potential grabbing unit 42 into the second node N2 of the pixel circuit 1.

[0076] It can be understood that, since the first sub-stage B3 is in the dual-gate closing stage B5, the capture period t1 and the write period t2 should both be in the dual-gate closing stage B5. In addition, the potential should be captured first and then the potential should be written. Therefore, in the time dimension, the write period t2 should be located after the capture period t1. Another point to note is that in order to ensure that the potential of the third node N3 in the write period t2 can be charged into the second node N2, the write period t2 should be located in the first sub-stage B3. The capture period t1 can be located in the first sub-stage B3 or before the first sub-stage B3, and this embodiment does not limit this.

[0077] Those skilled in the art will appreciate that compared to Figure 3 In the embodiment shown, the third node N3 is directly electrically connected to the second node N2 of the corresponding pixel circuit 1. Under this configuration of the embodiment, there is a transition phase of potential capture, and the operation of the entire pixel circuit 1 is more stable.

[0078] Optionally, the embodiment of the present invention does not limit the specific setting method of the potential capture unit 42 and the potential writing unit 43. Those skilled in the art can set them according to actual needs. Any method that can achieve potential capture and potential writing is within the scope of the technical solution protected by the embodiment of the present invention.

[0079] You can continue to refer to Figure 8In an exemplary embodiment, the potential capture unit 42 may include a second transistor 44 and a first storage capacitor 45, the two ends of the second transistor 44 are electrically connected to the third node N3 and the first plate c1 of the first storage capacitor 45, respectively, and the second plate c2 of the first storage capacitor 45 is connected to a fixed potential; the control end of the second transistor 44 receives a potential capture control signal S3, and the second transistor 44 is used to be turned on within the capture period t1 under the control of the potential capture control signal S3; the potential writing unit 43 includes a third transistor 46, the two ends of the third transistor 46 are electrically connected to the second node N2 and the first plate c1 of the first storage capacitor 45, respectively, the control end of the third transistor 46 receives a potential write control signal S4, and the third transistor 46 is used to be turned on within the write period t2 under the control of the potential write control signal S4.

[0080] like Figure 8 As shown in , the potential capture unit 42 is composed of a second transistor 44 and a first storage capacitor 45. The control end of the second transistor 44 receives the potential capture control signal S3. The second transistor 44 is also used to connect the third node N3 and a certain plate of the first storage capacitor 45 (which may be the first plate c1). The other plate of the first storage capacitor 45 (which may be the second plate c2) is connected to the fixed potential signal. In the capture period t1, the potential capture control signal S3 controls the second transistor 44 to turn on. When the second transistor 44 is turned on, the potential of the third node N3 connected to the second transistor 44 is stored in the first storage capacitor 45.

[0081] The potential writing unit 43 may be composed of a third transistor 46, the control end of the third transistor 46 receives the potential writing control signal S4, and the third transistor 46 may be used to connect the second node N2 of the pixel circuit and the first plate c1 of the first storage capacitor 45. In the writing period t2, the potential writing control signal S4 controls the third transistor 46 to be turned on, and the third transistor 46 writes the potential of the third node N3 of the pixel circuit 1 to the second node N2 of the pixel circuit 1.

[0082] Optionally, when the reset module 5 includes a dual-gate transistor 3, the third transistor 46 is also used to turn off in the second sub-stage B4 under the control of the potential writing control signal S4; when the compensation module 6 includes a dual-gate transistor 3, the third transistor 46 is also used to turn off in the second sub-stage B4 under the control of the potential writing control signal S4.

[0083] Specifically, when the reset module 5 is a dual-gate transistor 3, the second sub-stage B4 is the reset stage ta, and in the second sub-stage B4, the potential writing control signal S4 controls the third transistor 46 to be turned off; when the compensation module 6 is a dual-gate transistor 3, the second sub-stage B4 is the threshold compensation stage tb, and in the threshold compensation stage tb, the potential writing control signal S4 controls the third transistor 46 to be turned off. Exemplarily, when the third transistor 46 is a P-type transistor, in the second sub-stage B4 (reset stage ta or threshold compensation stage tb), the potential writing control signal S4 should be high level to control the third transistor 46 to be turned off. Thus, it is possible to ensure that the reset module 5 resets the potential of the first node N1, or the compensation module 6 compensates the potential of the first node N1, and in the reset stage ta or the threshold compensation stage tb, the third transistor 46 is turned off to prevent the third transistor 46 from charging the potential of the third node N3 into the first node N1.

[0084] You can continue to refer to Figure 8 As an optional embodiment, the second plate c2 of the first storage capacitor 45 can be electrically connected to the cathode of the light emitting element 2. The cathode of the light emitting element 2 is connected to a fixed low potential, and the cathode of the light emitting element 2 can be directly connected to the second plate c2, thereby simplifying the preparation process of the potential grabbing unit 42.

[0085] In the display panel shown in the above embodiment, the clamping module 4 corresponding to each pixel circuit 1 includes a potential grabbing unit 42 and a potential writing unit 43. Optionally, in other possible embodiments, the display panel may include a plurality of pixel circuits 1 arranged in sequence along the row direction and the column direction respectively; all pixel circuits 1 or the clamping modules 4 in the pixel circuits 1 of the same row share the same potential grabbing unit 42.

[0086] Specifically, a plurality of pixel circuits 1 are arranged in sequence along the row direction and the column direction, and the column direction is the first direction. Among them, since the potential capture unit 42 is used to capture and store the potential of the third node N3 in the pixel circuit 1, different pixel circuits 1 can be set to share a potential capture unit 42, and the potential writing unit 43 in the pixel circuit 1 sharing the potential capture unit 42 is electrically connected to the same potential capture unit 42. For example, the clamping modules 4 of all pixel circuits 1 share a potential capture unit 42, and each clamping module 4 extracts the potential from the potential capture unit 42, and only one potential capture unit 42 can be set in the display panel. For another example, the clamping modules 4 of the pixel circuits 1 in the same row share a potential capture unit 42, and the clamping modules 4 in the same row extract the potential from the same potential capture unit 42. When N rows of pixel circuits 1 are provided in the display panel, N potential capture units 42 can be provided in the display panel.

[0087] Optional, can still refer to Figure 4When a compensation module 6 is provided in the pixel circuit, the compensation module 6 is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor in the second sub-stage B4; the display panel includes a first operating mode, and the first operating mode includes a writing frame A1 and a holding frame A2; in the writing frame A1, the non-luminous stage B2 of the pixel circuit 1 includes a second sub-stage B4; in the non-luminous stage B2 in the holding frame A2, the compensation module 6 of the pixel circuit 1 is normally closed.

[0088] The role of the compensation module 6 is mentioned in the above embodiment. In the second sub-phase B4, the data signal Vdata is written into the first node N1. The low-frequency display mode of the display panel can be defined as the first working mode. The first working mode includes writing frame A1 and holding frame A2. Writing frame A1 and holding frame A2 are the same as those mentioned in the related art.

[0089] Specifically, the second sub-stage B4 is the non-luminous stage B2 in the write frame A1. In the second sub-stage B4, the data write control signal S2 is at a low level, the data write module 8 and the compensation module 6 are both turned on, and the data signal Vdata is written into the first node N1; and in the non-luminous stage B2 of the hold frame A2, the data write control signal S2 is at a low level, the data write module 8 and the compensation module 6 are both turned off, and the data signal Vdata is no longer written, and the data write module 8 and the compensation module 6 are in a normally closed state. At this time, if the compensation module 6 is a dual-gate transistor 3, in the time dimension, the first sub-stage B3 can be located in the non-luminous stage B2 in the write frame A1 and the hold frame A2. In the non-luminous stage B2 in the write frame A1 and the hold frame A2, the clamp control signal S-RST jumps to a low level, and the clamp module 4 is turned on.

[0090] Still can refer to Figure 3 or Figure 5 The pixel circuit 1 is also provided with an anode initialization module 9, which is connected between the anode initialization signal terminal Vref2 and the anode of the light-emitting element 2; the control terminal of the anode initialization module 9 receives the anode initialization signal, and the anode initialization module resets the anode of the light-emitting element 2 under the control of the anode initialization signal; the anode initialization signal is multiplexed into a clamping control signal S-RST.

[0091] Specifically, the anode of the light-emitting element 2 is also electrically connected to one end of the anode initialization module 9, and the other end of the anode initialization module 9 is connected to the initialization signal terminal Vref2. The control end of the anode initialization module 9 is used to receive the anode initialization signal. In the anode initialization stage, the anode initialization signal controls the anode initialization module 9 to turn on, and the initialization signal Vref2 provided by the anode initialization signal terminal Vref2 reaches the anode of the light-emitting element 2 through the anode initialization module 9, thereby resetting the anode of the light-emitting element 2.

[0092] In this embodiment, the anode initialization signal can be multiplexed into the clamping control signal S-RST. In the time dimension, the anode initialization stage can be set to at least partially overlap with the first sub-stage B3. In the anode initialization stage, the first sub-transistor 31 and the second sub-transistor 32 are both turned off; at the same time, the clamping module 4 is turned on to clamp the potential of the second node N2 to the potential of the third node N3. Among them, the anode initialization module 9 can be an anode initialization transistor 91, but is not limited thereto.

[0093] The anode initialization signal is multiplexed as the clamp control signal S-RST, and there is no need to set up an additional clamp control signal S-RST transmission line, which will not increase the display panel manufacturing process too much and will not affect the layout of the existing control signal transmission lines.

[0094] Fig.10 A driving timing diagram of another pixel circuit provided by an embodiment of the present invention, Fig.10 The drive timing shown is applicable to Figure 3 The pixel circuit is shown in FIG. Fig.10 As shown in the figure, the non-luminous stage B2 includes a clamping time period B6, during which the clamping module 4 is turned on; in the time dimension, the non-luminous stage B2 lasts from the luminous end time point to the next luminous start time point; the distance D1 between the clamping time period B6 and the luminous start time point of the non-luminous stage B2 is greater than the distance D2 from the luminous end time point of the non-luminous stage B2.

[0095] The clamping time period B6 is at least part of the time period in the first sub-stage B3. Those skilled in the art can understand that, in the time dimension, the light-emitting end point at the end of one light-emitting process to the light-emitting start point at the beginning of the next light-emitting process is a non-light-emitting stage B2, and the clamping time period B6 is in the non-light-emitting stage B2. The clamping control signal S-RST controls the clamping module to turn on in the clamping time period B6. In this embodiment, Fig.10 As shown in , in a non-luminous stage B2, the distance D2 between the clamping time period B6 and the luminous end point where the last luminous end is ended can be set to be less than or equal to the distance D1 between the clamping time period B6 and the luminous start point where the next luminous start is started. In simple terms, the clamping time period B6 is in the front section of the non-luminous stage B2. Thus, in the non-luminous stage B2, the potential of the second node N2 is first pulled up, so that the second node N2 can be maintained at a higher potential for a certain period of time, which is conducive to improving the stability of the potential of the second node N2.

[0096] You can continue to refer to Fig.10The non-luminous stage B2 includes a clamping time period B6 and a second sub-stage B4; in the clamping time period B6, the clamping module 9 is turned on; in the second sub-stage B4, the first sub-transistor 31 and the second sub-transistor 32 are both turned on; the duration T1 of the clamping time period B6 satisfies: T2≤T1≤T3-T2; wherein T2 is the duration of the second sub-stage B4, and T3 is the duration of the non-luminous stage B2.

[0097] like Fig.10 As shown in , in this embodiment, the non-light-emitting stage B2 can be divided into a clamping time period B6 and a second sub-stage B4, and the clamping time period B6 can overlap with the first sub-stage B3 in the time dimension. In the clamping time period B6, the first sub-transistor 31 and the second sub-transistor 32 are both turned off. The second sub-stage B4 and the clamping time period B6 alternate, and in the second sub-stage B4, the first sub-transistor 31 and the second sub-transistor 32 are both turned on.

[0098] refer to Fig.10 In this embodiment, the duration T1 of the clamping time period B6, the duration T2 of the second sub-stage B4, and the duration T3 of the non-luminous stage B2 can satisfy the following relationship: T2≤T1≤T3-T2. It can be understood that the total duration of the clamping time period B6 and the second sub-stage B4 in the same non-luminous stage B2 will not exceed the total duration of the non-luminous stage B2, that is, T1≤T3-T2; at the same time, the duration of the clamping module 9 working should not be less than the duration of the reset module 5 or the compensation module 6 working, that is, T2≤T1, to ensure that the potential of the third node N3 has enough time to charge the second node N2.

[0099] The embodiment of the present invention does not limit the specific setting values ​​of the duration of each stage, and those skilled in the art can set them according to actual needs.

[0100] Based on the same concept, an embodiment of the present invention further provides a display device, Fig.11 A schematic diagram of a display device according to an embodiment of the present invention is provided. Fig.11 , the display device may include any one of the display panels 100 provided in the above embodiments. Moreover, since the display device is made of the above display panel, it has the same or corresponding technical effects of the above display panel. It should be noted that the display device also includes other devices for supporting the normal operation of the display device. Specifically, the display device can be a mobile phone, a tablet, a computer, a television, a wearable smart device, etc., which is not limited by the embodiments of the present invention.

[0101] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: including a pixel circuit and a light emitting element; The pixel circuit includes a driving transistor, a dual-gate transistor, a data writing module and a clamping module; The driving transistor is used to provide a driving current for the light emitting element; The data writing module is used to provide a data signal for the driving transistor; The gate of the driving transistor and the first electrode of the dual-gate transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node; The dual-gate transistor includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a third node; The working process of the pixel circuit includes a non-luminous phase, and the non-luminous phase includes a first sub-phase; in the first sub-phase, the first sub-transistor and the second sub-transistor are both turned off; The clamping module is connected to the second node and the third node respectively, and is used to clamp the potential of the second node to the potential of the third node during at least a part of the time period of the first sub-phase; The non-luminous stage includes a clamping time period, during which the clamping module is turned on; in the time dimension, the non-luminous stage lasts from the luminous end time point to the next luminous start time point; the distance between the clamping time period and the luminous start time point of the non-luminous stage is greater than the distance between the clamping time period and the luminous end time point of the non-luminous stage.

2. The display panel according to claim 1, characterized in that: The non-light-emitting stage further includes a second sub-stage, in which the first sub-transistor and the second sub-transistor are both turned on; The pixel circuit further includes a reset module, the reset module is used to provide a reset signal for the first node in the second sub-phase, and the reset module includes the dual-gate transistor; or, The pixel circuit further includes a compensation module, which is used to detect and self-compensate for a deviation of a threshold voltage of the driving transistor in the second sub-phase, and the compensation module includes the dual-gate transistor.

3. The display panel according to claim 2, characterized in that: The clamp module comprises a first transistor, two ends of the first transistor are respectively connected to the second node and the third node, and a control end of the first transistor receives a clamp control signal; The first transistor is configured to be turned on during at least a partial period of the first sub-phase under the control of the clamp control signal.

4. The display panel according to claim 3, characterized in that: When the reset module includes the dual-gate transistor, the first transistor is further configured to be turned off in the second sub-phase under the control of the clamp control signal; When the compensation module includes the dual-gate transistor, the first transistor is further configured to be turned off in the second sub-phase under the control of the clamp control signal.

5. The display panel according to claim 4, characterized in that: The pixel circuit also includes a data storage module; The reset module is connected between the reset signal terminal and the first node, the control terminal of the reset module receives a reset control signal, and the reset module is used to provide a reset signal to the first node under the control of the reset control signal; The data writing module is connected to the data signal terminal and the first electrode of the driving transistor, and the control terminal of the data writing module receives a data writing control signal; The compensation module is connected between the second electrode of the driving transistor and the first node; the data storage module is connected between the first power supply voltage terminal and the first node; The data writing module is used to write a data signal to the first node via the driving transistor and the compensation module in sequence under the control of the data writing control signal, and the data storage module is used to store the data signal written to the first node.

6. The display panel according to claim 5, characterized in that: The display panel includes N rows of pixel circuits and M cascaded first shift registers, wherein N and M are both positive integers greater than or equal to 1, and N<M; The first shift register is used to provide a first scanning signal to the pixel circuit, and the first scanning signal provided by the first shift registers at each level is sequentially shifted by the same distance in time sequence; In the pixel circuit of the nth row, the first shift register of the nth stage provides the first scanning signal as the reset control signal to the control end of the reset module, and the first shift register of the n+1th stage provides the first scanning signal as the data writing control signal to the control end of the data writing module; Here, n is a positive integer greater than or equal to 1 and less than or equal to N.

7. The display panel according to claim 6, characterized in that: The display panel further includes N cascaded second shift registers; The second shift register is used to provide a second scanning signal to the pixel circuit, and the second scanning signal provided by each stage of the second shift register is sequentially shifted by the same distance in time sequence; The second shift register at the nth stage provides the second scanning signal as the clamp control signal to the first transistors in the pixel circuits in the nth row.

8. The display panel according to claim 7, characterized in that: The display panel includes a display area, and the first shift register and the second shift register are respectively located at two sides of the display area in a row direction.

9. The display panel according to claim 2, characterized in that: The operation process of the pixel circuit further includes a dual-gate closing stage, in which the first sub-transistor and the second sub-transistor are both turned off; the first sub-stage is within the dual-gate closing stage; The clamping module comprises a potential grabbing unit and a potential writing unit, wherein the potential grabbing unit is used to grab and store the potential of the third node within a grabbing period; The potential writing unit is used to write the potential of the third node to the second node within a writing period; In the time dimension, the capture period and the write period are both located in the dual-gate closing phase, and the write period is located in the first sub-phase, and the write period is located after the capture period.

10. The display panel according to claim 9, characterized in that: The potential capture unit includes a second transistor and a first storage capacitor, two ends of the second transistor are electrically connected to the third node and the first plate of the first storage capacitor respectively, and the second plate of the first storage capacitor receives a fixed potential signal; The control terminal of the second transistor receives a potential grabbing control signal, and the second transistor is used to be turned on within the grabbing period under the control of the potential grabbing control signal; The potential writing unit includes a third transistor, the two ends of the third transistor are electrically connected to the second node and the first plate of the first storage capacitor respectively, the control end of the third transistor receives a potential writing control signal, and the third transistor is used to be turned on during the writing period under the control of the potential writing control signal.

11. The display panel according to claim 10, characterized in that: When the reset module includes the dual-gate transistor, the third transistor is further used to be turned off in the second sub-stage under the control of the potential writing control signal; When the compensation module includes the dual-gate transistor, the third transistor is further configured to be turned off in the second sub-phase under the control of the potential writing control signal.

12. The display panel according to claim 10, characterized in that: The second electrode plate of the first storage capacitor is electrically connected to the cathode of the light emitting element.

13. The display panel according to claim 9, characterized in that: The display panel comprises a plurality of pixel circuits sequentially arranged in a row direction and a column direction respectively; All the pixel circuits or the clamping modules in the pixel circuits in the same row share the same potential grabbing unit.

14. The display panel according to claim 1, characterized in that: The non-light-emitting stage further includes a second sub-stage, in which the first sub-transistor and the second sub-transistor are both turned on; The pixel circuit further comprises a compensation module, the compensation module being used for detecting and self-compensating for a deviation of a threshold voltage of the driving transistor in the second sub-phase; The display panel includes a first operating mode, the first operating mode including writing frames and holding frames; In the writing frame, the non-light-emitting stage of the pixel circuit includes a third sub-stage; in the third sub-stage, the compensation module is turned on; During the non-light-emitting phase in the holding frame, the pixel circuit compensation module is normally closed.

15. The display panel according to claim 3, characterized in that: The pixel circuit further includes an anode initialization module, wherein the anode initialization module is connected between the anode initialization signal terminal and the anode of the light emitting element; The control end of the anode initialization module receives an anode initialization signal, and the anode initialization module resets the anode of the light-emitting element under the control of the anode initialization signal; The anode initialization signal is multiplexed into the clamp control signal.

16. The display panel according to claim 1, characterized in that: The non-light-emitting stage also includes a second sub-stage; during the clamping time period, the clamping module is turned on; in the second sub-stage, both the first sub-transistor and the second sub-transistor are turned on; The duration T1 of the clamping time period satisfies: T2≤T1≤T3-T2; Among them, T2 is the duration of the second sub-stage, and T3 is the duration of the non-light-emitting stage.

17. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-16.

Images