A trench gate power mosfet device resistant to single event burnout and a method of manufacturing the same

Abstract

The application discloses a trench gate power MOSFET device with anti-single event burnout reinforcement and a preparation method thereof, which comprises the following steps: etching a deep trench at a center position of the device and forming a P-type shielding area and depositing N-type polysilicon; forming a current expansion layer between a boron-doped area and an N-type drift area by means of ion implantation; and forming a P-type high-concentration doped area and an N-type high-concentration source area above the boron-doped area by means of ion implantation. According to the technical scheme, the internal electric field of the device can be modulated, the electric field distribution on the heavy ion incident track is smoother, the instantaneous power density of the device is reduced, the local high temperature is reduced, the trench oxide layer is protected from high temperature, the forward conduction capability of the device is improved, and the anti-single event burnout capability of the device can be remarkably improved without sacrificing the basic electrical characteristics of the device.

Description

Technical Field

[0001] This invention relates to the field of radiation hardening technology for power semiconductor devices, and in particular to a trench gate power MOSFET device resistant to single-particle burn-out and its fabrication method. Background Technology

[0002] Power MOSFET devices possess advantages such as high drive current, high breakdown voltage, high speed, low power consumption, and high output power. They can achieve power control and conversion across different ranges and are widely used in consumer electronics, industrial equipment, and aerospace fields, with enormous development potential in space applications. Power semiconductor devices are typically characterized by small size and high operating voltage, making their operational stability susceptible to the influence of natural radiation environments in space, particularly the triggering of the Single Event Burnout (SEB) effect. SEB is usually induced by heavy ion radiation. When heavy ions are incident perpendicularly into a device in a turned-off state, a large number of electron-hole pairs are generated along the incident trajectory. Due to the Kirk effect, a peak electric field and severe shock ionization are generated at the drift / substrate uniform junction, leading to intense local heating. Furthermore, the strong electric field inside the device causes holes to flow through the P-body region to the source metal and electrons to the drain metal. Hole current triggers parasitic bipolar junction transistors (BJTs), amplifying the internal current of the device. The current-induced heating effect generates more heat, leading to the SEB effect due to thermal breakdown.

[0003] Since the discovery of SEB, numerous SEB hardening methods have been studied and proposed extensively. For example, P-type hardening methods can be implemented within the device. + Source region expansion, in N - Introducing a buffer layer between the drift region and the substrate, and introducing minority carrier lifetime recombination centers in the drift region, can effectively improve the device's SEB resistance, but at the same time, they sacrifice the device's basic electrical characteristics. For example, P + Source region extension methods tend to reduce the carrier concentration in the channel region, which can lower the forward conduction current density of the device. The introduction of a buffer layer, while reducing the peak electric field of the substrate junction, also increases the forward conduction resistance. The introduction of minority carrier lifetime recombination centers inevitably increases the reverse leakage current density of the device, leading to increased power consumption, which does not meet the low power consumption requirements of aerospace semiconductor devices. Furthermore, current single-event burn-in resistance hardening structures for power semiconductor devices mainly focus on planar gate power MOSFETs, lacking single-event burn-in resistance hardening structures for trench gate power MOSFETs. Summary of the Invention

[0004] This invention provides a trench gate power MOSFET device with single-particle burn-through hardening and its fabrication method, to overcome the problem that existing SEB hardening structures sacrifice the basic electrical characteristics of the device.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A trench gate power MOSFET device reinforced against single-event burn-out includes:

[0007] N-type substrate region;

[0008] The N-type drift region is located on the upper surface of the N-type substrate region.

[0009] N-type polycrystalline silicon, wherein the N-type polycrystalline silicon is located in a deep trench in the middle above the N-type drift region;

[0010] A current spreading layer, the current spreading layer being located on the upper surface of the N-type drift region and on both sides of the N-type polysilicon;

[0011] Boron-doped regions, wherein the boron-doped regions are located on the upper surface of the current spreading layer and on both sides of the N-type polysilicon;

[0012] A P-type high-concentration doped region and an N-type high-concentration source region, wherein the P-type high-concentration doped region is located between the N-type polysilicon and the N-type high-concentration source region;

[0013] Drain electrode, the drain electrode being located below the N-type substrate region;

[0014] The source electrode is located above the N-type polysilicon, the P-type high-concentration doped region, and the N-type high-concentration source region.

[0015] A gate, which is above the current spreading layer and connected to the N-type high-concentration source region and the boron-doped region, and the gate is symmetrically arranged with the N-type polysilicon as the center;

[0016] The P-type shielding regions are located between the N-type polysilicon and the N-type drift region, and between the gate and the current spreading layer.

[0017] Furthermore, the deep trench has a depth of 4.4 μm and a width of 2 μm;

[0018] The oxide layer in the deep trench has a thickness of 0.1 μm, and the N-type polycrystalline silicon has a depth of 3.9 μm and a width of 1.8 μm.

[0019] Furthermore, the epitaxial width of the current spreading layer is 8.4 μm, the overall epitaxial thickness is 1.8 μm, and the ion doping concentration is 5 × 10⁻⁶. 16 cm -3 .

[0020] Furthermore, the P-type shielding region has a width of 2 μm, a thickness of 0.4 μm, and an ion doping concentration of 7 × 10⁻⁶. 17 cm -3 .

[0021] Furthermore, a method for fabricating a trench gate power MOSFET device reinforced against single-particle burn-out includes the following steps:

[0022] S1. A P-type substrate region required for fabricating a power MOSFET device is formed on the upper surface of the P-type substrate region by multiple epitaxial layers to sequentially form a P-type drift region, a current spreading layer, and a boron-doped region.

[0023] S2. A P-type high-concentration doped region is formed in the middle of the upper surface of the boron doped region by ion implantation, and an N-type high-concentration source region is formed on both sides of the P-type high-concentration doped region by ion implantation again.

[0024] S3. Using etching technology, a deep trench is etched in the middle of the top of the obtained component, and shallow trenches are etched on both sides of the top.

[0025] S4. A P-type shielding area is formed at the bottom of the deep trench and the bottom of the shallow trench respectively by ion implantation;

[0026] S5. Using thermal oxidation technology, N-type polysilicon is formed in the deep trench, and a gate is formed in the shallow trench;

[0027] S6. Metallize the upper surface of the N-type polysilicon, the P-type high-concentration doped region, and the N-type high-concentration source region to form the source electrode, and metallize the lower surface of the N-type substrate region to form the drain electrode.

[0028] Beneficial effects: By forming a deep trench at the center of the power MOSFET device and forming a P-type shielding region and N-type polysilicon below the deep trench through ion implantation, and forming a current spreading layer below the boron doped region, the present invention can significantly improve the device's resistance to single-event burn-out without sacrificing electrical characteristics. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a traditional trench gate power MOSFET device.

[0031] Figure 2 This is a schematic diagram of the trench gate power MOSFET device structure reinforced against single-particle burn-out according to the present invention;

[0032] Figure 3 This is a schematic diagram of the structure corresponding to step S1 in the preparation method of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure corresponding to step S2 in the preparation method of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure corresponding to step S3 in the preparation method of the present invention;

[0035] Figure 6 This is a schematic diagram of the structure corresponding to step S4 in the preparation method of the present invention;

[0036] Figure 7 This is a schematic diagram of the structure corresponding to step S5 in the preparation method of the present invention;

[0037] Figure 8 This is a schematic diagram of the structure corresponding to step S6 in the preparation method of the present invention;

[0038] Figure 9 Temperature simulation diagram of a traditional trench gate power MOSFET device structure;

[0039] Figure 10 This is a temperature simulation diagram of the reinforced structure of the present invention;

[0040] Figure 11 This is a flowchart of the preparation method of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1

[0043] This embodiment provides a trench gate power MOSFET device with single-event burn-through hardening, including:

[0044] N-type substrate region 100;

[0045] N-type drift region 101, the N-type drift region 101 being located on the upper surface of the N-type substrate region 100;

[0046] N-type polysilicon 102, the N-type polysilicon 102 being located in a deep trench in the middle above the N-type drift region 101;

[0047] A current spreading layer 103 is provided on the upper surface of the N-type drift region 101 and on both sides of the N-type polysilicon 102.

[0048] Boron-doped region 104, the boron-doped region 104 being located on the upper surface of the current spreading layer 103 and on both sides of the N-type polysilicon 102;

[0049] P-type high-concentration doped region 105 and N-type high-concentration source region 106, wherein the P-type high-concentration doped region 105 is located between the N-type polysilicon 102 and the N-type high-concentration source region 106;

[0050] Drain 200, the drain 200 being below the N-type substrate region 100;

[0051] Source 201, the source 201 being above the N-type polysilicon 102, the P-type high-concentration doped region 105 and the N-type high-concentration source region 106;

[0052] Gate 202, which is above the current spreading layer 103 and connected to the N-type high-concentration source region 106 and the boron doped region 104, and the gate 202 is symmetrically arranged with the N-type polysilicon 102 as the center.

[0053] P-type shielding region 203, wherein the P-type shielding region 203 is located between the N-type polysilicon 102 and the N-type drift region 101, and between the gate 202 and the current spreading layer 103.

[0054] Specifically, such as Figure 2 The diagram shown is a schematic representation of the cell structure of the trench gate power MOSFET device reinforced against single-particle burn-out according to the present invention. Figure 1 The diagram shown is a schematic of the cell structure of a traditional trench gate power MOSFET device. Figure 2 and Figure 1 The difference is that a deep trench is formed in the middle above the N-type drift region 101, and N-type polysilicon 102 is deposited in the deep trench. On both sides of the N-type polysilicon 102, there are two sets of current extension layers 103, two sets of boron doped regions 104, two sets of P-type high-concentration doped regions 105 and two sets of N-type high-concentration source regions 106 respectively. Gates 202 are provided on the top left and right sides of the device respectively.

[0055] Specifically, simulation verification is used to verify... Figure 1 and Figure 2A comparative study of two structures was conducted: An 1800V trench-gate power MOSFET device was selected. The traditional structure has a cell width of 8.4 μm, a thickness of 28.5 μm, and an ion doping concentration of 5 × 10⁻⁶ in the drift region. 15 cm -3 The cell width of the structure of this invention is 8.4 μm, the thickness is 28.5 μm, and the ion doping concentration in the drift region is 3 × 10⁻⁶. 15 cm -3 The linear energy transfer (LET) of the incident ions was 0.5 pC / μm. The incident trajectory was selected above the N-type high-concentration source region 106, i.e., perpendicularly incident and penetrating the entire device. The charge density generated by the incident ions followed a Gaussian distribution with the following parameters: trajectory radius of 0.05 μm, and initial charge generation time of 4 × 10⁻⁶. -12 s, the width of the Gaussian function is 2×10 -12 s.

[0056] In this embodiment, as Figure 9 As shown, when the incident ion LET value is 0.5 pC / μm, the drain voltage is 1500 V, and the incident position is located above the N-type high-concentration source region and perpendicular to the device surface, Figure 1 The SEB device with the structure shown has a global temperature exceeding 3000K, and the temperature continues to rise over time, far exceeding the sublimation temperature of silicon carbide (2200K), causing thermal breakdown of the device.

[0057] like Figure 10 As shown, when the incident ion LET value is 0.5 pC / μm, the drain voltage is 1500 V, and the incident position is located above the N-type high-concentration source region and perpendicular to the device surface, Figure 2 The SEB device with the structure shown can reduce its global temperature to a maximum of 2200K, which is no higher than the sublimation temperature of silicon carbide (2200K), without thermal breakdown. This is precisely because... Figure 2 The structure forms an N-type polysilicon 102 at the center of the device, which can effectively modulate the internal electric field of the device, making the electric field distribution on the heavy ion incident trajectory smoother, reducing the device power density and thus reducing local high temperature. The N-type polysilicon is connected to the source 201, generating a transverse electric field inside the device, changing the hole flow direction, and preventing a large number of holes from flowing into the boron-doped region 104 and triggering the parasitic bipolar transistor, thus significantly reducing the internal current density of the device and reducing the heat generated by the current thermal effect. The P-type shielding region 203 below the trench is used to protect the trench oxide layer from the influence of the high electric field. The current spreading layer 103 can effectively improve the forward conduction capability of the device, and can significantly improve the device's resistance to single-event burn-out without sacrificing the basic electrical characteristics.

[0058] Example 2

[0059] This embodiment provides a method for fabricating a trench gate power MOSFET device with single-particle burn-through resistance, such as... Figure 11 As shown, it includes the following steps:

[0060] S1. A P-type substrate region 100 required for fabricating a power MOSFET device is formed on the upper surface of the P-type substrate region 100 by multiple epitaxial layers, forming an N-type drift region 101, a current spreading layer 103, and a boron doped region 104.

[0061] S2. A P-type high-concentration doped region 105 is formed in the middle of the upper surface of the boron doped region 104 by ion implantation, and an N-type high-concentration source region 106 is formed on both sides of the P-type high-concentration doped region 105 by ion implantation again.

[0062] S3. Using etching technology, a deep trench is etched in the middle of the top of the obtained component, and shallow trenches are etched on both sides of the top.

[0063] S4. A P-type shielding region 203 is formed at the bottom of the deep trench and the bottom of the shallow trench respectively by ion implantation;

[0064] S5. Using thermal oxidation technology, N-type polysilicon 102 is formed in the deep trench, and gate 202 is formed in the shallow trench;

[0065] S6. Metallize the upper surfaces of the N-type polysilicon 102, the P-type high-concentration doped region 105 and the N-type high-concentration source region 106 to form a source electrode 201, and metallize the lower surface of the N-type substrate region 100 to form a drain electrode 200.

[0066] The deep trench has a depth of 4.4 μm and a width of 2 μm;

[0067] The oxide layer in the deep trench has a thickness of 0.1 μm, and the N-type polycrystalline silicon has a depth of 3.9 μm and a width of 1.8 μm.

[0068] The current spreading layer 103 has an epitaxial width of 8.4 μm, an overall epitaxial thickness of 1.8 μm, and an ion doping concentration of 5 × 10⁻⁶. 16 cm -3 ;

[0069] The P-type shielding region 203 has a width of 2 μm, a thickness of 0.4 μm, and an ion doping concentration of 7 × 10⁻⁶. 17 cm -3 .

[0070] Specifically, such as Figure 3 As shown,

[0071] Specifically, such as Figure 6As shown, corresponding to step S4, a P-type shielding region 203 is formed at the bottom of the deep trench and the bottom of the shallow trench obtained above by ion implantation. The width of the P-type shielding region 203 is 2 μm, the thickness is 0.4 μm, and the ion doping concentration is 7 × 10⁻⁶. 17 cm -3 .

[0072] Specifically, such as Figure 7 As shown, corresponding to step S5, N-type polysilicon 102 is formed in the obtained deep trench using thermal oxidation technology, and gate 202 is formed in the obtained shallow trench. The thickness of the oxide layer in the deep trench is 0.1 μm, the depth of the N-type polysilicon 102 is 3.9 μm, and the width is 1.8 μm.

[0073] Specifically, such as Figure 8 As shown, corresponding to step S6, the upper surface of the obtained component is metallized to form the source 201, and the lower surface is metallized to form the drain 200, thus obtaining the ruggedized power MOSFET device of the present invention.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A trench gate power MOSFET device reinforced against single-particle burn-out, characterized in that, include: N-type substrate region (100); N-type drift region (101), the N-type drift region (101) is on the upper surface of the N-type substrate region (100); N-type polysilicon (102), the N-type polysilicon (102) being located in a deep trench in the middle above the N-type drift region (101); A current spreading layer (103) is located on the upper surface of the N-type drift region (101) and on both sides of the N-type polysilicon (102). Boron-doped region (104) is located on the upper surface of the current spreading layer (103) and on both sides of the N-type polysilicon (102). The P-type high-concentration doped region (105) and the N-type high-concentration source region (106) are located between the N-type polysilicon (102) and the N-type high-concentration source region (106). Drain (200), the drain (200) being located below the N-type substrate region (100); Source (201), the source (201) being above the N-type polysilicon (102), the P-type high-concentration doped region (105) and the N-type high-concentration source region (106); A gate (202) is located above the current spreading layer (103) and connected to the N-type high-concentration source region (106) and the boron-doped region (104), and the gate (202) is symmetrically arranged with the N-type polysilicon (102) as the center. P-type shielding region (203) is located between the N-type polysilicon (102) and the N-type drift region (101), and between the gate (202) and the current spreading layer (103).

2. The trench gate power MOSFET device with single-particle burn-in resistant reinforcement according to claim 1, characterized in that, The deep trench has a depth of 4.4 μm and a width of 2 μm; The oxide layer in the deep trench has a thickness of 0.1 μm, and the N-type polycrystalline silicon has a depth of 3.9 μm and a width of 1.8 μm.

3. The trench gate power MOSFET device reinforced against single-event burn-out according to claim 1, characterized in that, The current spreading layer (103) has an epitaxial width of 8.4 μm, an overall epitaxial thickness of 1.8 μm, and an ion doping concentration of 5 × 10⁻⁶. 16 cm -3 .

4. The trench gate power MOSFET device with single-particle burn-in resistant reinforcement according to claim 1, characterized in that, The P-type shielding region (203) has a width of 2 μm, a thickness of 0.4 μm, and an ion doping concentration of 7 × 10⁻⁶. 17 cm -3 .

5. A method for fabricating a trench gate power MOSFET device with single-particle burn-through resistance according to any one of claims 1 to 4, characterized in that, Includes the following steps: S1. A P-type substrate region (100) required for fabricating a power MOSFET device is formed on the upper surface of the P-type substrate region (100) by multiple epitaxial layers, forming an N-type drift region (101), a current spreading layer (103), and a boron doped region (104). S2. A P-type high-concentration doped region (105) is formed in the middle of the upper surface of the boron doped region (104) by ion implantation, and an N-type high-concentration source region (106) is formed on both sides of the P-type high-concentration doped region (105) by ion implantation again. S3. Using etching technology, a deep trench is etched in the middle of the top of the obtained component, and shallow trenches are etched on both sides of the top. S4. A P-type shielding area (203) is formed at the bottom of the deep trench and the bottom of the shallow trench respectively by ion implantation; S5. Using thermal oxidation technology, N-type polycrystalline silicon (102) is formed in the deep trench, and a gate (202) is formed in the shallow trench; S6. The upper surfaces of the N-type polysilicon (102), the P-type high-concentration doped region (105) and the N-type high-concentration source region (106) are metallized to form a source electrode (201), and the lower surface of the N-type substrate region (100) is metallized to form a drain electrode (200).

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