A radar jamming detection method based on radio frequency sampling

Abstract

The present invention relates to the field of radar signal processing, and in particular to a method for quickly detecting the operating frequency of an externally interfered radar. The present invention adopts an AD radio frequency sampling chip, and the front end of the radar receiver only has filtering and amplification links. The broadband signal A / D conversion is placed close to the radio frequency antenna, which can quickly digitize analog signals with larger amplitudes. At the same time, the sampling signal is digitally mixed and filtered and extracted inside the AD chip to reduce the amount of data transmitted and the subsequent data processing time. The FPGA receives the AD sampled I / Q data through the JESD204B high-speed link, and only performs mixing and filtering on the I / Q data to calculate the signal amplitude value, so that the frequency of the interference signal can be determined. The method has a small number of devices, a simple architecture, a small amount of calculation, and low requirements for FPGA chip resources, while greatly shortening the time consumed in interference detection.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing, and in particular to a method for rapidly detecting external interference with radar operating frequency. Background Art

[0002] In modern warfare, the struggle for air and electromagnetic supremacy is becoming increasingly fierce. Radar, as a weapon combining air and electromagnetic warfare, has become increasingly valuable. Radar detects targets by radiating electromagnetic waves through space, which are then reflected by the radar. Jamming radar can prevent it from detecting, tracking, or locating a target, or cause useful information to be lost among numerous false targets, preventing it from obtaining true target information. Active jamming of the radar's operating frequency is currently the primary method for soft-killing radars.

[0003] In today's increasingly complex electromagnetic environment, radar frequency hopping technology is a crucial anti-interference measure and a key indicator of radar anti-interference performance. Currently, the speed of a radar's frequency hopping is primarily determined by the interference detection time and the response time of the frequency source. Optimizing the hardware and algorithms of the interference detection module is a key means of improving radar frequency hopping speed and has a direct impact on anti-interference effectiveness. Therefore, all new radars are placing significant emphasis on radar interference detection, striving for higher, faster, and more accurate anti-interference effectiveness.

[0004] Traditional interference detection methods typically filter RF signals through limiting filtering, low-noise amplification, analog mixing (down-conversion), and filtering to an intermediate frequency (IF). After A / D conversion, the data is stored and then analyzed using an FFT spectrum analysis to determine the interference frequency band. This method requires numerous analog components, large amounts of data, and complex calculations. Determining the interference frequency band is time-consuming, significantly impacting the timeliness of interference detection. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention provides a radar jammer detection method based on RF sampling. This method utilizes an AD RF sampling chip, with the radar receiver front end consisting solely of filtering and amplification. This method performs A / D conversion of broadband signals as close to the RF antenna as possible, digitizing the larger analog signal. This invention features a small number of components, a simple architecture, and minimal computational effort.

[0006] The technical solution of the present invention is: a radar interference detection method based on radio frequency sampling, characterized in that it includes the following steps:

[0007] Step A: Select appropriate frequency according to radar operating frequency and perform multiple mixing;

[0008] Step 1. Select the target carrier frequency f c ;

[0009] Step 2: First mixing in AD:

[0010] After mixing, RF sampling outputs I / Q signals:

[0011] I0=x(t)*cos(α);

[0012] Q0=-x(t)*sin(α);

[0013] x(t) is the sampled signal;

[0014]

[0015]

[0016] f t is the actual mixing frequency; α is the radian value converted from the primary mixing frequency; n is the number of binary complement bits inside the RF sampling chip; f s is the RF sampling frequency,

[0017] After mixing, the I0 / Q0 signal is filtered and extracted by the RF sampling chip, and then the output data is I1 / Q1;

[0018] Step 3: Secondary mixing in FPGA compensates for the frequency deviation of primary mixing:

[0019] Output I / Q signal value after secondary mixing:

[0020] I2=Q1*cos(β)+I1*sin(β);

[0021] Q2=I1*cos(β)-Q1*sin(β);

[0022]

[0023] β is the radian value converted from the secondary mixing frequency; f p The frequency value that needs to be compensated for the secondary mixing; f a is the FPGA internal NCO enable frequency;

[0024] Step 4: Third frequency mixing in FPGA:

[0025] The radar has k operating frequencies, namely f1, f2, f3...f k-1 、f k ,

[0026] The signal after mixing:

[0027] I3=Q2*cos(γ)+I2*sin(γ);

[0028] Q3=I2*cos(γ)-Q2*sin(γ);

[0029]

[0030] Y is the radian value converted from the third-order mixing frequency; f d is the minimum step between adjacent frequency points; h is the detection frequency point number;

[0031] Step B: Select appropriate filter according to radar operating bandwidth;

[0032] Step C: Obtain the signal amplitude and calculate the signal-to-noise ratio to determine whether there is interference at the current frequency.

[0033] The present invention has the following beneficial effects: Compared with previous methods of performing multi-channel filtering or collecting large amounts of data for FFT in FPGAs or computer software, the present invention reduces the amount of data transmission and subsequent data processing time. For example, when the FPGA operates at 200MHz, the method of the present invention can control the processing time to 50ns to 100ns, which previously generally required more than 1ms. The invention also requires fewer components, has a simple architecture, and requires less computation. The method does not require the invocation of a large number of FIR filters or the storage of large amounts of data, thereby reducing the consumption of device resources. It also has low requirements for FPGA chip resources and greatly shortens the time required for interference detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is the hardware structure diagram.

[0035] Figure 2 The data processing flow chart is shown in Figure 2.

[0036] Figure 3 Sample diagram of the internal working principle of the RF chip.

[0037] Figure 4 This is the working principle diagram of the FPGA program. Specific embodiments

[0038] The technical solution of the present invention is further described below with reference to the accompanying drawings.

[0039] like Figures 1 to 4 As shown, the present invention provides a radar interference detection method based on radio frequency sampling, which includes the following steps:

[0040] Step A: Select appropriate frequencies according to the radar operating frequency and perform multiple mixing.

[0041] Step 1: Since the interference frequency is only effective for the radar operating frequency, the target carrier frequency of the RF sampling chip mixing is selected according to the radar operating frequency. In order to prevent aliasing and maximize the use of the sampling bandwidth of the RF chip, the first operating frequency f1 or the last operating frequency f1 of the radar is generally selected.k As the target carrier frequency f c .

[0042] Step 2: Perform a frequency mixing at the radar RF sampling end:

[0043] Each digital downconverter (DDC) in the RF sampling chip has an n-bit digital coherent oscillator (NCO) to support the frequency conversion process. The NCO adjusts the input spectrum to a DC signal, which is then effectively filtered by the filter inside the RF sampling chip to prevent signal aliasing. The RF sampling mixing frequency parameters are calculated based on the internal mixer of the RF sampling chip using the following formula:

[0044]

[0045] NCO_FTW is the binary complement value representing the chip, that is, the internal mixing frequency of the chip.

[0046] n is the number of binary complement bits inside the RF sampling chip.

[0047] f s is the RF sampling frequency (clock rate) in Hz.

[0048] f c is the desired target carrier frequency in Hz.

[0049] Mod() is the remainder function.

[0050] round() is a rounding function.

[0051] After mixing, RF sampling outputs I / Q signals:

[0052] I0=x(t)*cos(α);

[0053] Q0=--x(t)*sin(α);

[0054] x(t) is the sampled signal.

[0055]

[0056]

[0057] f t is the actual mixing frequency in Hz.

[0058] α is the radian value converted from the primary mixing frequency.

[0059] After mixing, the I0 / Q0 signal is filtered and extracted inside the RF sampling chip, reducing the data rate while ensuring the integrity of the signal spectrum, and outputting the data I1 / Q1.

[0060] Each DDC in the RF sampling chip has only one n-bit NCO. Due to the limitation of the number of binary complement bits inside the chip, a single mixing operation cannot accurately mix the input signal to zero frequency. In this case, a secondary mixing operation is required on the FPGA receiving data I1 / Q1.

[0061] Step 3: Secondary mixing inside the FPGA compensates for the frequency deviation of the primary mixing:

[0062] The primary frequency mixing is performed by setting the register value inside the RF sampling chip. When calculating NCO_FTW, rounding is performed. The decimal part is discarded and converted to a larger frequency. Mixing compensation is required inside the FPGA to accurately mix the target frequency to zero frequency. The calculation formula is as follows:

[0063]

[0064]

[0065] f p The frequency value that needs to be compensated for the secondary mixing, in Hz.

[0066] m is the number of bits of the FPGA internal NCO two's complement code.

[0067] f a It is the FPGA internal NCO enable frequency, in Hz.

[0068] NCO_BC is the two's complement value of the NCO inside the FPGA.

[0069] Output I / Q signal value after secondary mixing:

[0070] I2=Q1*cos(β)+I1*sin(β);

[0071] Q2=I1*cos(β)-Q1*sin(β);

[0072]

[0073] β is the radian value converted from the second mixing frequency.

[0074] Through the secondary mixing inside the FPGA, the target carrier frequency f c Accurately mixing to zero intermediate frequency solves the frequency deviation caused by internal mixing in the RF sampling chip.

[0075] Step 4: Select the path according to all the operating frequencies of the radar system and perform three-way mixing inside the FPGA:

[0076] The radar has k operating frequencies, namely f1, f2, f3...f k-1 、fk The minimum step between adjacent frequency points is f d , calculate the NCO binary complement value of the FPGA internal step frequency according to the formula, the formula is as follows:

[0077]

[0078] When detecting the hth operating frequency point, the mixing NCO_TH value is:

[0079] NCO_TH=h*NCO_BJ(1≤h≤k)

[0080] Within a radar pulse repetition period PRI, the value of the third-order mixing NCO_TH generated by the NCO inside the FPGA can be quickly changed by continuously changing the value of the detection frequency h. The output I / Q signal value after the third mixing is:

[0081] I3=Q2*cos(γ)+I2*sin(γ);

[0082] Q3=I2*cos(γ)-Q2*sin(Y);

[0083]

[0084] γ is the radian value converted from the third-order mixing frequency.

[0085] The main purpose of the third mixing is to quickly scan the radar's operating frequency points. To ensure the reliability of data calculation, the value of h at each detection frequency point only needs to be maintained at 4-10 working clock cycles.

[0086] Step B: Select an appropriate filter based on the radar operating bandwidth.

[0087] According to the radar working bandwidth, an FIR filter is established to filter out signals other than zero frequency, and the I / Q value after the third mixing is filtered through the filter:

[0088] I4=I3*FIR(t);

[0089] Q4=Q3*FIR(t);

[0090] The filtered signal I4 / Q4 is the DC component of the desired target signal.

[0091] Step C: Obtain the signal amplitude and calculate the signal-to-noise ratio to determine whether there is interference at the current frequency.

[0092] Collect the input signal and calculate the signal amplitude value:

[0093]

[0094] Under the condition of no interference outside the radar, collect the noise signal and calculate the noise amplitude A N And store, the noise amplitude A N It is best to store it in the device in advance and directly retrieve it when using it, which can improve the detection speed. At the hth frequency point, calculate the signal amplitude A h .

[0095] Signal-to-noise ratio is SNR h =A h -A N

[0096] When SNR h When it is greater than the set threshold value, the current frequency f can be determined h There is interference.

[0097] The method provided in this article uses three-way mixing to quickly change the h value in the FPGA and obtain the signal amplitude value to quickly determine whether there is active interference at the current frequency point.

[0098] The following is a detailed example of specific parameters:

[0099] The radar pulse repetition period PRI used in this embodiment is 1ms, and the sampling frequency f s is 1.2GHz, the target carrier frequency f c =960MHz, the radar has k = 10 operating frequency points, namely f1 = 960MHz, f2 = 980MHz, f3 = 1000MHz...f9 = 1120MHz, f 10 =1140MHz, the step size between adjacent frequency points is f d =20MHz. The RF sampling chip samples the AD9680 of ADI Company. The internal two's complement code bit number n = 12 bits. The FPGA internal NC0 two's complement code bit number is set to m = 20. The FPGA internal NCO enable frequency value f a =200MHz.

[0100] Step 1: Calculate the binary complement value of the internal mixing NCO of the RF sampling chip

[0101]

[0102]

[0103]

[0104] The FPGA configures the NCO inside the RF sampling chip using the calculated NCO_FTW value via SPI mode. The input detection signal is converted to data I0 / Q0 through RF sampling analog-to-digital conversion, and filtered and decimated to obtain data I1 / Q1.

[0105] Step 2: Calculate the frequency deviation and the NCO value of the second mixing FPGA internal mixer

[0106] f p =960000-959765.625=234.375Hz

[0107]

[0108] Configure the FPGA internal NCO according to the calculated NCO_BC value (NCO working clock is f a =200MHz), the output secondary mixing NCO value and I1 / Q1 are calculated according to the formula

[0109] I2=Q1*cos(β)+I1*sin(β);

[0110] Q2=I1*cos(β)-Q1*sin(β);

[0111]

[0112] The I2 / Q2 value after secondary mixing can be obtained by calculation.

[0113] Step 3: Calculate the NCO value of the third mixing FPGA internal step mixer

[0114]

[0115] After calculating the step size NCO_BJ, call the FPGA internal multiplier and calculate the value according to the formula

[0116] NCO_TH=h*NCO_BJ(1≤h≤k)

[0117] The NCO_TH value at the hth frequency point can be calculated in real time. The calculation of each frequency point is maintained for 5 clock cycles (this clock cycle can be adjusted according to needs), that is, the h value in the FPGA changes once every 5 clock cycles. The output of the third mixing NCO value and I2 / Q2 is calculated according to the formula

[0118] I3=Q2*cos(γ)+I2*sin(γ);

[0119] Q3=I2*cos(γ)-Q2*sin(γ);

[0120]

[0121] The I3 / Q3 value after secondary mixing can be obtained by calculation.

[0122] Step 4: Filter to obtain the target signal amplitude value and determine whether there is interference

[0123] The I3 / Q3 values after three times are filtered through FIR to obtain the data I4 / Q4, and the signal amplitude A is calculated. h At this time, the amplitude is judged, when SNR h =A h -A N When the value is greater than the threshold, it is considered that there is interference at the current frequency point and frequency hopping is required to avoid the interference.

Claims

1. A radar interference detection method based on radio frequency sampling, characterized by: The following steps are involved: Step A: Select appropriate frequency according to radar operating frequency and perform multiple mixing; Step 1. Select the target carrier frequency ; Step 2: First mixing in AD: After mixing, RF sampling outputs I / Q signals: ; is the sampling signal; ; ; is the actual mixing frequency; It is the radian value converted from the primary mixing frequency; It is the number of binary complement bits inside the RF sampling chip; is the RF sampling frequency; After mixing / The signal is filtered and extracted by the RF sampling chip and then output as data / ; Step 3: Secondary mixing in FPGA compensates for the frequency deviation of primary mixing: Output I / Q signal value after secondary mixing: ； is the radian value converted from the secondary mixing frequency; The frequency value that needs to be compensated for secondary mixing; is the FPGA internal NCO enable frequency; Step 4: Select the path according to all the operating frequencies of the radar system and perform the third mixing in the FPGA: Radar complete set The working frequencies are 、 、 … 、 , The minimum step between adjacent frequency points is , calculate the NCO two's complement value of the FPGA internal step frequency, the formula is: ; In the detection When the working frequency is The values are: ; Within a radar pulse repetition period PRI, by continuously changing the detection frequency The value of each detection frequency The value is maintained for 4-10 working clock cycles, changing the third frequency mixing generated by the NCO inside the FPGA The value of The signal after mixing: ； is the radian value converted from the third-order mixing frequency; Minimum step size between adjacent frequency points; is the detection frequency number; Step B: Select appropriate filter according to radar operating bandwidth; Step C: Obtain the signal amplitude and calculate the signal-to-noise ratio to determine whether there is interference at the current frequency.

2. The radar interference detection method based on radio frequency sampling according to claim 1, characterized in that: Target carrier frequency The first operating frequency Or the final operating frequency .

3. The radar interference detection method based on radio frequency sampling according to claim 1, characterized in that: The specific steps of step B are as follows: filtering the I / Q value after the third mixing through a filter: Filtered signal / is the DC component of the desired target signal.

4. The radar interference detection method based on radio frequency sampling according to claim 1, characterized in that: The specific process of step C is: collect the input signal and calculate the signal amplitude value: ; Calculate the noise amplitude and store it in When the frequency point is reached, the signal amplitude is calculated. ; The signal-to-noise ratio is ;when When it is greater than the set threshold, the current frequency can be determined There is interference.

5. The radar interference detection method based on radio frequency sampling according to claim 1, characterized in that: Noise amplitude Stored in the device in advance.

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