Chip testing method, device, storage medium and chip

Abstract

Embodiments of the present application disclose a chip testing method and device, a storage medium and a chip, and relate to the field of chips. The embodiments of the present application use a same set of programs to test chips of different packaging modes, improve compatibility of a testing process, and reduce workload of programming of testing code. In addition, test data generated by a chip is stored in an external memory outside the chip, compared with that the testing device actively collects the test data on IO pins of the chip, IO operation of the chip can be reduced, and processing overhead of the chip can be reduced.

Description

Technical Field

[0001] This application relates to the field of chips, and more particularly to a chip testing method, apparatus, storage medium, and chip. Background Technology

[0002] Before mass production, chips undergo a Final Test (FT). For cost reasons, the same core die may use different packaging methods, and chips with different packaging methods may have different numbers of I / O pins. In existing FTs, the test equipment communicates with each I / O pin of the chip to complete the test process. However, when testing chips with different packaging methods, it is necessary to configure the test equipment and the test code within the chip according to the chip's I / O pin distribution. This significantly increases the workload of writing test code and reduces testing efficiency. Summary of the Invention

[0003] This application provides a chip testing method, apparatus, storage medium, and chip, which can solve the problem of low testing efficiency in existing technologies where test equipment requires writing test code for chips with different packaging methods. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a chip testing method, wherein the chip is provided with a first debugging pin and a second debugging pin, the first debugging pin and the second debugging pin are I / O pins, the first debugging pin is connected to the clock pin of the off-chip memory, and the second debugging pin is connected to the data pin of the off-chip memory;

[0005] The method includes:

[0006] When the preset conditions are met, switch to test mode;

[0007] In test mode, a clock signal is received via the first debug pin;

[0008] Receive test commands from the test equipment via the second debug pin;

[0009] Execute the test operation according to the test instruction;

[0010] If the test operation generates test data, the test data is written to the off-chip memory via the second debug pin.

[0011] Secondly, embodiments of this application provide a chip testing device applied to a chip, wherein the chip is provided with a first debugging pin and a second debugging pin, the first debugging pin and the second debugging pin being I / O pins, the first debugging pin being connected to the clock pin of an external memory, and the second debugging pin being connected to the data pin of the external memory;

[0012] The chip testing device includes:

[0013] The switching unit is used to switch to test mode when preset conditions are met;

[0014] The transceiver unit is used to receive a clock signal through the first debug pin in test mode;

[0015] The transceiver unit is also configured to receive test commands from the test equipment via the second debug pin;

[0016] An execution unit is used to execute test operations according to the test instructions;

[0017] The write unit is used to write the test data generated by the test operation to the off-chip memory via the second debug pin.

[0018] Thirdly, embodiments of this application provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the above-described method steps.

[0019] Fourthly, embodiments of this application provide a chip that may include a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed by the above-described method steps.

[0020] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0021] Interacting with the chip via two common debug pins: one provides a clock signal, and the other serves as an input pin for the test equipment to send test commands. The chip executes test operations based on these commands and writes the generated test data to external memory. The test equipment then reads this data from the external memory to determine if the test passed. This allows the test equipment to test chips with the same core but different packages without modifying the programs on either the test equipment or the chip. The same program can be used to test chips with different packages, improving test compatibility and reducing the workload of writing test code. Furthermore, storing the chip's test data in external memory reduces I / O operations and lowers processing overhead compared to the test equipment actively collecting data from the chip's I / O pins. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the network architecture provided in the embodiments of this application;

[0024] Figure 2 This is a schematic flowchart of the chip testing method provided in the embodiments of this application;

[0025] Figure 3 This is a schematic diagram of the memory space distribution of the on-chip memory provided in an embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the structure of a chip testing device provided in this application;

[0027] Figure 5 This is a schematic diagram of the structure of a chip provided in this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0029] It should be noted that the chip testing method provided in this application is generally executed by a chip testing device, which is typically located within the chip.

[0030] Figure 1 An exemplary system architecture that can be applied to the chip testing method or chip testing apparatus of this application is shown.

[0031] like Figure 1 As shown, the system architecture may include: test equipment 1, chip 2, off-chip memory 3, and test fixture ( Figure 1 (Not shown in the diagram), the test fixture is equipped with one or more sockets, and the chip is embedded in the socket to communicate with the test equipment and the off-chip memory 3.

[0032] In this system, test device 1, chip 2, and external memory 3 communicate via serial ports. Specifically, test device 1 communicates with chip 2 via serial port, chip 2 communicates with external memory 3 via serial port, and test device 1 communicates with external memory 3 via serial port. For example, the serial communication protocol is SPI (Serial Peripheral Interface), and the corresponding external memory is an SPI interface flash memory.

[0033] In this application, chip 2 can be a microcontroller, processor, or other integrated circuit that performs control functions, such as an STM32 chip. In existing technology, chip 2 has multiple I / O pins, at least two of which are debug pins: a first debug pin (debug1) and a second debug pin (debug2). In normal operating mode, the debug pins function as ordinary I / O pins, while in test mode, they perform debugging functions. In this embodiment, the first debug pin serves as the clock signal input pin, and the second debug pin serves as the control command input pin. Test device 1 is connected to chip 2 via the first and second debug pins. The first debug pin of chip 2 is connected to the clock pin (clk) of the external memory, and the second debug pin of chip 2 is connected to the data pin (data) of the external memory.

[0034] Test equipment 1 includes, but is not limited to, test machines, test hosts, or test servers.

[0035] It should be understood that Figure 1 The number of test equipment, chips, and off-chip memory shown is for illustrative purposes only. The number can be arbitrary, depending on implementation requirements.

[0036] The following will be combined with the appendix Figure 2 This application provides a detailed description of the chip testing method provided in its embodiments. The chip testing apparatus in these embodiments may be... Figure 1 The chip testing device shown.

[0037] Please see Figure 2 This is a flowchart illustrating a chip testing method provided in an embodiment of this application. Figure 2 As shown, the method described in this application embodiment may include the following steps:

[0038] S201. When the preset conditions are met, switch to test mode.

[0039] In this embodiment, preset conditions include, but are not limited to: receiving a user's switching command, receiving a specified sequence on the second debug pin, or detecting a high level on the first or second debug pin. When these preset conditions are met, the chip switches to test mode. In test mode, the testing equipment tests the chip to check whether its various indicators are normal. In contrast to test mode, the chip can also be in normal operating mode. In normal operating mode, the first and second debug pins function as ordinary I / O pins, and the chip calls the main program code in its on-chip memory to execute corresponding functions.

[0040] S202. In test mode, receive the clock signal through the first debug pin.

[0041] In this embodiment, the first debug pin of the chip serves as a clock pin to receive a clock signal. The clock signal can be provided by a test device or by an external clock source. This application does not impose any restrictions. The clock signal provides a clock source for the chip's operation.

[0042] S203: Receive test commands from the test equipment via the second debug pin.

[0043] In this embodiment, the second debug pin receives test instructions from the test device. The test instructions include, but are not limited to: read register instructions, write register instructions, read on-chip memory instructions, write on-chip memory instructions, program continue execution instructions, and program start address setting instructions.

[0044] The read register instruction is used to read the value of a register in the chip. The read register instruction carries the register address and write opcode. After receiving the read register instruction, the chip looks up the corresponding register according to the register address, then reads the value in the register, and writes the read value to the external memory through the second debug pin.

[0045] The write register instruction is used to write values ​​to the chip's registers. The write register instruction carries the register address, the value to be written, and the write opcode. After receiving the write register instruction, the chip looks up the corresponding register according to the register address and then writes the value into the register.

[0046] The read on-chip memory instruction is used to read the value of the on-chip memory in the chip. The on-chip memory includes ROM and RAM, and includes multiple storage units. Each storage unit corresponds to a storage unit address. The size of the storage unit can be determined according to actual needs. The read on-chip memory instruction carries the storage unit address and read opcode. The chip writes the read value to the off-chip memory through the second debug pin.

[0047] Furthermore, after the main program code is written, the chip determines whether the main program code is correct based on the instructions from the on-chip memory of the test device. The determination process is as follows: the chip reads the main program code and the corresponding CRC check code in the main code area, calculates the CRC check code obtained from the main program code, and compares whether the calculated CRC check code and the read CRC check code are the same. If they are the same, the verification passes; otherwise, the verification fails.

[0048] The write-on-chip memory instruction is used to write values ​​to the on-chip memory. The write-on-chip memory instruction carries the memory cell address, the value to be written, and the write operation code. After receiving the write-on-chip memory instruction, the chip first performs an erase operation on the sector where the memory cell is located, and then performs the write operation.

[0049] The program continue execution instruction is used to instruct the chip to continue executing the program. After the chip completes the test of a test item, it will perform a waiting operation to wait for the next test item to be executed. After the test equipment sends the program continue execution instruction to the chip, the chip will execute the next test item.

[0050] The program start address setting instruction is used to set the starting address of the chip's main program code. The chip will execute the main program code at this starting address after power-on.

[0051] For example: see Figure 3 The diagram shows the storage space distribution of the chip's on-chip memory. The on-chip memory includes a boot sector and a main code sector, which are distributed continuously. The chip sets the starting address of the main code sector according to the program start address. After power-on, the chip runs the main program code in the main code sector.

[0052] S204. Execute the test operation according to the test command.

[0053] S205. If the test operation generates test data, write the test data to the off-chip memory through the second debug pin.

[0054] In this test, a write operation modifies the value of the on-chip memory or register; a write operation reads the value of the on-chip register or register and then writes the read value (i.e., test data) to the off-chip memory via the second debug pin. Furthermore, the off-chip memory can be an SPI interface flash memory. After the test equipment completes the test, it reads the test data from the off-chip memory and compares it with pre-stored standard data to determine whether the chip test passed. By using off-chip memory to store test data, the test equipment does not need to collect data on the I / O pins, improving test efficiency.

[0055] In the embodiments of this application, when the test device tests the chip, it interacts with the chip through two common debug pins. One debug pin provides a clock signal to the chip, and the other debug pin serves as an input pin for the test device to send test commands. The chip executes test operations based on the test commands from the test device, and then writes the test data generated during the test into external memory. The test device can then read the test data from the external memory to determine whether the test has passed. In this way, when testing chips with the same core but different packaging methods, the test device does not need to modify the programs in the test device and the chip. The same program can be used to test chips with different packaging methods, improving the compatibility of the testing process and reducing the workload of writing test code. Furthermore, by storing the test data generated by the chip in external memory, compared to the test device actively collecting test data on the chip's I / O pins, the chip's I / O operations can be reduced, lowering the chip's processing overhead.

[0056] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0057] Please see Figure 4 This illustration shows a schematic diagram of a chip testing apparatus provided in an exemplary embodiment of this application, hereinafter referred to as apparatus 4. Apparatus 4 can be implemented as all or part of a chip through software, hardware, or a combination of both. Apparatus 4 includes: a switching unit 401, a transceiver unit 402, an execution unit 403, and a writing unit 404.

[0058] The switching unit 401 is used to switch to test mode when preset conditions are met;

[0059] The transceiver unit 402 is used to receive a clock signal through the first debug pin in test mode;

[0060] The transceiver unit 402 is also used to receive test commands from the test equipment via the second debugging pin;

[0061] Execution unit 403 is used to execute test operations according to the test instructions;

[0062] The write unit 404 is used to write the test data generated by the test operation to the off-chip memory via the second debug pin.

[0063] In one or more possible embodiments, the test instructions include:

[0064] Read register instructions, write register instructions, read on-chip memory instructions, write on-chip memory instructions, program continue execution instructions, or program start address setting instructions.

[0065] In one or more possible embodiments, the chip and the off-chip memory communicate via the Serial Peripheral Interface (SPI) protocol.

[0066] In one or more possible embodiments, the test operation is performed according to the test instruction:

[0067] The main program code and associated CRC checksum are read from the main code area according to the read memory instruction;

[0068] Calculate the CRC code based on the main program code read;

[0069] Compare whether the read CRC code and the calculated CRC code are the same;

[0070] If they are the same, then the main program code verification passes;

[0071] If they are not the same, then the main program code verification passes.

[0072] In one or more possible embodiments, the preset conditions include: receiving a switching command from a user; or receiving a specified sequence from a test device via a second debug pin; or detecting that the levels on the first debug pin and the second debug pin are high.

[0073] In one or more possible embodiments, the clock signal is provided by the test equipment or by an external clock source.

[0074] In one or more possible embodiments, the chip is an STM32 series chip.

[0075] It should be noted that the device 4 provided in the above embodiments is only illustrated by the division of the above functional modules when executing the chip testing method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the above functions. In addition, the chip testing device and the chip testing method embodiments provided in the above embodiments belong to the same concept, and the implementation process can be found in the method embodiments, which will not be repeated here.

[0076] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0077] This application also provides a computer storage medium that can store multiple instructions, which are adapted to be loaded and executed by a processor as described above. Figure 2 The method steps of the illustrated embodiment can be found in the following documentation for detailed execution. Figure 2 The specific details of the illustrated embodiments will not be elaborated here.

[0078] This application also provides a computer program product that stores at least one instruction, which is loaded and executed by the processor to implement the chip testing method described in the above embodiments.

[0079] Please see Figure 5 This provides a schematic diagram of a chip structure for an embodiment of this application. Figure 5 As shown, the chip 500 may include: at least one processor 501, at least one network interface 504, memory 503, and at least one communication bus 502.

[0080] The communication bus 502 is used to enable communication between these components.

[0081] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0082] The processor 501 may include one or more processing cores.

[0083] Processor 501 connects various parts within chip 500 using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory 503, and by calling data stored in memory 503. Optionally, processor 501 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 501 can integrate one or more of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem can also be implemented as a separate chip without being integrated into processor 501.

[0084] The memory 503 may include random access memory (RAM) or read-only memory. Optionally, the memory 503 may include a non-transitory computer-readable storage medium. The memory 503 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 503 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 503 may also be at least one storage device located remotely from the aforementioned processor 501. Figure 5 As shown, the memory 503, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.

[0085] exist Figure 5 In the chip 500 shown, the processor 501 can be used to call the application program stored in the memory 503 and specifically execute, such as... Figure 2 The method shown can be referred to for details. Figure 2 As shown, it will not be elaborated further here.

[0086] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0087] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A chip testing method, characterized in that, The chip is applied to a device with a first debug pin and a second debug pin, both of which are I / O pins. The first debug pin is connected to the clock pin of the external memory, and the second debug pin is connected to the data pin of the external memory. The chip's on-chip memory includes a boot sector and a main code sector, which are distributed continuously. The chip sets the starting address of the main code sector according to the program start address, and after power-on, the chip runs the main program code in the main code sector according to the starting address. The method includes: When the preset conditions are met, switch to test mode; In test mode, a clock signal is received via the first debug pin; Receive test commands from the test equipment via the second debug pin; Execute the test operation according to the test instruction; If the test operation generates test data, the test data is written to the off-chip memory via the second debug pin. Test instructions include, but are not limited to: read register instructions, write register instructions, read on-chip memory instructions, write on-chip memory instructions, program continue execution instructions, and program start address setting instructions. The main program code and associated CRC code in the main code area are read according to the read on-chip memory instructions. The CRC code is calculated based on the read main program code. The read CRC code and the calculated CRC code are compared. If they are the same, the main program code verification passes; if they are not the same, the main program code verification fails. The chip and the off-chip memory communicate via the Serial Peripheral Interface (SPI) protocol.

2. The method according to claim 1, characterized in that, The preset conditions include: receiving a switching command from the user; or receiving a specified sequence from the test device through the second debugging pin; or detecting that the level on the first debugging pin and the second debugging pin is high.

3. The method according to claim 2, characterized in that, The clock signal is provided by the test equipment or an external clock source.

4. The method according to claim 3, characterized in that, The chip in question is an STM32 series chip.

5. A chip testing device, characterized in that, The chip is applied to a device with a first debug pin and a second debug pin, both of which are I / O pins. The first debug pin is connected to the clock pin of the external memory, and the second debug pin is connected to the data pin of the external memory. The chip's on-chip memory includes a boot sector and a main code sector, which are distributed continuously. The chip sets the starting address of the main code sector according to the program start address, and after power-on, the chip runs the main program code in the main code sector according to the starting address. The chip testing device includes: The switching unit is used to switch to test mode when preset conditions are met; The transceiver unit is used to receive a clock signal through the first debug pin in test mode; The transceiver unit is also configured to receive test commands from the test equipment via the second debug pin; An execution unit is used to execute test operations according to the test instructions; The writing unit is used to write test data generated by the test operation to the off-chip memory via the second debug pin. Test instructions include, but are not limited to: read register instructions, write register instructions, read on-chip memory instructions, write on-chip memory instructions, program continue execution instructions, and program start address setting instructions. Based on the read on-chip memory instruction, the main program code and associated CRC code in the main code area are read. The CRC code is calculated based on the read main program code. The read CRC code and the calculated CRC code are compared. If they are the same, the main program code verification passes; otherwise, the main program code verification fails. The chip and the off-chip memory communicate via the Serial Peripheral Interface (SPI) protocol.

6. A computer storage medium, characterized in that, The computer storage medium stores multiple instructions, which are adapted to be loaded by a processor and executed as described in any one of claims 1 to 4.

7. A chip, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed as described in any one of claims 1 to 4.

Images