A device structure and a method of fabricating the same
By forming a concave structure of a conductive two-dimensional material layer and an etch stop layer on the surface of the metal interconnect, the problem of damage to the underlying metal interconnect during via formation is solved, achieving high conductivity and self-alignment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
- Filing Date
- 2022-11-02
- Publication Date
- 2026-06-26
AI Technical Summary
Existing technologies are prone to damaging the underlying metal interconnects when forming vias, and the contact resistance and volume resistance are relatively large, making it difficult to effectively reduce the damage to the interconnect metal and achieve via structures.
A conductive two-dimensional material layer is formed on the surface of the metal interconnect, and a concave structure is formed on the two-dimensional material layer by etching a stop layer. The hydrophobicity and lack of dangling bonds of the two-dimensional material layer are used to achieve selective deposition, forming self-aligned vias, and avoiding excessive etching damage to the underlying metal interconnect.
It improves electron migration rate, reduces contact resistance and bulk resistance of vias, protects underlying metal interconnects, and ensures good contact between vias and underlying metal interconnects.
Smart Images
Figure CN115588649B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a device structure suitable for back-end metal interconnects and its fabrication method. Background Technology
[0002] With the advancement of Moore's Law, the pitch between metal interconnects in back-end processes is continuously shrinking. In back-end processes, via technology is used to interconnect metal interconnects across different layers. To prevent displacement between the via and the underlying metal interconnect, traditional self-alignment methods typically reduce the critical size of the via to ensure good contact. However, this method increases the contact resistance between the via filler metal and the metal interconnect, as well as the via's own bulk resistance.
[0003] Fully self-aligned via (VW) technology first requires creating a height difference between the surface of the metal interconnect located in the trench and the surface of the dielectric layer outside the trench, i.e., forming a concave topography on the metal interconnect surface relative to the dielectric layer surface. Then, a dry etch stop layer is deposited on the dielectric layer surface containing the metal interconnect. Utilizing the concave topography formed on the metal interconnect surface ensures complete alignment between the VW and the underlying metal interconnect, thereby reducing the bulk resistance and contact resistance of the VW by maximizing its critical dimensions.
[0004] Currently, the mainstream technical approach involves creating concave topography on the underlying copper interconnects using wet / dry etching after the underlying copper interconnects have been filled and planarized. However, in this process, the plasma in dry etching and the chemical reagents in wet etching can easily cause damage to the copper metal of the underlying interconnects and result in surface unevenness and other defects.
[0005] Therefore, effectively reducing damage to interconnect metals and achieving through-hole structures is a significant challenge. Summary of the Invention
[0006] The purpose of this invention is to overcome the above-mentioned defects in the prior art and to provide a device structure and its fabrication method.
[0007] To achieve the above objectives, the technical solution of the present invention is as follows:
[0008] This invention provides a method for fabricating a device structure, comprising:
[0009] Provide a substrate having a first dielectric layer formed thereon;
[0010] A first metal interconnect exposed on the surface is formed in the first dielectric layer;
[0011] A conductive two-dimensional material layer pattern is formed on the surface of the first metal interconnect;
[0012] An etch stop layer is formed on the first dielectric layer and the two-dimensional material layer, such that the surface of the etch stop layer on the first dielectric layer is higher than the surface of the etch stop layer on the two-dimensional material layer, so as to form a concave structure on the etch stop layer above the two-dimensional material layer;
[0013] A second dielectric layer is formed on the etch stop layer;
[0014] A first through-hole is formed in the second dielectric layer, with its bottom stopping on the surface of the etch stop layer at the bottom surface of the concave structure;
[0015] Remove the etch stop layer located on the bottom surface of the concave structure to form a second through hole whose bottom stops at the surface of the two-dimensional material layer.
[0016] Further, the step of forming an etch stop layer on the first dielectric layer and the two-dimensional material layer, such that the surface of the etch stop layer on the first dielectric layer is higher than the surface of the etch stop layer on the two-dimensional material layer, to form a concave structure on the etch stop layer above the two-dimensional material layer, specifically includes:
[0017] A first etch stop layer material deposition is performed, utilizing the hydrophobic and dangling bond-free properties of the surface of the two-dimensional material layer to selectively deposit the first etch stop layer material on the first dielectric layer to form a first etch stop layer, and the surface of the first etch stop layer is made higher than the surface of the two-dimensional material layer to form a first concave structure between the surface of the first etch stop layer and the surface of the two-dimensional material layer.
[0018] The surface of the two-dimensional material layer is modified to increase the activation energy of the surface of the two-dimensional material layer;
[0019] A second etch stop layer material deposition is performed to form a second etch stop layer on the first etch stop layer and the two-dimensional material layer, and the surface of the second etch stop layer on the first etch stop layer is higher than the surface of the second etch stop layer on the bottom surface of the first concave structure, so as to form a second concave structure between the surface of the second etch stop layer on the first etch stop layer and the surface of the second etch stop layer on the bottom surface of the first concave structure, thereby forming the concave structure on the second etch stop layer above the two-dimensional material layer.
[0020] Furthermore, the two-dimensional material layer includes a graphene layer.
[0021] Furthermore, the graphene layer is formed by selective growth or transfer.
[0022] Furthermore, by performing hydroxylation modification on the surface of the graphene layer, hydroxyl active groups are attached to the surface of the graphene layer to increase the activation energy of the graphene layer surface.
[0023] Furthermore, the surface of the graphene layer is modified by hydroxylation using carboxylic acids or polyols containing hydroxyl groups.
[0024] Furthermore, the first through-hole is formed in the second dielectric layer using a damascus inlay process, and / or the etch stop layer located on the bottom surface of the concave structure is removed using a wet etching process.
[0025] The present invention also provides a device structure comprising, from bottom to top: a first dielectric layer, an etch stop layer, and a second dielectric layer;
[0026] A first metal interconnect with exposed surface is formed in the first dielectric layer;
[0027] A conductive two-dimensional material layer pattern is formed on the surface of the first metal interconnect.
[0028] A concave structure is formed above the two-dimensional material layer on the etch stop layer, and a window penetrating the etch stop layer is provided on the bottom surface of the concave structure;
[0029] A through-hole is formed in the second dielectric layer, and the bottom of the through-hole is connected to the surface of the two-dimensional material layer through the window.
[0030] Furthermore, the two-dimensional material layer has a modified surface.
[0031] Furthermore, the critical dimension of the through hole is greater than, equal to, or less than the lateral dimension of the concave structure.
[0032] As can be seen from the above technical solution, the present invention can effectively improve the electron migration rate and the conductivity between the upper and lower metal interconnects by forming a two-dimensional material layer pattern on the first metal interconnect located in the first dielectric layer. Simultaneously, by utilizing the hydrophobic properties and lack of dangling bonds on the surface of the two-dimensional material layer, the etch stop layer (first etch stop layer) material can be selectively deposited on the first dielectric layer. This allows for the formation of a concave structure on the etch stop layer (second etch stop layer) above the two-dimensional material layer, enabling interconnection with the first metal interconnect when vias are formed in the second dielectric layer. The lines achieve self-alignment through the concave topographic structure, and the critical size of the via can be appropriately relaxed, effectively ensuring that the second dielectric layer material deposited in the concave topographic structure can be completely removed. In addition, when forming the via, the etch stop layer (second etch stop layer) above the two-dimensional material layer can be used to avoid excessive etching that could damage the first metal interconnect below. After the via is formed, a window is formed on the etch stop layer (second etch stop layer) on the bottom surface of the concave structure, which can ensure complete release of the surface of the first metal interconnect while avoiding damage to the first metal interconnect. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of a device structure according to a preferred embodiment of the present invention;
[0034] Figure 2 This is a flowchart of a device structure fabrication method according to a preferred embodiment of the present invention;
[0035] Figures 3-9 According to a preferred embodiment of the present invention Figure 2 A schematic diagram of the process steps for fabricating a device structure using this method. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.
[0037] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0038] Please see Figure 1 , Figure 1 This is a schematic diagram of a device structure according to a preferred embodiment of the present invention. Figure 1 As shown, a device structure of the present invention includes, from bottom to top: a first dielectric layer 11, an etch stop layer 14, and a second dielectric layer 15.
[0039] In an optional embodiment, the device structure of the present invention may be a device structure based on a complementary metal-oxide-semiconductor back-end via structure.
[0040] In an optional embodiment, the device structure of the present invention may also be a device structure based on the back-end via structure of a fin field-effect transistor.
[0041] In an alternative embodiment, the first dielectric layer 11 may be disposed on a substrate (not shown).
[0042] In an alternative embodiment, the substrate may include a semiconductor material substrate, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate.
[0043] In an alternative embodiment, an active region may be formed on the substrate, and device structures such as gate and source / drain may be formed on the substrate of the active region.
[0044] In an alternative embodiment, another dielectric material layer may be disposed between the substrate and the first dielectric layer 11.
[0045] In an alternative embodiment, the first dielectric layer 11 may be made of a conventional dielectric material. For example, the first dielectric layer 11 may be made of a dielectric material such as silicon oxide, silicon carbide, or black diamond.
[0046] A first metal interconnect 13 with exposed surface is formed in the first dielectric layer 11. In an alternative embodiment, a first trench 12 structure is formed in the first dielectric layer 11, and the first metal interconnect 13 can be formed in the first trench 12 by filling.
[0047] In an alternative embodiment, the surface of the first metal interconnect 13 may be flush with the surface of the first dielectric layer 11.
[0048] In an alternative embodiment, the surface of the first metal interconnect 13 may also be higher or lower than the surface of the first dielectric layer 11.
[0049] In an optional embodiment, the first dielectric layer 11 and the first metal interconnect 13 therein together constitute the first metal interconnect layer.
[0050] In one alternative embodiment, the first metal interconnect layer can be any metal interconnect layer located below the uppermost metal interconnect layer in a multilayer metal interconnect layer disposed on the substrate. For example, when three metal interconnect layers are disposed on the substrate, the first metal interconnect layer can be the first or second metal interconnect layer below the third metal interconnect layer. This can be deduced similarly.
[0051] Please see Figure 1 A patterned structure of a conductive two-dimensional material layer 20 is formed on the surface of the first metal interconnect 13.
[0052] In an optional embodiment, the width of the two-dimensional material layer 20 pattern may correspond to the linewidth of the first metal interconnect 13, thereby covering the surface of the first metal interconnect 13.
[0053] An etch stop layer 14 covers the surfaces of the first dielectric layer 11 and the two-dimensional material layer 20. A concave structure 18 is formed on the etch stop layer 14 located above the two-dimensional material layer 20. That is, the surface of the etch stop layer 14 located above the two-dimensional material layer 20 is lower than the surface of the etch stop layer 14 located on the first dielectric layer 11 on both sides of the two-dimensional material layer 20.
[0054] The concave structure 18 has a window 19 on its bottom surface that penetrates the etch stop layer 14, so that the bottom surface of the concave structure 18 is connected to the surface of the two-dimensional material layer 20.
[0055] In an alternative embodiment, the lateral dimension of window 19 may correspond to the width of the two-dimensional material layer 20 graphic.
[0056] Furthermore, the etch stop layer 14 can form a structure that surrounds the sides of the window 19.
[0057] Please see Figure 1 A through-hole 16 is formed in the second dielectric layer 15. The position of the through-hole 16 corresponds to the position of the first metal interconnect 13. That is, the position of the through-hole 16 corresponds to the vertical position of the concave structure 18, the window 19, and the two-dimensional material layer 20 pattern. Furthermore, the bottom of the through-hole 16 is connected to the surface of the two-dimensional material layer 20 through the concave structure 18 and the window 19 in sequence.
[0058] Furthermore, a second trench 17 structure may be formed in the second dielectric layer 15 above the through hole 16. The upper end of the second trench 17 may form an opening on the surface of the second dielectric layer 15, and the lower end of the second trench 17 may be connected to the top of the through hole 16.
[0059] In an alternative embodiment, the through-hole 16 and the second trench 17 connected above it together form a damascus mosaic structure in the second dielectric layer 15.
[0060] Furthermore, the damascus inlay structure and concave structure 18 and window 19 may also be filled with metal to form a conductive via 16 that forms an ohmic contact with the first metal interconnect 13 through the two-dimensional material layer 20, and a second metal interconnect that forms an ohmic contact with the conductive via 16 in the second trench 17 located above the conductive via 16.
[0061] In an alternative embodiment, the two-dimensional material layer 20 may have a modified surface.
[0062] In an optional embodiment, the two-dimensional material layer 20 may include a graphene layer 20' or other two-dimensional material layer 20 capable of improving electron migration rate and enhancing the conductivity of metal interconnects. Further, the upper surface of the graphene layer 20' may be a modified surface to alter the original hydrophobic and dangling bond-deficient characteristics of the graphene material surface. This significantly improves the deposition capability of the etch stop layer 14 material on the surface of the graphene layer 20' when forming the concave structure 18.
[0063] In an alternative embodiment, the critical dimension of the through-hole 16 may be larger than the lateral dimension of the concave structure 18. Preferably, the longitudinal projected profile of the through-hole 16 can completely encompass the lateral dimension of the concave structure 18, such as... Figure 1 The structure is shown with a through hole 16 located on the right side.
[0064] In another alternative embodiment, the critical dimension of the through-hole 16 may be equal to or substantially equal to the lateral dimension of the concave structure 18, such as... Figure 1 The structure of another through hole 16 located on the left side is shown.
[0065] In other alternative embodiments, the critical dimension of the through hole 16 may also be smaller than the lateral dimension of the concave structure 18.
[0066] In an alternative embodiment, the etch stop layer 14 may be a single-layer or multi-layer stacked structure.
[0067] In an alternative embodiment, the etch stop layer 14 material may include a material such as alumina that has a high etch selectivity with respect to the first dielectric layer 11 and the second dielectric layer 15.
[0068] In an optional embodiment, the material of the second dielectric layer 15 may include dielectric materials such as silicon oxide, silicon carbide, or black diamond.
[0069] In one alternative embodiment, the material of the first metal interconnect 13 may include at least one of metals such as copper, molybdenum, and ruthenium, or an alloy thereof. Alternatively, the material of the first metal interconnect 13 may include other metals besides those mentioned above, or an alloy thereof.
[0070] In one alternative embodiment, the second metal interconnect material may include at least one of metals such as copper, molybdenum, and ruthenium, or an alloy thereof. Alternatively, the second metal interconnect material may include other metals besides those mentioned above, or an alloy thereof.
[0071] The following detailed description of a device structure fabrication method of the present invention, with reference to specific embodiments and accompanying drawings, provides a detailed explanation.
[0072] Please see Figure 2 The present invention provides a method for fabricating a device structure, which can be used to fabricate the aforementioned device structure, and may include the following steps:
[0073] Step S1: Provide a substrate on which a first dielectric layer is formed.
[0074] Please see Figure 3 Taking the fabrication of a via structure in the back end of a fin field-effect transistor device as an example, the fins and front-end structures such as gate and source / drain can be completed first on a silicon substrate, for example, according to the fin field-effect transistor fabrication process.
[0075] Then, the subsequent processes are performed on the silicon substrate with the above structure.
[0076] First, a conventional deposition process can be used to form, for example, a silicon oxide first dielectric layer 11 on a silicon substrate (not shown) with the above structure.
[0077] In an alternative embodiment, other dielectric material layers and related device structures, such as gate leads and source / drain leads, may also be formed between the silicon substrate and the first dielectric layer 11.
[0078] Step S2: Form a first metal interconnect exposed on the surface in the first dielectric layer.
[0079] Please see Figure 3 In an alternative embodiment, a photolithography and etching process may be used to form a first trench 12 on the surface of the first dielectric layer 11, and a metal filling process may be used to fill the first trench 12 with, for example, copper.
[0080] Then, processes such as chemical mechanical polishing can be used to planarize the surface of the filled copper metal, thereby forming the first metal interconnect 13 in the first trench 12.
[0081] The first dielectric layer 11 and the first metal interconnect 13 therein together constitute the first metal interconnect layer.
[0082] The first metal interconnect layer can be any metal interconnect layer located below the topmost metal interconnect layer in a multilayer metal interconnect layer disposed on a silicon substrate.
[0083] Step S3: Form a conductive two-dimensional material layer pattern on the surface of the first metal interconnect.
[0084] Please see Figure 4 In an optional embodiment, a conductive two-dimensional material layer 20, such as graphene, can be formed on the surface of the first metal interconnect 13 using selective growth or transfer methods, and the surface of the first metal interconnect 13 can be covered. Utilizing the two-dimensional carbon atom structure of graphene, the electron migration rate can be effectively improved, enhancing the conductivity of the metal interconnect.
[0085] Step S4: An etch stop layer is formed on the first dielectric layer and the two-dimensional material layer, such that the surface of the etch stop layer on the first dielectric layer is higher than the surface of the etch stop layer on the two-dimensional material layer, so as to form a concave structure on the etch stop layer above the two-dimensional material layer.
[0086] Please see Figure 5 In an alternative embodiment, a first etch stop layer 141 material, such as alumina, may be deposited on the surface of the device structure formed in the above steps using processes such as chemical vapor deposition or atomic layer deposition.
[0087] When depositing the first etch stop layer 141 material, the hydrophobic properties and lack of dangling bonds on the surface of the graphene layer 20' can be utilized to make it difficult for the precursor used to generate alumina to be adsorbed on the surface of the graphene layer 20', thus making it difficult to form alumina deposition. This allows the alumina first etch stop layer 141 material to be selectively deposited on the first dielectric layer 11.
[0088] Alumina can be grown through atomic layer chemical reactions with precursors such as trimethylaluminum and water or oxygen.
[0089] Thus, after deposition, the first etch stop layer 141 will be formed only (or essentially only) on the first dielectric layer 11, and the surface of the first etch stop layer 141 on the first dielectric layer 11 will be higher than the surface of the graphene layer 20'. This creates a transitional first concave structure 181 between the surface of the first etch stop layer 141 on the first dielectric layer 11 and the surface of the graphene layer 20'. The sidewalls of the first concave structure 181 are formed by the sides of the first etch stop layer 141 located on both sides of the graphene layer 20', and the bottom surface of the first concave structure 181 is formed by the surface of the graphene layer 20'.
[0090] Next, a final etch stop layer 14 structure needs to be formed on the surface of the graphene layer 20' for subsequent formation of the via 16, and a concave structure 18 with the final morphology needs to be formed.
[0091] Please see Figure 6In an optional embodiment, a hydroxylation modification process, for example, can be used to modify the surface of the graphene layer 20' to attach hydroxyl active groups to the surface of the graphene layer 20', thereby increasing the activation energy of the surface of the graphene layer 20'.
[0092] Furthermore, hydroxyl-containing carboxylic acid materials, such as 3,4,9,10-perylenetetracarboxylic acid, can be used to hydroxylate and modify the surface of the graphene layer 20'.
[0093] Furthermore, polyol materials, such as propanol and butanol, can also be used to hydroxylate and modify the surface of the graphene layer 20'.
[0094] Please see Figure 7 In an alternative embodiment, a second etch stop layer 142 material, such as alumina, may be deposited on the surface of the device structure formed in the above steps using processes such as chemical vapor deposition or atomic layer deposition.
[0095] When the second etch stop layer 142 material is deposited using processes such as chemical vapor deposition or atomic layer deposition, the hydroxyl modification treatment on the surface of the graphene layer 20' will have a better effect on improving the adsorption capacity of the precursor used to generate alumina on the surface of the graphene layer 20', thereby forming a dense deposition layer of alumina second etch stop layer 142 material on the modified graphene layer 20' surface.
[0096] Thus, a second etch stop layer 142 is formed on the previously formed first etch stop layer 141 and on the surface of the modified graphene layer 20'. Based on the previously formed first concave structure 181, and taking advantage of the fact that the deposition rate of alumina on the first etch stop layer 141 is still greater than that on the surface of the modified graphene layer 20', the surface of the second alumina etch stop layer 142 formed on the first etch stop layer 141 is higher than the surface of the second alumina etch stop layer 142 on the bottom surface of the first concave structure 181 (i.e., the surface of the graphene layer 20'). Therefore, a second concave structure 182 is formed between the surface of the second etch stop layer 142 on the first etch stop layer 141 and the surface of the second etch stop layer 142 on the bottom surface of the first concave structure 181. In other words, a final concave structure 182 is formed above the graphene layer 20', located on the second etch stop layer 142 and formed by the second concave structure 182.
[0097] The first etch stop layer 141 and the second etch stop layer 142 together form the final etch stop layer 14 structure for subsequent formation of the via 16. The etch stop layer 14 located above the graphene layer 20' includes the second etch stop layer 142, and the etch stop layer 14 located outside the graphene layer 20' includes a stacked structure of the first etch stop layer 141 and the second etch stop layer 142.
[0098] Furthermore, the first etch stop layer 141 and the second etch stop layer 142 together form a concave structure 18 with the final morphology.
[0099] Step S5: Form a second dielectric layer on the etch stop layer.
[0100] Please see Figure 8 In an alternative embodiment, conventional deposition processes can be used to form, for example, a second dielectric layer 15 of silicon oxide and a mask layer, on a silicon substrate with the above-described structure.
[0101] The second dielectric layer 15 is used to form the metal interconnect layer above the first metal interconnect layer, namely the second metal interconnect layer.
[0102] Step S6: Form a first through-hole in the second dielectric layer, with the bottom of the etch stop layer surface stopping at the bottom surface of the concave structure.
[0103] Please see Figure 8 In an optional embodiment, a back-end integrated process and a damascus inlay process can be used to form a first through-hole 161 and a second trench 17 structure located above and connected to the first through-hole 161 in the second dielectric layer 15.
[0104] By utilizing the formed concave structure 18, the critical dimensions of the first via 161 can be widened in the subsequent integrated process through photolithography self-alignment, so that the first via 161 completely covers the concave structure 18 and the first metal interconnect 13 below in the lateral width. This allows the material of the second dielectric layer 15 deposited in the concave structure 18 to be completely removed in the dry etching process for the second dielectric layer 15, thereby forming the first via 161 in the second dielectric layer 15, with its bottom stopping on the surface of the etch stop layer 14 on the bottom surface of the concave structure 18.
[0105] Figure 8 The image shows the structure when the critical dimension of a first via 161 on the right side is widened to be greater than the linewidth of the first metal interconnect 13; and in contrast, the image shows the structure when the critical dimension of another first via 161 on the left side is the same as the linewidth of the first metal interconnect 13.
[0106] Meanwhile, the aluminum oxide layer, as the etch stop layer 14 during dry etching, effectively avoids damage to the underlying first metal interconnect 13 caused by over-etching.
[0107] Step S7: Remove the etch stop layer located on the bottom surface of the concave structure to form a second through hole whose bottom stops at the surface of the two-dimensional material layer.
[0108] Please see Figure 9 In an alternative embodiment, a wet etching process can be used to remove the second etch stop layer 142 located on the bottom surface of the concave structure 18, thereby forming a through window 19 on the bottom surface of the concave structure 18, thus opening the surface of the graphene layer 20'.
[0109] At this point, the bottom of the first through-hole 161 will extend into the surface of the graphene layer 20' due to the opening of the bottom surface of the concave structure 18, thereby forming a second through-hole 162 with increased height and connected to the surface of the graphene layer 20', i.e., the bottom of the second through-hole 162 stops at the surface of the graphene layer 20'. The second through-hole 162 replaces the first through-hole 161, forming the through-hole 16 structure with the final shape.
[0110] By using a wet etching process, the second aluminum oxide etching stop layer 142 located on the bottom surface of the concave structure 18 can be effectively removed. This ensures the complete release of the first trench 12 of the lower first metal interconnect layer, while also effectively preventing damage to the copper first metal interconnect 13.
[0111] Subsequently, a metal filling process can be used to fill the formed second trench 17 and via 16 with, for example, copper, to form a second metal interconnect and a conductive via 16 with good ohmic contact with the first metal interconnect 13 through the graphene layer 20' at the lower end.
[0112] The second dielectric layer 15 and the second metal interconnect line therein together constitute a second metal interconnect layer located above the first metal interconnect layer and interconnected by conductive vias 16.
[0113] In summary, by forming a graphene two-dimensional material layer 20 pattern on the first metal interconnect 13 located in the first dielectric layer 11, the present invention can effectively improve the electron migration rate and the conductivity between the upper and lower metal interconnects. Simultaneously, by utilizing the hydrophobic and dangling bond-free properties of the graphene two-dimensional material layer 20 surface, a first etch stop layer 141 material, such as alumina, can be selectively deposited on the first dielectric layer 11. This allows for the formation of a concave structure 18 with a downward-curved surface on the second etch stop layer 142, such as alumina, above the graphene two-dimensional material layer 20. This enables self-alignment between the via 16 formed in the second dielectric layer 15 and the first metal interconnect 13 via the concave structure 18, and allows for a more relaxed critical size of the via 16, effectively ensuring the complete removal of the second dielectric layer 15 material deposited within the concave structure 18. Furthermore, when forming the via 16, the second etch stop layer 142 above the graphene two-dimensional material layer 20 can be used to avoid excessive etching that could damage the first metal interconnect 13 below. After the via 16 is formed, a through window 19 is formed on the second etch stop layer 142 on the bottom surface of the concave structure 18, which can ensure complete release of the surface of the first metal interconnect 13 while also avoiding damage to the first metal interconnect 13.
[0114] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A method for fabricating a device structure, characterized in that, include: Provide a substrate having a first dielectric layer formed thereon; A first metal interconnect exposed on the surface is formed in the first dielectric layer; A conductive two-dimensional material layer pattern is formed on the surface of the first metal interconnect; An etch stop layer is formed on the first dielectric layer and the two-dimensional material layer, such that the surface of the etch stop layer on the first dielectric layer is higher than the surface of the etch stop layer on the two-dimensional material layer, to form a concave structure on the etch stop layer above the two-dimensional material layer. Specifically, this includes: performing a first etch stop layer material deposition, utilizing the hydrophobicity and lack of dangling bonds on the surface of the two-dimensional material layer to selectively deposit the first etch stop layer material on the first dielectric layer to form a first etch stop layer, and ensuring that the surface of the first etch stop layer is higher than the surface of the two-dimensional material layer, to form a second etch stop layer between the surface of the first etch stop layer and the surface of the two-dimensional material layer. A concave structure; the surface of the two-dimensional material layer is modified to increase the activation energy of the surface of the two-dimensional material layer; a second etch stop layer material deposition is performed to form a second etch stop layer on the first etch stop layer and the two-dimensional material layer, and the surface of the second etch stop layer on the first etch stop layer is higher than the surface of the second etch stop layer on the bottom surface of the first concave structure, so as to form a second concave structure between the surface of the second etch stop layer on the first etch stop layer and the surface of the second etch stop layer on the bottom surface of the first concave structure, thereby forming the concave structure on the second etch stop layer above the two-dimensional material layer; A second dielectric layer is formed on the etch stop layer; A first through-hole is formed in the second dielectric layer, with its bottom stopping on the surface of the etch stop layer at the bottom surface of the concave structure; Remove the etch stop layer located on the bottom surface of the concave structure to form a second through hole whose bottom stops at the surface of the two-dimensional material layer.
2. The device structure fabrication method according to claim 1, characterized in that, The two-dimensional material layer includes a graphene layer.
3. The device structure fabrication method according to claim 2, characterized in that, The graphene layer is formed by selective growth or transfer.
4. The device structure fabrication method according to claim 2, characterized in that, By performing hydroxylation modification on the surface of the graphene layer, hydroxyl active groups are attached to the surface of the graphene layer, thereby increasing the activation energy of the graphene layer surface.
5. The device structure fabrication method according to claim 4, characterized in that, The surface of the graphene layer is modified by hydroxylation using carboxylic acids or polyols containing hydroxyl groups.
6. The device structure fabrication method according to claim 1, characterized in that, The first through-hole is formed in the second dielectric layer using a damascus inlay process, and / or the etch stop layer located on the bottom surface of the concave structure is removed using a wet etching process.
7. A device structure, characterized in that, From bottom to top, it includes: a first dielectric layer, an etch stop layer, and a second dielectric layer; A first metal interconnect with exposed surface is formed in the first dielectric layer; A conductive two-dimensional material layer pattern is formed on the surface of the first metal interconnect, and the two-dimensional material layer has a modified surface; A concave structure is formed above the two-dimensional material layer on the etch stop layer. A window penetrating the etch stop layer is provided on the bottom surface of the concave structure, and the sidewalls and bottom surface of the concave structure are formed by the etch stop layer. The sidewalls of the window are surrounded by the etch stop layer. A through-hole is formed in the second dielectric layer, and the bottom of the through-hole is connected to the surface of the two-dimensional material layer through the window; The device structure is prepared using the device structure preparation method according to any one of claims 1 to 6.
8. The device structure according to claim 7, characterized in that, The critical dimension of the through hole is greater than, equal to, or less than the lateral dimension of the concave structure.