Low voltage high linearity heterojunction heit device based on junction field effect modulation

Abstract

This invention provides a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation, comprising a substrate, a buffer layer, and a multilayer heterostructure of at least two alternating layers of barrier and channel layers. Source and drain electrodes are located on either side of the barrier layer and extend into the buffer layer. A passivation layer is formed on the upper surface of the barrier layer. A gate trench is formed in the middle region of the passivation layer, extending through the passivation layer to the upper surface of the barrier layer. The gate electrode includes multiple discrete gate pillars and a gate cap. The multiple discrete gate pillars are periodically arranged along the gate width direction, located within the gate trench, and extend through at least two alternating layers of barrier and channel layers into the buffer layer. The gate cap is located on the upper surface of the multiple discrete gate pillars, supported by the pillars, and has no contact with the passivation and barrier layers. A metal interconnect layer is electrically connected to the source and drain electrodes. This design achieves both low subthreshold swing and meets the application requirements of low power consumption and high linearity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a low-voltage high-linearity heterojunction (HEMT) device based on junction field-effect modulation. Background Technology

[0002] Gallium nitride (GaN), a third-generation semiconductor, has become an ideal material for fabricating high-frequency, high-efficiency power devices due to its superior material properties such as high electron saturation velocity, high mobility, and high critical breakdown electric field. With the rapid development of 5G / 6G millimeter-wave communication technology, wireless communication systems are placing higher demands on the output power density and operating efficiency of power devices. To overcome the current density bottleneck of traditional single-layer heterojunction HEMTs, researchers have developed multilayer heterojunction HEMT devices, inducing multiple two-dimensional electron gas (2DEG) channels to achieve higher current densities. However, as the number of heterojunction layers increases, the total thickness of the barrier layer increases accordingly, leading to a gradual weakening of the gate control capability of channels farther from the gate, causing problems such as threshold voltage drift and subthreshold swing degradation. Simultaneously, in multi-channel structures, the thicker channel layers hinder effective electron coupling between different channels, resulting in a multi-peak characteristic in the device's transconductance curve, severely deteriorating its linearity and intermodulation characteristics, thus limiting the practical application of multi-channel GaN devices in modern wireless communication systems. In addition, existing technologies mainly focus on flattening the transconductance curve, but fail to effectively solve the problem of increased knee voltage (Vknee) caused by increased channel layer number and insufficient gate control capability. Higher knee voltage means that the device needs a larger drain bias to enter the saturation operating region, which significantly increases static and dynamic power consumption and limits its application in low power supply voltage systems (such as portable devices and base station power amplifier preamplifiers).

[0003] To improve the gate control capability and electrical performance of multilayer heterojunction HEMT devices, several technical solutions have been proposed. One solution is to use a Fin structure, such as a multi-channel AlGaN / GaN metal-oxide-semiconductor high electron mobility transistor with a three-dimensional gate. Another solution is to use deeply embedded ohmic contacts, such as a deeply embedded ohmic contact structure that penetrates the multilayer heterojunction. However, the above-mentioned existing technologies have significant shortcomings: in the deep-embedded ohmic contact technology, the large-scale coverage of the strong electric field can cause serious heat dissipation problems, and the increase in gate-drain capacitance and gate-source capacitance negatively affects frequency characteristics; in the Fin structure, the additional gate control capability introduced by the side gate leads to an increase in gate capacitance, which also causes degradation in device frequency performance. Therefore, existing technologies have failed to effectively solve the problem of increased knee voltage caused by the increase in the number of channel layers, resulting in the inability of the device to achieve both low subthreshold swing and meet the application requirements of low power consumption and high linearity. Summary of the Invention

[0004] The purpose of this invention is to provide a low-voltage, high-linearity heterojunction HEMT device based on junction field effect modulation, which solves the problem that existing technologies cannot achieve both low subthreshold swing and low power consumption and high linearity in application requirements.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: The first aspect of the present invention provides a low-voltage high-linearity heterojunction HEMT device based on junction field effect modulation, comprising a substrate, a buffer layer and a multilayer heterostructure arranged sequentially from bottom to top, wherein the multilayer heterostructure includes at least two alternately stacked barrier layers and channel layers. The source electrode is formed in the edge region of one side of the barrier layer, and the source electrode sequentially penetrates at least two alternately stacked barrier layers and channel layers into the buffer layer. The drain electrode is formed in the edge region on the other side of the barrier layer. The drain electrode passes through at least two alternately stacked barrier layers and channel layers into the buffer layer. A passivation layer is formed on the upper surface of the barrier layer and is in contact with the inner walls of the source and drain electrodes. The gate trench is formed in the middle region of the passivation layer and extends through the passivation layer to the upper surface of the barrier layer. The gate electrode includes multiple discrete gate pillars and a gate cap. The multiple discrete gate pillars are arranged periodically along the gate width direction. The multiple discrete gate pillars are located in the gate trench and extend through at least two alternately stacked barrier layers and channel layers into the buffer layer. The gate cap is located on the upper surface of the multiple discrete gate pillars and is supported by the multiple discrete gate pillars, and has no contact with the passivation layer and barrier layer. The metal interconnect layer is electrically connected to the source and drain electrodes.

[0006] A second aspect of this invention provides a method for fabricating a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation, comprising: A buffer layer and a multilayer heterostructure are epitaxially grown sequentially on a substrate. The multilayer heterostructure includes at least two alternating barrier layers and channel layers. Source metal and drain metal are photolithographically etched and deposited on the two edge regions of the barrier layer, respectively, and then annealed to form source electrode and drain electrode. The source electrode and drain electrode penetrate at least two alternately stacked barrier layers and channel layers into the buffer layer. A passivation layer is deposited on the upper surface of the barrier layer, and the passivation layer is in contact with the inner walls of the source electrode and the drain electrode. Photolithography is used to etch the passivation layer in the middle region to form a gate trench, which penetrates the passivation layer to the upper surface of the barrier layer. A periodic gate pillar pattern is defined in the gate trench by electron beam lithography, and at least two alternating stacked barrier layers and channel layers are etched at intervals along the gate width direction, and a portion of the buffer layer is etched to form a periodically arranged groove. The gate metal is evaporated and deposited within the groove, and then peeled off to form multiple discrete gate pillars; Gate metal is evaporated and deposited on multiple discrete gate pillars to form a gate cap, which is supported by multiple discrete gate pillars and has no contact with the passivation layer and barrier layer. Photolithography is used to deposit interconnect metal layers to bring out electrodes.

[0007] Compared to existing technologies, the low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation provided by this invention includes a substrate, a buffer layer, and a multilayer heterostructure arranged sequentially from bottom to top. The multilayer heterostructure includes at least two alternatingly stacked barrier layers and channel layers; a source electrode is formed in one edge region of the barrier layer, and the source electrode sequentially penetrates at least two alternatingly stacked barrier layers and channel layers into the buffer layer; a drain electrode is formed in the other edge region of the barrier layer, and the drain electrode sequentially penetrates at least two alternatingly stacked barrier layers and channel layers into the buffer layer; a passivation layer is formed in... The barrier layer is formed on the upper surface and contacts the inner walls of the source and drain electrodes; the gate trench is formed in the middle region of the passivation layer and penetrates the passivation layer to the upper surface of the barrier layer; the gate electrode includes multiple discrete gate pillars and a gate cap, the multiple discrete gate pillars are periodically arranged along the gate width direction, the multiple discrete gate pillars are located in the gate trench and penetrate through at least two alternately stacked barrier layers and channel layers to the buffer layer, and the gate cap is located on the upper surface of the multiple discrete gate pillars and is supported by the multiple discrete gate pillars and has no contact with the passivation layer and barrier layer; the metal interconnect layer is electrically connected to the source and drain electrodes. In this way, the depletion region is directly modulated through the sidewalls of multiple discrete gate pillars extending into the buffer layer, enhancing gate control capability and achieving a lower subthreshold swing. Simultaneously, the periodic arrangement of multiple discrete gate pillars along the gate width allows multiple channels to open synchronously, flattening the transconductance curve and significantly improving linearity. The electric field concentration effect generated by the nanochannel structure (i.e., the narrow conductive region between adjacent discrete gate pillars) formed by the periodically arranged discrete gate pillars accelerates carrier saturation, significantly reducing the knee voltage and achieving low-power operation. Therefore, the device of this invention can achieve both low subthreshold swing and meet the application requirements of low power consumption and high linearity. Attached Figure Description

[0008] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1A schematic diagram of a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation is shown. Figure 2 A schematic diagram of a junction field-effect transistor is shown. Figure 3 A schematic diagram illustrating the transition principle of a junction field-effect transistor in a HEMT device is shown. Figure 4 A schematic diagram illustrating the distribution of discrete gate pillars and nanochannels along the gate width direction is shown. Figure 5 The diagram schematically illustrates the depletion region and electron distribution within a longitudinal section in a single cycle along the gate width direction as the bias voltage increases; Figure 6 A schematic diagram illustrating the comparison of subthreshold characteristics of two different gate-type three-channel devices is shown. Figure 7 A schematic diagram illustrating the comparison of capacitance-voltage curves for two different gate-type three-channel devices is shown. Figure 8 A schematic diagram illustrating the comparison of transconductance curves for two different gate-type three-channel devices is shown. Figure 9 A schematic diagram illustrating the comparison of output characteristics of two different gate-type three-channel devices under the same gate voltage is shown. Figure 10 This schematically illustrates the electric field distribution in a top-view cross-section (without passivation) under different grid pillar patterns. Figure 1 ; Figure 11 This schematically illustrates the electric field distribution in a top-view cross-section (without passivation) under different grid pillar patterns. Figure 2 ; Figure 12 This schematically illustrates the electric field distribution in a top-view cross-section (without passivation) under different grid pillar patterns. Figure 3 ; Figure 13 A flowchart illustrating the fabrication method of a low-voltage, high-linearity heterojunction HEMT device based on junction field effect modulation is shown. Figure 14 The diagram schematically illustrates the growth of the buffer layer and the multilayer heterojunction, as well as the process flow diagram for forming the source and drain electrodes. Figure 15 The schematic diagram illustrates the process flow for depositing the passivation layer and forming the gate trench; Figure 16 A schematic diagram illustrates the process flow for forming periodically arranged grooves and multiple discrete grid posts; Figure 17 The diagram schematically illustrates the process flow for forming the grid cap mask and the grid cap itself. Figure 18 The schematic diagram illustrates the process flow for washing away the photoresist and depositing the interconnect metal layer.

[0009] Explanation of reference numerals in the attached figures 1. Substrate; 2. Buffer layer; 3. Multilayer heterostructure; 31. Barrier layer; 32. Channel layer; 4. Source electrode; 5. Drain electrode; 6. Passivation layer; 7. Gate trench; 8. Gate electrode; 81. Multiple discrete gate pillars; 82. Gate cap; 9. Metal interconnect layer. Detailed Implementation

[0010] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0011] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by one of ordinary skill in the art.

[0012] The methods described in the embodiments of the present invention will be explained in detail below.

[0013] Figure 1 The schematic diagram shows the structure of a low-voltage high-linearity heterojunction HEMT device based on junction field effect modulation. The low-voltage high-linearity heterojunction HEMT device based on junction field effect modulation includes a substrate 1, a buffer layer 2 and a multilayer heterostructure 3 arranged sequentially from bottom to top. The multilayer heterostructure 3 includes at least two alternately stacked barrier layers 31 and channel layers 32. The source electrode 4 is formed in the edge region of one side of the barrier layer 31. The source electrode 4 passes through at least two alternately stacked barrier layers 31 and channel layers 32 into the buffer layer 2. The drain electrode 5 is formed in the edge region on the other side of the barrier layer 31. The drain electrode 5 passes through at least two alternately stacked barrier layers 31 and channel layers 32 into the buffer layer 2. A passivation layer 6 is formed on the upper surface of the barrier layer 31 and is in contact with the inner walls of the source electrode 4 and the drain electrode 5. The gate trench 7 is formed in the middle region of the passivation layer 6 and extends through the passivation layer 6 to the upper surface of the barrier layer 31. The gate electrode 8 includes a plurality of discrete gate pillars 81 and a gate cap 82. The plurality of discrete gate pillars 81 are arranged periodically along the gate width direction. The plurality of discrete gate pillars 81 are located in the gate trench 7 and extend through at least two alternately stacked barrier layers 31 and channel layers 32 into the buffer layer 2. The gate cap 82 is located on the upper surface of the plurality of discrete gate pillars 81 and is supported by the plurality of discrete gate pillars 81, and has no contact with the passivation layer 6 and the barrier layer 31. The metal interconnect layer 9 is electrically connected to the source electrode 4 and the drain electrode 5.

[0014] Specifically, a buffer layer 2, a multilayer heterostructure 3, and a passivation layer 6 are sequentially formed on the substrate 1. The heterostructure consists of alternating channel layers 32 and barrier layers 31. The total number of heterojunctions in the multilayer heterostructure 3 is not less than two. Metal interconnect layers 9 are disposed on the source electrode 4 and drain electrode 5. The passivation layer 6 covers the barrier layer 31 except for the gate trench 7. Arrayed gate pillars are provided along the gate width direction, penetrating the barrier layer 31 and extending into the buffer layer 2. The metal interconnect layer 9 is used for leads.

[0015] As an optional embodiment of the present invention, the plurality of discrete grid posts 81 are rectangular, circular or triangular in shape.

[0016] As an optional embodiment of the present invention, the width of each discrete gate post is 50nm-500nm.

[0017] Specifically, along the gate width direction, the width of each discrete gate post is 50nm-500nm, and the spacing between multiple discrete gate posts 81 is similar to the width.

[0018] As an optional embodiment of the present invention, the plurality of discrete gate pillars 81 extend into the buffer layer 2 to a depth of 20nm-50nm.

[0019] As an optional embodiment of the present invention, a gate cap 82 is a suspended structure, and there are gaps between the lower surface of the gate cap 82 and the upper surface of the passivation layer 6 and the upper surface of the barrier layer 31, and the gate cap 82 is supported by the upper surfaces of a plurality of discrete gate pillars 81.

[0020] As an optional embodiment of the present invention, the thickness of the passivation layer 6 is 20nm-120nm, and the material of the passivation layer 6 is one or more of SiN, SiO2 and Al2O3.

[0021] For example, the thickness of passivation layer 6 is 20 nm, 60 nm or 120 nm.

[0022] As an optional embodiment of the present invention, the material of the barrier layer 31 is one or more of AlGaN, AlN, InAlN, ScAlN, InAlGaN and N-face GaN.

[0023] As an optional embodiment of the present invention, both the source electrode 4 and the drain electrode 5 are ohmic contact metals, and the ohmic contact metals include a Ti / Al / Ni / Au metal stack.

[0024] As an optional embodiment of the present invention, the substrate 1 is made of one or more of sapphire, SiC and Si, and the buffer layer 2 is made of GaN.

[0025] Multiple discrete gate pillars 81 are evenly arranged along the gate width direction. The gate electrode 8 is disposed on the passivation layer 6 near the source electrode 4. This increases the gate-drain spacing, thereby improving the device breakdown voltage.

[0026] Specifically, Figure 2 A schematic diagram of a junction field-effect transistor is shown below. Figure 2 As shown, this invention combines the working principle of a junction field-effect transistor, such as... Figure 2 The n-channel JFET device shown has an applied voltage V. GS and V DS Both can change the thickness of the pn junction depletion layer, thereby changing the length and width of the channel. The gates on both sides control the depletion region along the direction perpendicular to the channel. The source-drain electrode difference makes the depletion layer trapezoidal along the channel direction. For an n-channel JFET device, its pinch-off voltage V P Less than 0, when V GS =0V, the channel is fully open, and the conductivity is at its maximum. When V P <V GS At <0V, the channel width varies with gate voltage. As the drain voltage increases, the depletion region near the drain becomes wider, and the channel becomes narrower. DS When a certain threshold is reached, the channel near the drain is almost pinched off, and the current is in constant saturation. GS ≤V P The depletion regions on both sides are connected, and the channel is interrupted. Utilizing the operating principle of the depletion-type JFET device described above, the discontinuous gate pins divide the device into several nanochannels similar to those of a junction field-effect transistor. Figure 3 The schematic diagram illustrates the transition principle of a junction field-effect transistor in a HEMT device. Figure 4 A schematic diagram illustrating the distribution of discrete gate pillars and nanochannels along the gate width direction is shown below. Figure 3 and Figure 4 As shown, the core of this structure lies in relying on the gate foot sidewalls to create a depletion region in the channel. An external bias voltage controls the thickness and extension direction of the depletion layer. As the gate voltage gradually increases, the depletion region formed by the sidewalls gradually widens, and the number of charge carriers per unit cross-section of the channel gradually decreases. The specific process is as follows: Figure 5 As shown, Figure 5The diagram schematically illustrates the depletion region and electron distribution within a longitudinal section in a single cycle along the gate width as the bias voltage increases, until the channel is almost pinched off when the drain voltage reaches a certain value, and the current is in a constant state.

[0027] Devices are pinched off by the depletion region generated by the side gates on both sides of the channel, such as Figure 1 As shown in the longitudinal cross-sectional view along the gate width direction of the device, there is no passivation layer 6 above the channel. Since the lateral spacing of a single sub-channel is much larger than the longitudinal thickness of the channel, and the growth rates of the sidewalls and the top depletion layer are similar, the passivation layer 6 above the channel is etched away to prevent the channel from being pinched off too quickly. Compared with planar devices, the device structure proposed in this invention abandons the control capability of the top gate cap 82 over the channel, and instead uses the side gate that extends into the buffer layer 2 to indirectly regulate the channel carriers. This structure has stronger gate control capability and fundamentally avoids the negative impact of the short-channel effect. Figure 6 As shown, Figure 6 The diagram schematically illustrates a comparison of the subthreshold characteristics of two different gate-type three-channel devices. Figure 6 The horizontal axis represents the gate voltage, and the vertical axis represents the drain current in logarithmic coordinates. It has better subthreshold characteristics of junction-type gate devices, so as to achieve good control of multiple heterojunctions with short gate length.

[0028] Because the channel pinch-off process of a device is gradual, taking a three-channel HEMT device as an example, such as Figure 7 As shown, Figure 7 A schematic diagram illustrating the comparison of capacitance-voltage curves for two different gate-type three-channel devices is shown. Figure 7 The horizontal axis represents the gate voltage, and the vertical axis represents the capacitance. Compared to conventional devices, heterojunction devices with arrayed buried gates exhibit a smoother step when the capacitance depletes during turn-on, reducing the impact of electrical stress on reliability and extending device lifespan. Furthermore, ordinary multi-channel devices suffer from significant transconductance curve fluctuations due to variations in channel turn-on sequence, resulting in multiple peaks. In contrast, heterojunction devices with arrayed buried gates provide more uniform channel control through discrete gate pillars, allowing multiple channels to turn on synchronously. Figure 8 As shown, Figure 8 A schematic diagram illustrating the comparison of transconductance curves for two different gate-type three-channel devices is shown. Figure 8 The horizontal axis represents the gate voltage, and the vertical axis represents the transconductance. Compared with conventional heterojunction devices, the transconductance curve of heterojunction devices with buried gates is flatter, which can significantly improve linearity and reduce signal distortion.

[0029] By embedding discrete gate pillars deep within buffer layer 2, the channel is divided into several independently distributed nano-conductive channels along the gate width direction. The total width of these conductive channels is smaller than the width of the source and drain terminals of the device, making the electric field lines within the channels more concentrated. Under the same bias voltage, the transverse electric field within the channels is significantly increased. This electric field concentration effect directly leads to a significant acceleration of the carrier saturation process, specifically as follows: Figure 9 As shown, Figure 9 This diagram schematically illustrates a comparison of the output characteristics of two different gate-type three-channel devices under the same gate voltage. Figure 9 The horizontal axis represents the drain voltage, and the vertical axis represents the drain current. Compared with traditional structures, heterojunction devices with arrayed buried gates can achieve channel current saturation at lower drain bias, thereby directly reducing the knee voltage. Furthermore, according to the formula... and It can be seen that both the output power and power-added efficiency of the device increase as the knee voltage decreases. Specifically, For output power, Maximum drain current, Breakdown voltage Knee voltage, Add efficiency to power. For input power, This represents DC power consumption.

[0030] Based on the above theory, different masks can be prepared by electron beam lithography to etch grooves with different cross-sectional shapes, as shown in the specific structure. Figures 10 to 12 As shown, devices are designed to meet different performance requirements. Figure 10 This schematically illustrates the electric field distribution in a top-view cross-section (without passivation) under different grid pillar patterns. Figure 1 The above technical solutions Figure 10 The conventional rectangular grid posts shown are mainly used in low-voltage applications; Figure 11 This schematically illustrates the electric field distribution in a top-view cross-section (without passivation) under different grid pillar patterns. Figure 2 ,like Figure 11 The circular grid pillars shown increase the number of electric field lines concentrated in a single channel, increase the electric field strength near the channel, and avoid uneven junction temperature at the sharp edge of the pattern. This allows for lower voltage while mitigating efficiency degradation caused by self-heating. Figure 12 This schematically illustrates the electric field distribution in a top-view cross-section (without passivation) under different grid pillar patterns. Figure 3 ,like Figure 12 The triangular grid pillar shown can be adjusted by changing the orientation of its apex, thereby altering the location of the electric field lines and controlling the position of the electric field peaks to prevent premature breakdown.

[0031] Based on the above Figure 1As can be seen from the implementation, the low-voltage high-linearity heterojunction HEMT device based on junction field effect modulation in this embodiment of the invention includes a substrate 1, a buffer layer 2, and a multilayer heterostructure 3 arranged sequentially from bottom to top. The multilayer heterostructure 3 includes at least two alternately stacked barrier layers 31 and channel layers 32; a source electrode 4 is formed in one edge region of the barrier layer 31, and the source electrode 4 sequentially penetrates at least two alternately stacked barrier layers 31 and channel layers 32 into the buffer layer 2; a drain electrode 5 is formed in the other edge region of the barrier layer 31, and the drain electrode 5 sequentially penetrates at least two alternately stacked barrier layers 31 and channel layers 32 into the buffer layer 2; and a passivation layer 6 is formed on the barrier layer 31. The upper surface of layer 31 is in contact with the inner walls of source electrode 4 and drain electrode 5; gate trench 7 is formed in the middle region of passivation layer 6, and the gate trench 7 penetrates the passivation layer 6 to the upper surface of barrier layer 31; gate electrode 8 includes a plurality of discrete gate pillars 81 and a gate cap 82, the plurality of discrete gate pillars 81 are periodically arranged along the gate width direction, the plurality of discrete gate pillars 81 are located in gate trench 7, and penetrate through at least two alternately stacked barrier layers 31 and channel layers 32 to extend into buffer layer 2, a gate cap 82 is located on the upper surface of the plurality of discrete gate pillars 81, and is supported by the plurality of discrete gate pillars 81, and has no contact with passivation layer 6 and barrier layer 31; metal interconnect layer 9 is electrically connected to source electrode 4 and drain electrode 5. In this way, the depletion region is directly generated by the sidewalls of multiple discrete gate pillars 81 extending into the buffer layer 2, enhancing the gate control capability and thus achieving a lower subthreshold swing. Simultaneously, the periodic arrangement of multiple discrete gate pillars 81 along the gate width direction allows multiple channels to open synchronously, flattening the transconductance curve and significantly improving linearity. The electric field concentration effect generated by the nanochannel structure (i.e., the narrow conductive region between adjacent discrete gate pillars) formed by the periodically arranged discrete gate pillars 81 accelerates carrier saturation, significantly reducing the knee voltage and achieving low-power operation. Therefore, the device of this invention can achieve a low subthreshold swing while simultaneously meeting the application requirements of low power consumption and high linearity.

[0032] Figure 13 The illustration schematically depicts a method for fabricating a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to an embodiment of the present invention. See [link to documentation]. Figure 2 As shown, the fabrication method of this low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation may include: S1301, A buffer layer 2 and a multilayer heterostructure 3 are epitaxially grown sequentially on a substrate 1.

[0033] The multilayer heterostructure 3 includes at least two alternating barrier layers 31 and channel layers 32.

[0034] Specifically, Figure 14 The schematic diagram illustrates the growth of the buffer layer 2 and the multilayer heterojunction, as well as the process flow diagram for forming the source electrode 4 and the drain electrode 5. (See attached diagram.) Figure 14 As shown, a buffer layer 2 and a multilayer heterojunction are sequentially grown on a substrate 1. The substrate 1 is made of sapphire, SiC or Si, the buffer layer 2 is GaN, and any barrier layer 31 in the multilayer heterojunction is made of AlGaN or InAlN, AlN or other materials.

[0035] S1302. Source metal and drain metal are photolithographically etched and deposited on the two edge regions of the barrier layer 31, and then annealed to form source electrode 4 and drain electrode 5.

[0036] In this process, the source electrode 4 and the drain electrode 5 both penetrate at least two alternately stacked barrier layers 31 and channel layers 32 into the buffer layer 2.

[0037] Specifically, Figure 14 The schematic diagram illustrates the growth of the buffer layer 2 and the multilayer heterojunction, as well as the process flow diagram for forming the source electrode 4 and the drain electrode 5. (See attached diagram.) Figure 14 As shown, source and drain patterns are photolithographically etched on barrier layer 31 and source and drain metals are deposited, followed by thermal annealing. The source and drain metals used are Ti / Al / Ni / Au in sequence.

[0038] S1303, A passivation layer 6 is deposited on the upper surface of the barrier layer 31.

[0039] The passivation layer 6 is in contact with the inner walls of the source electrode 4 and the drain electrode 5.

[0040] Specifically, Figure 15 The schematic diagram illustrates the process flow for depositing the passivation layer 6 and forming the gate trench 7. See [link / reference]. Figure 15 As shown, a passivation layer 6 is deposited. The passivation layer 6 can be one or more of SiN, SiO2 and Al2O3, and the growth method is physical vapor deposition, chemical vapor deposition or atomic layer deposition, etc.

[0041] S1304. Photolithography is performed to etch the passivation layer 6 in the middle region to form a gate trench 7, which penetrates the passivation layer 6 to the upper surface of the barrier layer 31.

[0042] Specifically, Figure 15 The schematic diagram illustrates the process flow for depositing the passivation layer 6 and forming the gate trench 7. See [link / reference]. Figure 15 As shown, a mask for the gate trench 7 is fabricated, and the gate trench 7 is formed by etching the passivation layer 6 in the middle region.

[0043] S1305. A periodic gate pillar pattern is defined in the gate trench 7 by electron beam lithography, and at least two alternately stacked barrier layers 31 and channel layers 32 are etched at intervals along the gate width direction, and a portion of the buffer layer 2 is etched to form a periodically arranged trench.

[0044] Specifically, Figure 16A schematic diagram illustrating the process of forming periodically arranged grooves and multiple discrete grid posts 81 is shown. See [link to diagram]. Figure 16 As shown, a gate foot mask is fabricated at the gate groove 7, and then the entire barrier layer 31 and a buffer layer 2 of a certain thickness are etched to form a periodically arranged groove of a specific shape. The groove can be a columnar groove.

[0045] S1306. Evaporate and deposit gate metal in the groove, and peel it off to form multiple discrete gate pillars 81.

[0046] Specifically, Figure 16 A schematic diagram illustrating the process of forming periodically arranged grooves and multiple discrete grid posts 81 is shown. See [link to diagram]. Figure 16 As shown, a gate pin mask is fabricated by electron beam lithography, and gate metal is deposited by evaporation in the groove. Multiple discrete gate pillars 81 are then peeled off.

[0047] S1307. Evaporate and deposit gate metal on multiple discrete gate pillars 81 to form gate cap 82. Gate cap 82 is supported by multiple discrete gate pillars 81 and has no contact with passivation layer 6 and barrier layer 31.

[0048] Specifically, Figure 17 The schematic diagram illustrates the process flow for forming the mask for gate cap 82 and the process for forming gate cap 82. See [link to relevant documentation]. Figure 17 As shown, a mask for the gate cap 82 is fabricated by electron beam lithography to stabilize the gate pillars and elevate the gate cap 82; gate metal is evaporated and deposited on multiple discrete gate pillars 81 to form the gate cap 82.

[0049] S1308, photolithography and deposition of interconnect metal layers to bring out electrodes.

[0050] Specifically, Figure 18 The schematic diagram illustrates the process flow for washing away the photoresist and depositing the interconnect metal layer. See [link to relevant documentation]. Figure 18 As shown, the photoresist of the shaped gate pins is washed away to obtain a complete buried gate without passivation layer 6 support. The metal interconnect layer 9 is then fabricated. The interconnect layer is photolithographically lithographically formed and interconnect metals are deposited using a stepper. The interconnect metals used are Ti / Au in sequence.

[0051] The following will provide three specific embodiments of the fabrication method of the low-voltage high-linearity heterojunction HEMT device based on junction field effect modulation of the present invention.

[0052] Example 1: The discrete gate pin cross-section, i.e., the shape of multiple discrete gate pillars 81, adopts a rectangular shape. Taking a three-channel AlGaN / GaN heterojunction HEMT device as an example, the specific process steps are as follows: Step 1: Grow a multilayer heterostructure on an epitaxial substrate.

[0053] 1a) A silicon carbide epitaxial substrate was selected, and a 2μm thick GaN layer was grown on the surface of the epitaxial substrate as a buffer layer 2 using the metal-organic chemical vapor deposition (MOCVD) process. 1b) Using MOCVD, a 40 nm thick undoped GaN layer and a 22 nm thick AlGaN barrier layer 31 are sequentially epitaxially grown on the surface of the GaN buffer layer 2, wherein the Al composition is 20%; 1c) Repeat step 1b) twice to obtain a multilayer heterostructure with three channels 3.

[0054] Step 2: Preparation of source-drain ohmic contacts.

[0055] 2a) Spin-coat photoresist onto the sample surface, and define the patterned areas of source electrode 4 and drain electrode 5 by photolithography: 2b) An electron beam evaporation system is used, with a vacuum level better than 2×10⁻⁶. -6 Under Torr conditions, Ti / Al / Ni / Au metal stacks are deposited sequentially; 2c) Perform a stripping process to remove the metal outside the pattern, followed by rapid thermal annealing in an N2 atmosphere (830°C, 30 seconds) to promote the formation of a low-resistance ohmic contact between the metal and the semiconductor.

[0056] Step 3: Create countertop partitions.

[0057] 3a) Define the active region using photolithography; 3b) The Inductively Coupled Plasma (ICP) dry etching technique is used to sequentially etch the AlGaN barrier layer 31 and GaN buffer layer 2 in the electrically isolated region to achieve mesa isolation of the active region. The total etching depth is 100 nm.

[0058] Step 4: SiN passivation layer deposition.

[0059] Using plasma-enhanced chemical vapor deposition (PECVD) technology, a SiN thin film with a thickness of about 60 nm was grown on the entire device surface at 250 °C with SiH4 and NH3 as the reaction gas source, as a surface SiN passivation layer.

[0060] Step 5: Deeply etch the opening of the gate groove 7 and the nano-groove array.

[0061] 5a) Openings in the gate area; A gate pattern is photolithographically etched on the SiN passivation layer. Then, CF4 / O2 plasma is used to selectively etch the SiN passivation layer in the exposed area until the surface of the underlying AlGaN barrier layer 31 is exposed, forming the gate trench 7.

[0062] 5b) Deep trench array etching; Within the gate trench 7, a periodic gate trench 7 pattern is defined using electron beam lithography. Deep etching is then performed using ICP with an etching formula specific to nitrides to completely etch through all AlGaN barrier layers 31 and GaN channel layers within the gate trench 7. Subsequently, the underlying GaN buffer layer 2 is etched, with the etching depth of the buffer layer 2 controlled at 20-50 nm, ultimately forming a periodically arranged rectangular trench array that penetrates the heterojunction and is deeply embedded within the buffer layer 2.

[0063] Step 6: Gate fabrication.

[0064] 6a) Metal vapor deposition of grid pillars; Within the gate trench 7, a periodic gate pillar pattern is defined using electron beam lithography. Through evaporation and stripping processes, Ni / Au / Ni multilayer metal is filled into the trench array to form multiple discrete metal gate pillars, i.e., multiple discrete gate pillars 81, that conform to the shape of the trench.

[0065] 6b) Metal deposition forms an unsupported gate cap 82; A second photolithography process is performed to evaporate a thicker layer of gate metal on top of the multiple discrete gate pillars 81, forming a suspended gate cap 82 connecting the discrete gate pillars. This structure ensures that the gate electrode 8 is coupled to the channel only through the gate pillars, avoiding interference from the top SiN passivation layer. Finally, the gate metal is annealed at 860°C for 60 seconds to complete the gate fabrication.

[0066] Step 7, metal interconnection.

[0067] 7a) Photolithography and etching of the SiN passivation layer to remove the 60nm thick SiN passivation layer in the interconnect opening area; 7b) Evaporate interconnect metal on the electrodes and SiN passivation layer in the metal interconnect region and on the photoresist outside the metal interconnect region to form metal interconnect layer 9. Metal interconnect layer 9 is a metal stack structure consisting of two layers, Ti and Au, arranged from bottom to top, to bring out electrodes and complete device fabrication.

[0068] Example 2: Based on Example 1, Example 2 replaces the rectangular pattern with a circular pattern when defining the gate pillar pattern using electron beam lithography. That is, the multiple discrete gate pillars 81 are circular in shape. For details, please refer to [link to example]. Figure 11 , Figure 11This is a top cross-sectional view (without passivation) of another low-voltage, high-linearity HEMT device based on junction field-effect modulation technology provided in this embodiment of the invention. The HEMT device includes a substrate 1, a buffer layer 2, a source electrode 4, a drain electrode 5, a multilayer heterostructure 3, a passivation layer 6, a gate electrode 8, and a metal interconnect layer 9.

[0069] Specifically, the substrate 1, buffer layer 2, source electrode 4, drain electrode 5, multilayer heterostructure 3, passivation layer 6, gate electrode 8, and metal interconnect layer 9 in the device structure are consistent with those described in Embodiment 1, and will not be repeated in this Embodiment 2.

[0070] In this second embodiment, the top view of a single gate slot 7 is circular, which increases the number of electric field lines gathered in the nanochannel, increases the electric field strength near the channel, and avoids uneven junction temperature at the sharp edge of the pattern. This can achieve low pressure while slowing down the efficiency degradation caused by self-heating effect.

[0071] Example 3: Based on Example 1, Example 3 replaces the rectangular pattern with an isosceles triangular pattern when defining the gate pillar pattern using electron beam lithography. That is, the multiple discrete gate pillars 81 are shaped like isosceles triangles. Please refer to [link to example]. Figure 12 , Figure 12 This is a top cross-sectional view (without passivation) of another low-voltage, high-linearity HEMT device based on junction field-effect modulation technology provided in this embodiment of the invention. The HEMT device includes a substrate 1, a buffer layer 2, a source electrode 4, a drain electrode 5, a multilayer heterostructure 3, a passivation layer 6, a gate electrode 8, and a metal interconnect layer 9.

[0072] Specifically, the substrate 1, buffer layer 2, source electrode 4, drain electrode 5, multilayer heterostructure 3, passivation layer 6, gate electrode 8, metal interconnect layer 9, etc. in the device structure are consistent with the description in Embodiment 1, and will not be repeated in this Embodiment 3.

[0073] In this third embodiment, a triangular prism-shaped groove array is formed after deep etching. The sharp apex of the triangle can guide and concentrate the electric field lines. By designing the apex to face the drain or source, the position of the peak electric field in the channel can be actively controlled, achieving low voltage while controlling the electric field peak to avoid premature breakdown.

[0074] The nanochannel structure (i.e., the narrow conductive region between multiple discrete gate pillars 81) proposed in this invention, based on the junction field-effect principle, differs from traditional multilayer heterojunction high electron mobility transistors. This structure completely abandons the control of channel carriers by the top gate cap 82, instead directly controlling the channel using the sidewalls of the discrete gate feet deep within the buffer layer 2. This design significantly suppresses the subthreshold characteristic degradation caused by the short-channel effect, achieving efficient control of multiple channels in the thicker barrier layer 31 through the short gate structure. Based on the junction field-effect modulation principle, the capacitance change is gradual when the device is turned on, reducing electrical stress. The discrete gate pillars facilitate the synchronous turn-on of multiple channels, flattening the transconductance curve, significantly improving the linearity of the device, and reducing signal distortion.

[0075] One of the most significant benefits of this invention is the fundamental reduction in the operating voltage requirement of the device. The electric field concentration and carrier saturation acceleration effect achieved through the nanochannel structure significantly lowers the knee voltage compared to conventional multichannel HEMTs and Fin-like structures that only optimize linearity. This translates to: lower quiescent power consumption, requiring a lower drain bias voltage to achieve the same output current, resulting in reduced DC power consumption; higher power-added efficiency; and lower knee voltage. It can effectively improve power-added efficiency and reduce the operating power consumption of devices, thereby overcoming the key bottleneck of multi-channel HEMT in low-power, high-efficiency RF applications. It enables devices to be more compatible with low-supply-voltage RF front-end modules and mobile terminals, providing a key device-level solution for the next generation of high-efficiency and energy-saving communication and electronic systems.

[0076] This invention is not limited to conventional rectangular gate pillars; it can also use circular gate pillars to achieve ultra-low voltage operation, or use triangular gate pillars to improve breakdown characteristics by adjusting the position of electric field peaks. This allows for targeted optimization of electric field distribution, thermal management, or breakdown characteristics, enabling flexible design and customization of device performance and providing broad compatibility.

[0077] It should be noted that the description of the above embodiments of the fabrication method for low-voltage, high-linearity heterojunction HEMT devices based on junction field-effect modulation is similar to the description of the above embodiments of low-voltage, high-linearity heterojunction HEMT devices based on junction field-effect modulation, and has similar beneficial effects. For technical details not disclosed in the embodiments of the fabrication method for low-voltage, high-linearity heterojunction HEMT devices based on junction field-effect modulation of the present invention, please refer to the description of the embodiments of low-voltage, high-linearity heterojunction HEMT devices based on junction field-effect modulation of the present invention for understanding.

[0078] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation, characterized in that, It includes a substrate, a buffer layer and a multilayer heterostructure arranged sequentially from bottom to top, wherein the multilayer heterostructure includes at least two alternately stacked barrier layers and channel layers; A source electrode is formed in one edge region of the barrier layer, and the source electrode sequentially penetrates the at least two alternately stacked barrier layers and channel layers into the buffer layer; A drain electrode is formed in the edge region on the other side of the barrier layer, and the drain electrode sequentially penetrates the at least two alternately stacked barrier layers and channel layers into the buffer layer; A passivation layer is formed on the upper surface of the barrier layer and contacts the inner walls of the source electrode and the drain electrode; A gate trench is formed in the middle region of the passivation layer, and the gate trench extends through the passivation layer to the upper surface of the barrier layer; The gate electrode includes a plurality of discrete gate pillars and a gate cap. The plurality of discrete gate pillars are arranged periodically along the gate width direction. The plurality of discrete gate pillars are located in the gate trench and extend through the at least two alternately stacked barrier layers and channel layers into the buffer layer. The gate cap is located on the upper surface of the plurality of discrete gate pillars and is supported by the plurality of discrete gate pillars, and has no contact with the passivation layer and the barrier layer. A metal interconnect layer is electrically connected to the source electrode and the drain electrode.

2. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The shape of the plurality of discrete grid posts is rectangular, circular or triangular.

3. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The width of each discrete gate post is 50nm-500nm.

4. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The plurality of discrete gate pillars extend into the buffer layer to a depth of 20nm-50nm.

5. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The gate cap is a suspended structure, with gaps between the lower surface of the gate cap and the upper surface of the passivation layer and the upper surface of the barrier layer, and the gate cap is supported by the upper surfaces of the plurality of discrete gate pillars.

6. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The passivation layer has a thickness of 20nm-120nm, and the material of the passivation layer is one or more of SiN, SiO2 and Al2O3.

7. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The barrier layer is made of one or more of AlGaN, AlN, InAlN, ScAlN, InAlGaN, and N-plane GaN.

8. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, Both the source electrode and the drain electrode are ohmic contact metals, and the ohmic contact metals include a Ti / Al / Ni / Au metal stack.

9. The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation according to claim 1, characterized in that, The substrate is made of one or more of sapphire, SiC, and Si, and the buffer layer is made of GaN.

10. A method for fabricating a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation, characterized in that, The low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation as described in any one of claims 1-9 comprises: A buffer layer and a multilayer heterostructure are epitaxially grown sequentially on a substrate. The multilayer heterostructure includes at least two alternating barrier layers and channel layers. Source metal and drain metal are photolithographically etched and deposited on the two edge regions of the barrier layer, respectively, and then annealed to form source electrode and drain electrode. The source electrode and the drain electrode pass through the at least two alternately stacked barrier layers and channel layers into the buffer layer. A passivation layer is deposited on the upper surface of the barrier layer, and the passivation layer is in contact with the inner walls of the source electrode and the drain electrode; Photolithography is used to etch the passivation layer in the middle region to form a gate trench that extends through the passivation layer to the upper surface of the barrier layer. A periodic gate pillar pattern is defined in the gate trench by electron beam lithography, and at least two alternately stacked barrier layers and channel layers are etched at intervals along the gate width direction, and a portion of the buffer layer is etched to form a periodically arranged groove. The gate metal is evaporated and deposited within the groove, and then peeled off to form multiple discrete gate pillars; The gate metal is evaporated and deposited on the plurality of discrete gate pillars to form a gate cap, the gate cap being supported by the plurality of discrete gate pillars and having no contact with the passivation layer and the barrier layer; Photolithography is used to deposit interconnect metal layers to bring out electrodes.

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