LDMOS device and method of manufacturing the same

Abstract

This invention provides an LDMOS device and its manufacturing method. The device includes a substrate, a drift region, a body region, an isolation structure, a main gate, multiple discrete floating auxiliary gates, and a barrier dielectric layer covering the auxiliary gates. A metal interconnect structure extends to the surface of the barrier dielectric layer, using the barrier dielectric layer as a coupling medium to modulate the potential of the auxiliary gates. The manufacturing method includes providing a substrate and forming an active region and an isolation structure, forming the main and auxiliary gates, forming a re-injection region, and forming the barrier dielectric layer, an interlayer dielectric layer, contact vias, and interconnect structures. This invention utilizes the coupling of the auxiliary bias potential of the barrier dielectric layer to the auxiliary gates to dynamically balance the surface electric field of the drift region. Without increasing the thickness of the isolation structure, it effectively improves the breakdown voltage without sacrificing the on-resistance, significantly optimizing the application performance and reliability of high-voltage power devices.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to an LDMOS device and its manufacturing method. Background Technology

[0002] Double-diffused metal-oxide-semiconductor (DMOS) devices are widely used in power management circuits due to their high voltage tolerance, high current drive capability, and extremely low power consumption. In typical lateral double-diffused metal-oxide-semiconductor (LDMOS) devices, the breakdown voltage (BV) is usually optimized by setting isolation structures (such as field oxide layers or shallow trench isolation structures) on the surface of the drift region, and an attempt is made to balance the trade-off between the breakdown voltage and the on-resistance (Ron).

[0003] In existing shallow trench isolation (STI) LDMOS structures, the gate is typically partially extended and mounted on the STI. Increasing the STI thickness can effectively improve the device's breakdown voltage. However, increasing the thickness of the isolation structure compresses the current path in the underlying drift region, leading to a significant increase in the device's on-resistance.

[0004] For medium- and high-voltage LDMOS devices, achieving precise modulation of the surface electric field in the drift region and improving breakdown voltage performance without significantly increasing the thickness of the isolation structure is a major technical challenge in the field of power devices. Existing field plate or isolation designs still have limitations in further optimizing the trade-off between breakdown voltage and on-resistance. Summary of the Invention

[0005] To address the problem that increasing the breakdown voltage of existing LDMOS devices by increasing the thickness of the isolation structure leads to an increase in the on-resistance of the device, this invention provides a lateral double-diffused metal-oxide-semiconductor LDMOS device and its manufacturing method.

[0006] This invention provides a laterally double-diffused metal-oxide-semiconductor (LDMOS) device, comprising:

[0007] A semiconductor substrate having a drift region and a bulk region;

[0008] An isolation structure is located on the surface of the drift region;

[0009] The main gate is located above the channel region;

[0010] Multiple auxiliary gates are arranged at intervals above the isolation structure and are in an electrically floating state;

[0011] Source and drain regions, including the first doped implantation region;

[0012] A barrier dielectric layer covers the auxiliary gate;

[0013] Interlayer dielectric layer, covering the main gate, auxiliary gate and barrier dielectric layer;

[0014] Metal interconnect structure, penetrating the interlayer dielectric layer and extending to the surface of the barrier dielectric layer;

[0015] In this configuration, the metal interconnect structure is set to use a barrier dielectric layer as a coupling medium to modulate the potential of the auxiliary gate.

[0016] Preferably, the isolation structure is an ultra-shallow trench isolation structure or a stepped field oxide layer structure.

[0017] Preferably, the thickness of the isolation structure is 100 angstroms to 3000 angstroms.

[0018] Preferably, the main gate extends above a portion of the isolation structure, and the overlap width between the main gate and the isolation structure is less than 2 micrometers.

[0019] Preferably, it further includes a second doped implantation region disposed within the body region.

[0020] Preferably, the LDMOS device is an N-type LDMOS device or a P-type LDMOS device; when the LDMOS device is an N-type LDMOS device, the drift region is N-type, the body region is P-type, the first doped injection region is N-type, and the second doped injection region is P-type; when the LDMOS device is a P-type LDMOS device, the drift region is P-type, the body region is N-type, the first doped injection region is P-type, and the second doped injection region is N-type.

[0021] Preferably, the barrier dielectric layer is composed of a metal silicide reaction barrier material.

[0022] Preferably, an insulating dielectric etch stop layer is provided below the interlayer dielectric layer, the insulating dielectric etch stop layer including a bottom silicon oxide layer and a top silicon nitride layer.

[0023] Preferably, the metal interconnect structure includes a contact plug, a first metal layer, a through-hole, and a second metal layer.

[0024] Preferably, the auxiliary gate is electrically connected to the main gate, source region, or drain region through a metal interconnect structure.

[0025] The present invention also provides a method for manufacturing an LDMOS device, comprising the following steps:

[0026] Step 1: Provide a semiconductor substrate, form a drift region and a bulk region in the semiconductor substrate, and form an isolation structure on the surface of the drift region;

[0027] Step 2: Form a gate dielectric layer and a gate conductive material layer. Pattern the gate conductive material layer to form a main gate above the channel region and multiple auxiliary gates above the isolation structure. The auxiliary gates are in an electrically floating state.

[0028] Step 3: Form sidewall structures on the main gate and auxiliary gate sidewalls, and perform an implantation process on the semiconductor substrate to form the first doped implantation region of the source and drain regions;

[0029] Step 4: Form a barrier dielectric layer covering the surface of the auxiliary gate;

[0030] Step 5: Deposit an interlayer medium layer and form contact holes in the interlayer medium layer that expose the surface of the barrier medium layer;

[0031] Step 6: Form contact plugs in the contact holes and form a metal interconnect structure coupled to the auxiliary gate through the contact plugs.

[0032] Preferably, step three further includes forming a second heavily doped implantation region located within the body region.

[0033] Preferably, in step one, the thickness of the isolation structure is 100 angstroms to 3000 angstroms.

[0034] Preferably, in step two, the width of the main gate extending above the isolation structure is less than 2 micrometers.

[0035] Preferably, the LDMOS device is an N-type LDMOS device or a P-type LDMOS device; when the LDMOS device is an N-type LDMOS device, in step one, the drift region is N-type and the body region is P-type; in step three, the first doped injection region is N-type, and in certain embodiments, the second doped injection region is P-type; when the LDMOS device is a P-type LDMOS device, in step one, the drift region is P-type and the body region is N-type; in step three, the first doped injection region is P-type, and in certain embodiments, the second doped injection region is N-type.

[0036] Preferably, after step four and before step five, the process further includes: performing a metal silicide process to form a metal silicide on the exposed surface not covered by the barrier dielectric layer.

[0037] Preferably, in step five, before forming the interlayer dielectric layer, an insulating dielectric etch stop layer comprising a bottom silicon oxide layer and a top silicon nitride layer is formed by a deposition process.

[0038] Preferably, in step five, after forming the interlayer dielectric layer, planarization is performed using a chemical mechanical polishing process.

[0039] Preferably, in step six, the metal interconnect structure is coupled to the auxiliary gate through the barrier dielectric layer, and the modulation potential is electrically connected to the main gate, source region, or drain region.

[0040] As described above, the LDMOS device and its manufacturing method of the present invention have the following beneficial effects:

[0041] This invention employs multiple discrete and floating auxiliary gates above an ultra-shallow isolation structure. By utilizing the capacitive coupling effect formed between the metal interconnect structure and the auxiliary gates through a barrier dielectric layer for potential modulation, a smooth lateral potential gradient can be established on the drift region surface using the capacitive coupling mechanism without increasing the physical thickness of the isolation structure, effectively suppressing electric field peaks near the drain. Experimental and simulation results show that this invention can increase the device breakdown voltage from approximately 145V to approximately 167V while maintaining a linear leakage current fluctuation difference of less than 2%, significantly optimizing the trade-off between breakdown voltage and on-resistance. Furthermore, this invention utilizes the barrier dielectric layer in the metal silicide process as the coupling medium, achieving high compatibility with existing semiconductor logic process platforms and enabling low-cost secondary development of the device's breakdown voltage performance. Attached Figure Description

[0042] Figure 1 The diagram shows a process flow diagram of the LDMOS device manufacturing method of the present invention.

[0043] Figure 2 The diagram shows the process structure of the main gate and auxiliary gate after their formation according to the present invention.

[0044] Figure 3 The diagram shows the process structure after the formation of the sidewalls, source region, drain region and heavily doped implantation region of the present invention.

[0045] Figure 4 The diagram shown is a schematic representation of the process structure after the formation of the local barrier dielectric layer according to the present invention.

[0046] Figure 5 The diagram shows the process structure after the deposition and etching stop layer and the interlayer dielectric layer of the present invention.

[0047] Figure 6 The diagram shows the process structure after the contact hole is formed according to the present invention.

[0048] Figure 7 The diagram shows the process structure of the present invention after forming the contact plug and the first metal layer.

[0049] Figure 8 The diagram shows the process structure after the formation of the through-hole and the second metal layer according to the present invention.

[0050] Figure 9The diagram shown is a structural schematic of an embodiment of the present invention where the auxiliary gate is coupled to the source.

[0051] Figure 10 The diagram shows another embodiment of the present invention, in which the auxiliary gate is coupled to both the low-voltage electrode and the high-voltage electrode.

[0052] Figure 11 This is a schematic diagram of another embodiment of the present invention in which the auxiliary gate is short-circuited and coupled through a first metal layer;

[0053] Figure 12 The diagram shows a circuit layout and interconnection structure of an auxiliary gate coupled to a low-voltage node according to the present invention.

[0054] Figure 13 The graph shows a comparison of the breakdown voltage (BV) between the structure of this invention and the conventional structure.

[0055] Figure 14 The graph shows a simulation comparison of the linear leakage current (IdLin) between the structure of this invention and the conventional structure. Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] This application provides a laterally double-diffused metal-oxide-semiconductor (LDMOS) device, comprising:

[0058] The semiconductor substrate 101 has a drift region 106 and a body region 107.

[0059] The isolation structure 102 is located on the surface of the drift region 106.

[0060] The main gate 104 is located above the channel region. Multiple auxiliary gates 104-n are spaced apart above the isolation structure 102 and are electrically floating.

[0061] The source and drain regions include the first heavily doped implantation region 109.

[0062] A barrier dielectric layer 201 covers the auxiliary gate 104-n. An interlayer dielectric layer 114 covers the main gate 104, the auxiliary gate 104-n, and the barrier dielectric layer 201.

[0063] The metal interconnect structure extends through the interlayer dielectric layer 114 and to the surface of the barrier dielectric layer 201. The metal interconnect structure is configured to use the barrier dielectric layer 201 as a coupling medium to modulate the potential of the auxiliary gate 104-n electrode.

[0064] This device structure overcomes the limitation of traditional high-voltage devices that rely on increasing the thickness of the isolation structure to improve voltage withstand. By setting multiple controlled-potential auxiliary gates 104-n above the ultra-shallow isolation structure, and utilizing the capacitive coupling effect formed by the blocking dielectric layer 201, a continuous and smooth lateral potential gradient is established on the surface of the drift region. (Reference) Figure 13 As shown in the BV curve, compared to the traditional structure, the breakdown voltage of the device in this application (This work) is increased from approximately 145 volts to approximately 167 volts, and the breakdown voltage (BW) is increased by approximately 20 volts. (See also...) Figure 14 The drain linear current IdLin curve shown in the figure indicates that the linear leakage current of the structure in this application differs from that of the traditional structure by less than 2%, achieving an excellent trade-off between extremely low on-resistance and ultra-high breakdown voltage, and greatly expanding the safe operating area of ​​power integrated circuits.

[0065] In some embodiments, the semiconductor substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0066] In some embodiments, the isolation structure 102 is an ultra-shallow trench isolation structure or a stepped field oxide layer structure. In some embodiments, the thickness of the isolation structure 102 is 100 angstroms to 3000 angstroms. The isolation structure 102 comprises a dielectric material filled by high-density plasma chemical vapor deposition, subatmospheric pressure chemical vapor deposition, or high aspect ratio process (HARP), and the filling material is selected from low dielectric constant dielectrics such as silica, fluorosilicone glass (FSG), borosilicate glass (BPSG), or carbon-doped silicon oxide (SiOC). In some embodiments, a flowable chemical vapor deposition (FCVD) process can also be used to achieve seamless filling, and densification annealing is performed after filling to optimize dielectric quality.

[0067] In some embodiments, the main gate 104 extends above a portion of the isolation structure 102, and the overlap width between the main gate 104 and the isolation structure 102 is less than 2 micrometers. This narrow overlap design effectively reduces gate-drain capacitance while providing sufficient surface space between the main gate edge and the drain for arranging multiple auxiliary gates 104-n. Each auxiliary gate segment, acting as an independent potential modulation unit, can work in conjunction with the isolation structure 102 to precisely deplete the surface charge in the drift region, thereby improving device reliability without increasing current path impedance.

[0068] In some embodiments, a second heavily doped implantation region 110 is further included within the body region 107. In some embodiments, the LDMOS device is an N-type or P-type device; when it is N-type, the drift region 106 is N-type, the body region 107 is P-type, the first heavily doped implantation region 109 is N-type, and the second heavily doped implantation region 110 is P-type; when it is P-type, the polarities are opposite. The implanted ions are selected from phosphorus, arsenic, antimony, boron, indium, or boron difluoride. The first heavily doped implantation region 109 and the second heavily doped implantation region 110 can be implanted with high doses using self-aligned positions defined by the sidewall structure 108. The source / drain regions may also include lightly doped drains (LDDs) or moderately doped extended regions formed by lower energy implantation. The body region 107 and the drift region 106 employ multi-energy-level ion implantation combined with long-term high-temperature advance annealing to obtain a predetermined concentration profile.

[0069] In some embodiments, the barrier dielectric layer 201 is composed of a metal silicide reactive barrier layer material. The material of the barrier dielectric layer 201 is selected from materials such as silicon oxide, silicon nitride, and silicon oxynitride. The barrier dielectric layer 201 is formed by plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), and is subsequently locally retained on the surface of the auxiliary gate 104-n using a photolithography process. The relative permittivity and thickness of the barrier dielectric layer 201 directly determine the coupling efficiency of the bias potential to the auxiliary gate 104-n.

[0070] In some embodiments, an insulating dielectric etch stop layer 112 is further provided below the interlayer dielectric layer 114, including a bottom silicon oxide layer 112-1 and a top silicon nitride layer 112-2. The insulating dielectric etch stop layer 112 can also be formed using materials such as silicon carbide, silicon carbonitride, and silicon oxynitride through a thin film deposition process. This double or multilayer stack utilizes the differences in atomic bonding between materials to provide precise stop markers through optical emission spectroscopy monitoring during reactive ion etching of contact holes. In addition, the top silicon nitride layer 112-2 can also utilize its inherent internal stress to fine-tune the carrier mobility of the underlying channel, helping to improve the drive current performance of the device.

[0071] In some embodiments, the metal interconnect structure includes a contact plug 115, a first metal layer 116, a via 117, and a second metal layer 118. The metal material is selected from copper, aluminum, aluminum-copper alloys, tungsten, cobalt, or ruthenium. The contact plug 115 is typically a tungsten plug, but a cobalt plug can also be used to achieve a lower contact resistance response. The metal interconnect structure can be manufactured using an aluminum process based on subtractive processing, or a copper damascene process or double damascene process based on additive processing. A diffusion barrier layer, made of titanium, titanium nitride, tantalum, tantalum nitride, manganese, or alloys thereof, is provided beneath each metal layer to prevent conductive atoms from diffusing into the interlayer dielectric layer 114. (Reference) Figures 9 to 12 Multilayer wiring utilizes vertical-level jumpers to direct specific potentials to the coupling interface above the auxiliary gate 104-n.

[0072] In some embodiments, the metal interconnect structure is coupled to the auxiliary gate 104-n through the barrier dielectric layer 201, and the modulation potential is electrically connected to the main gate 104, the source region, or the drain region.

[0073] refer to Figure 9 One coupling implementation is shown, in which the barrier dielectric layer 201 above the auxiliary gates 104-1 to 104-n is directly electrically shorted to the source region or low-voltage electrodes such as the main gate 104 via contact plugs 115-1 to 115-n, the first metal layers 116-1 to 116-n, and vias 117-1 to 117-n, and the interconnect path is mainly realized through the second metal layer 118-1. This mode of far-end coupling using high-layer metal wiring can utilize the parasitic capacitance generated by the multilayer interconnects and the coupling effect of the barrier dielectric layer 201 to establish a stable zero-potential or negative-potential sensing region above the isolation structure 102. Since the auxiliary gates 104-n are physically discrete and floating, this biasing method can force the electric field lines on the surface of the drift region 106 to be pressed downward, expanding the width of the surface depletion region, thereby eliminating the local electric field spikes at the oxide interface near the drain.

[0074] refer to Figure 10Another coupling implementation is shown, namely a hybrid coupling mode. In this embodiment, a portion of the cells in the auxiliary gates 104-n (e.g., auxiliary gates 104-1 and 104-2 near the source) are coupled to low-voltage electrodes such as the gate or source via contact plugs and a metal layer, while another portion of the auxiliary gate cells (e.g., auxiliary gates 104-n near the drain) are coupled to high-voltage electrodes such as the drain via a metal path. This asymmetric potential distribution logic artificially "stretches" the electric field on the surface of the drift region 106 by establishing multiple different potential steps above the same isolation structure 102. The high-voltage auxiliary gate near the drain can share part of the drain voltage drop, reducing the electrical stress at the edge of the main gate and making the work function distribution inside the device smoother. This technique of flexibly configuring potential points through a back-end metal mask allows for dynamic fine-tuning of device performance according to different breakdown voltage design requirements.

[0075] refer to Figure 11 This illustrates yet another coupling implementation, characterized in that the auxiliary gate 104-n is short-circuited coupled through the first metal layer 116. Figure 11 This demonstrates that auxiliary gates 104-1 to 104-n are shorted to low-potential nodes such as the source or gate via paths such as the first metal layer 116-1. Compared to Figure 9 The proposed solution shortens the physical path of electrical coupling, significantly reducing the RC delay of displacement current during charging and discharging, and improving the electric field modulation response speed of the auxiliary gate 104-n during high-frequency dynamic switching. The barrier dielectric layer 201 acts as a crucial capacitive barrier, ensuring not only that the polysilicon gate does not experience DC crosstalk with the metal plug, but also enhancing the longitudinal projection efficiency of the electric field through its high dielectric constant material properties. This contributes to achieving superior surface protection in thinner isolation layer environments (100 Å to 3000 Å).

[0076] refer to Figure 12 This illustrates a circuit layout implementation where auxiliary gates are coupled to low-voltage electrode nodes such as the gate or source. Multiple auxiliary gates 104-1, 104-2, and 104-n are spaced apart above the isolation structure 102 and are electrically floating.

[0077] With the synergy of these four different coupling configurations, the electric field distribution of the device was optimally corrected. Figure 13 The BV simulation comparison curves shown indicate that the BV value of the traditional structure is approximately 145V, while the BV value of the structure of this invention is increased to approximately 167V, achieving a withstand voltage gain of over 20V. This improvement in withstand voltage is not achieved through simple physical size stacking, but rather through back-end metal wiring, which enables a secondary reshaping of the electrical performance of the isolation structure 102.

[0078] A reference method for manufacturing LDMOS devices Figure 1 The process diagram, executed by a semiconductor integrated manufacturing system, includes the following steps:

[0079] Step 1: Provide a semiconductor substrate 101, form a drift region 106 and a body region 107 in the semiconductor substrate 101, and form an isolation structure 102 on the surface of the drift region 106.

[0080] In some embodiments, the thickness of the isolation structure 102 in step one is 100 angstroms to 3000 angstroms. Specifically, the system first deposits a hard mask on the substrate, forms ultra-shallow trenches by anisotropic reactive ion etching, then fills them with oxide filler and performs chemical mechanical polishing. The isolation structure 102 can also be grown using a local thermal oxidation process to grow a stepped oxide layer. The method for forming the drift region 106 and the body region 107 includes ion implantation according to a preset mask, followed by rapid thermal annealing (RTA) or laser annealing to activate the particles. The initial material of the semiconductor substrate 101 can be selected from silicon wafers whose resistivity is controlled by an epitaxial gradient.

[0081] Step 2: Form a gate dielectric layer 103 and a gate conductive material layer. Pattern the gate conductive material layer to form a main gate 104 above the channel region and a plurality of auxiliary gates 104-n above the isolation structure 102. The auxiliary gates 104-n are in an electrically floating state.

[0082] refer to Figure 2 The system uses photoresist 500 as a mask. In some embodiments, the method for forming the gate dielectric layer 103 includes forming an interface oxide layer on the surface of the semiconductor substrate 101 through pretreatment before patterning the gate. The material can be selected from silicon dioxide or silicon oxynitride. The interface oxide layer can be prepared by dry thermal oxidation, in-situ vapor generation process, wet oxidation process, atmospheric pressure chemical vapor deposition, or chemical oxidation method using chemical oxidants such as hydrogen peroxide or ozone. Subsequently, a high dielectric constant dielectric layer can be deposited on top of the interface oxide layer using atomic layer deposition, plasma-enhanced chemical vapor deposition, or metal-organic chemical vapor deposition. The gate conductive material layer is selected from heavily doped polycrystalline silicon, or it can be replaced with a metal gate (MG) structure containing a work function adjustment metal. The method for patterning the conductive layer includes plasma dry etching based on fluorine-based or chlorine-based reactive gases. A single patterning process simultaneously defines the main gate 104 and discrete auxiliary gates 104-1, 104-2, and 104-n. The main gate 104 is confined to a position where the overlap width over the isolation structure 102 is less than 2 micrometers. Since the auxiliary gates are defined in the same polysilicon layer, extremely high alignment uniformity and high consistency between the gates are ensured, facilitating the establishment of a stable lateral coupling bias environment.

[0083] Step 3: Form sidewall structures 108 on the main gate 104 and auxiliary gate sidewalls, and perform an implantation process on the semiconductor substrate 101 to form the first heavily doped implantation region 109 of the source and drain regions.

[0084] refer to Figure 3 The system first deposits one or more dielectric thin films (such as silicon nitride or silicon oxide), followed by maskless etch-back to form the sidewall structure 108. In some embodiments, step three further includes forming a second heavily doped implantation region 110 located within the body region 107. The first heavily doped implantation region 109 and the second heavily doped implantation region 110 are formed by self-aligned ion implantation, using the sidewall width as a lateral offset to form a heavily doped distribution in the active region. The energy and beam sweep of the implanted ions are automatically adjusted according to the pattern density. After implantation, annealing is performed to eliminate lattice defects. The body region 107 always maintains the depth distribution pre-formed in step one, and the second heavily doped implantation region 110 provides stable electrical contact within it.

[0085] In some embodiments, the polarity of the doped region in steps one and three is determined by the target polarity of the N-type or P-type device.

[0086] Step 4: Form a barrier dielectric layer 201 covering the surface of the auxiliary gate 104-n.

[0087] refer to Figure 4 The barrier dielectric layer 201 is formed by depositing a silicon dioxide or silicon nitride thin film over an entire layer, followed by pattern transfer and etching. The barrier dielectric layer 201 selectively covers the floating auxiliary gate array, and its edges may overlap with the sidewall structure 108. Here, the barrier dielectric layer 201 serves as the dielectric core for field plate bias. By adjusting its film structure and impurity content, its capacitance density as a decoupling capacitor can be optimized, enabling the device to maintain stable potential sensing even under high-voltage dynamic driving.

[0088] In some embodiments, after step four and before step five, the method further includes performing a metal silicide process to form a metal silicide on the exposed surface not covered by the barrier dielectric layer 201. Referring to TSMC's self-aligned silicide process, the system first sputters a layer of refractory metal with a thickness of approximately tens to hundreds of angstroms via physical vapor deposition. The material is selected from nickel, platinum, cobalt, titanium, or alloys thereof. Subsequently, a two-stage rapid thermal treatment induces a solid-state reaction between metal protons and the exposed polycrystalline or monocrystalline silicon. The presence of the barrier dielectric layer 201 ensures that the auxiliary gate 104-n polycrystalline silicon is physically encapsulated and does not react with the metal, thereby maintaining the high resistivity and physical isolation of each auxiliary gate unit and preventing charge loss due to silicide connections. This step effectively reduces source / drain contact impedance and main gate impedance.

[0089] Step 5: Deposit interlayer medium layer 114, and form contact holes 115-n in interlayer medium layer 114 that expose the surface of barrier medium layer 201.

[0090] refer to Figure 5 First, an insulating dielectric etching stop layer 112 (112-1, 112-2) with stepped coverage is deposited. Then, an interlayer dielectric layer 114 is deposited using methods such as subatmospheric chemical vapor deposition (SACVD) or high-density plasma chemical vapor deposition (HDCVD). The material is selected from fluorinated silicon glass or undoped silicon glass. After deposition, the interlayer dielectric layer 114 is planarized using a chemical mechanical polishing (CMP) process.

[0091] refer to Figure 6 The hole positions are defined using photolithography, and reactive ion etching is performed to form the contact holes 115. During the etching of the contact holes 115-n used for modulation, the manufacturing system controls the etching gas ratio so that the bottom of the hole precisely rests on the top of the barrier dielectric layer 201. Since the contact holes do not penetrate the barrier dielectric layer 201, the resulting non-contact contacts provide a basis for the modulation of parasitic charges between the main gate and drain.

[0092] Step 6: Form a contact plug in the contact hole 115-n and form a metal interconnect structure coupled to the auxiliary gate 104-n through the contact plug.

[0093] refer to Figure 7 The first layer of the metal interconnect structure begins with the deposition of a diffusion barrier layer (such as titanium / titanium nitride) and the filling of tungsten plugs as contact plugs 115 by chemical vapor deposition. Subsequently, a first metal layer 116 is deposited and patterned using photoresist 501. The first metal layer 116 can be an aluminum-copper alloy or a metal segment from a copper damask process.

[0094] refer to Figure 8 An intermetallic dielectric layer 119 is deposited on the first metal layer. The material can be selected from low-k or very low-k (ELK) materials, such as a carbon-doped silicon oxide film, and is formed by chemical vapor deposition. Planarization and photolithography etching are performed on the intermetallic dielectric layer to form vias 117 and wiring trenches for the second metal layer 118. The metal interconnects can be formed using a copper double damask process based on electrochemical plating (ECP). A tantalum / tantalum nitride barrier layer and a copper seed layer are sputtered first, followed by copper filling and CMP removal of excess copper material. The via 117 connects the first metal layer 116 and the second metal layer 118 in the vertical direction.

[0095] In some embodiments, in step six, the metal interconnect structure is coupled to the modulated potential through the barrier dielectric layer 201 to the auxiliary gate 104-n, and the modulated potential is electrically connected to the main gate 104, the source region, or the drain region.

[0096] refer to Figure 9 One coupling implementation is shown, in which the barrier dielectric layer 201 above the auxiliary gates 104-1 to 104-n is directly electrically shorted to the source region or low-voltage electrodes such as the main gate 104 via contact plugs 115-1 to 115-n, the first metal layers 116-1 to 116-n, and vias 117-1 to 117-n, and the interconnect path is mainly realized through the second metal layer 118-1. This mode of far-end coupling using high-layer metal wiring can utilize the parasitic capacitance generated by the multilayer interconnects and the coupling effect of the barrier dielectric layer 201 to establish a stable zero-potential or negative-potential sensing region above the isolation structure 102. Since the auxiliary gates 104-n are physically discrete and floating, this biasing method can force the electric field lines on the surface of the drift region 106 to be pressed downward, expanding the width of the surface depletion region, thereby eliminating the local electric field spikes at the oxide interface near the drain.

[0097] refer to Figure 10 Another coupling implementation is shown, namely a hybrid coupling mode. In this embodiment, a portion of the cells in the auxiliary gates 104-n (e.g., auxiliary gates 104-1 and 104-2 near the source) are coupled to low-voltage electrodes such as the gate or source via contact plugs and a metal layer, while another portion of the auxiliary gate cells (e.g., auxiliary gates 104-n near the drain) are coupled to high-voltage electrodes such as the drain via a metal path. This asymmetric potential distribution logic artificially "stretches" the electric field on the surface of the drift region 106 by establishing multiple different potential steps above the same isolation structure 102. The high-voltage auxiliary gate near the drain can share part of the drain voltage drop, reducing the electrical stress at the edge of the main gate and making the work function distribution inside the device smoother. This technique of flexibly configuring potential points through a back-end metal mask allows for dynamic fine-tuning of device performance according to different breakdown voltage design requirements.

[0098] refer to Figure 11 This illustrates yet another coupling implementation, characterized in that the auxiliary gate 104-n is short-circuited coupled through the first metal layer 116. Figure 11 This demonstrates that auxiliary gates 104-1 to 104-n are shorted to low-potential nodes such as the source or gate via paths such as the first metal layer 116-1. Compared to Figure 9The proposed solution shortens the physical path of electrical coupling, significantly reducing the RC delay of displacement current during charging and discharging, and improving the electric field modulation response speed of the auxiliary gate 104-n during high-frequency dynamic switching. The barrier dielectric layer 201 acts as a crucial capacitive barrier, ensuring not only that the polysilicon gate does not experience DC crosstalk with the metal plug, but also enhancing the longitudinal projection efficiency of the electric field through its high dielectric constant material properties. This contributes to achieving superior surface protection in thinner isolation layer environments (100 Å to 3000 Å).

[0099] refer to Figure 12 This illustrates a circuit layout implementation where auxiliary gates are coupled to low-voltage electrode nodes such as the gate or source. Multiple auxiliary gates 104-1, 104-2, and 104-n are spaced apart above the isolation structure 102 and are electrically floating.

[0100] With the synergy of these four different coupling configurations, the electric field distribution of the device was optimally corrected. Figure 13 The BV simulation comparison curves shown indicate that the BV value of the traditional structure is approximately 145V, while the BV value of the structure of this invention is increased to approximately 167V, achieving a withstand voltage gain of over 20V. This improvement in withstand voltage is not achieved through simple physical size stacking, but rather through back-end metal wiring, which enables a secondary reshaping of the electrical performance of the isolation structure 102.

[0101] In some embodiments, the metal interconnect layers corresponding to the four coupling methods described above can be manufactured using advanced copper damask processes. The intermetallic dielectric layer 119 can be porous silicon carbonitride, carbon-doped silicon oxide, or a nanoporous low-dielectric-constant dielectric formed by spin coating. Trenches and vias are defined within the intermetallic dielectric layer 119 using a dual patterning process, followed by the deposition of a diffusion barrier layer composed of tantalum, tantalum nitride, cobalt, ruthenium, or metallic manganese. The main conductive material can be electroplated copper, with a cobalt or ruthenium capping layer deposited on the copper layer surface to enhance electromigration resistance. The coupling capacitance can be further fine-tuned by introducing a high-k dielectric at the intermetallic interface or adjusting the interlayer spacing of the interconnects. For scenarios requiring simultaneous improvement in power conversion efficiency and withstand voltage, an adaptive field satisfying a specific frequency response can be artificially created by optimizing the overlap area of ​​the second metal layer 118 and the first metal layer 116. This three-dimensional modulation architecture, which extends upwards from the semiconductor substrate 101 to the multilayer metal, greatly enhances the robustness of LDMOS under high voltage and high current pulse operating conditions while ensuring that the linear current fluctuation of IdLin is less than 2%, providing a highly reliable physical basis for high-performance power management chips.

[0102] refer to Figure 13The graph shows a comparison of the breakdown voltage strength between the structure of this application and the conventional structure. The vertical axis represents the drain current Id, and the horizontal axis represents the drain voltage Vd. Curve "Traditional" corresponds to a conventional field plate structure or a thick STI structure, with a breakdown voltage BV of approximately 145V. Curve "This work" corresponds to a device employing the aforementioned ultra-shallow isolation structure 102 (thickness 100 Å to 3000 Å) and a discrete auxiliary gate 104-n potential modulation scheme, with a breakdown voltage BV increased to approximately 167V. Simulation data and test results demonstrate that the induced potential generated by the aforementioned potential modulation mechanism can shunt a voltage of approximately 20V or more. Without physically thickening the isolation structure 102 and without causing current path limitation, the structure of this application successfully alleviates the electric concentration effect near the drain through adaptive charge distribution. This performance improvement directly reflects the superiority of the floating auxiliary gate 104-n combined with the barrier dielectric layer 201 as the modulation core, enabling high-voltage LDMOS devices to achieve higher reliability redundancy while maintaining a compact size.

[0103] In some embodiments, for implementing Figures 9 to 12 The complex interconnect layers can be formed using a copper-based electrochemical plating (ECP) process. First, metal trenches and vias 117 are formed in the intermetallic dielectric layer 119 using dry etching. The material of the intermetallic dielectric layer 119 can be selected from carbon-doped silicon oxide, silicon hydroxide, or nanoporous ultra-low-k materials formed by spin coating. After forming the trenches, a diffusion barrier layer is formed on the sidewalls and bottom using physical vapor deposition or atomic layer deposition (ALD). The barrier layer material can be selected from titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or a self-formed manganese-based oxide film. Subsequently, a seed layer composed of copper, cobalt, or ruthenium is formed on the surface of the barrier layer. The trenches are then filled with a metal substrate material, which can be selected from copper, cobalt, ruthenium, silver, or gold. After filling, the manufacturing system performs a high-temperature thermal annealing process to promote metal grain coalescence and release internal thermal stress. Finally, chemical mechanical polishing (CMP) is used to remove excess metal, achieving planarization of the entire chip surface. This multi-layered, highly conductive metal network not only ensures that the modulation bias potential can be conducted with low loss to the contact plugs 115-n above the auxiliary gate 104-n, but also achieves precise shaping of the surface potential energy of the drift region 106 through the parasitic capacitance coupling formed between it and the floating polysilicon below. Combined with an isolation structure with a thickness of 100 Å to 3000 Å, the system can switch between various modulation scenarios, from source feedback to adaptive drain bias, simply by changing the design of the back-end metal mask. Ultimately, this increases the device breakdown voltage BV to approximately 167V, with the linear drain current IdLin fluctuating by less than 2%, demonstrating significant engineering value.

[0104] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LDMOS device, characterized in that, include: The semiconductor substrate (101) has a drift region (106) and a bulk region (107). An isolation structure (102) is located on the surface of the drift region (106); The main gate (104) is located above the channel region; Multiple auxiliary gates (104-n) are spaced apart above the isolation structure (102) and are in an electrically floating state; Source and drain regions, including the first doped implantation region (109). A barrier dielectric layer (201) covers the auxiliary gate (104-n); An interlayer dielectric layer (114) covers the main gate (104), the auxiliary gate (104-n), and the barrier dielectric layer (201). A metal interconnect structure extends through the interlayer dielectric layer (114) and to the surface of the barrier dielectric layer (201); The metal interconnect structure is configured to use the barrier dielectric layer (201) as a coupling medium to modulate the potential of the auxiliary gate (104-n).

2. The LDMOS device according to claim 1, characterized in that: The isolation structure (102) is an ultra-shallow trench isolation structure or a stepped field oxide layer structure.

3. The LDMOS device according to claim 1, characterized in that: The thickness of the isolation structure (102) is 100 angstroms to 3000 angstroms.

4. The LDMOS device according to claim 1, characterized in that: The main gate (104) extends over a portion of the isolation structure (102), and the overlap width between the main gate (104) and the isolation structure (102) is less than 2 μm.

5. The LDMOS device according to claim 1, characterized in that: The LDMOS device is an N-type LDMOS device or a P-type LDMOS device; when the LDMOS device is an N-type LDMOS device, the drift region (106) is N-type, the body region (107) is P-type, the first heavily doped injection region (109) is N-type, and the second heavily doped injection region (110) is P-type; when the LDMOS device is a P-type LDMOS device, the drift region (106) is P-type, the body region (107) is N-type, the first heavily doped injection region (109) is P-type, and the second heavily doped injection region (110) is N-type.

6. The LDMOS device according to claim 5, characterized in that: The barrier medium layer (201) is composed of a metal silicide reaction barrier material.

7. The LDMOS device according to claim 1, characterized in that: Below the interlayer dielectric layer (114), there is also an insulating dielectric etch stop layer (112), which includes a bottom silicon oxide layer (112-1) and a top silicon nitride layer (112-2).

8. The LDMOS device according to claim 1, characterized in that: The metal interconnect structure includes a contact plug (115), a first metal layer (116), an inter-metal via (117), and a second metal layer (118).

9. The LDMOS device according to claim 8, characterized in that: The auxiliary gate (104-n) is electrically connected to the main gate (104), source region, or drain region through the metal interconnect structure.

10. A method for manufacturing an LDMOS device, characterized in that, include: Step 1: Provide a semiconductor substrate (101), form a drift region (106) and a body region (107) in the semiconductor substrate (101), and form an isolation structure (102) on the surface of the drift region (106). Step 2: Form a gate dielectric layer (103) and a gate conductive material layer. Pattern the gate conductive material layer to form a main gate (104) above the channel region and a plurality of auxiliary gates (104-n) above the isolation structure (102). The auxiliary gates (104-n) are in an electrically floating state. Step 3: A sidewall structure (108) is formed on the sidewalls of the main gate (104) and the auxiliary gate (104-n), and an implantation process is performed in the semiconductor substrate (101) to form the first heavily doped implantation region (109) of the source and drain regions. Step 4: Form a barrier dielectric layer (201) covering the surface of the auxiliary gate (104-n). Step 5: Deposit an interlayer medium layer (114) and form contact holes (115-n) in the interlayer medium layer (114) that expose the surface of the barrier medium layer (201). Step 6: Form a contact plug in the contact hole (115-n) and form a metal interconnect structure coupled to the auxiliary gate (104-n) through the contact plug.

11. The method for manufacturing an LDMOS device according to claim 10, characterized in that: In step three, the heavily doped implantation region (110) is formed within the body region (107).

12. The method for manufacturing an LDMOS device according to claim 10, characterized in that: The LDMOS device is an N-type LDMOS device or a P-type LDMOS device; when the LDMOS device is an N-type LDMOS device, in step one, the drift region (106) is N-type and the body region (107) is P-type; in step three, the first heavily doped injection region (109) is N-type, and in the specific implementation of claim 11, the second heavily doped injection region (110) is P-type; when the LDMOS device is a P-type LDMOS device, in step one, the drift region (106) is P-type and the body region (107) is N-type; in step three, the first heavily doped injection region (109) is P-type, and in the specific implementation of claim 11, the second heavily doped injection region (110) is N-type.

13. The method for manufacturing an LDMOS device according to claim 10, characterized in that: In step four, the barrier dielectric layer (201) is used as a metal silicide reaction barrier layer to cover the top of the auxiliary gate (104-n).

14. The method for manufacturing an LDMOS device according to claim 13, characterized in that: After step four and before step five, the process further includes performing a metal silicide process to form a metal silicide on the exposed surface not covered by the barrier dielectric layer (201).

15. The method for manufacturing an LDMOS device according to claim 10, characterized in that: In step five, before forming the interlayer dielectric layer (114), an insulating dielectric etch stop layer (112) including a bottom silicon oxide layer (112-1) and a top silicon nitride layer (112-2) is formed by a deposition process.

16. The method for manufacturing an LDMOS device according to claim 10, characterized in that: In step five, after the interlayer dielectric layer (114) is formed, a chemical mechanical polishing planarization process is performed.

17. The method for manufacturing an LDMOS device according to claim 10, characterized in that: In step six, the metal interconnect structure is coupled to the auxiliary gate (104-n) through the barrier dielectric layer (201) by the modulation potential, and the modulation potential is electrically connected to the main gate (104), the source region or the drain region.

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