LDMOS structure and its manufacturing method

Abstract

This application provides an LDMOS structure and a method for manufacturing the LDMOS structure. The structure includes: a substrate with mutually spaced doped well regions and drift regions formed internally; at least two spaced isolation trenches formed within the drift regions; at least two field plate structures formed within the isolation trenches; each field plate structure includes a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the substrate; and at least two isolation structures formed within the isolation trenches; the isolation structures are located on the side of the conductive layer away from the substrate. This application overcomes the limitations imposed by existing LDMOS devices on breakdown voltage and on-resistance, improving the overall performance of the LDMOS device.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor technology, specifically to an LDMOS structure and a method for manufacturing the LDMOS structure. Background Technology

[0002] LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) devices are widely used in automotive electronics, mobile communications, and industrial control due to their advantages such as high voltage withstand capability, high power handling capability, good thermal stability, and good process compatibility.

[0003] Among the various performance parameters of LDMOS devices, breakdown voltage and on-resistance are the two main parameters used to evaluate the overall performance of LDMOS devices as power switches. Specifically, breakdown voltage is used to determine the voltage level to which the LDMOS device can be used, and on-resistance is used to measure the power loss of the LDMOS device when it is in the on-state.

[0004] However, in existing LDMOS devices, the breakdown voltage and on-resistance are mutually limiting, which means that the overall performance improvement of LDMOS devices is limited by the balance between the breakdown voltage and on-resistance, making it difficult to meet the performance requirements of LDMOS devices in various application scenarios. Summary of the Invention

[0005] In view of this, several embodiments of this application provide an LDMOS structure and a method for manufacturing the LDMOS structure to improve the overall performance of LDMOS devices.

[0006] In one aspect, an embodiment of this application provides an LDMOS structure, the LDMOS structure comprising: a substrate; a doped well region and a drift region formed therein, spaced apart from each other; at least two spaced isolation trenches formed in the drift region; at least two field plate structures formed in the isolation trenches; the field plate structures comprising a field oxide layer formed on the surface of the isolation trenches and a conductive layer formed on the side of the field oxide layer away from the substrate; at least two isolation structures formed in the isolation trenches; the isolation structures being located on the side of the conductive layer away from the substrate.

[0007] Optionally, the opening size of the isolation trench is positively correlated with the distance between the isolation trench and the doped well region.

[0008] Optionally, the isolation trench has a bottom surface and a side surface; the field oxygen layer includes a bottom field oxygen portion formed on the bottom surface of the isolation trench and a side field oxygen portion formed on the side surface of the isolation trench; with the growth direction of the field oxygen layer as the thickness direction, the thickness of the bottom field oxygen portion along the thickness direction is positively correlated with the opening size of the isolation trench.

[0009] Optionally, taking the extension direction of the isolation trench as the depth direction, the ratio of the thickness of the bottom oxygen portion along the thickness direction to the depth of the isolation trench along the depth direction falls within the range of 1:40 to 1:7; the ratio of the thickness of the conductive layer along the thickness direction to the depth of the isolation trench along the depth direction falls within the range of 1:9 to 1:7.

[0010] In another aspect, one embodiment of this application provides a method for manufacturing an LDMOS structure, the method comprising: providing a semiconductor substrate; forming at least two spaced-apart isolation trenches within the semiconductor substrate; forming a field plate structure within each isolation trench; the field plate structure including a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the semiconductor substrate; forming an isolation structure within each isolation trench on the side of the conductive layer away from the semiconductor substrate; performing ion implantation on the semiconductor substrate to obtain the LDMOS structure; the LDMOS structure comprising a substrate with mutually spaced drift regions and doped well regions formed internally.

[0011] Optionally, the step of providing a semiconductor substrate includes: providing a transition substrate; the transition substrate includes a substrate, a buffer layer formed on the surface of the substrate, and a hard mask material layer formed on the side of the buffer layer away from the substrate; wherein at least two spaced trenches are formed in the substrate; the opening size of the trenches gradually increases along the arrangement direction of the trenches; the trenches have a bottom surface and a side surface; performing a linear oxidation process to form an oxide isolation layer covering the bottom surface and side surface of the trenches; depositing a hard mask material on the side of the hard mask material layer away from the substrate and the side of the oxide isolation layer away from the substrate to obtain an intermediate substrate; performing a dry etching process on the intermediate substrate until the bottom surface of the trench with the largest opening is exposed to form the at least two isolation trenches to obtain the semiconductor substrate.

[0012] Optionally, the at least two isolation trenches include a first isolation trench with a maximum opening and a second isolation trench with an opening smaller than the first isolation trench; the step of forming a field plate structure in each of the isolation trenches includes: performing a local oxidation process on the bottom surface of the first isolation trench to form a first bottom field oxide portion on the bottom surface of the first isolation trench; removing the hard mask material in the semiconductor substrate; forming the conductive layer on the side of the first bottom field oxide portion away from the substrate and on the side of the oxide isolation layer away from the substrate to obtain the field plate structure; in the field plate structure formed in the first isolation trench, the field oxide layer includes the first bottom field oxide portion and a first side field oxide portion composed of an oxide isolation layer covering the side surface of the first isolation trench; in the field plate structure formed in the second isolation trench, the field oxide layer includes a second bottom field oxide portion composed of an oxide isolation layer covering the bottom surface of the second isolation trench and a second side field oxide portion composed of an oxide isolation layer covering the side surface of the second isolation trench.

[0013] Optionally, the step of removing the hard mask material from the semiconductor substrate includes: performing wet cleaning on the semiconductor substrate to remove the hard mask material from the semiconductor substrate; wherein the wet cleaning solution is at least one of phosphoric acid, a mixed solution of phosphoric acid and acetic acid, and a mixed solution of phosphoric acid and nitric acid.

[0014] Optionally, the step of forming an isolation structure in each isolation trench on the side of the conductive layer away from the semiconductor substrate includes: depositing an isolation material in each isolation trench on the side of the conductive layer away from the semiconductor substrate to form an isolation material layer; and grinding the isolation material layer with the surface of the conductive layer away from the buffer layer as the grinding endpoint to obtain the isolation structure.

[0015] Optionally, the step of performing ion implantation on the semiconductor substrate to obtain the LDMOS structure includes: implanting ions into the semiconductor substrate to obtain a substrate in which the drift region and the doped well region are formed, such that the at least two isolation trenches are located within the drift region, and the opening size of the isolation trenches is positively correlated with the distance between the isolation trenches and the doped well region.

[0016] In several embodiments provided in this application, by forming mutually spaced drift regions and doped well regions within a substrate, wherein at least two spaced isolation trenches are formed within the drift regions, and at least two field plate structures are formed within the isolation trenches, each field plate structure including a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the substrate, and then forming at least two isolation structures within the isolation trenches such that the isolation structures are located on the side of the conductive layer away from the substrate, the unexpected effects achieved include: the field plate structure composed of the field oxide layer and the conductive layer makes the internal electric field of the LDMOS device tend to be smooth, reducing the risk of local electric field breakdown and improving the breakdown voltage capability of the LDMOS device; and the multiple spaced isolation structures increase the effective width of the drift region, optimize the conductive path of the drift region, thereby reducing the on-resistance of the LDMOS device, breaking through the mutual limitation between breakdown voltage and on-resistance in existing LDMOS devices, and improving the overall performance of the LDMOS device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the structure of an LDMOS device provided for related technologies.

[0019] Figure 2 This is a schematic flowchart illustrating the manufacturing method of the LDMOS structure provided in this application embodiment.

[0020] Figure 3 This is a schematic diagram of the process of providing a semiconductor substrate provided in an embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the structure of the transition substrate provided in an embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the formation of an oxide isolation layer provided in an embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the structure of the intermediate substrate provided in an embodiment of this application.

[0024] Figure 7 This is a schematic diagram of the structure of a semiconductor substrate provided in an embodiment of this application.

[0025] Figure 8 This is a schematic diagram illustrating the process of forming a field plate structure in each isolation trench, as provided in an embodiment of this application.

[0026] Figure 9 This is a schematic diagram of a first bottom oxygen region formed on the bottom surface of a first isolation trench, provided as an embodiment of this application.

[0027] Figure 10 This is a schematic diagram of removing hard mask material according to an embodiment of this application.

[0028] Figure 11 This is a schematic diagram of the formation of a conductive layer provided in an embodiment of this application.

[0029] Figure 12 This is a schematic diagram illustrating the process of forming an isolation structure in each isolation trench, as provided in an embodiment of this application.

[0030] Figure 13 This is a schematic diagram illustrating the formation of an isolation material layer within each isolation trench, as provided in an embodiment of this application.

[0031] Figure 14 This is a schematic diagram of grinding the isolation material to obtain the isolation structure, as provided in an embodiment of this application.

[0032] Figure 15 This is a schematic diagram showing the removal of a portion of the conductive layer, as provided in an embodiment of this application.

[0033] Figure 16 This is a schematic diagram of the LDMOS structure provided in an embodiment of this application.

[0034] Figure 17 This is a schematic diagram of removing the buffer layer provided in an embodiment of this application.

[0035] Figure 18 This is a schematic diagram of the formation of a gate oxide layer provided in an embodiment of this application.

[0036] Figure 19 This is a schematic diagram illustrating the formation of the source doped region, drain doped region, and gate structure provided in the embodiments of this application.

[0037] Structural designation explanation

[0038] 10. Silicon substrate; 11. Shallow trench isolation structure; 12. P-type well region; 13. N-type drift region; 14. Source region; 15. Drain region; 16. Bulk contact region; 41. Polysilicon gate; 42. Field plate layer; 100. Transition substrate; 110. Substrate; 120. Buffer layer; 130. Hard mask material layer; 140. Trench; 141. First trench; 142. Second trench; 150. Oxide isolation layer; 160. Hard mask deposition layer; 200. Intermediate substrate; 300. Semiconductor substrate; 310. Isolation trench; 311. First isolation trench; 312. Second isolation trench 320. First field oxide layer; 321. First bottom field oxide layer; 322. First side field oxide layer; 330. Conductive layer; 340. Second field oxide layer; 341. Second bottom field oxide layer; 342. Second side field oxide layer; 350. Isolation material layer; 351. Isolation structure; 360. Drift region; 370. Doped well region; 400. LDMOS structure; 410. Gate oxide layer; 420. Gate structure; 421. Gate oxide layer; 422. Gate; 423. Gate sidewall; 430. Drain doped region; 440. Source doped region; 450. Body contact doped region. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0041] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0042] With the widespread use of LDMOS devices in various high-voltage applications, the performance requirements for LDMOS devices are becoming increasingly stringent. However, in related technologies, the limiting relationship between breakdown voltage and on-resistance hinders the improvement of the overall performance of LDMOS devices.

[0043] On the one hand, breakdown voltage is a core electrical parameter for evaluating the breakdown voltage capability of LDMOS devices. In LDMOS devices provided by related technologies, the breakdown voltage capability is mainly achieved by the drift region with a low doping concentration. When the device is in the off state and subjected to high voltage, the depletion region will mainly expand in different directions within the drift region. Due to the high resistivity of the drift region, it can withstand most of the applied voltage, thereby reducing the peak electric field intensity at the channel edge and optimizing the electric field distribution inside the device. Since the length and doping concentration of the drift region have a direct impact on the electric field distribution inside the device, researchers usually increase the length of the drift region or decrease the doping concentration of the drift region to improve the breakdown voltage of the device.

[0044] On the other hand, on-resistance is a core electrical parameter for evaluating the power efficiency of LDMOS devices. The length and doping concentration of the drift region have a critical impact on on-resistance. To save chip area and reduce device conduction losses, researchers typically shorten the length of the drift region or increase its doping concentration.

[0045] In summary, drift region design aimed at increasing breakdown voltage leads to increased on-resistance, while drift region design aimed at reducing on-resistance comes at the cost of sacrificing the device's breakdown voltage. Therefore, the overall performance of LDMOS devices provided by related technologies is typically a balance between breakdown voltage and on-resistance.

[0046] Please see Figure 1 To maximize overall device performance while maintaining a balance between breakdown voltage and on-resistance, researchers have improved the structure of LDMOS devices in related technologies. Specifically, compared to the original LDMOS device, the improved LDMOS device retains the basic structure of the original LDMOS device. That is, the improved LDMOS device still has a P-type well region 12 and an N-type drift region 13 within the silicon substrate 10, a polysilicon gate 41 on the surface of the silicon substrate 10, an active region 14 and a body contact region 16 formed within the P-type well region 12, and a drain region 15 formed within the N-type drift region 13. The improvements mainly include the following two aspects:

[0047] First, researchers constructed multiple spaced shallow trench isolation (STI) structures 11 within the N-type drift region 13. Specifically, each STI structure 11 is an inverted multi-level stepped structure, and the greater the distance between the STI structure 11 and the P-type well region 12, the more steps the STI structure 11 has, and the larger the opening size. Since the dielectric constant of the material (such as oxide) of the STI structure 11 is typically lower than that of silicon, the electric field distribution within the N-type drift region 13 can be optimized using the "dielectric constant modulation" effect, thereby increasing the device's breakdown voltage without increasing the device's on-resistance. Furthermore, by constructing multi-level stepped shallow trench isolation structures 11 with opening sizes increasing with distance from the P-type well region 12, new electric field peaks can be added without increasing the electric field area. This disperses the originally concentrated electric field peaks to the edges of multiple electric field intensity steps, thereby reducing the peak electric field intensity, decreasing the degree of impact ionization, and improving the device's thermionic effect.

[0048] Secondly, the researchers set multiple field plate layers 42 on the surface of the N-type drift region 13 at positions corresponding to the shallow trench isolation structure 11. Each field plate layer 42 and the corresponding shallow trench isolation structure 11 are combined to form a field plate structure, thereby using multiple field plate structures to adjust the electric field inside the N-type drift region 13 and optimize the electric field distribution inside the device.

[0049] However, researchers found that the performance improvement of the improved LDMOS device was limited and still could not meet the performance requirements of LDMOS devices in various application scenarios when testing the overall performance of the improved LDMOS device.

[0050] Further investigation reveals that the limited performance improvement of the improved LDMOS device stems from the following process: First, multiple multi-level stepped trenches are formed in the substrate using a dry etching process; then, isolation material is filled into these trenches; finally, the filled isolation material is planarized to obtain the shallow trench isolation structure 11. Consequently, the shallow trench isolation structure 11 has relatively sharp corners. When the LDMOS device operates at high voltage (e.g., greater than 50V), the high voltage is primarily borne by the drain region at the high potential end. At this point, the sharp corners of the shallow trench isolation structure 11 near the drain region will form a strong electric field concentration, becoming the highest point of electric field strength in the entire device. Since these sharp corners are far from the surface of the N-type drift region 13, the field plate structure formed by the field plate layer 42 on the surface of the N-type drift region 13 and the shallow trench isolation structure 11 cannot effectively regulate the electric field distribution in this region. Therefore, the electric field concentration at sharp corners may accelerate the flow of charge carriers through these areas, exacerbating the hot carrier injection (HCI) effect and leading to performance degradation such as threshold voltage drift, increased on-resistance, and reduced reliability.

[0051] Therefore, it is necessary to provide a method for manufacturing LDMOS structures that can improve the breakdown voltage of the device, reduce the on-resistance of the device, and suppress the negative impact of hot carrier injection effect on the performance of LDMOS devices, thereby improving the overall performance of the device.

[0052] Please see Figure 2 One embodiment of this application provides a method for manufacturing an LDMOS structure. The method may include steps S110, S130, S150, and S170.

[0053] S110: Provides a semiconductor substrate.

[0054] In this embodiment, at least two spaced-apart isolation trenches can be formed within the semiconductor substrate. These isolation trenches can accommodate field plate structures and isolation structures. This embodiment does not impose a specific limit on the number of isolation trenches. When the number of isolation trenches exceeds two, the spacing between adjacent isolation trenches can be equal or unequal.

[0055] Please see Figure 3 In order to prepare a semiconductor substrate having at least two spaced-apart isolation trenches formed inside, in this embodiment, the step of providing the semiconductor substrate may include sub-steps S111, S112, S113 and S114.

[0056] S111: Provides a transition substrate.

[0057] Please see Figure 4 In this embodiment, the transition substrate 100 may include a substrate 110, a buffer layer 120 formed on the surface of the substrate 110, and a hard mask material layer 130 formed on the side of the buffer layer 120 away from the substrate 110.

[0058] In this embodiment, the substrate 110 can serve as the basis for forming the semiconductor structure. Specifically, the substrate 110 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate 110 can be made of materials such as silicon (Si), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), or silicon carbide (SiC). The substrate 110 can be a single-layer structure or a multi-layer structure. In this embodiment, considering factors such as dielectric loss requirements, manufacturing process, manufacturing cost, and the convenience of subsequent oxidation processes, the substrate 110 can be a single-crystal silicon wafer or an epitaxial silicon wafer.

[0059] In this embodiment, the buffer layer 120 can be used to achieve stress transition between the substrate 110 and the hard mask material layer 130. Specifically, due to the lattice mismatch and difference in thermal expansion coefficient between the hard mask material layer 130 and the substrate 110, directly forming the hard mask material layer 130 on the surface of the substrate 110 may cause the substrate 110 to warp. Therefore, the buffer layer 120 can be used to absorb the stress brought by the hard mask material, reducing damage to the surface of the substrate 110. In addition, the buffer layer 120 can also be used as an etching stop layer in the etching process. For example, the material of the buffer layer 120 can be silicon dioxide (SiO2).

[0060] In this embodiment, the hard mask material layer 130 can serve as a mask in the subsequent dry etching process. Specifically, the material of the hard mask material layer 130 can be a nitride, such as silicon nitride (SiN).

[0061] In this embodiment, at least two spaced trenches 140 may be formed within the substrate 110. Specifically, the trenches 140 may be formed by dry etching of the substrate 110 based on a hard mask material layer 130, serving as the basis for forming the isolation trenches. Each trench 140 may have a bottom surface and a side surface. Taking the extension direction of the trench 140 as the depth direction, the depth of the trench 140 along the depth direction may fall within the range of 3500 Å to 4500 Å. For example, the depth of the trench 140 along the depth direction may be 3500 Å, 4000 Å, or 4500 Å.

[0062] When an LDMOS device is operating at high voltage, the electric field strength is greater closer to the drain. Correspondingly, when using isolation and field plate structures to uniformly distribute the electric field within the drift region, the region closer to the drain requires higher electric field regulation capabilities. Therefore, to improve the regulation capability of the isolation and field plate structures subsequently formed within the isolation trenches on the electric field distribution within the drift region, the opening sizes of different trenches 140 can be different. Specifically, along the arrangement direction of the trenches 140, the opening size of the trenches 140 gradually increases; that is, the closer the trench 140 is to the region where the drain will be formed, the larger the opening of the trench 140. At least two trenches 140 may include a first trench 141 with the largest opening and a second trench 142 with an opening smaller than that of the first trench 141.

[0063] S112: Perform a linear oxidation process to form an oxide isolation layer covering the bottom and sides of the trench.

[0064] Please see Figure 5 To repair the damage to the substrate 110 material caused during the dry etching process to form trenches, and to achieve isolation between the conductive layer subsequently formed in the trenches and the substrate 110, in this embodiment, a linear oxidation process can be performed on the transition substrate to form an oxide isolation layer 150 covering the bottom and sides of the trenches. Specifically, the material of the oxide isolation layer 150 can be silicon dioxide. Taking the growth direction of the oxide isolation layer 150 as the thickness direction, the oxide isolation layer 150 can have a relatively small thickness along the thickness direction, and the thickness of the oxide isolation layer 150 along the thickness direction can fall within the range of 90 Å to 120 Å. For example, the thickness of the oxide isolation layer 150 along the thickness direction can be 90 Å, 100 Å, 110 Å, or 120 Å.

[0065] S113: Deposit hard mask material on the side of the hard mask material layer away from the substrate and on the side of the oxide isolation layer away from the substrate to obtain an intermediate substrate.

[0066] S114: Perform a dry etching process on the intermediate substrate until the bottom surface of the trench with the largest opening is exposed, forming at least two isolation trenches to obtain a semiconductor substrate.

[0067] To mitigate the electric field concentration caused by sharp corners in shallow trench isolation structures in related technologies, researchers considered creating a "gradient field oxygen" layer in at least two trenches. This means that the field oxygen layer formed in trenches with different opening sizes has different thicknesses along the thickness direction, and the field oxygen layer formed in trenches with larger openings has a greater thickness along the thickness direction. This allows the field oxygen layer to reduce the sharpness of the trench corners, making the electric field distribution near the trench corners more uniform.

[0068] To achieve "gradient field oxygen," a localized oxidation process is required to oxidize designated locations on the substrate 110. In related technologies, the localized oxidation process typically involves: fabricating a mask for localized oxidation, exposing only the areas on the wafer requiring localized oxidation; then performing photolithography and etching based on this mask to expose these areas; and finally, performing localized oxidation at these locations. To reduce the number of masks used in the localized oxidation process and lower process costs, a barrier layer can be formed on the surface of the oxide isolation layer 150 first, followed by removing the barrier layer at the designated locations and the oxide isolation layer 150 it covers, thus exposing the substrate 110.

[0069] Please see Figure 6 To reduce the impact of subsequent localized oxidation processes on the oxide isolation layer 150, in this embodiment, hard mask material can be deposited on the side of the hard mask material layer 130 away from the substrate 110 and the side of the oxide isolation layer 150 away from the substrate 110 using deposition processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, forming a hard mask deposition layer 160, thus obtaining the intermediate substrate 200. In this way, on the one hand, the hard mask deposition layer 160 can be used as a barrier layer in the localized oxidation process; on the other hand, since the hard mask material layer 130 and the hard mask deposition layer 160 are made of the same material, they can be removed together in subsequent processes, reducing process complexity and saving process costs.

[0070] Please see Figure 7 In this embodiment, after depositing the hard mask material, a dry etching process can be performed on the intermediate substrate until the bottom surface of the trench with the largest opening is exposed. Specifically, since the same dry etching process has different etching effects on trenches with different opening sizes, in the second trench with a smaller opening, the hard mask material covering the bottom surface of the trench is difficult to remove completely due to the sidewall effect. However, in the first trench with the largest opening, the reaction between the etching gas and the hard mask material is more thorough, and all the hard mask material covering the bottom surface of the trench can be removed. Furthermore, since the oxide isolation layer 150 has a relatively small thickness along the thickness direction, it is easily removed together with the hard mask material during the dry etching process. Therefore, the execution time of the dry etching process can be controlled, and the moment when the bottom surface of the first trench with the largest opening is exposed can be used as the etching stop point, that is, the etching stops when the bottom surface of the first trench is exposed. After etching stops, the thickness of the hard mask material remaining in the trench along the thickness direction is negatively correlated with the size of the trench opening. That is, the smaller the opening of the trench, the greater the thickness of the hard mask material remaining in the trench along the thickness direction.

[0071] In this embodiment, after etching stops, in at least two trenches, the bottom surface of the first trench is exposed, the bottom surface of the second trench is sequentially covered with an oxide isolation layer 150 and a hard mask material, and the sides of all trenches are sequentially covered with an oxide isolation layer 150 and a hard mask material, thereby forming at least two isolation trenches 310 to obtain a semiconductor substrate 300. The at least two isolation trenches 310 include a first isolation trench 311 with the largest opening and a second isolation trench 312 with an opening smaller than that of the first isolation trench 311.

[0072] S130: A field plate structure is formed within each isolation trench.

[0073] To enhance the field plate structure's control over the electric field distribution in the drift region, a field plate structure can be formed within the isolation trench according to its shape, thereby shortening the distance between the field plate structure and the corner of the isolation structure.

[0074] Please see Figure 8 In this embodiment, the step of forming a field plate structure in each isolation trench may include sub-steps S131, S132 and S133.

[0075] S131: Perform a local oxidation process on the bottom surface of the first isolation trench to form a first bottom oxygen section on the bottom surface of the first isolation trench.

[0076] Please see Figure 9 Since the first isolation trench 311 is closest to the drain-doped region after its formation, the electric field distribution adjustment capability of the field plate structure formed within the first isolation trench 311 is most critical in order to smooth the electric field distribution within the drift region. Therefore, to smooth the sharp corners of the first isolation trench 311, researchers considered using a field oxide layer instead of the corners directly formed by dry etching to mitigate the impact of hot carrier injection on device performance.

[0077] To increase the thickness of the field oxygen layer formed in the first isolation trench 311 along the thickness direction, in this embodiment, the exposed bottom surface of the first isolation trench 311 can be locally oxidized to form a first bottom field oxygen portion 321. For example, local oxidation can be performed using a thermal oxidation process, causing the exposed bottom surface of the first isolation trench 311 to react with oxygen or water vapor to form the first bottom field oxygen portion 321.

[0078] In this embodiment, the thickness of the first bottom oxygen layer 321 along the thickness direction can be controlled by controlling the local oxidation process conditions. Specifically, the growth rate of the first bottom oxygen layer 321 can be controlled by controlling parameters such as the oxidation temperature, oxidation pressure, and oxidation atmosphere type of the local oxidation. The higher the oxidation temperature and the greater the oxidation pressure, the faster the oxidation reaction rate, that is, the faster the growth rate of the first bottom oxygen layer 321. Alternatively, using a steam oxidation atmosphere instead of a dry oxygen oxidation atmosphere can also accelerate the growth rate of the first bottom oxygen layer 321. In addition, the first bottom oxygen layer 321 can also be directly controlled by controlling the local oxidation time parameter. The longer the time, the greater the thickness of the formed first bottom oxygen layer 321 along the thickness direction.

[0079] S132: Remove hard mask material from the semiconductor substrate.

[0080] Please see Figure 10 To reduce the residue of hard mask material and to minimize damage to the formed structure, especially the oxide isolation layer 150, during the removal of hard mask material, a wet solution method can be used to remove the hard mask material, which has a higher selectivity for the hard mask material and a lower selectivity for the materials of the oxide isolation layer 150 and the buffer layer 120.

[0081] In this embodiment, the step of removing the hard mask material from the semiconductor substrate may include: performing wet cleaning (WET) on the semiconductor substrate to remove the hard mask material. The wet cleaning solution may be at least one of phosphoric acid (H3PO4), a mixed solution of phosphoric acid and acetic acid (CH3COOH), or a mixed solution of phosphoric acid and nitric acid (HNO3). For example, the wet cleaning solution may be phosphoric acid at a temperature in the range of 150°C to 180°C.

[0082] S133: A conductive layer is formed on the side of the buffer layer away from the substrate, the side of the first bottom field oxygen layer away from the substrate, and the side of the oxide isolation layer away from the substrate, to obtain a field plate structure.

[0083] Please refer to the following: Figure 10 and Figure 11After removing the hard mask material, a first bottom field oxide portion 321 is formed on the bottom surface of the first isolation trench, and the sides are covered by an oxide isolation layer 150. Both the bottom and sides of the second isolation trench are covered by the oxide isolation layer 150. Thus, a conductive layer 330 can be deposited on the side of the buffer layer 120 away from the substrate 110, the side of the first bottom field oxide portion 321 in the first isolation trench away from the substrate 110, and the side of the oxide isolation layer 150 in the second isolation trench away from the substrate 110. This allows for the formation of a first field plate structure matching the shape of the first isolation trench in the first isolation trench, and a second field plate structure matching the shape of the second isolation trench in the second isolation trench. Specifically, the first field plate structure may include a first field oxide layer 320 and a partially formed conductive layer 330 within the first isolation trench. The second field plate structure may include a second field oxide layer 340 and a partially formed conductive layer 330 within the second isolation trench.

[0084] In this embodiment, the first field oxygen layer 320 includes a first bottom field oxygen portion 321 and a first side field oxygen portion 322 formed by an oxide isolation layer 150 covering the side surface of the first isolation trench. The second field oxygen layer 340 includes a second bottom field oxygen portion 341 formed by an oxide isolation layer 150 covering the bottom surface of the second isolation trench. Figure 11 (shown by the dashed circle in the middle) and a second side field oxygen portion 342 consisting of an oxide isolation layer 150 covering the side of the second isolation trench. Therefore, the thickness of the first bottom field oxygen portion 321 in the thickness direction is greater than the thickness of the second bottom field oxygen portion 341 in the thickness direction, thus realizing "gradient field oxygen".

[0085] In this embodiment, the conductive layer 330 can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition. Specifically, the material of the conductive layer 330 can be polycrystalline silicon, or metals such as tungsten (W) or copper (Cu).

[0086] To ensure that the shape of the field plate structure matches the shape of the isolation trench, the thickness of the field oxide layer along the thickness direction of the field plate structure needs to be controlled to reduce deformation of the field plate structure. In this embodiment, the extension direction of the isolation trench is taken as the depth direction, and the ratio of the thickness of the bottom field oxide layer along the thickness direction to the depth of the isolation trench can fall within the range of 1:40 to 1:7.

[0087] Regarding the first isolation trench, since its bottom surface is exposed, the depth of the first isolation trench along the depth direction is the same as that of the first trench along the depth direction. The first bottom field oxygen portion 321 is formed through a local oxidation process, and the first side field oxygen portion 322 is composed of an oxide isolation layer 150. Therefore, the thickness of the first bottom field oxygen portion 321 along the thickness direction is greater than the thickness of the first side field oxygen portion 322 along the thickness direction. The ratio of the thickness of the first bottom field oxygen portion 321 along the thickness direction to the depth of the first isolation trench along the depth direction can be controlled to be close to the larger end value of the aforementioned ratio range. Taking a depth of 4000 Å for example, the thickness of the first bottom field oxygen portion 321 along the thickness direction can fall within the range of 450 Å to 550 Å. For example, the thickness of the first bottom field oxygen portion 321 along the thickness direction can be 450 Å, 500 Å, or 550 Å.

[0088] Regarding the second isolation trench, since its bottom surface is covered by the oxide isolation layer 150 and the remaining hard mask material, but both the oxide isolation layer 150 and the remaining hard mask material have relatively small thicknesses along the thickness direction, the depth of the second isolation trench along the depth direction is slightly less than the depth of the second isolation trench itself. The second bottom field oxygen portion 341 and the second side field oxygen portion 342 are both composed of the oxide isolation layer 150, and their thicknesses along the thickness direction are essentially the same. Therefore, the ratio of the thickness of the second bottom field oxygen portion 341 along the thickness direction to the depth of the second isolation trench 312 along the depth direction can be controlled to be close to the smaller end value of the aforementioned ratio range.

[0089] To reduce deformation of the field plate structure, in addition to controlling the thickness of the field oxide layer along the thickness direction, it is also necessary to control the thickness of the conductive layer 330 along the thickness direction. In this embodiment, the ratio of the thickness of the conductive layer 330 along the thickness direction to the depth of the isolation trench can fall within the range of 1:9 to 1:7. Since the conductive layers 330 in different isolation trenches are formed in the same process step, the thickness of the conductive layer 330 along the thickness direction in different isolation trenches is basically the same. Taking a depth of 4000 Å along the depth direction of the isolation trench as an example, the thickness of the conductive layer 330 along the thickness direction can fall within the range of 450 Å to 550 Å. For example, the thickness of the conductive layer 330 along the thickness direction can be 450 Å, 500 Å, or 550 Å.

[0090] S150: In each isolation trench, an isolation structure is formed on the side of the conductive layer away from the semiconductor substrate.

[0091] To reduce the interference of subsequent fabrication processes on the electric field distribution adjustment capability of the field plate structure, and to achieve electrical isolation between the field plate structure and subsequent metal interconnect layers and other structures, as well as to achieve the planarization of the overall surface of the LDMOS structure and improve the production yield of LDMOS devices, after forming a field plate structure in each isolation trench, an isolation structure to fill the remaining space of the isolation trench can be formed on the side of the conductive layer of the field plate structure away from the semiconductor substrate.

[0092] Please see Figure 12 In this embodiment, the step of forming an isolation structure on the side of the conductive layer away from the semiconductor substrate within each isolation trench may include sub-steps S151 and S152.

[0093] S151: In each isolation trench, an isolation material is deposited on the side of the conductive layer away from the semiconductor substrate to form an isolation material layer.

[0094] Please see Figure 13 To improve the isolation effect between different components, the density of the isolation structure material is required to be high. Therefore, in this embodiment, a high-density plasma (HDP) process can be used to deposit isolation material in each isolation trench to form an isolation material layer 350. Specifically, to ensure that the isolation structure can completely fill the remaining space of the isolation trench, the distance between the surface of the isolation material layer 350 away from the substrate 110 and the substrate 110 is greater than the distance between the conductive layer 330 away from the substrate 110 and the substrate 110.

[0095] S152: The insulating material layer is ground with the side of the conductive layer away from the buffer layer as the grinding endpoint to obtain the insulating structure.

[0096] Please see Figure 14 To improve wafer surface flatness and increase the production yield of subsequent fabrication processes, in this embodiment, chemical mechanical polishing (CMP) can be used to polish the isolation material layer. The conductive layer 330 is used as the polishing stop layer. Polishing is stopped when the surface of the conductive layer 330 away from the buffer layer 120 is exposed, resulting in the isolation structure 351 formed in each isolation trench.

[0097] Please see Figure 15After filling the isolation trench using the field plate structure and isolation structure 351, to reduce the risk of short circuits inside the device, a dry etching process can be used to remove the exposed conductive layer 330 on the semiconductor substrate surface. To minimize damage to the isolation structure 351 and the buffer layer 120 covered by the conductive layer 330 during the removal process, a gas with high material selectivity for the conductive layer 330 and low material selectivity for the isolation layer can be used for dry etching. Thus, after all the exposed conductive layer 330 is removed, the distance between the surface of the isolation structure 351 away from the substrate 110 and the substrate 110 is greater than the distance between the surface of the buffer layer 120 away from the substrate 110 and the substrate 110.

[0098] S170: Ion implantation is performed on the semiconductor substrate to obtain an LDMOS structure.

[0099] To improve the control over the distribution of doped regions in the LDMOS structure 400, and to enhance the electric field distribution adjustment capability of the field plate structure, after removing the conductive layer 330 covering the buffer layer 120, the drift region and doped well region can be defined in the substrate 110 by ion implantation to obtain the LDMOS structure 400.

[0100] Please see Figure 16 In this embodiment, the step of performing ion implantation on a semiconductor substrate to obtain an LDMOS structure may include: implanting ions into the semiconductor substrate to obtain a substrate with a drift region 360 and a doped well region 370 formed inside, such that at least two isolation trenches are located within the drift region 360, and the opening size of the isolation trenches is positively correlated with the distance between the isolation trenches and the doped well region 370.

[0101] In this embodiment, the function of the drift region 360 is the same as that of the drift region 360 in the LDMOS device provided in the related art, and will not be repeated here. Specifically, the drift region 360 can be formed on one side of the isolation trench in the substrate 110, such that at least two isolation trenches are located within the drift region 360.

[0102] In this embodiment, the doped well region 370 can be used to form the body region of the LDMOS device. Specifically, the doped well region 370 can provide a basis for the subsequent formation of the source doped region and the body contact doped region. The doped well region 370 can be formed on the side of the substrate 110 away from the isolation trench.

[0103] In this embodiment, the doping type of the doped well region 370 is opposite to that of the drift region 360. For example, the doped well region 370 can be P-type doped, and the drift region 360 can be N-type doped. The doping concentration of the doped well region 370 is greater than that of the drift region 360.

[0104] In this embodiment, the buffer layer 120 can be used to protect the substrate 110 during ion implantation and reduce lattice damage to the substrate 110.

[0105] Since the drain will be formed in the drift region 360 during the subsequent fabrication process of the LDMOS device, in order to reduce the risk of breakdown caused by excessive local electric field strength in the LDMOS device, improve the device's withstand voltage capability, and improve the performance degradation caused by the hot carrier injection effect, in this embodiment, after the formation of the doped well region 370 and the drift region 360, the opening size of the isolation trench is positively correlated with the distance between the isolation trench and the doped well region 370. That is, the farther the distance between the isolation trench and the doped well region 370, the larger the opening of the isolation trench.

[0106] Please refer to the following: Figures 17 to 19 After obtaining the LDMOS structure, the LDMOS device can be fabricated by sequentially performing the following process steps.

[0107] First, the buffer layer 120 on the surface of the substrate 110 is etched away.

[0108] Secondly, an oxidation process or a deposition process is used to form a gate oxide material layer 410 on the surface of the substrate 110.

[0109] Subsequently, part of the gate oxide material layer 410 is etched away to obtain the gate oxide layer 421.

[0110] Next, a gate 422 is formed on the side of the gate oxide layer 421 away from the substrate 110, and a gate sidewall 423 is formed on the side of the gate 422 to obtain a gate structure 420. Specifically, the gate structure 420 may include a gate oxide layer 421, a gate 422, and a gate sidewall 423.

[0111] Finally, ion implantation is performed on the LDMOS structure to form a drain doped region 430 within the drift region 360, and a source doped region 440 and a body contact doped region 450 within the doped well region 370, thus obtaining the LDMOS device. Specifically, the doping concentration of the drain doped region 430 is greater than that of the drift region 360. The doping concentrations of both the source doped region 440 and the body contact doped region 450 are greater than those of the doped well region 370. The doping type of the drain doped region 430 is the same as that of the source doped region 440, but different from that of the body contact doped region 450.

[0112] During the operation of the aforementioned LDMOS device, the field plate structures formed in different isolation trenches can be connected to different potentials to suppress the concentration of the electric field on the device surface, improve the uniformity of the electric field distribution on the device surface, thereby improving the electric field distribution in the drift region 360 and enhancing the device's withstand voltage capability.

[0113] Please continue reading. Figure 16 Another embodiment of this application provides an LDMOS structure 400, which may include a substrate, at least two field plate structures, and at least two isolation structures 351.

[0114] In this embodiment, drift regions 360 and doped well regions 370 spaced apart can be formed within the substrate. The drift regions 360 can be used to withstand voltage to improve the breakdown voltage capability of the LDMOS device, while the doped well regions 370 can be used to form the body region of the LDMOS device. Specifically, at least two spaced isolation trenches are formed within the drift regions 360.

[0115] In this embodiment, the field plate structure can be used to adjust the electric field distribution of the drift region 360. Specifically, the field plate structure is formed in an isolation trench, and one field plate structure can be formed in each isolation trench. The field plate structure may include a field oxide layer formed on the surface of the isolation trench and a conductive layer 330 formed on the side of the field oxide layer away from the substrate. The field oxide layer may include a bottom field oxide portion formed on the bottom surface of the isolation trench and a side field oxide portion formed on the side surface of the isolation trench.

[0116] In this embodiment, the isolation structure 351 can be used to achieve electrical isolation between different components. Specifically, the isolation structure 351 is formed on the side of the conductive layer 330 away from the substrate within the isolation trench, and one isolation structure 351 can be formed in each isolation trench.

[0117] To enhance the field distribution adjustment capability of the field plate structure, in this embodiment, the isolation trench has a bottom surface and a side surface. The opening size of the isolation trench is positively correlated with the distance between the isolation trench and the doped well region 370; that is, the greater the distance between the isolation trench and the doped well region 370, the larger the opening of the isolation trench. Correspondingly, taking the growth direction of the field oxide layer as the thickness direction, the thickness of the bottom field oxide portion along the thickness direction is positively correlated with the opening size of the isolation trench; that is, the larger the opening of the isolation trench where the field plate structure is located, the greater the thickness of the bottom field oxide portion along the thickness direction.

[0118] To ensure the shape of the field plate structure matches the shape of the isolation trench and further enhance the field plate structure's ability to adjust the electric field distribution, in this embodiment, the extension direction of the isolation trench is taken as the depth direction, and the ratio of the thickness of the bottom field oxygen portion along the thickness direction to the depth of the isolation trench along the depth direction falls within the range of 1:40 to 1:7. Furthermore, the ratio of the thickness of the conductive layer 330 along the thickness direction to the depth of the isolation trench along the depth direction falls within the range of 1:9 to 1:7.

[0119] For other technical effects of the LDMOS structure 400 described in the above embodiments, please refer to other embodiments of this application for comparison and explanation, and they will not be repeated here.

[0120] In the LDMOS structure and manufacturing method of the LDMOS structure provided in the embodiments of this application, by forming mutually spaced drift regions and doped well regions in the substrate, wherein at least two spaced isolation trenches are formed in the drift regions, and at least two field plate structures are formed in the isolation trenches, the field plate structure includes a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the substrate, and then at least two isolation structures are formed in the isolation trenches, such that the isolation structures are located on the side of the conductive layer away from the substrate, the unexpected effects achieved include: on the one hand, the field plate structure composed of the field oxide layer and the conductive layer and the isolation The close proximity of the trench corners allows for the adjustment of the electric field distribution near the corners using the field plate structure. This smooths the internal electric field of the LDMOS device, reduces the risk of localized electric field breakdown, and improves the breakdown voltage capability of the LDMOS device. On the other hand, the isolation structure distributed in multiple spaced isolation trenches increases the effective width of the drift region and optimizes the conductive path of the drift region, thereby reducing the on-resistance of the LDMOS device. This overcomes the limitations between breakdown voltage and on-resistance in existing LDMOS devices and improves the overall performance of the LDMOS device.

[0121] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0122] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0123] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0124] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0125] In the several embodiments provided in this application, it should be understood that the disclosed LDMOS structure can be implemented in other ways. For example, the embodiments of the LDMOS structure described above are merely illustrative.

[0126] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An LDMOS structure, characterized in that, The LDMOS structure includes: A substrate; wherein doped well regions and drift regions are formed therein; wherein at least two spaced isolation trenches are formed in the drift regions; At least two field plate structures are formed within the isolation trench; the field plate structure includes a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the substrate; At least two isolation structures are formed within the isolation trench; the isolation structures are located on the side of the conductive layer away from the substrate; At least two of the isolation trenches are prepared in the following manner: A linear oxidation process is performed on a transition substrate to form an oxide isolation layer covering the bottom and sides of trenches in the transition substrate. The transition substrate includes a substrate, a buffer layer formed on the surface of the substrate, and a hard mask material layer formed on the side of the buffer layer away from the substrate. At least two spaced trenches are formed in the substrate. The opening size of the trenches gradually increases along the arrangement direction of the trenches. The trenches have a bottom surface and a side surface. A hard mask material is deposited on the side of the hard mask material layer away from the substrate and on the side of the oxide isolation layer away from the substrate to obtain an intermediate substrate; A dry etching process is performed on the intermediate substrate until the bottom surface of the trench with the largest opening is exposed, forming at least two isolation trenches.

2. The LDMOS structure according to claim 1, characterized in that, The opening size of the isolation trench is positively correlated with the distance between the isolation trench and the doped well region.

3. The LDMOS structure according to claim 1 or 2, characterized in that, The isolation trench has a bottom surface and a side surface; the field oxygen layer includes a bottom field oxygen portion formed on the bottom surface of the isolation trench and a side field oxygen portion formed on the side surface of the isolation trench; with the growth direction of the field oxygen layer as the thickness direction, the thickness of the bottom field oxygen portion along the thickness direction is positively correlated with the opening size of the isolation trench.

4. The LDMOS structure according to claim 3, characterized in that, With the extension direction of the isolation trench as the depth direction, the ratio of the thickness of the bottom oxygen portion along the thickness direction to the depth of the isolation trench along the depth direction falls within the range of 1:40 to 1:7; the ratio of the thickness of the conductive layer along the thickness direction to the depth of the isolation trench along the depth direction falls within the range of 1:9 to 1:

7.

5. A method for manufacturing an LDMOS structure, characterized in that, The method for manufacturing the LDMOS structure includes: A semiconductor substrate is provided; at least two spaced-apart isolation trenches are formed within the semiconductor substrate; A field plate structure is formed within each of the isolation trenches; the field plate structure includes a field oxide layer formed on the surface of the isolation trench and a conductive layer formed on the side of the field oxide layer away from the semiconductor substrate; Within each of the isolation trenches, an isolation structure is formed on the side of the conductive layer away from the semiconductor substrate; Ion implantation is performed on the semiconductor substrate to obtain the LDMOS structure; the LDMOS structure includes a substrate with mutually spaced drift regions and doped well regions formed inside; The step of providing the semiconductor substrate includes: A transition substrate is provided; the transition substrate includes a substrate, a buffer layer formed on the surface of the substrate, and a hard mask material layer formed on the side of the buffer layer away from the substrate; wherein at least two spaced trenches are formed in the substrate; the opening size of the trenches gradually increases along the arrangement direction of the trenches; the trenches have a bottom surface and a side surface; A linear oxidation process is performed to form an oxide isolation layer covering the bottom and sides of the trench; A hard mask material is deposited on the side of the hard mask material layer away from the substrate and on the side of the oxide isolation layer away from the substrate to obtain an intermediate substrate; A dry etching process is performed on the intermediate substrate until the bottom surface of the trench with the largest opening is exposed, forming the at least two isolation trenches to obtain the semiconductor substrate.

6. The method for manufacturing an LDMOS structure according to claim 5, characterized in that, The at least two isolation trenches include a first isolation trench with the largest opening and a second isolation trench with an opening smaller than that of the first isolation trench; The step of forming a field plate structure within each of the said isolation trenches includes: A local oxidation process is performed on the bottom surface of the first isolation trench to form a first bottom oxygen part. Remove the hard mask material from the semiconductor substrate; The conductive layer is formed on the side of the buffer layer away from the substrate, the side of the first bottom field oxygen portion away from the substrate, and the side of the oxide isolation layer away from the substrate to obtain the field plate structure; in the field plate structure formed in the first isolation trench, the field oxygen layer includes the first bottom field oxygen portion and a first side field oxygen portion composed of an oxide isolation layer covering the side of the first isolation trench; in the field plate structure formed in the second isolation trench, the field oxygen layer includes a second bottom field oxygen portion composed of an oxide isolation layer covering the bottom surface of the second isolation trench and a second side field oxygen portion composed of an oxide isolation layer covering the side of the second isolation trench.

7. The method for manufacturing an LDMOS structure according to claim 6, characterized in that, The step of removing the hard mask material from the semiconductor substrate includes: The semiconductor substrate is subjected to wet cleaning to remove the hard mask material in the semiconductor substrate; wherein the wet cleaning solution is at least one of phosphoric acid, a mixed solution of phosphoric acid and acetic acid, and a mixed solution of phosphoric acid and nitric acid.

8. The method for manufacturing an LDMOS structure according to claim 5, characterized in that, The step of forming an isolation structure on the side of the conductive layer away from the semiconductor substrate within each of the isolation trenches includes: Within each of the isolation trenches, an isolation material is deposited on the side of the conductive layer away from the semiconductor substrate to form an isolation material layer; The insulating material layer is ground with the surface of the conductive layer away from the buffer layer as the grinding endpoint to obtain the insulating structure.

9. The method for manufacturing an LDMOS structure according to claim 5, characterized in that, The step of performing ion implantation on the semiconductor substrate to obtain the LDMOS structure includes: Ions are implanted into the semiconductor substrate to obtain a substrate in which the drift region and the doped well region are formed, such that the at least two isolation trenches are located within the drift region, and the opening size of the isolation trenches is positively correlated with the distance between the isolation trenches and the doped well regions.

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