High-density dreamos device and method of manufacturing the same
By forming multiple channel doped regions and combining them with well regions in LDMOS devices, the problems of hot carrier injection effect and processing complexity are solved, achieving low resistance and high current density in high-density DreaMOS devices and improving device consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU WATECH ELECTRONICS CO LTD
- Filing Date
- 2020-12-18
- Publication Date
- 2026-06-26
AI Technical Summary
Existing LDMOS devices are prone to hot carrier injection under high voltage and high current conditions, resulting in high on-resistance, low current density, complex fabrication process, and poor device consistency.
Multiple channel doped regions are formed in the epitaxial layer by ion implantation, distributed below and to the side of the gate, which simplifies the fabrication process, reduces thermal processes, and forms a three-dimensional structure with the well region, thus suppressing the hot carrier injection effect.
It reduces on-resistance by 85%, increases current density to 4.5 times that of traditional LDMOS devices, and improves device consistency and performance.
Smart Images
Figure CN114649414B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a DreaMOS device, in particular to a high-density DreaMOS device and a manufacturing method thereof, and belongs to the technical field of semiconductors. BACKGROUND
[0002] Figure 1 The LDMOS device provided by the present application has the same conductivity type for the source region, the drain extension region and the drain region, the conductivity type of the channel doping region under the gate is the same as that of the body region but opposite to that of the source region, and the drain extension region and the drain extension region increase the breakdown voltage of the LDMOS device, thereby increasing the output power of the device, as shown in FIG. 1. Figure 1 The well region 17 in the existing LDMOS device is formed by ion implantation and long-time high-temperature annealing treatment, so as to form the channel of the device by laterally diffusing the body region and making it contact with the drain extension region. However, the long-time high-temperature annealing treatment increases the thermal process of the device, reduces the consistency of the device, and causes the junction depth of the device to be deep, thereby increasing the capacitance of the device.
[0003] The existing LDMOS device is prone to hot carrier injection effect in a high-voltage and large-current scenario, the carriers enter the gate oxide region, aggravate the changes of the parameters such as on-resistance, saturation current, threshold voltage and breakdown voltage of the device, and reduce the service life of the device. Moreover, with the increase of the doping concentration of the drain extension region, the hot carrier effect is aggravated, and in order to improve the efficiency of the device, the doping concentration of the drain extension region is desired to be increased by those skilled in the art. The existing LDMOS device is trapped in the hot carrier injection effect, and cannot reduce the on-resistance to improve the performance of the device. Meanwhile, the device structure of the existing LDMOS device is completely consistent along the vertical direction of the paper, as shown in the top view device structure shown in FIG. 2, the channel of the device only exists directly below the gate, which causes the effective channel area of the device to be small, thereby causing the current density of the device to be small. Figure 1 Figure 2 The main purpose of the present application is to provide a high-density DreaMOS device and a manufacturing method thereof, so as to overcome the deficiencies in the prior art. SUMMARY
[0004] The main purpose of the present application is to provide a high-density DreaMOS device and a manufacturing method thereof, so as to overcome the deficiencies in the prior art.
[0005] To achieve the above-mentioned purposes, the technical solutions adopted by the present application include:
[0006] The embodiment of the present application provides a high-density DreaMOS device, which comprises a semiconductor structure layer and a gate oxide layer and a gate cooperating with the semiconductor structure layer, the semiconductor structure layer comprises an epitaxial layer and a source region, a well region, a well region contact region, a drain region extension region and a drain region formed in the epitaxial layer, and a channel doping region is further formed in the epitaxial layer, the channel doping region is at least distributed below the gate and on the side of the gate, and the channel doping region is connected with the source region, the drain region extension region and the well region respectively.
[0007] The embodiment of the present application further provides a manufacturing method of the high-density DreaMOS device, which comprises the following steps:
[0008] The epitaxial layer is provided, and the well region is processed and formed in the epitaxial layer by using an ion implantation method, the ion implantation energy of the well region is 50Kev-1500Kev, and the concentration is 5E12cm^-2-1E14cm^-2;
[0009] The well region contact region, the drain region extension region and the drain region are processed and formed in the epitaxial layer by using the ion implantation method;
[0010] The epitaxial layer is implanted multiple times by using the ion implantation method to form multiple channel doping regions, and the multiple channel doping regions correspond to the below area and the side area of the gate respectively, wherein the ion implantation energy of the channel doping region corresponding to the below area of the gate is 15Kev-250Kev, the concentration is 1E10cm^-2-1E14cm^-2, the ion implantation energy of the channel doping region corresponding to the side area of the gate is 15Kev-250Kev, and the concentration is 1E10cm^-2-1E14cm^-2;
[0011] The gate oxide layer is formed on the epitaxial layer, and the gate is formed on the gate oxide layer.
[0012] Compared with the prior art, the present application has the following advantages:
[0013] The three-dimensional high-density DreaMOS device provided by the embodiment of the present application forms the well region by using the ion implantation method, reduces the thermal process of processing, simplifies the manufacturing process and improves the device consistency.
[0014] The three-dimensional high-density DreaMOS device provided by the embodiment of the present application performs channel doping before manufacturing and forming the gate, the formed channel doping region is combined with the well region to inhibit the hot carrier injection effect, under the same hot carrier injection life condition, the on-resistance of the high-density DreaMOS device provided by the embodiment of the present application is reduced by 85%, and the current density is 4.5 times that of the traditional LDMOS device. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 This is a schematic diagram of a cross-section formed along direction A of a conventional power LDMOS device provided by the inventor;
[0016] Figure 2 A top view of a conventional power LDMOS device provided by the inventor;
[0017] Figure 3 This is a top view of a high-density DreaMOS device provided in a typical embodiment of the present invention;
[0018] Figure 4 This is a schematic diagram of a cross-section formed along the A direction of a high-density Dreamos device, provided in a typical embodiment of the present invention.
[0019] Figure 5 This is a schematic diagram of a cross-section formed along the B direction of a high-density Dreamos device, provided in a typical embodiment of the present invention.
[0020] Explanation of reference numerals in the attached figures: 11-gate region, 12-gate oxide layer, 13-source region, 14-drain extension region, 15-drain region, 16-well contact region, 17-well region, 18-epitaxy layer, 19-substrate, 21-gate region, 22-gate oxide layer, 23-source region, 24-drain extension region, 25-drain region, 26-well contact region, 27-well region, 28-epitaxy layer, 29-substrate, 210-channel doped region. Detailed Implementation
[0021] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.
[0022] LDMOS: Lateral Double diffusion Metal Oxide Semiconductor.
[0023] DreaMOS: Drain Extended Advance Metal Oxide Semiconductor.
[0024] To address the shortcomings of traditional LDMOS device fabrication processes, such as numerous thermal processes, poor device consistency, difficulty in controlling junction depth and large capacitance, limitations due to hot carrier injection effects, inability to reduce on-resistance, and low device efficiency and current density, this invention provides a three-dimensional high-density DreaMOS device. This reduces thermal processes, simplifies the fabrication process, improves device consistency, and, more importantly, suppresses the hot carrier injection effect, further reducing device resistance and improving device performance. Simultaneously, to increase the device's current density, this invention also forms a side channel in the region corresponding to the gate side of the three-dimensional high-density DreaMOS device, increasing the effective channel area and further enhancing the current density. Simulation tests show that compared to... Figure 1 Compared to the conventional LDMOS device shown, the three-dimensional high-density DreaMOS device provided in this embodiment of the invention has an 85% lower on-resistance and a current density that is 4.5 times that of the conventional LDMOS device.
[0025] This invention provides a high-density DreamoShock device, comprising a semiconductor structure layer and a gate oxide layer and a gate that cooperate with the semiconductor structure layer. The semiconductor structure layer includes an epitaxial layer and a source region, a well region, a well contact region, a drain extension region, and a drain region formed within the epitaxial layer. A channel doped region is also formed within the epitaxial layer. The channel doped region is distributed at least in the region below and on the side of the gate. The channel doped region is also connected to the source region, the drain extension region, and the well region, respectively.
[0026] Furthermore, the channel doped region is distributed in the region below the gate and in the regions on both sides of the gate.
[0027] Furthermore, the high-density DreamoMOS device includes multiple channel doped regions, which are respectively distributed in the region below the gate and the regions on both sides, wherein the multiple channel doped regions are connected sequentially.
[0028] Furthermore, the doping concentration of the channel doped region distributed in the region below the gate is 1E10cm^-2 to 1E14cm^-2, and the thickness is 0.2μm to 4μm. The doping concentration of the channel doped region distributed in the region on the side of the gate is 1E10cm^-2 to 1E14cm^-2, and the thickness is 0.2μm to 4μm.
[0029] In some more specific embodiments, the epitaxial layer is provided with a first channel doped region, a second channel doped region, and a third channel doped region, which are connected in sequence. The first channel doped region and the third channel doped region are respectively distributed on both sides of the gate, and the second channel doped region is distributed below the gate. The doping concentrations of the first channel doped region, the second channel doped region, and the third channel doped region are 1E10cm^-2~1E14cm^-2, 1E10cm^-2~1E14cm^-2, and 1E10cm^-2~1E14cm^-2, respectively, and the thicknesses are 0.2μm~4μm, 0.2μm~4μm, and 0.2μm~4μm, respectively.
[0030] In some more specific implementations, the high-density Dreamos device includes multiple gates, and the channel doped regions are distributed in the lower and side regions of each gate, and the multiple channel doped regions corresponding to the multiple gates are connected in sequence.
[0031] Furthermore, the plurality of gates are sequentially spaced apart between the source region and the drain region extension region along a specified direction, wherein the gate oxide layer is disposed between the gate and the channel doped region.
[0032] Furthermore, the gate is distributed within a containment trench formed by the channel doped region and the source and drain extension regions.
[0033] Furthermore, the top surface of the gate is flush with the top surfaces of the source region and the drain region extension region.
[0034] Furthermore, the gate has a length of 0.045 μm to 0.8 μm and a thickness of 0.1 μm to 0.4 μm.
[0035] Furthermore, the channel doped region, source region, drain region, and drain region extension region have the same conductivity type, and the well region, well region extension region, and epitaxial layer have the same conductivity type.
[0036] Furthermore, when there is a first voltage difference between the gate voltage and the threshold voltage, the effective channel and current path of the device are both located between the channel doped region and the well region. When the gate voltage is greater than the threshold voltage and there is a second voltage difference between the gate voltage and the threshold voltage, the effective channel of the device is located on the surface of the semiconductor structure layer.
[0037] This invention also provides a method for fabricating the high-density Dreamos device, comprising:
[0038] An epitaxial layer is provided, and a well region is formed in the epitaxial layer by ion implantation. The ion implantation energy of the well region is 50 KeV to 1500 KeV, and the concentration is 5E12cm^-2 to 1E14cm^-2.
[0039] The well region contact region, the drain region extension region, and the drain region are formed in the epitaxial layer by ion implantation.
[0040] Multiple channel doped regions are formed by multiple implantation of the epitaxial layer using ion implantation, and the multiple channel doped regions correspond to the lower region and the side region of the gate, respectively. The ion implantation energy of the channel doped region corresponding to the lower region of the gate is 15Kev to 250Kev, and the concentration is 1E10cm^-2 to 1E14cm^-2. The ion implantation energy of the channel doped region corresponding to the side region of the gate is 15Kev to 250Kev, and the concentration is 1E10cm^-2 to 1E14cm^-2.
[0041] A gate oxide layer is formed on the epitaxial layer, and a gate is formed on the gate oxide layer.
[0042] Furthermore, the fabrication method specifically includes: forming a plurality of gates on the epitaxial layer, and having channel doped regions correspondingly distributed in the lower region and the side regions of each gate.
[0043] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the material, thickness, processing technology and testing methods of each structural layer in the device are known to those skilled in the art.
[0044] Example 1
[0045] Please see Figures 3-5 A high-density DreamoShock device includes a semiconductor structure layer and a gate oxide layer 22 and a gate 21 that cooperate with the semiconductor structure layer. The semiconductor structure layer includes a substrate 29 and an epitaxial layer 28 disposed on the substrate. An active region 23, a well region 27, a well contact region 26, a drain extension region 24, a drain region 25, and a channel doped region 210 are formed in the epitaxial layer 28. The channel doped region 210 is distributed in the region below and the side region of the gate 21. The channel doped region 210 is also connected to the source region 23, the drain extension region 24, and the well region 27, respectively.
[0046] The channel doped region 210, source region 23, drain region 25 and drain extension region 24 have the same conductivity type, and the well region 27, well extension region 26 and epitaxial layer 28 have the same conductivity type.
[0047] For details, please refer toFigure 3 and Figure 5 The channel doped region 210 is distributed in the region below the gate 21 and in the side regions opposite to the two opposite sides of the gate 21. The gate oxide layer 22 is distributed between the gate 21 and the channel doped region 210. It can be understood that the high-density DreaMOS device provided in this embodiment has a channel doped region in the region below the gate 21 and in the two side regions of the gate 21. That is, in the high-density DreaMOS device provided in this embodiment, a channel is formed in the region below the gate 21 and on the two sides. By setting at least two channels, the channel area of the device can be effectively increased.
[0048] Specifically, it can be understood that in this embodiment, each gate may correspond to a channel doped region, which is distributed in the lower region and two side regions of the gate. Alternatively, each gate may correspond to multiple channel doped regions, that is, one channel doped region is distributed in the lower region of the gate, and at least two channel doped regions are respectively distributed in two opposite side regions of the gate, and the multiple channel doped regions are connected sequentially.
[0049] Specifically, the doping concentration of the channel doped region distributed below the gate is 1E10cm^-2 to 1E14cm^-2, and the thickness is 0.2μm to 4μm. The doping concentration of the channel doped region distributed on the side of the gate is 1E10cm^-2 to 1E14cm^-2, and the thickness is 0.2μm to 4μm.
[0050] For details, please refer to the following document again. Figures 3-5 The gate 21 is distributed in a receiving trench formed by the channel doped region 210, the source region 23, and the drain extension region 24, and the top surface of the gate 21 is flush with the top surface of the source region 23 and the drain extension region 24.
[0051] For more specific implementation plans, please refer to Figure 4The high-density DreamoMOS device includes multiple gates 21 and multiple gate oxide layers 22. The multiple gates 21 are sequentially spaced between the source region 23 and the drain region extension 24 along a specified direction. The channel doped regions 210 are distributed in the lower and side regions of each gate 21. That is, each gate 21 has a gate oxide layer 22 around and below it. The channel doped regions 210 are located outside the gate oxide layers 22 on the lower and two sides of each gate 21. All channel doped regions have the same conductivity type. Channels are formed in the regions corresponding to the lower and two sides of each gate 21, thereby providing a channel for charge carriers to move from the source region to the drain region. The multiple channel doped regions corresponding to the multiple gates 21 are also sequentially connected. The length of each gate is 0.045 μm to 0.8 μm and the thickness is 0.1 μm to 0.4 μm.
[0052] Specifically, when the gate voltage is slightly higher than the threshold voltage, the effective channel and carrier path of the high-density DreaMOS device are located inside the semiconductor structure layer, specifically between the channel doped region 210 and the well region 27. The effective channel and carrier path are far from the surface of the semiconductor structure layer, which reduces the probability of hot carrier injection under the gate voltage condition where the hot carrier injection effect is most likely to occur. When the gate voltage is further increased, the effective channel and carrier path of the device are located on the surface of the semiconductor structure layer, just like the traditional LDMOS device, thus ensuring the transconductance and device performance of the device at higher gate voltages.
[0053] Comparative Example 1
[0054] Comparative Example 1 provides a structure of an LDMOS device as follows: Figure 1 and Figure 2 As shown, this LDMOS device along... Figure 1 The device structures are completely identical in the direction perpendicular to the paper plane. Among them, 11 is the gate region of the LDMOS device, 12 is the gate oxide layer, 13 is the source region of the device, 14 is the drain extension region of the device, 15 is the drain region of the device, 16 is the well contact region of the device, 17 is the well region of the device, 18 is the epitaxial layer of the device, and 19 is the substrate of the device.
[0055] Simulation tests were performed on the devices in Example 1 and Comparative Example 1. The simulation results showed that, compared with the LDMOS device in Comparative Example 1, the on-resistance of the three-dimensional high-density Dreamos device in Example 1 was reduced by 85%, and the current density was 4.5 times that of the conventional LDMOS device.
[0056] The present invention provides a three-dimensional high-density Dreamos device with dual channels. When the gate voltage is slightly greater than the threshold voltage, the potential difference between the gate and the channel is less than that of conventional devices. However, after the gate voltage increases, the potential difference between the gate and the channel becomes comparable to that of conventional devices, thereby reducing the probability of hot carrier injection effect in the device and significantly improving the current density of the device.
[0057] Specifically, the present invention provides a three-dimensional high-density Dreamos device in which a well region is formed by ion implantation before the formation of the polysilicon gate, and a channel doped region with the same doping type as the source region is implemented in the channel.
[0058] When the gate voltage is near the threshold voltage, the effective channel of the device is located between the channel doped region and the well region, and mainly below the channel doped region. At this time, the current path (which can also be understood as the carrier path) is located inside the semiconductor structure layer, away from the surface of the semiconductor structure layer, especially in the region where the drain extension region and the well region are most prone to hot carrier injection effect, thereby reducing the probability of the device experiencing hot carrier injection effect. When the gate voltage is greater than the threshold voltage to a certain extent, the effective channel of the device is located on the surface of the semiconductor structure layer. Since the hot carrier injection effect is improved, a higher doping concentration can be used in the drain extension region (the doping concentration range of existing devices is 1E12cm^-2 to 3E12cm^-2, and the doping concentration range of the device of the present invention is 1E12cm^-2 to 8E12cm^-2), thereby reducing the on-resistance of the device and increasing the current density.
[0059] In addition, directly using ion implantation to process the well region reduces the long high-temperature annealing process after ion implantation in traditional LDMOS devices, thereby reducing the thermal process of device processing, improving device consistency, and thus enabling better control of the junction depth of the device.
[0060] The present invention provides a three-dimensional high-density DreamoMOS device, which forms a well region by ion implantation, reducing the thermal process during fabrication, simplifying the fabrication process, and improving device consistency. Furthermore, channel doping is performed before the gate is formed, and the resulting channel doped region combines with the well region to suppress the hot carrier injection effect. Under the same hot carrier injection lifetime conditions, the on-resistance of the high-density DreamoMOS device provided by the present invention is reduced by 85%, and the current density is 4.5 times that of the conventional LDMOS device.
[0061] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A high-density DreamoShock device, comprising a semiconductor structure layer and a gate oxide layer and a gate electrode cooperating with the semiconductor structure layer, wherein the semiconductor structure layer comprises an epitaxial layer and a source region, a well region, a well contact region, a drain extension region, and a drain region formed within the epitaxial layer, characterized in that: The epitaxial layer also contains a channel doped region, which is distributed at least in the region below the gate and on both sides of the gate. The doping concentration of the channel doped region distributed in the region below the gate is 1E10cm^-2 to 1E14cm^-2 and the thickness is 0.2μm to 4μm. The doping concentration of the channel doped region distributed in the region on the side of the gate is 1E10cm^-2 to 1E14cm^-2 and the thickness is 0.2μm to 4μm. The channel doped region is also connected to the source region, the drain region extension region and the well region, respectively. The gate is distributed within a containment trench formed by the channel doped region and the source and drain extension regions. The channel doped region, source region, drain region, and drain extension region have the same conductivity type, and the well region, well extension region, and epitaxial layer have the same conductivity type. When the gate voltage is near the threshold voltage, the effective channel and current path of the device are both located between the channel doped region and the well region. However, when the gate voltage is greater than the threshold voltage, and the gate voltage is greater than the threshold voltage to a certain extent, the effective channel of the device is located on the surface of the semiconductor structure layer.
2. The high-density Dreamos device according to claim 1, characterized in that... It includes multiple channel doped regions, which are respectively distributed in the area below the gate and the areas on both sides, wherein the multiple channel doped regions are connected in sequence.
3. The high-density Dreamos device according to claim 1, characterized in that: The epitaxial layer comprises a first channel doped region, a second channel doped region, and a third channel doped region, which are sequentially connected. The first and third channel doped regions are respectively distributed on both sides of the gate, and the second channel doped region is distributed below the gate. The doping concentrations of the first, second, and third channel doped regions are 1E10cm^-2~1E14cm^-2, 1E10cm^-2~1E14cm^-2, and 1E10cm^-2~1E14cm^-2, respectively, and their thicknesses are 0.2μm~4μm, 0.2μm~4μm, and 0.2μm~4μm, respectively.
4. The high-density Dreamos device according to claim 1, characterized in that... It includes multiple gates, and the channel doped regions are distributed in the lower and side regions of each gate. The multiple channel doped regions corresponding to the multiple gates are also connected in sequence.
5. The high-density Dreamos device according to claim 4, characterized in that: The plurality of gates are sequentially spaced apart between the source region and the drain region extension region along a specified direction, wherein the gate oxide layer is disposed between the gate and the channel doped region.
6. The high-density Dreamos device according to claim 1, characterized in that: The top surface of the gate is flush with the top surfaces of the source region and the drain region extension.
7. The high-density Dreamos device according to claim 5, characterized in that: The gate has a length of 0.045μm to 0.8μm and a thickness of 0.1μm to 0.4μm.
8. A method for fabricating a high-density Dreamos device as described in any one of claims 1-7, characterized in that... include: An epitaxial layer is provided, and a well region is formed in the epitaxial layer by ion implantation. The ion implantation energy is 50Kev~1500Kev, and the concentration is 5E12cm^-2-1E14cm^-2. The well contact region, drain extension region, and drain region are formed in the epitaxial layer by ion implantation. The process parameters of each region are selected according to the device operating voltage.
9. The method for fabricating a high-density Dreamos device according to claim 8, characterized in that: Multiple channel doped regions are formed by multiple implantation of the epitaxial layer using ion implantation, and these multiple channel doped regions correspond to the region below the gate and the regions on both sides of the gate, respectively. The ion implantation energy of the channel doped region corresponding to the region below the gate is 15 KeV~250 KeV, and the concentration is 1E10 cm^-2~1E14 cm^-2. The ion implantation energy of the channel doped region corresponding to the region on the side of the gate is 15 KeV~250 KeV, and the concentration is 1E10 cm^-2~1E14 cm^-2. A gate oxide layer is formed on the epitaxial layer, and a gate is formed on the gate oxide layer.
10. The method for fabricating a high-density Dreamos device according to claim 8, characterized in that: The fabrication method specifically includes: forming a plurality of gates on the epitaxial layer, and distributing channel doped regions in the lower and side regions of each gate.