Trench gate ldmos structure and fabrication method therefor
By enlarging the critical dimensions of the gate trench to form an inverted L-shaped structure, the problems of high etching process difficulty and dependence on lithography machines are solved, thus reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HANGZHOU FULLSEMI SEMICON CO LTD
- Filing Date
- 2025-06-12
- Publication Date
- 2026-06-25
AI Technical Summary
The etching process for trench gate LDMOS structures in existing technologies is difficult and relies on high-precision lithography machines, which increases manufacturing costs.
By expanding the critical dimension of the gate trench from the deep trench region to a portion of the first conductivity type well region adjacent to it, an inverted L-shaped gate trench is formed, increasing the etching process window and the photolithography process window during electrical lead-out.
This reduces the difficulty of etching and the precision requirements of lithography machines, thereby lowering manufacturing costs.
Smart Images
Figure CN2025100633_25062026_PF_FP_ABST
Abstract
Description
Trench Gate LDMOS Structure and Fabrication Method Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a trench gate LDMOS structure and its fabrication method. Background Technology
[0002] Trench LDMOS exhibits significant advantages in power management due to its high integration and current carrying capacity, low on-resistance, fast switching performance, high reliability, low noise, and miniaturization and lightweight design. Figure 1 shows a currently optimized trench LDMOS structure with a T-shaped trench gate, specifically a trench gate structure 20 formed within an insulating deep trench 21. This design not only reduces energy loss and improves efficiency but also enhances device durability and reliability by improving thermal characteristics. Although the manufacturing process is relatively complex, the high efficiency and reliability of trench LDMOS reduce overall system costs, improving economics and application range. It has become a preferred semiconductor device, especially in applications requiring high efficiency and compact design, such as switching power supplies, DC / DC converters, and motor drives.
[0003] With the miniaturization and integration of semiconductor devices, as shown in Figure 2, the optimized Trench LDMOS structure places higher demands on the etching process when forming the smaller CD gate trench 22. In addition, as shown in Figure 3, correspondingly, the smaller CD lead-out electrode holes 23 also place higher demands on the photolithography process when electrically leading out the trench gate structure 20. Furthermore, the smaller CD trench gate structure 20 also places higher demands on the overlay accuracy during the subsequent electrical lead-out of the trench gate structure, making the fabrication of the entire structure highly dependent on high-precision photolithography machines, thus increasing manufacturing costs. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench gate LDMOS structure and its fabrication method, which solves the problems of the existing "T"-shaped trench gate LDMOS structure, which increases the difficulty of etching process, is highly dependent on high-precision lithography machine, and thus increases manufacturing cost.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a trench gate LDMOS structure, the method comprising the following steps:
[0006] A semiconductor substrate is provided, the semiconductor substrate including a first conductivity type well region extending inwardly from the upper surface of the semiconductor substrate;
[0007] A deep trench is formed within the first conductivity type well region, extending inward from the upper surface of the first conductivity type well region;
[0008] Ion implantation is performed on the sidewalls and bottom wall of the deep trench to form a first conductivity type doped layer on the surface of the deep trench;
[0009] The deep trench shall be filled at least completely with insulating material;
[0010] The insulating material in a portion of the deep trench sidewall is etched from top to bottom to a first preset depth, and the first conductivity type well region in a portion of the deep trench sidewall is etched from top to bottom to a second preset depth, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench.
[0011] A gate dielectric layer and a gate conductive layer are sequentially formed in the gate trench to form a gate structure;
[0012] A source doped layer of the second conductivity type and a drain doped layer of the second conductivity type are respectively formed in the first conductivity type well regions on both sides of the deep trench. The source doped layer of the second conductivity type is closer to the gate structure, and the drain doped layer of the second conductivity type is farther away from the gate structure. The first conductivity type is opposite to the second conductivity type.
[0013] An electrode lead-out structure is formed to electrically lead out the gate structure, the source doped layer of the second conductivity type, and the drain doped layer of the second conductivity type, respectively.
[0014] Optionally, the diameter of the upper portion of the gate trench is not less than 0.1 μm, and the second preset depth is not less than...
[0015] Optionally, the process further includes forming an oxygen pad layer on the surface of the deep trench before forming the first conductivity type doped layer.
[0016] Optionally, after filling the deep trench with insulating material, the process further includes a step of planarizing the insulating material, wherein the planarized insulating material has a predetermined thickness above the surface of the semiconductor substrate, and the predetermined thickness of the insulating material serves as a hard mask layer.
[0017] Furthermore, the method for forming the gate trench includes:
[0018] A hard mask layer and a photoresist layer are sequentially formed on the surface of the semiconductor substrate;
[0019] The hard mask layer is patterned using photolithography to form a patterned hard mask layer, which exposes the surface of the insulating material in a portion of the deep trench sidewall and a portion of the first conductive type well region connected to the portion of the deep trench sidewall.
[0020] The corresponding insulating material and the first conductivity type well region are etched using the patterned photoresist layer and the patterned hard mask layer as masks to form the gate trench.
[0021] Furthermore, the method for forming the gate structure includes:
[0022] The gate dielectric layer is formed on the surface of the gate trench using a thermal oxidation process;
[0023] A gate conductive layer that at least fills the gate trench is formed on the gate dielectric layer using a CVD deposition process;
[0024] The gate conductive layer is ground using CMP process, and after grinding, the upper surface of the gate conductive layer is lower than the upper surface of the well region of the first conductivity type.
[0025] Furthermore, after forming the gate structure, the method further includes the step of forming an insulating coating layer covering the gate structure on the surface of the semiconductor substrate.
[0026] Furthermore, the semiconductor substrate further includes a second conductivity type well region extending inward from the upper surface of the semiconductor substrate, wherein the second conductivity type well region is connected to the first conductivity type well region; after forming the insulating coating layer, the step of forming a shallow trench isolation structure in the second conductivity type well region is further included.
[0027] The present invention also provides a trench gate LDMOS structure, the trench gate LDMOS structure comprising:
[0028] A semiconductor substrate, the semiconductor substrate including a first conductivity type well region extending inwardly from the upper surface of the semiconductor substrate;
[0029] A deep trench extending inward from the upper surface of the first conductivity type well region;
[0030] A first conductivity type doped layer is formed on the surface of the deep trench;
[0031] A gate structure consisting of a gate dielectric layer and a gate conductive layer, wherein a portion of the gate structure is formed at a first preset depth in a portion of the deep trench sidewall region, and another portion is formed at a second preset depth in a portion of the first conductivity type well region connected to the portion of the deep trench sidewall region.
[0032] Insulating material, at least filling the deep trenches except for the gate structure;
[0033] A source doped layer and a drain doped layer of a second conductivity type, wherein the source doped layer of the second conductivity type is closer to the gate structure, and the drain doped layer of the second conductivity type is farther from the gate structure, and the first conductivity type is opposite to the second conductivity type;
[0034] An electrode lead-out structure electrically leads out the gate structure, the source doped layer of the second conductivity type, and the drain doped layer of the second conductivity type.
[0035] Optionally, the aperture of the upper portion of the gate structure is not less than 0.1 μm, and the second preset depth is not less than...
[0036] As described above, the trench gate LDMOS structure and its fabrication method of the present invention expand the critical dimension (CD) of the gate trench from the deep trench region to a portion of the first conductivity type well region connected thereto, thereby forming an inverted L-shaped gate trench. This effectively increases the process window for etching to form the gate trench and reduces the etching difficulty. In addition, based on the inverted L-shaped gate trench, the gate structure formed is also inverted L-shaped overall. Therefore, when electrically leading out the gate structure, the increased aperture size of the upper part of the gate structure effectively increases the photolithography process window for forming the lead-out electrode holes on the gate structure, thereby reducing the precision requirements of the photolithography machine and reducing the overlay precision when forming the lead-out electrode holes on the gate structure. Attached Figure Description
[0037] Figure 1 shows a schematic cross-sectional view of an example Trench LDMOS structure.
[0038] Figure 2 shows a schematic cross-sectional view of the gate trench formed during the fabrication process of the Trench LDMOS structure in Figure 1.
[0039] Figure 3 shows a schematic cross-sectional view of the formation of the lead-out electrode hole during the fabrication process of the Trench LDMOS structure in Figure 1.
[0040] Figures 4 to 19 show cross-sectional structural schematic diagrams of each step in the fabrication process of the trench gate LDMOS structure of the present invention.
[0041] Component Labeling Explanation: 10 Semiconductor Substrate; 100 First Conductivity Type Well Region; 101 Second Conductivity Type Well Region; 102 Deep Trench; 103 Oxide Pad Layer; 104 First Conductivity Type Doped Layer; 105 Insulating Material; 106 Hard Mask Layer; 107 Photoresist Layer; 108 Patterned Hard Mask Layer; 11 Gate Structure; 110 Gate Trench; 111 Gate Dielectric Layer; 112 Gate Conductive Layer; 12 Insulating Coating Layer; 13 Shallow Trench Isolation Structure; 14 Second Conductivity Type Source Doped Layer; 15 Second Conductivity Type Drain Doped Layer; 16 Electrode Lead-out Structure; 17 Dielectric Layer; 160 Lead-out Electrode Hole; 20 Trench Gate Structure; 21 Insulating Deep Trench; 22 Gate Trench; 23 Lead-out Electrode Hole. Detailed Implementation
[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0043] Please refer to Figures 4 to 19. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0044] This embodiment provides a method for fabricating a trench gate LDMOS structure, the method comprising the following steps:
[0045] S1, providing a semiconductor substrate, the semiconductor substrate including a first conductivity type well region extending inwardly from the upper surface of the semiconductor substrate;
[0046] S2, a deep trench extending inward from the upper surface of the first conductive type well region is formed in the first conductive type well region.
[0047] S3, Ion implantation is performed on the sidewalls and bottomwalls of the deep trench to form a first conductivity type doped layer on the surface of the deep trench;
[0048] S4, the deep trench is at least completely filled with insulating material;
[0049] S5, etching the insulating material in the partial area of the deep trench sidewall at a first preset depth from top to bottom and etching the first conductive type well region in the partial area connected to the partial area of the deep trench sidewall at a second preset depth from top to bottom, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench.
[0050] S6, a gate dielectric layer and a gate conductive layer are sequentially formed in the gate trench to form a gate structure;
[0051] S7, a source doped layer of the second conductivity type and a drain doped layer of the second conductivity type are formed in the first conductivity type well regions on both sides of the deep trench, wherein the source doped layer of the second conductivity type is closer to the gate structure, and the drain doped layer of the second conductivity type is farther away from the gate structure, and the first conductivity type is opposite to the second conductivity type.
[0052] S8, forming an electrode lead-out structure, electrically leading out the gate structure, the source doped layer of the second conductivity type, and the drain doped layer of the second conductivity type, respectively.
[0053] The trench gate LDMOS structure fabrication method of this embodiment expands the critical dimension (CD) of the gate trench from the deep trench region to a portion of the first conductivity type well region connected to it, thereby forming an inverted L-shaped gate trench. This effectively increases the process window for etching the gate trench and reduces the etching difficulty. In addition, based on the inverted L-shaped gate trench, the overall gate structure is also inverted L-shaped. Therefore, when electrically leading out the gate structure, the increased aperture size of the upper part of the gate structure effectively increases the photolithography process window for forming the lead-out electrode holes on the gate structure, thereby reducing the precision requirements of the photolithography machine and reducing the overlay precision when forming the lead-out electrode holes on the gate structure.
[0054] The fabrication method of the trench gate LDMOS structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0055] As shown in Figure 4, step S1 is performed first, providing a semiconductor substrate 10, which includes a first conductivity type well region 100 extending inward from the upper surface of the semiconductor substrate 10.
[0056] The semiconductor substrate 10 can be a semiconductor substrate such as silicon, silicon germanium, or silicon carbide, or a semiconductor substrate with an epitaxial layer already grown on it. The semiconductor substrate can be an intrinsic semiconductor substrate or a doped semiconductor substrate. When the semiconductor substrate 10 is a doped semiconductor substrate, the doping type is set according to the type of LDMOS to be formed. For example, when a P-type LDMOS needs to be formed, the semiconductor substrate 10 is a P-type doped semiconductor substrate; when an N-type LDMOS needs to be formed, the semiconductor substrate 10 is an N-type doped semiconductor substrate. In this embodiment, the semiconductor substrate 10 is selected as a silicon substrate.
[0057] As an example, the first conductivity type well region 100 can be formed by ion implantation diffusion. The first conductivity type can be either P-type or N-type, which is opposite to the doping type of the semiconductor substrate 10. For example, when the semiconductor substrate 10 is a P-type doped semiconductor substrate, the first conductivity type well region 100 is an N-type well region; when the semiconductor substrate 10 is an N-type doped semiconductor substrate, the first conductivity type well region 100 is a P-type well region.
[0058] As an example, as shown in Figure 4, a termination protection structure is typically formed on the outer periphery of the device region. Therefore, the semiconductor substrate 10 also includes a second conductivity type well region 101 connected to the first conductivity type well region 100, to form the required termination protection structure in the second conductivity type well region 101. The second conductivity type well region 101 can also be formed by ion implantation diffusion. The first conductivity type is opposite to the second conductivity type; that is, when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conductivity type is P-type, the second conductivity type is N-type.
[0059] As shown in Figure 5, step S2 is then performed to form a deep trench 102 extending inward from the upper surface of the first conductive type well region 100 within the first conductive type well region 100.
[0060] However, the specific parameters of the deep trench 102, such as depth and width, are not excessively limited; they can be selected according to actual needs.
[0061] As a specific example, the method for forming the deep trench 102 includes: firstly, forming a hard mask layer and a photoresist layer sequentially on the surface of the semiconductor substrate 10; then, performing photolithographic patterning on the photoresist layer; next, etching the hard mask layer based on the patterned photoresist layer to obtain a patterned hard mask layer; then, etching the exposed semiconductor substrate 10 based on the patterned hard mask layer to obtain the deep trench 102; and finally, removing the patterned hard mask layer.
[0062] As an example, in order to reduce the problem of local electric field concentration in subsequent LDMOS devices, the corners of the formed deep trench 102 can be rounded.
[0063] As shown in Figure 7, step S3 is then performed, in which ion implantation is performed on the sidewalls and bottom wall of the deep trench 102 to form a first conductivity type doped layer 104 on the surface of the deep trench 102. This first conductivity type doped layer 104 subsequently serves as the drift region and channel region of the LDMOS structure.
[0064] As shown in Figure 6, as an example, an oxide pad layer 103 can be formed on the surface of the deep trench 102 before forming the first conductivity type doped layer 104. For example, the oxide pad layer 103 can be formed using a chemical vapor deposition (CVD) process or a thermal oxidation process. When the semiconductor substrate 10 is selected as a silicon substrate in this embodiment, the oxide pad layer 103 is a silicon oxide oxide pad layer. The oxide pad layer 103 can serve as a surface barrier layer during ion implantation to form the first conductivity type doped layer 104, effectively reducing the tunneling effect during ion implantation and ensuring the uniformity of ion implantation. Preferably, the oxide pad layer 103 is formed using a thermal oxidation process. On the one hand, it can be used as a surface barrier layer during ion implantation to form the first conductivity type doped layer 104; on the other hand, the thermal oxidation process can repair surface damage caused during etching to form the deep trench 102.
[0065] As an example, when the first conductivity type doped layer 104 is of N-type conductivity, the doping ions can be N-type conductive ions such as P and As; when the first conductivity type doped layer 104 is of P-type conductivity, the doping ions can be P-type conductive ions such as B and Al.
[0066] As shown in Figure 8, the next step is S4, in which insulating material 105 is used to at least fill the deep trench 102.
[0067] The deep trench 102 can be filled using a CVD process or a HARP (High Aspect Ratio Process) process with strong via-filling capabilities. The insulating material 105 can be any suitable insulating filling material. When the semiconductor substrate 10 in this embodiment is selected as a silicon substrate, the insulating material is preferably silicon oxide.
[0068] As shown in Figure 9, as an example, after the insulating material 105 at least fills the deep trench 102, the insulating material 105 can be planarized to facilitate subsequent processes. For example, chemical mechanical polishing (CMP) can be used for planarization. After planarization, the surface of the insulating material 105 can be flush with the surface of the semiconductor substrate 10 or higher than the surface of the semiconductor substrate 10 by a predetermined thickness (as shown in Figure 9). In this embodiment, it is preferable that after planarization, the surface of the insulating material 105 is higher than the surface of the semiconductor substrate 10 by a predetermined thickness. This predetermined thickness of insulating material can be directly used as a hard mask layer for subsequent etching to form the gate trench, thereby saving process steps and reducing manufacturing costs.
[0069] As shown in Figure 12, step S5 is then performed, etching the insulating material 105 in the sidewall portion of the deep trench 102 at a first preset depth from top to bottom, and etching the first conductive type well region 100 portion connected to the sidewall portion of the deep trench 102 at a second preset depth from top to bottom, wherein the second preset depth is less than the first preset depth, forming an inverted L-shaped gate trench 110.
[0070] It should be noted that the overall shape of the gate trench 110 is an inverted L-shape. As the gate trench 110 is positioned on different sides of the deep trench 102, the inverted L-shape changes accordingly, as shown in Figure 12. When the gate trench 110 is on the right side wall of the deep trench 102, its shape resembles an "Γ" shape; similarly, when the gate trench 110 is on the left side wall of the deep trench 102, its shape resembles... type.
[0071] As shown in Figure 12, in this step, the shape of the gate trench 110 is set to an inverted L-shape, and the diameter L of the upper part of the gate trench 110 is significantly increased, thereby effectively increasing the etching process window when etching to form the gate trench 110 and reducing the etching difficulty. In addition, when etching to form the gate trench 110, the depth ratio of "|" to "-" in the inverted L-shaped gate trench 110 can be achieved by adjusting the etching selectivity ratio of the insulating material 105 and the semiconductor substrate material.
[0072] As shown in Figure 12, as an example, the aperture L of the upper portion of the gate trench is not less than 0.1 μm. Furthermore, to ensure that over-etching of the electrode leads during the subsequent electrode lead-out process of the gate structure does not penetrate the gate structure, the second preset depth, i.e., the depth of the "-" portion in the gate trench 110, is not less than...
[0073] As a specific example, the method for forming the gate trench 110 includes the following steps:
[0074] S51, as shown in Figure 9, a hard mask layer 106 is first formed on the surface of the semiconductor substrate 10. It should be noted that after planarizing the insulating material 105 in step S4, if the surface of the insulating material 105 is flush with the surface of the semiconductor substrate 10, then in this step, a hard mask layer 106 needs to be re-formed on the surface of the semiconductor substrate 10. If the surface of the insulating material 105 is higher than the surface of the semiconductor substrate 10 by a predetermined thickness after planarization, then the insulating material 105 of the predetermined thickness is directly used as the hard mask layer 106 in this step.
[0075] S52, as shown in Figures 10 and 11, a patterned photoresist layer 107 is then formed on the hard mask layer 106 (as shown in Figure 10), and the hard mask layer 106 is etched based on the patterned photoresist layer 107 to form a patterned hard mask layer 108 (as shown in Figure 11). The patterned hard mask layer 108 exposes the surface of the insulating material 105 in a portion of the deep trench sidewall and a portion of the first conductive type well region 100 connected to the portion of the deep trench sidewall. This step can also effectively reduce the precision requirements of the lithography machine.
[0076] S53, as shown in FIG12, the corresponding insulating material 105 and the first conductive type well region 100 are then etched using the patterned photoresist layer 107 and the patterned hard mask layer 108 as masks to form the gate trench 110; finally, the patterned photoresist layer 107 is removed.
[0077] As shown in Figure 14, step S6 is then performed, in which a gate dielectric layer 111 and a gate conductive layer 112 are sequentially formed in the gate trench 110 to form a gate structure 11.
[0078] When the semiconductor substrate 10 in this embodiment is selected as a silicon substrate, the gate dielectric layer 111 is selected as a silicon oxide gate dielectric layer, preferably formed by a thermal oxidation process, and the gate conductive layer 112 is selected as a polysilicon gate conductive layer.
[0079] As a specific example, the method for forming the gate structure 11 includes the following steps:
[0080] S61, as shown in Figure 13, firstly, the gate dielectric layer 111 is formed on the surface of the gate trench 110 using a thermal oxidation process.
[0081] S62, as shown in FIG13, then a gate conductive layer 112 that at least fills the gate trench 110 is formed on the gate dielectric layer 111 using a CVD deposition process.
[0082] S63, as shown in Figure 14, the gate conductive layer 112 is ground using CMP process. After grinding, the upper surface of the gate conductive layer 112 is lower than the upper surface of the first conductive type well region 100.
[0083] As shown in Figure 15, further, after forming the gate structure 11, the method includes forming an insulating coating layer 12 covering the gate structure 11 on the surface of the semiconductor substrate. Preferably, the material of the insulating coating layer 12 is the same as that of the insulating material 105, for example, both are silicon oxide.
[0084] As shown in Figure 16, further, after forming the insulating coating layer 12, the step of forming a shallow trench isolation structure 13 in the second conductivity type well region 101 is also included; as described above, since after step S63, the upper surface of the gate conductive layer 112 is lower than the upper surface of the first conductivity type well region 100, the surface of the gate structure 11 is not easily damaged during the planarization process of the isolation material filled in the shallow trench isolation structure 13.
[0085] As shown in Figure 17, step S7 is then performed, in which a source doped layer 14 of the second conductivity type and a drain doped layer 15 of the second conductivity type are formed on the first conductivity type well region 100 on both sides of the deep trench. The source doped layer 14 of the second conductivity type is closer to the gate structure 11, and the drain doped layer 15 of the second conductivity type is farther away from the gate structure 11. The first conductivity type is opposite to the second conductivity type.
[0086] As shown in Figures 18 and 19, step S8 is performed to form an electrode lead-out structure 16, which electrically leads out the gate structure 11, the source doped layer 14 of the second conductivity type, and the drain doped layer 15 of the second conductivity type, respectively.
[0087] As a specific example, the method of forming the electrode lead-out structure 16 includes:
[0088] S81, as shown in FIG18, firstly, a dielectric layer 17 is formed on the insulating covering layer 12, and the dielectric layer 17 is planarized.
[0089] S82, as shown in Figure 18, the dielectric layer 17 is then photolithographically etched to form lead-out electrode holes 160 in the corresponding regions of the gate structure 11, the source doped layer 14 of the second conductivity type, and the drain doped layer 15 of the second conductivity type. As described above, based on the inverted L-shaped gate trench 110, the gate structure 11 formed is also generally inverted L-shaped. Therefore, in the photolithography process of this step, due to the increased aperture size of the upper part of the gate structure 11, the photolithography process window of the formed lead-out electrode holes 160 can be effectively increased, thereby reducing the precision requirements of the photolithography machine and also reducing the overlay precision of the lead-out electrode holes 160 formed on the gate structure 11.
[0090] S83, as shown in Figure 19, the lead-out electrode hole 160 is then filled with a conductive metal material, and the conductive metal material is planarized to remove the conductive metal material outside the lead-out electrode hole 160, thereby obtaining the electrode lead-out structure 16.
[0091] This embodiment also provides a trench gate LDMOS structure, which can be fabricated using the method described above, but is not limited to this method. Any other suitable fabrication method can also be used, as long as the trench gate LDMOS structure can be obtained. When the trench gate LDMOS structure is fabricated using the method described in this embodiment, the beneficial effects that can be achieved can be found in the detailed discussion of the above fabrication method, and will not be repeated below.
[0092] As shown in Figure 19, the trench gate LDMOS structure includes:
[0093] Semiconductor substrate 10, the semiconductor substrate 10 including a first conductivity type well region 100 extending inwardly from the upper surface of the semiconductor substrate;
[0094] A deep trench 102 (as shown in Figure 5) extends inward from the upper surface of the first conductivity type well region 100.
[0095] A first conductivity type doped layer 104 is formed on the surface of the deep trench 102;
[0096] A gate structure 11 is composed of a gate dielectric layer 111 and a gate conductive layer 112. A portion of the gate structure 11 is formed at a first preset depth in a portion of the sidewall region of the deep trench 102, and another portion is formed at a second preset depth in a portion of the first conductivity type well region 100 that is connected to the portion of the sidewall region of the deep trench.
[0097] Insulating material 105 at least fills the deep trench 102 except for the gate structure 11;
[0098] The source doped layer 14 and the drain doped layer 15 of the second conductivity type are respectively, wherein the source doped layer 14 of the second conductivity type is close to the gate structure 11, and the drain doped layer 15 of the second conductivity type is away from the gate structure 11. The first conductivity type is opposite to the second conductivity type.
[0099] The electrode lead-out structure 16 electrically leads out the gate structure 11, the source doped layer 14 of the second conductivity type, and the drain doped layer 15 of the second conductivity type.
[0100] As an example, the aperture of the upper portion of the gate structure 11 is not less than 0.1 μm, and the second preset depth is not less than...
[0101] In summary, this invention provides a trench gate LDMOS structure and its fabrication method. By expanding the critical dimension (CD) of the gate trench from the deep trench region to a portion of the adjacent first conductivity type well region, an inverted L-shaped gate trench is formed. This effectively increases the process window for etching the gate trench and reduces etching difficulty. Furthermore, based on the inverted L-shaped gate trench, the overall gate structure is also inverted L-shaped. Therefore, during electrical lead-out of the gate structure, the increased aperture size of the upper portion effectively increases the photolithography process window for forming the lead-out electrode holes on the gate structure, thereby reducing the precision requirements of the photolithography machine and lowering the overlay precision when forming the lead-out electrode holes. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0102] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a trench gate LDMOS structure, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including a first conductivity type well region extending inwardly from the upper surface of the semiconductor substrate; A deep trench is formed within the first conductivity type well region, extending inward from the upper surface of the first conductivity type well region; Ion implantation is performed on the sidewalls and bottom wall of the deep trench to form a first conductivity type doped layer on the surface of the deep trench; The deep trench shall be filled at least completely with insulating material; The insulating material in a portion of the deep trench sidewall is etched from top to bottom to a first preset depth, and the first conductivity type well region in a portion of the deep trench sidewall is etched from top to bottom to a second preset depth, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench. A gate dielectric layer and a gate conductive layer are sequentially formed in the gate trench to form a gate structure; A source doped layer of the second conductivity type and a drain doped layer of the second conductivity type are respectively formed in the first conductivity type well regions on both sides of the deep trench. The source doped layer of the second conductivity type is closer to the gate structure, and the drain doped layer of the second conductivity type is farther away from the gate structure. The first conductivity type is opposite to the second conductivity type. An electrode lead-out structure is formed to electrically lead out the gate structure, the source doped layer of the second conductivity type, and the drain doped layer of the second conductivity type, respectively.
2. The method for fabricating a trench gate LDMOS structure according to claim 1, characterized in that: The diameter of the upper portion of the gate trench is not less than 0.1 μm, and the second preset depth is not less than...
3. The method for fabricating a trench gate LDMOS structure according to claim 1, characterized in that: The process includes forming an oxygen pad layer on the surface of the deep trench before forming the first conductivity type doped layer.
4. The method for fabricating a trench gate LDMOS structure according to claim 1, characterized in that: After filling the deep trench with insulating material, the process further includes a step of planarizing the insulating material. The planarized insulating material has a predetermined thickness above the surface of the semiconductor substrate, and the predetermined thickness of the insulating material serves as a hard mask layer.
5. The method for fabricating a trench gate LDMOS structure according to any one of claims 1 to 4, characterized in that, The method of forming the gate trench includes: A hard mask layer and a photoresist layer are sequentially formed on the surface of the semiconductor substrate; The hard mask layer is patterned using photolithography to form a patterned hard mask layer, which exposes the surface of the insulating material in a portion of the deep trench sidewall and a portion of the first conductive type well region connected to the portion of the deep trench sidewall. The corresponding insulating material and the first conductivity type well region are etched using the patterned photoresist layer and the patterned hard mask layer as masks to form the gate trench.
6. The method for fabricating a trench gate LDMOS structure according to claim 5, characterized in that, The method of forming the gate structure includes: The gate dielectric layer is formed on the surface of the gate trench using a thermal oxidation process; A gate conductive layer that at least fills the gate trench is formed on the gate dielectric layer using a CVD deposition process; The gate conductive layer is ground using CMP process, and after grinding, the upper surface of the gate conductive layer is lower than the upper surface of the well region of the first conductivity type.
7. The method for fabricating a trench gate LDMOS structure according to claim 6, characterized in that: After forming the gate structure, the method further includes the step of forming an insulating coating layer covering the gate structure on the surface of the semiconductor substrate.
8. The method for fabricating a trench gate LDMOS structure according to claim 7, characterized in that: The semiconductor substrate further includes a second conductivity type well region extending inward from the upper surface of the semiconductor substrate, wherein the second conductivity type well region is connected to the first conductivity type well region; after forming the insulating coating layer, the method further includes the step of forming a shallow trench isolation structure in the second conductivity type well region.
9. A trench gate LDMOS structure, characterized in that, The trench gate LDMOS structure includes: A semiconductor substrate, the semiconductor substrate including a first conductivity type well region extending inwardly from the upper surface of the semiconductor substrate; A deep trench extending inward from the upper surface of the first conductivity type well region; A first conductivity type doped layer is formed on the surface of the deep trench; A gate structure consisting of a gate dielectric layer and a gate conductive layer, wherein a portion of the gate structure is formed at a first preset depth in a portion of the deep trench sidewall region, and another portion is formed at a second preset depth in a portion of the first conductivity type well region connected to the portion of the deep trench sidewall region. Insulating material, at least filling the deep trenches except for the gate structure; A source doped layer and a drain doped layer of a second conductivity type, wherein the source doped layer of the second conductivity type is closer to the gate structure, and the drain doped layer of the second conductivity type is farther from the gate structure, and the first conductivity type is opposite to the second conductivity type; An electrode lead-out structure electrically leads out the gate structure, the source doped layer of the second conductivity type, and the drain doped layer of the second conductivity type.
10. The trench gate LDMOS structure according to claim 9, characterized in that: The aperture of the upper portion of the gate structure is not less than 0.1 μm, and the second preset depth is not less than...