LDMOS device

Abstract

This application relates to an LDMOS device, comprising: a source region; a drain region; a gate; a drift region, at least partially located between the source and drain regions; an insulating dielectric layer extending from the drift region to the gate; a first shallow trench isolation structure located below a first side edge of the gate, and the first shallow trench isolation structure extending downward into the drift region; the first side being the side of the gate away from the source region; and a field plate structure located on the insulating dielectric layer and above the region between the first shallow trench isolation structure and the drain region, the bottom of the field plate structure not overlapping with the first shallow trench isolation structure. This invention achieves relatively low manufacturing costs while balancing HCI reliability, current capability, and Rdson.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to an LDMOS device. Background Technology

[0002] As a core device in BCD (Bipolar-CMOS-DMOS) technology, LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) typically requires low on-resistance and high voltage withstand capability, and we also hope that LDMOS can have good HCI (Hot Carrier Influence) reliability. Summary of the Invention

[0003] Therefore, it is necessary to provide an LDMOS device that can balance low on-resistance and good HCI reliability.

[0004] An LDMOS device includes: a source region; a drain region; a gate; a drift region at least partially located between the source region and the drain region; an insulating dielectric layer extending from the drift region to the gate; a first shallow trench isolation structure located below a first side edge of the gate, and the first shallow trench isolation structure extending downward into the drift region; the first side being the side of the gate away from the source region; and a field plate structure located on the insulating dielectric layer and above the region between the first shallow trench isolation structure and the drain region, the bottom of the field plate structure not overlapping with the first shallow trench isolation structure.

[0005] The aforementioned LDMOS device features a very small first shallow trench isolation structure (STI) along the length of the conductive channel, located only near the edge of the first gate side. Compared to a large STI in the drift region, this results in a shorter current path (the current path between the static operating current Idlin and the saturation operating current Idsat). Furthermore, the small STI provides less obstruction to drift region injection, which is beneficial for achieving sufficient carrier concentration. Therefore, this LDMOS device exhibits a lower on-resistance (Rdson) and stronger current capability compared to a scheme with a large STI in the drift region. Since the point of strongest impact ionization during device operation is located at the first shallow trench isolation structure, the relatively thick STI structure is less susceptible to damage from impact ionization, thus providing superior HCI reliability.

[0006] In one embodiment, the field plate structure includes a perforated field plate, the perforated field plate including conductive material filling the field plate contact holes, the field plate contact holes being located above the drift region, the bottom of the conductive material contacting a first main surface of the insulating dielectric layer, the first main surface being the side of the insulating dielectric layer facing away from the drift region, and the bottom of the conductive material not overlapping with the first shallow trench isolation structure.

[0007] In one embodiment, the field plate structure includes a field plate layer located on the insulating dielectric layer, the field plate layer being made of metal and / or alloy, the bottom of the field plate layer not overlapping with the first shallow trench isolation structure, and the LDMOS device further includes a conductive material filling the field plate contact hole, the bottom of the conductive material being in contact with the field plate layer.

[0008] In one embodiment, the LDMOS device further includes a first metal interconnect located on the field plate contact hole and above the gate, the first metal interconnect electrically connecting the gate and the conductive material through the gate contact hole above the gate.

[0009] In one embodiment, the gate is made of polycrystalline silicon.

[0010] In one embodiment, the gate is located above the region between the source region and the drain region.

[0011] In one embodiment, the source region, drain region, and drift region have a first conductivity type, and the doping concentration of the source region and drain region is greater than the doping concentration of the drift region. The LDMOS device further includes: a first well region, in which the source region is located, and the first well region has a second conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; and a body lead-out region, having a second conductivity type, located in the first well region, and the doping concentration of the body lead-out region is greater than the doping concentration of the first well region.

[0012] In one embodiment, the LDMOS device further includes: an isolation well region, wherein the drift region is located between the isolation well region and the first well region, the isolation well region having a ring structure that laterally surrounds the drift region and the first well region; a buried region, wherein the bottom of the isolation well region extends to the buried region, and the drift region and the first well region are located above the buried region; and an isolation lead-out region located in the isolation well region, wherein the isolation lead-out region has the same conductivity type as the buried region and the isolation well region, and the doping concentration of the isolation lead-out region is greater than that of the isolation well region.

[0013] In one embodiment, the LDMOS device further includes a second shallow trench isolation structure located between the isolation lead-out region and the drain region, wherein the first shallow trench isolation structure and the second shallow trench isolation structure have the same depth, and / or the first shallow trench isolation structure and the second shallow trench isolation structure are formed in the same step.

[0014] In one embodiment, the LDMOS device further includes a second well region, the first well region being located within the second well region, the drift region being located between the second well region and the isolation well region, the bottom of the second well region extending to the buried region, the conductivity type of the second well region being the same as that of the first well region, and the doping concentration of the second well region being less than that of the first well region.

[0015] In one embodiment, the LDMOS device is a P-channel LDMOS device, the source region and drain region are P-type regions, and the drift region is a P-type drift region.

[0016] In one embodiment, the insulating dielectric layer includes a metal silicide barrier layer. Attached Figure Description

[0017] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0018] Figure 1 This is a schematic diagram of an exemplary PLDMOS using a 0.18-micron BCD process.

[0019] Figure 2 This is a schematic diagram of a PLDMOS structure using a BCD process at another exemplary 0.18-micron process node.

[0020] Figure 3 This is a schematic diagram of a PLDMOS structure using a BCD process at another exemplary 0.18-micron process node.

[0021] Figure 4 This is a schematic diagram of the structure of an LDMOS device in one embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the formation of each STI structure in one embodiment of this application. Detailed Implementation

[0023] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0029] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0030] Figure 1 This is a schematic diagram of an exemplary PLDMOS (P-channel laterally diffused metal-oxide-semiconductor field-effect transistor) using a 0.18-micron BCD process. It shows the structure of the drift region (i.e.,...) Figure 1 A perforated field plate structure is set on the high-voltage P-type drift region (HV Pshift) of the PLDMOS structure. While maintaining the integrity of the device's drift region, a perforated field plate is added in the middle of the drift region to assist in drift region depletion. The silicon surface of the drift region in this PLDMOS structure has a certain concentration of drift region impurities implanted. The current path (all current paths in this specification refer to the current paths of the static operating current Idlin and the saturation operating current Idsat) is... Figure 1(Indicated by arrows) The current can directly reach the drain terminal through the surface of the drift region, thus the current path is the shortest, and the device's Rdson is relatively small. However, since the current is concentrated on the device surface, surface collision ionization is relatively strong, especially at the boundary of the polysilicon (polycrystalline silicon) region located in the JFET (junction field-effect transistor) region. Figure 1 The weak points of HCI are marked with spikes. The oxide layer in the JFET region is generally the gate oxide, and therefore relatively thin. Prolonged charge accumulation under a high electric field easily leads to the accumulation of defects within the oxide layer, resulting in poor HCI reliability. This manifests as the inability to pass full-area HCI reliability testing, and at certain voltage levels (Vgs, gate-source voltage), it can only be used at voltages lower than Vdd. If application at Vdd is required, only devices with higher voltage ratings can be used, but the increase in device size and the decrease in current capability will be very significant.

[0031] Figure 2 This is a schematic diagram of a PLDMOS structure using a 0.18-micron BCD process, as another example. Its drift region (i.e....) Figure 2 The high-voltage P-type drift region (HV Pshift) in the PLDMOS structure utilizes a shallow trench isolation (STI) structure. Polyp junctions extend from the JFET region to the STI region above the drift region, utilizing a portion of the polyp junction on the STI to assist in the depletion of the drift region. In this PLDMOS structure, the point of strongest impact ionization is mostly located at the STI corner (i.e.,...). Figure 2 The device features a weak point in the HCI (Hydrogen-Induced Compatibility) marked with a spike (or the bottom of the STI). The polyline material on the STI provides auxiliary depletion of the drift region, resulting in good HCI reliability and a long AC lifetime in HCI reliability testing. The device is less prone to corner defects in Vds (drain-source voltage) at various voltage levels, and can pass all HCI reliability tests. It can operate at 1.1 × Vdd voltage levels at all Vgs. The disadvantage is that because the drift region surface is entirely STI, the current path must travel from the source end through the JFET region and then around to the drift region body under the STI to reach the drain end. Figure 2 (Indicated by arrows), instead of a straight line from Source to Drain; and because the STI is deeper, drift region injection will be blocked by the STI, resulting in the loss of some injected impurities (such as Boron ions), which further reduces the carrier concentration in the current path and reduces the current capability of the device.

[0032] Figure 3This is a schematic diagram of a PLDMOS structure using a 0.18-micron BCD process. An additional mini STI mask layer and corresponding process steps are added. By using photolithography and etching steps at different levels than the standard STI process, the effect of shallow STI in the drift region is achieved (i.e., replacing the standard STI with a shallower mini STI). Figure 2 STI in the mid-drift region). Its current path ratio Figure 2 The device shown is shorter, and because the mini STI is very shallow, drift region implantation virtually eliminates the loss of implanted impurities (such as Boron ions) at the mini STI, achieving good HCI reliability, high current capability, and a small device size simultaneously. However, the additional mask and process layers increase the manufacturing cost compared to... Figure 1 and Figure 2 The proposed solution is much more advanced, and because it introduces the additional process layer step of mini STI, it will affect other devices on the same chip. It is not suitable for HCI improvement of already frozen process (because it will cause changes in the characteristics of other devices on the same chip).

[0033] Figure 4 This is a schematic diagram of the structure of an LDMOS device according to an embodiment of this application. Because... Figure 4 Because it has a symmetrical structure, some structures are numbered only on one side. Figure 4 In the illustrated embodiment, the semiconductor device includes a drift region 132, a source region 142, a drain region 144, a gate 146, a first well region 126, an insulating dielectric layer 152, a first shallow trench isolation structure 162, and a field plate structure.

[0034] Drift region 132 is at least partially located between source region 142 and drain region 144. Insulating dielectric layer 152 extends from drift region 132 to gate 146. First shallow trench isolation structure 162 is a structure extending along the length of the conductive channel (i.e.,...). Figure 4The small-sized STI (Shallow Trench Isolation) along the X-axis is chosen because a large STI in the drift region 132 would increase the on-resistance of the device. A smaller STI minimizes the impact on the current path, sacrificing minimal current capability for high-quality HCI lifetime. The first shallow trench isolation structure 162 is located below the edge near the first side of the gate 146 (the first side being the side of the gate 146 away from the source region 142), and extends downward into the drift region 132. The field plate structure is located on the insulating dielectric layer 152 and above the region between the first shallow trench isolation structure 162 and the drain region 144. The bottom of the field plate structure does not overlap with the first shallow trench isolation structure 162 in the vertical direction (i.e., the orthographic projection of the lower surface of the field plate structure onto the plane containing the upper surface of the first shallow trench isolation structure 162 does not coincide with the first shallow trench isolation structure 162), meaning that because the first shallow trench isolation structure 162 is small, it does not extend below the field plate structure. The vertical direction is perpendicular to the length and width of the conductive channel, i.e. Figure 4 The Z-axis direction in the equation.

[0035] exist Figure 4 In the illustrated embodiment, the field plate structure includes a perforated field plate 154. The perforated field plate 154 includes components filling the contact holes of the field plate ( Figure 4 The conductive material (not shown in the diagram) has a field plate contact hole located above the drift region 132. The bottom of the conductive material in the field plate contact hole contacts the first main surface (i.e., the front surface) of the insulating dielectric layer 152. The bottom of the conductive material does not overlap with the first shallow trench isolation structure 162 in the vertical direction. That is, the size of the first shallow trench isolation structure 162 is small, so it will not extend to the field plate 154 in the length direction of the conductive channel. In one embodiment of this application, the cross-section of the field plate 154 is elongated, and the size of the field plate 154 can be set according to the actual process.

[0036] In the aforementioned LDMOS device, the first shallow trench isolation structure 162 has a very small dimension along the length of the conductive channel, located only near the edge of the first side of the gate 146. Compared to setting a large-sized STI in the drift region 132, the current path of the LDMOS device is shorter, and the small-sized STI obstructs drift region injection less, which is beneficial for obtaining sufficient carrier concentration. Therefore, this LDMOS device has a smaller on-resistance (Rdson) and stronger current capability compared to the scheme of setting a large-sized STI in the drift region 132. Since the point of strongest impact ionization intensity during device operation is located at the first shallow trench isolation structure 162, the thick oxide layer of the STI structure makes it less susceptible to damage due to impact ionization, thus exhibiting better HCI reliability. The field plate structure can assist in the overall depletion of the rear end of the drift region.

[0037] In one embodiment of this application, the field plate structure may also employ a metal film layer as the field plate. Specifically, the field plate structure includes a field plate layer located on the insulating dielectric layer 152 (specifically referring to the insulating dielectric layer 152 on the drift region 132, excluding the insulating dielectric layer 152 on the gate 146). The field plate layer is made of metal and / or alloy. Field plate contact holes are also provided on the field plate layer, and these contact holes are filled with conductive material. The bottom of the conductive material contacts the field plate layer to form an electrical connection. The bottom of the field plate layer does not overlap with the first shallow trench isolation structure 162 in the vertical direction; that is, the first shallow trench isolation structure 162 is small in size and therefore does not extend into the field plate layer along the length of the conductive channel.

[0038] In one embodiment of this application, the LDMOS device further includes a first metal interconnect 172 located on the field plate contact hole and above the gate 146. The first metal interconnect 172 electrically connects the gate 146 and the conductive material in the field plate contact hole through the gate contact hole 156 (which is filled with conductive material) above the gate 146, thereby pulling the potential of the field plate structure to the potential of the gate 146.

[0039] In one embodiment of this application, the gate 146 is made of polysilicon. Figure 4 In the illustrated embodiment, the gate 146 overlaps with the first shallow trench isolation structure 162 by a certain size, i.e., it rests on the first shallow trench isolation structure 162. Through the polysilicon overlapping on the first shallow trench isolation structure 162, the front end of the drift region at the location of maximum auxiliary electric field is depleted, and the electric field strength in the corner region of the foremost first shallow trench isolation structure 162 is weakened. The field plate structure assists in the overall depletion of the rear end of the drift region. In one embodiment of this application, the first shallow trench isolation structure 162 starts in the JFET region and ends inside the drift region 132 in the direction of the conductive channel length.

[0040] In one embodiment of this application, the insulating dielectric layer 152 is a silicide area block (SAB). Self-aligned silicide (salicide) is a relatively simple and convenient contact metallization process. During the fabrication of semiconductor devices, some areas require a salicide process, while others require a non-salicide process. For devices requiring a non-salicide process, the properties of salicide are utilized by covering the areas requiring non-salicide with a material that does not react with the metal. This material used to cover the non-salicide areas is called a self-aligned silicide area block (SAB).

[0041] In one embodiment of this application, the source region 142, drain region 144, and drift region 132 have a first conductivity type, and the doping concentration of the source region 142 and drain region 144 is greater than the doping concentration of the drift region 132. The LDMOS device also includes a first well region 126 and a body lead-out region 141. The source region 142 and body lead-out region 141 are located in the first well region 126, which has a second conductivity type. Figure 4 In the illustrated embodiment, the LDMOS device is a P-channel LDMOS device with a first conductivity type of P-type and a second conductivity type of N-type. In other embodiments, the LDMOS device may also be an N-channel LDMOS device with a first conductivity type of N-type and a second conductivity type of P-type. The body lead-out region 141 has a second conductivity type, and the doping concentration of the body lead-out region 141 is greater than the doping concentration of the first well region 126.

[0042] In one embodiment of this application, the LDMOS device further includes an isolation well region 124, a buried region 112, and an isolation lead-out region 138. The drift region 132 is located between the isolation well region 124 and the first well region 126. The isolation well region 124 has a ring structure and laterally surrounds the drift region 132 and the first well region 126. Figure 4 The isolation well regions 124 on both sides are portions of the annular structure on the left and right sides, respectively. The bottom of the isolation well region 124 extends to the buried region 112. The drift region 132 and the first well region 126 are located above the buried region 112. Therefore, the annular isolation well region 124 and the buried region 112 below it form a cylindrical structure that surrounds the sides and bottom, forming a PN junction isolation. The isolation lead-out region 138 is located in the isolation well region 124. The isolation lead-out region 138 has the same conductivity type as the buried region 112 and the isolation well region 124, and the doping concentration of the isolation lead-out region 138 is greater than that of the isolation well region 124. Figure 4 In the embodiment shown, a contact hole is provided on the isolation lead-out area 138, and the potential of the isolation lead-out area 138 is led out as an isolation lead-out. The isolation potential can be adjusted by connecting an external potential to the contact hole.

[0043] In one embodiment of this application, the LDMOS device further includes a second shallow trench isolation structure 164 located between the isolation lead-out region 138 and the drain region 144. The first shallow trench isolation structure 162 and the second shallow trench isolation structure 164 have the same depth, and / or the first shallow trench isolation structure 162 and the second shallow trench isolation structure 164 are formed in the same process step. The first shallow trench isolation structure 162 and the second shallow trench isolation structure 164 are formed in the same process step, relative to... Figure 3 The mini STI scheme shown eliminates the need for an additional photomask and corresponding process steps for the STI in the drift region, thus saving manufacturing costs and improving manufacturing efficiency.

[0044] In one embodiment of this application, the LDMOS device further includes a second well region 122. A first well region 126 is located within the second well region 122, a drift region 132 is located between the second well region 122 and the isolation well region 124, and the bottom of the second well region 122 extends to the buried region 112. The conductivity type of the second well region 122 is the same as that of the first well region 126, and the doping concentration of the second well region 122 is lower than that of the first well region 126.

[0045] In one embodiment of this application, the LDMOS device further includes a third well region 128 located within the isolation well region 124, and an isolation lead-out region 138 located within the third well region 128. The third well region 128 and the isolation lead-out region 138 have the same conductivity type. The doping concentration of the third well region 128 is greater than the doping concentration of the isolation well region 124 but less than the doping concentration of the isolation lead-out region 138. Figure 4 In the embodiment shown, the conductivity type of the buried region 112, the second well region 122, the first well region 126, the isolation well region 124 and the third well region 128 are all N-type, the second well region 122 and the isolation well region 124 are deep N-wells, and the buried region 112 is an N-type buried layer.

[0046] In one embodiment of this application, the LDMOS device further includes a fourth well region 134 located outside the isolation well region 124, and a substrate lead-out region 136 located within the fourth well region 134. The fourth well region 134 and the substrate lead-out region 136 have the same conductivity type as the substrate 110, and the doping concentration of the substrate lead-out region 136 is greater than the doping concentration of the fourth well region 134. Figure 4 In the embodiment shown, substrate 110 is a P-type substrate Psub, and drift region 132 is located in P-type region 111. P-type region 111 may be a part of substrate 110, or it may be a P-type epitaxial layer epitaxially formed on substrate 110.

[0047] In one embodiment of this application, the LDMOS device further includes a third shallow trench isolation structure 166 located between the substrate lead-out region 136 and the isolation lead-out region 138. The first shallow trench isolation structure 162, the second shallow trench isolation structure 164, and the third shallow trench isolation structure 166 have the same depth, and the first shallow trench isolation structure 162, the second shallow trench isolation structure 164, and the third shallow trench isolation structure 166 are formed in the same process step. Figure 5 This is a schematic diagram of the formation of each STI structure in one embodiment of this application.

[0048] Based on all the above embodiments, this application only requires modification to the photolithography of the polysilicon layer (corresponding to gate 146), the active region (corresponding to each STI—including the first shallow trench isolation structure 162, the second shallow trench isolation structure 164, the third shallow trench isolation structure 166, etc.), and the contact holes (field plate contact holes, gate contact holes 156, etc.) to realize the LDMOS device structure of this application. No additional photolithography or process steps are required, nor is a long-cycle re-tapeout (wafer fabrication) necessary. There is no need to worry about the impact on other unrelated devices in the same chip. It is suitable for both launch as a new device on a frozen process platform and for introduction during the development of new processes.

[0049] In one embodiment of this application, the above-described LDMOS device is suitable for a BCD process platform with a 0.18-micron process node; in other embodiments, it can also be applied to process platforms with other critical dimensions (CD).

[0050] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An LDMOS device, characterized in that, include: Source region; Drain region; Gate; The drift region is at least partially located between the source region and the drain region; An insulating dielectric layer extends from the drift region to the gate; The first shallow trench isolation structure is located below the first side edge of the gate, and the first shallow trench isolation structure extends downward into the drift region; The first side is the side of the gate that is away from the source region; The field plate structure is located on the insulating dielectric layer and above the region between the first shallow trench isolation structure and the drain region, and the bottom of the field plate structure does not overlap with the first shallow trench isolation structure.

2. The LDMOS device according to claim 1, characterized in that, The field plate structure includes a perforated field plate, the perforated field plate comprising conductive material filled in contact holes of the field plate, the contact holes of the field plate being located above the drift region, the bottom of the conductive material contacting a first main surface of the insulating dielectric layer, the first main surface being the side of the insulating dielectric layer facing away from the drift region, and the bottom of the conductive material not overlapping with the first shallow trench isolation structure; or The field plate structure includes a field plate layer located on the insulating dielectric layer. The field plate layer is made of metal and / or alloy. The bottom of the field plate layer does not overlap with the first shallow trench isolation structure. The LDMOS device also includes a conductive material filling the field plate contact hole. The bottom of the conductive material is in contact with the field plate layer.

3. The LDMOS device according to claim 2, characterized in that, It also includes a first metal connection located on the field plate contact hole and above the gate, the first metal connection electrically connecting the gate and the conductive material through the gate contact hole above the gate.

4. The LDMOS device according to claim 1, characterized in that, The gate is made of polycrystalline silicon.

5. The LDMOS device according to claim 1, characterized in that, The gate is located above the region between the source region and the drain region.

6. The LDMOS device according to claim 1, characterized in that, The source region, drain region, and drift region have a first conductivity type, and the doping concentration of the source region and drain region is greater than the doping concentration of the drift region. The LDMOS device further includes: A first well region, wherein the source region is located in the first well region, and the first well region has a second conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; The body lead-out region, having a second conductivity type, is located in the first well region, and the doping concentration of the body lead-out region is greater than that of the first well region.

7. The LDMOS device according to claim 6, characterized in that, Also includes: An isolation trap region, wherein the drift region is located between the isolation trap region and the first trap region, and the isolation trap region is a ring structure that laterally surrounds the drift region and the first trap region; The burial area, the bottom of the isolation trap area extends to the burial area, and the drift area and the first trap area are located above the burial area; An isolation lead-out region is located within the isolation trap region. The isolation lead-out region has the same conductivity type as the buried region and the isolation trap region. The doping concentration of the isolation lead-out region is greater than that of the isolation trap region.

8. The LDMOS device according to claim 7, characterized in that, It also includes a second shallow trench isolation structure located between the isolation lead-out region and the drain region, wherein the first shallow trench isolation structure and the second shallow trench isolation structure have the same depth, and / or the first shallow trench isolation structure and the second shallow trench isolation structure are formed in the same step.

9. The LDMOS device according to claim 7, characterized in that, It also includes a second well region, in which the first well region is located, the drift region is located between the second well region and the isolation well region, the bottom of the second well region extends to the buried region, the conductivity type of the second well region is the same as that of the first well region, and the doping concentration of the second well region is less than that of the first well region.

10. The LDMOS device according to any one of claims 1-9, characterized in that, The LDMOS device is a P-channel LDMOS device, wherein the source region and drain region are P-type regions, and the drift region is a P-type drift region.

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