A PCIE device bandwidth allocation method and related device

Abstract

The present application discloses a method for allocating bandwidth to a PCIE device, comprising: reading a pulse width modulation signal output by a board to be identified; performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information; identifying the duty cycle information based on a duty cycle bandwidth table to obtain corresponding bandwidth information; and allocating bandwidth to the board to be identified based on the bandwidth information. The duty cycle in the output pulse width modulation signal represents the bandwidth information of the board to be identified, and finally, bandwidth is allocated to the board to be identified based on the bandwidth information, thereby avoiding occupying more pins to determine bandwidth information, that is, avoiding pin occupation and improving hardware resource waste. The present application also discloses a PCIE device bandwidth allocation device, device, and computer-readable storage medium, which have the above beneficial effects.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a PCIE device bandwidth allocation method, a PCIE device bandwidth allocation device, a device, and a computer-readable storage medium. Background Art

[0002] Before a server system is powered on, the CPU (central processing unit) on the motherboard needs to know which boards are included in the server, the types of boards, and the PCIE (peripheral component interconnect express) channel bandwidths occupied by different boards. This allows the BIOS (Basic Input Output System) to allocate appropriate PCIE channel bandwidths to each board during power-up, preventing any board from becoming unusable during power-up. Therefore, the motherboard must identify the bandwidth of the downstream boards.

[0003] In the related art, the current PCIE device bandwidth allocation often uses the BWID (Bandwidth Identity) solution, which allocates 3 PINs (pins) as ID (Identity document) PINs on the SLIMLINE (thin-line cable) connector, and sets pull-up and pull-down resistors on the corresponding PINs on the riser adapter card or backplane at the other end of the cable. The combination of the three IDs is read by the BMC (Baseboard Management Controller) to allocate bandwidth. However, each board is equipped with several bandwidth identification devices, and the number of identification signals is large, often occupying more than three high-speed connector interfaces, which is not conducive to the setting of other more important functional signals. In addition, 20 SLIMLINE connectors will have 60 BWIDs that need to occupy pins, resulting in a large number of monitoring chip pins being occupied, resulting in a waste of hardware resources.

[0004] Therefore, how to improve the utilization of hardware resources in the server is a key issue that those skilled in the art are concerned about. Summary of the Invention

[0005] The purpose of this application is to provide a PCIE device bandwidth allocation method, PCIE device bandwidth allocation device, device and computer-readable storage medium to avoid large-scale occupation of chip pins and improve the utilization of hardware resources.

[0006] To solve the above technical problems, the present application provides a PCIE device bandwidth allocation method, comprising:

[0007] Read the pulse width modulation signal output by the board to be identified;

[0008] Performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information;

[0009] Identifying the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information;

[0010] Bandwidth is allocated to the board to be identified based on the bandwidth information.

[0011] Optionally, the process of identifying the pulse width modulation signal output by the board to be identified includes:

[0012] The to-be-identified board outputs the pulse width modulation signal based on a timer chip in response to a board insertion instruction.

[0013] Optionally, the pulse width modulation signal output by the board to be identified is read, including:

[0014] The pulse width modulation signal output by the board to be identified is read through the CPLD chip.

[0015] Optionally, performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information includes:

[0016] The pulse width modulation signal is clock sampled by CPLD to obtain the duty cycle information.

[0017] Optionally, after the CPLD obtains the duty cycle information, the method further includes:

[0018] The CPLD sets the bit corresponding to the duty cycle information in the bandwidth identification register to a high level.

[0019] Optionally, identifying the duty cycle information based on a duty cycle bandwidth table to obtain corresponding bandwidth information includes:

[0020] Reading the duty cycle bandwidth table;

[0021] The duty cycle information is matched with the duty cycle information in the duty cycle bandwidth table to obtain corresponding bandwidth information.

[0022] Optionally, allocating bandwidth to the board to be identified based on the bandwidth information includes:

[0023] The bandwidth of the board to be identified is configured based on the bandwidth information, so as to allocate bandwidth to the board to be identified.

[0024] The present application also provides a PCIE device bandwidth allocation device, comprising:

[0025] A signal reading module is used to read the pulse width modulation signal output by the board to be identified;

[0026] A duty cycle identification module, configured to identify the duty cycle of the pulse width modulation signal to obtain duty cycle information;

[0027] a bandwidth identification module, configured to identify the duty cycle information based on a duty cycle bandwidth table to obtain corresponding bandwidth information;

[0028] The bandwidth allocation module is used to allocate bandwidth to the board to be identified based on the bandwidth information.

[0029] The present application also provides a device, comprising:

[0030] memory for storing computer programs;

[0031] The processor is configured to implement the steps of the above-mentioned PCIE device bandwidth allocation method when executing the computer program.

[0032] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the PCIE device bandwidth allocation method described above are implemented.

[0033] The present application provides a method for allocating bandwidth to a PCIE device, comprising: reading a pulse width modulation signal output by a board to be identified; performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information; identifying the duty cycle information based on a duty cycle bandwidth table to obtain corresponding bandwidth information; and allocating bandwidth to the board to be identified based on the bandwidth information.

[0034] By reading the pulse width modulation signal output by the board to be identified, then performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifying the duty cycle information based on a duty cycle bandwidth table to obtain corresponding bandwidth information, that is, the duty cycle in the output pulse width modulation signal represents the bandwidth information of the board to be identified, and finally allocating bandwidth to the board to be identified based on the bandwidth information, it avoids occupying more pins to determine the bandwidth information, that is, it avoids pin occupation and improves the waste of hardware resources.

[0035] The present application also provides a PCIE device bandwidth allocation device, device and computer-readable storage medium, which have the above beneficial effects and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0037] Figure 1 A flowchart of a PCIE device bandwidth allocation method provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of the module structure of a PCIE device bandwidth allocation method provided in an embodiment of the present application;

[0039] Figure 3 A topological diagram of the principle of a PCIE device bandwidth allocation method provided in this application;

[0040] Figure 4 A schematic diagram of the structure of a PCIE device bandwidth allocation device provided in an embodiment of the present application;

[0041] Figure 5 A schematic structural diagram of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The core of this application is to provide a PCIE device bandwidth allocation method, PCIE device bandwidth allocation device, equipment and computer-readable storage medium to avoid large-scale occupation of chip pins and improve the utilization of hardware resources.

[0043] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0044] In the related art, the current PCIE device bandwidth allocation often uses the BWID solution, which allocates three pins as ID pins on the SLIMLINE connector, sets pull-up and pull-down resistors on the corresponding pins on the riser adapter card or backplane at the other end of the cable. The combination of the three IDs is read by the BMC and then the bandwidth is allocated. However, each board is equipped with several bandwidth identification devices, and the number of identification signals is large, often occupying more than three high-speed connector interfaces, which is not conducive to the setting of other more important functional signals. In addition, 20 SLIMLINE connectors will have 60 BWID pins that need to be occupied, resulting in a large number of monitoring chip pins being occupied, resulting in a waste of hardware resources.

[0045] Therefore, the present application provides a PCIE device bandwidth allocation method, which reads the pulse width modulation signal output by the board to be identified, then performs duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifies the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information, that is, the bandwidth information of the board to be identified is represented by the duty cycle in the output pulse width modulation signal, and finally, the bandwidth of the board to be identified is allocated based on the bandwidth information, avoiding occupying more pins to determine the bandwidth information, that is, avoiding the occupation of pins and improving the waste of hardware resources.

[0046] The following describes a method for allocating bandwidth to a PCIE device provided by the present application through an embodiment.

[0047] Please refer to Figure 1 , Figure 1 This is a flowchart of a PCIE device bandwidth allocation method provided in an embodiment of the present application.

[0048] In this embodiment, the method may include:

[0049] S101, reading the pulse width modulation signal output by the board to be identified;

[0050] It can be seen that this step aims to read the pulse width modulation signal output by the board to be identified.

[0051] The "unidentified card" refers to a card inserted into the mainboard and requiring bandwidth identification. In this embodiment, the unidentified card can output ID information by not occupying more pins, but instead output a pulse-width modulated signal, also known as a PWM (Pulse Width Modulation) signal. This PWM signal can be configured with different duty cycles to output signals with different bandwidths to the mainboard.

[0052] Among them, the pulse width modulation signal can be output through a timer chip.

[0053] The process of identifying the pulse width modulation signal output by the board may include:

[0054] The board to be identified responds to the board insertion instruction and outputs a pulse width modulation signal based on the timer chip.

[0055] As can be seen, this alternative solution primarily illustrates how to output a pulse-width modulated signal. In this alternative solution, the card to be identified responds to the card insertion instruction by outputting a pulse-width modulated signal based on a timer chip. The timer chip can be a 555 timer, an integrated circuit chip commonly used in timers, pulse generators, and oscillator circuits. The 555 can be used as a delay device, trigger, or oscillator in a circuit.

[0056] Furthermore, this step may include:

[0057] The pulse width modulation signal output by the board to be identified is read through the CPLD chip.

[0058] As can be seen, this optional solution primarily describes how to read pulse-width modulated signals. In this optional solution, the pulse-width modulated signal output by the board to be identified is read using a CPLD (Complex Programmable Logic Device) chip. This is a digital integrated circuit whose logic functions can be customized by the user according to their needs. Its basic design approach utilizes an integrated development software platform, schematics, hardware description languages, and other methods to generate the corresponding target file. The code is then transferred to the target chip via a download cable to implement the designed digital system. Reading the pulse-width modulated signal output by the board to be identified using the CPLD chip and identifying it can improve signal recognition efficiency, avoid occupying CPU performance for judgment, and improve signal processing efficiency.

[0059] S102, performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information;

[0060] Based on S101, in this step, the duty cycle of the pulse width modulation signal is identified to obtain the duty cycle information. Furthermore, in this step, the duty cycle of the pulse width modulation signal can be identified by a CPLD to obtain the duty cycle information. In other words, the duty cycle of the pulse width modulation signal is determined.

[0061] The duty cycle refers to the proportion of the power-on time relative to the total time within a pulse cycle. For example, in this embodiment, the duty cycle can be set to different ratios, such as a duty cycle of 75%, a duty cycle of 80%, or a duty cycle of 100%.

[0062] Furthermore, in this step, different duty cycles can be set based on different situations. For example, if the bandwidth requirement of the board is small, the duty cycle can be set to 3; if the bandwidth requirement of the board is large, 5 or more duty cycles can be set.

[0063] Furthermore, this step may include:

[0064] The pulse width modulation signal is clock sampled by CPLD to obtain duty cycle information.

[0065] As can be seen, this alternative solution mainly explains how to obtain the duty cycle information. In this alternative solution, the CPLD performs clock sampling on the pulse width modulation signal to obtain the duty cycle information. In other words, the duty cycle information is obtained by making a judgment based on the clock sampling.

[0066] Furthermore, after the CPLD obtains the duty cycle information, it also includes:

[0067] The CPLD sets the bit corresponding to the duty cycle information in the bandwidth identification register high.

[0068] As can be seen, this alternative primarily explains how to transmit duty cycle information. In this alternative, the CPLD sets the bit corresponding to the duty cycle information in the bandwidth identification register high. In other words, the CPLD contains a bandwidth identification register, and different bits in this register represent different duty cycle information. When a bit is high, it indicates that the current board's duty cycle is the duty cycle corresponding to that bit.

[0069] S103, identifying the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information;

[0070] Based on S102, this step aims to identify the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information.

[0071] The duty cycle bandwidth table is a table that maps set duty cycles to bandwidths. In other words, different duty cycles correspond to different bandwidths. This duty cycle bandwidth table can be a table based on experience, a table based on the type of board and its bandwidth, or a table based on the bandwidth limit of the motherboard. As can be seen, there is no single way to set the duty cycle bandwidth table in this embodiment. The table can be set in different ways based on different situations, and this is not specifically limited here.

[0072] Furthermore, this step may include:

[0073] Step 1, read the duty cycle bandwidth table;

[0074] Step 2: Match the duty cycle information with the duty cycle information in the duty cycle bandwidth table to obtain corresponding bandwidth information.

[0075] As can be seen, this optional solution primarily explains how to identify and obtain corresponding bandwidth information. In this optional solution, the duty cycle bandwidth table is read; the duty cycle information is matched with the duty cycle information in the duty cycle bandwidth table to obtain the corresponding bandwidth information. The duty cycle bandwidth table is a table of configured correspondences.

[0076] S104: Allocate bandwidth to the board to be identified based on the bandwidth information.

[0077] Based on S103, this step aims to allocate bandwidth to the board to be identified based on the bandwidth information.

[0078] Furthermore, this step may include:

[0079] Bandwidth is configured for the board to be identified based on the bandwidth information, thereby allocating bandwidth to the board to be identified.

[0080] This optional solution mainly describes how to configure bandwidth. This optional solution mainly configures bandwidth for the unidentified board based on bandwidth information, thereby allocating bandwidth to the unidentified board.

[0081] In summary, this embodiment reads the pulse width modulation signal output by the board to be identified, then performs duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifies the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information. That is, the bandwidth information of the board to be identified is represented by the duty cycle in the output pulse width modulation signal. Finally, bandwidth is allocated to the board to be identified based on the bandwidth information, thereby avoiding occupying more pins to determine the bandwidth information, that is, avoiding pin occupation and improving the waste of hardware resources.

[0082] The following further illustrates a PCIE device bandwidth allocation method provided by the present application through another specific embodiment.

[0083] Please refer to Figure 2 , Figure 2 A schematic diagram of the module structure of a PCIE device bandwidth allocation method provided in an embodiment of the present application.

[0084] This embodiment addresses the issue of excessive cable and connector pin usage by the card bandwidth identification device, requiring BWIDs to connect to the BMC's GPIO interface, thus consuming too many BMC GPIOs. Furthermore, to address the issue of multiple BWID pins required to distinguish between various PCIE bandwidth combinations, such as X4, X8, and X16, this embodiment proposes a solution for implementing BWIDs through PWM output from an IC device on a daughter card. The card to be identified only needs to send a single serial PWM signal to complete bandwidth sampling.

[0085] In this embodiment, the solution may include:

[0086] The BWID output module supports the flexibly configured NE555DR PWM controller module to output the bandwidth information of the daughter card.

[0087] The BWID identification module and the ID allocation and encoding assembly module mainly involve allocating the corresponding relationship between PWM duty cycle and bandwidth according to the various bandwidth combinations of PCIE devices, implementing the recognition of duty cycle and the design of corresponding register bits in CPLD, and the motherboard BMC reading the bandwidth information of the corresponding PCIE device in the CPLD bandwidth identification register through I2C.

[0088] The BMC management module detects the bandwidth status of the PCIE interface connected to the bandwidth identification device and transmits the bandwidth information to the PCH through the SMBUS bus between the BMC and the PCH.

[0089] The BIOS bandwidth configuration module, PCH BIOS obtains information such as the boards and the PCIE channel bandwidth required by the boards stored in the BMC, and allocates PCIE channel bandwidth to each board.

[0090] Based on the above modules, the method for bandwidth allocation in this embodiment may include:

[0091] S201 , the board to be identified responds to a board insertion instruction and outputs a pulse width modulation signal based on a timer chip.

[0092] S201, reading the pulse width modulation signal output by the board to be identified through the CPLD chip;

[0093] S202, performing clock sampling on the pulse width modulation signal through the CPLD to obtain duty cycle information;

[0094] S203, identifying the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information;

[0095] S204: Configure bandwidth for the board to be identified based on the bandwidth information to allocate bandwidth to the board to be identified.

[0096] Please refer to Figure 3 , Figure 3 This is a principle topology diagram of a PCIE device bandwidth allocation method provided in this application.

[0097] like Figure 3 As shown, taking the board 1 to be identified as an example, the board 1 to be identified can be an X4 backplane, an X16 riser, or a PCIE board carrier of any bandwidth.

[0098] The NE555R supports controlling the output of a PWM waveform with a corresponding duty cycle by changing the resistance and capacitance of the DISCH pin. The frequency calculation formula is T = 1.44 / ((R1 + 2R2) * C), where C = 0.022uF. The corresponding relationship between the output duty cycle of the NE555R and the voltage divider resistor is as follows:

[0099] Duty cycle 75%: R1 = 1.3 Kohm, R2 = 649 ohm;

[0100] Duty cycle 80%: R1 = 1.82 Kohm, R2 = 649 ohm;

[0101] Duty cycle 100%: R1=NC, R2=0.

[0102] Three bandwidths can be defined: X4, X8, and X16. The corresponding relationship between duty cycle and bandwidth is defined as follows: duty cycle 75% - X4, duty cycle 80% - X8, duty cycle 100% - X16.

[0103] For example, using board 1 to be identified, the motherboard CPLD can detect an 80% PWM duty cycle through clock sampling. The BMC, via I2C (Inter-Integrated Circuit, a two-wire serial bus), detects that the 80% bit in the CPLD's bandwidth identification register is set high. By comparing the duty cycle and bandwidth netlist in Flash, the BMC identifies board 1 as an X8 device. The BMC then notifies the PCH via the SMBUS bus to configure board 1 with an X8 bandwidth. If the number of bandwidths or rates to be detected increases, the PWM can be reversed by adding MOSFETs to the PWM, doubling the number of duty cycle types. This demonstrates that board bandwidth identification can be achieved through PWM signals.

[0104] As can be seen, in this embodiment, to address the issue of excessive cable and connector pin usage by the card bandwidth identification device, the BWID must be connected to the BMC's GPIO interface, occupying too many BMC GPIOs. Furthermore, to address the issue of requiring multiple BWID pins to distinguish between various PCIE bandwidth combinations, such as X4, X8, and X16, a modular design can be achieved by using a CPLD with a small number of pins.

[0105] It can be seen that this embodiment reads the pulse width modulation signal output by the board to be identified, then performs duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifies the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information. That is, the bandwidth information of the board to be identified is represented by the duty cycle in the output pulse width modulation signal, and finally, the bandwidth of the board to be identified is allocated based on the bandwidth information, thereby avoiding occupying more pins to determine the bandwidth information, that is, avoiding pin occupation and improving the waste of hardware resources.

[0106] The following is an introduction to a PCIE device bandwidth allocation apparatus provided in an embodiment of the present application. The PCIE device bandwidth allocation apparatus described below and the PCIE device bandwidth allocation method described above can refer to each other.

[0107] Please refer to Figure 4 , Figure 4 This is a structural diagram of a PCIE device bandwidth allocation device provided in an embodiment of the present application.

[0108] In this embodiment, the device may include:

[0109] The signal reading module 100 is used to read the pulse width modulation signal output by the board to be identified;

[0110] The duty cycle identification module 200 is used to identify the duty cycle of the pulse width modulation signal and obtain duty cycle information;

[0111] The bandwidth identification module 300 is used to identify the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information;

[0112] The bandwidth allocation module 400 is configured to allocate bandwidth to the boards to be identified based on the bandwidth information.

[0113] Optionally, the process of identifying the pulse width modulation signal output by the board includes:

[0114] The board to be identified responds to the board insertion instruction and outputs a pulse width modulation signal based on the timer chip.

[0115] Optionally, the signal reading module 100 is specifically configured to read a pulse width modulation signal output by a board to be identified through a CPLD chip.

[0116] Optionally, the duty cycle identification module 200 is specifically configured to perform clock sampling on the pulse width modulation signal through a CPLD to obtain duty cycle information.

[0117] Optionally, after obtaining the duty cycle information, the CPLD further includes:

[0118] The CPLD sets the bit corresponding to the duty cycle information in the bandwidth identification register high.

[0119] Optionally, the bandwidth identification module 300 is specifically configured to read a duty cycle bandwidth table; match the duty cycle information with the duty cycle information in the duty cycle bandwidth table to obtain corresponding bandwidth information.

[0120] Optionally, the bandwidth allocation module 400 is specifically configured to configure bandwidth for the unidentified board based on bandwidth information, thereby allocating bandwidth to the unidentified board.

[0121] It can be seen that this embodiment reads the pulse width modulation signal output by the board to be identified, then performs duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifies the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information. That is, the bandwidth information of the board to be identified is represented by the duty cycle in the output pulse width modulation signal, and finally, the bandwidth of the board to be identified is allocated based on the bandwidth information, thereby avoiding occupying more pins to determine the bandwidth information, that is, avoiding pin occupation and improving the waste of hardware resources.

[0122] This application also provides a device, please refer to Figure 5 , Figure 5 A schematic diagram of a structure of a device provided in an embodiment of the present application may include:

[0123] memory for storing computer programs;

[0124] The processor is configured to implement any of the steps of the above-mentioned PCIE device bandwidth allocation method when executing a computer program.

[0125] like Figure 5 FIG2 is a schematic diagram of the structure of the device, which may include a processor 10, a memory 11, a communication interface 12, and a communication bus 13. The processor 10, the memory 11, and the communication interface 12 communicate with each other via the communication bus 13.

[0126] In the embodiment of the present application, the processor 10 may be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field programmable gate array, or other programmable logic devices.

[0127] The processor 10 may call a program stored in the memory 11 . Specifically, the processor 10 may execute the operations in the embodiment of the abnormal IP identification method.

[0128] The memory 11 is used to store one or more programs. The program may include program code, and the program code includes computer operating instructions. In the embodiment of the present application, the memory 11 stores at least a program for implementing the following functions:

[0129] Read the pulse width modulation signal output by the board to be identified;

[0130] Performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information;

[0131] Identifying the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information;

[0132] Bandwidth is allocated to the board to be identified based on the bandwidth information.

[0133] In one possible implementation, the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function, etc.; the data storage area may store data created during use.

[0134] In addition, the memory 11 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.

[0135] The communication interface 12 may be an interface of a communication module, and is used to connect to other devices or systems.

[0136] Of course, it needs to be explained that Figure 5 The structure shown does not constitute a limitation on the device in the embodiment of the present application. In actual application, the device may include Figure 5 More or fewer components than shown, or combinations of certain components.

[0137] It can be seen that this embodiment reads the pulse width modulation signal output by the board to be identified, then performs duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifies the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information. That is, the bandwidth information of the board to be identified is represented by the duty cycle in the output pulse width modulation signal, and finally, the bandwidth of the board to be identified is allocated based on the bandwidth information, thereby avoiding occupying more pins to determine the bandwidth information, that is, avoiding pin occupation and improving the waste of hardware resources.

[0138] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned PCIE device bandwidth allocation methods can be implemented.

[0139] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which can store program codes.

[0140] For an introduction to the computer-readable storage medium provided in this application, please refer to the above method embodiment, and this application will not go into details here.

[0141] It can be seen that this embodiment reads the pulse width modulation signal output by the board to be identified, then performs duty cycle identification on the pulse width modulation signal to obtain duty cycle information, and finally identifies the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information. That is, the bandwidth information of the board to be identified is represented by the duty cycle in the output pulse width modulation signal, and finally, the bandwidth of the board to be identified is allocated based on the bandwidth information, thereby avoiding occupying more pins to determine the bandwidth information, that is, avoiding pin occupation and improving the waste of hardware resources.

[0142] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0143] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0144] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0145] The above describes in detail a PCIE device bandwidth allocation method, PCIE device bandwidth allocation device, device, and computer-readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A PCIE device bandwidth allocation method, characterized in that: include: Read the pulse width modulation signal output by the board to be identified; Performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information; Identifying the duty cycle information based on the duty cycle bandwidth table to obtain corresponding bandwidth information; Allocating bandwidth to the board to be identified based on the bandwidth information; The process of identifying the pulse width modulation signal output by the board to be identified includes: The board to be identified outputs the pulse width modulation signal based on the timer chip in the board to be identified in response to the board insertion instruction; Read the pulse width modulation signal output by the board to be identified, including: The pulse width modulation signal output by the board to be identified is read through the CPLD chip; Performing duty cycle identification on the pulse width modulation signal to obtain duty cycle information includes: Performing clock sampling on the pulse width modulation signal through a CPLD to obtain the duty cycle information; After the CPLD obtains the duty cycle information, the method further includes: The CPLD sets the bit corresponding to the duty cycle information in the bandwidth identification register to a high level; The duty cycle information is identified based on the duty cycle bandwidth table to obtain corresponding bandwidth information, including: Reading the duty cycle bandwidth table; The duty cycle information is matched with the duty cycle information in the duty cycle bandwidth table to obtain corresponding bandwidth information.

2. The PCIE device bandwidth allocation method according to claim 1, wherein: Allocating bandwidth to the board to be identified based on the bandwidth information includes: The bandwidth of the board to be identified is configured based on the bandwidth information, so as to allocate bandwidth to the board to be identified.

3. A PCIE device bandwidth allocation device, characterized in that: include: A signal reading module is used to read the pulse width modulation signal output by the board to be identified; A duty cycle identification module, configured to identify the duty cycle of the pulse width modulation signal to obtain duty cycle information; a bandwidth identification module, configured to identify the duty cycle information based on a duty cycle bandwidth table to obtain corresponding bandwidth information; A bandwidth allocation module, configured to allocate bandwidth to the board to be identified based on the bandwidth information; The process of identifying the pulse width modulation signal output by the board to be identified includes: The board to be identified outputs the pulse width modulation signal based on the timer chip in the board to be identified in response to the board insertion instruction; Signal reading module, specifically used for: The pulse width modulation signal output by the board to be identified is read through the CPLD chip; The duty cycle recognition module is specifically used for: Performing clock sampling on the pulse width modulation signal through a CPLD to obtain the duty cycle information; After the CPLD obtains the duty cycle information, the method further includes: The CPLD sets the bit corresponding to the duty cycle information in the bandwidth identification register to a high level; The bandwidth identification module is specifically configured to: read the duty cycle bandwidth table; match the duty cycle information with the duty cycle information in the duty cycle bandwidth table to obtain corresponding bandwidth information.

4. A device, characterized in that include: memory for storing computer programs; A processor, configured to implement the steps of the PCIE device bandwidth allocation method according to claim 1 or 2 when executing the computer program.

5. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the PCIE device bandwidth allocation method according to claim 1 or 2 are implemented.

Images