Display panel

Abstract

This invention discloses a display panel, comprising a substrate, a plurality of pixel structures, a plurality of first multiplexers, a plurality of second multiplexers, a circuit board, and a plurality of connection traces. The substrate has a display area, a hole disposed within the display area, a first non-display area located between the hole and the display area, and a second non-display area located on the side of the display area away from the hole. The pixel structures include a plurality of first pixel structures and a plurality of second pixel structures respectively disposed on opposite sides of the hole along a first direction. The first multiplexers disposed in the first non-display area are electrically connected to the first pixel structures. The second multiplexers disposed in the second non-display area are electrically connected to the second pixel structures. The circuit board is electrically connected to the first multiplexers via the plurality of connection traces disposed in the first non-display area.

Description

Technical Field

[0001] The present invention relates to a display panel, and more particularly to a display panel having holes. Background Technology

[0002] With the development of display technology, in addition to improved display quality, the diversified applications of display panels have also been unlocked. Designing display panels applicable to different usage scenarios has become the norm for related manufacturers. In recent years, smartwatches, fitness trackers, and other wearable electronic devices have demonstrated the infinite possibilities of display panels in daily life. Therefore, in addition to high requirements for environmental resistance, the aesthetically pleasing design of display panels used in these electronic devices has become a crucial aspect of product development. To achieve diverse aesthetic designs, freeform cutting technology for display panels has gradually become an essential technology for related manufacturers.

[0003] In the initial design phase of a product, to optimize the fit between the display panel and other components, openings corresponding to the shapes of other components can be designed at the edges or inside the display area. For example, the display panel used in a smartwatch needs to have openings surrounded by the display area so that the watch hands can pass through it. However, to ensure packaging yield, the drive circuit traces adjacent to the openings must be designed to avoid the packaging area. This inevitably reduces the displayable area of ​​the display panel. Therefore, how to increase the displayable area and improve the design margin of the appearance while ensuring packaging yield is a key development focus for manufacturers. Summary of the Invention

[0004] The present invention provides a display panel in which the non-display area at the edge of the hole in the display area has a small configuration space.

[0005] The display panel of the present invention includes a substrate, a plurality of pixel structures, a plurality of first multiplexers, a plurality of second multiplexers, a circuit board, and a plurality of connection traces. The substrate has a display area, a hole disposed within the display area, a first non-display area located between the hole and the display area, and a second non-display area located on the side of the display area away from the hole. The pixel structures are disposed within the display area and include a plurality of first pixel structures and a plurality of second pixel structures. The first pixel structures are disposed on one side of the hole along a first direction, and the second pixel structures are disposed on the other side of the hole along the first direction. The first pixel structures and the second pixel structures overlap along the first direction in the first non-display area. The first multiplexers are disposed within the first non-display area and are electrically connected to the first pixel structures. The second multiplexers are disposed within the second non-display area and are electrically connected to the second pixel structures. The circuit board is electrically bonded to the second non-display area and electrically connects the first multiplexers and the second multiplexers. The connection traces are disposed within the first non-display area and electrically connect the first multiplexers and the circuit board.

[0006] Based on the above, in a display panel according to an embodiment of the present invention, a hole is provided in the display area, and a non-display area is provided between the hole and the display area. Multiple pixel structures located on one side of the hole are electrically connected to a circuit board located on the other side of the hole via multiple connection traces disposed in the non-display area. Multiple multiplexers connecting these pixel structures and these connection traces are provided in the non-display area located on one side of the hole. The arrangement of these multiplexers effectively reduces the number of connection traces and reduces the configuration space required in the non-display area. Attached Figure Description

[0007] Figure 1 This is a top view schematic diagram of a display panel according to an embodiment of the present invention;

[0008] Figure 2 yes Figure 1 An enlarged schematic diagram of a portion of the display panel;

[0009] Figure 3 This is a top view schematic diagram of a display panel according to another embodiment of the present invention;

[0010] Figure 4 This is a top view schematic diagram of a display panel according to another embodiment of the present invention.

[0011] Symbol Explanation

[0012] 10, 10A, 10B: Display panels

[0013] 100, 100A: substrate

[0014] 100h, 100h”: Hole

[0015] 151, 152: Multiplexer

[0016] 210, 220, 210A, 220A: Package patterns

[0017] 300: Circuit board

[0018] 350: Driver chip

[0019] BP: Joint pad

[0020] CH: Signal Channel

[0021] DA, DA": Display area

[0022] D1, D2: Direction

[0023] DL: Data cable

[0024] GL: Scan line

[0025] NDA1, NDA1”: First non-display area

[0026] NDA2, NDA2”: Second non-display area

[0027] P1, P2a, P2b, P2c: Arrangement pitch

[0028] PX, PX1, PX2: Pixel structure

[0029] PXC1, PXC2a, PXC2b, PXC2c, PXC2d, PXC2e: pixel rows

[0030] WR1, WR2, WR1-A, WR2-A: Connecting cables Detailed Implementation

[0031] As used herein, “about,” “approximately,” “essentially,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” “essentially,” or “substantially” herein may be chosen to select a more acceptable range of deviations or standard deviations depending on the nature of the measurement, the cutting nature, or other properties, and a single standard deviation may not be applicable to all properties.

[0032] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, no intermediate elements are present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, an "electrical connection" may involve the presence of other elements between two elements.

[0033] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one figure is flipped, an element described as being "below" to another element will be oriented "above" to that element. Thus, the exemplary term "below" can include both "below" and "above" orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being "below" or "under" another element will be oriented "above" to that element. Thus, the exemplary terms "above" or "below" can include both "above" and "below" orientations.

[0034] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0035] Figure 1 This is a top view schematic diagram of a display panel according to an embodiment of the present invention. Figure 2 yes Figure 1 This is a magnified view of a portion of the display panel. Please refer to... Figure 1 and Figure 2 The display panel 10 includes a substrate 100. The substrate 100 has a display area DA, a hole 100h disposed in the display area DA, a first non-display area NDA1 located between the hole 100h and the display area DA, and a second non-display area NDA2 located on the side of the display area DA away from the hole 100h.

[0036] In this embodiment, the outer contour of the substrate 100 and the inner contour defining the hole 100h are, for example, circular, but not limited thereto. In other embodiments, at least one of the outer and inner contours of the substrate may also be square. The substrate 100 is made of glass, quartz, organic polymer, or other suitable transparent materials.

[0037] In this embodiment, the display area DA, the first non-display area NDA1, and the second non-display area NDA2 are each arranged around the hole 100h, and the display area DA is located between the first non-display area NDA1 and the second non-display area NDA2, but this is not a limitation. An encapsulation pattern 210 is provided in the first non-display area NDA1 closer to the hole 100h, while another encapsulation pattern 220 is provided in the second non-display area NDA2 farther from the hole 100h.

[0038] For example, the display panel 10 may further include another substrate (not shown) overlapping the substrate 100 and a display medium layer (not shown). Encapsulation patterns 210 and 220 each connect the substrate 100 to the other substrate to form a sealed space. The display medium layer is disposed within this sealed space. The display medium layer may be, for example, a liquid crystal layer or a light-emitting diode layer.

[0039] In this embodiment, the materials for the sealing pattern 210 and the encapsulation pattern 220 are, for example, glass frit, and the glass frit may include manganese oxide (MnOx), zinc oxide (ZnO), and magnesium oxide (MgO). However, the invention is not limited thereto. In other embodiments, the materials for the sealing pattern 210 and the encapsulation pattern 220 may also include acrylic resin, epoxy resin, photosensitive polymer materials, or other suitable sealing materials.

[0040] To drive the display medium layer to achieve image display, the display panel 10 also includes multiple pixel structures PX, multiple data lines DL, and multiple scan lines GL disposed within the display area DA. These data lines DL intersect with these scan lines GL and divide the display area DA into multiple pixel regions. Each of these pixel regions is provided with multiple pixel structures PX. In this embodiment, the multiple scan lines GL can be arranged along direction D1 and extend in direction D2, and the multiple data lines DL can be arranged along direction D2 and extend in direction D1. Direction D1 can be selectively perpendicular to direction D2, but is not limited thereto. For conductivity considerations, the data lines DL and scan lines GL are generally made of metallic materials, such as aluminum, copper, molybdenum, chromium, palladium, or alloys thereof, or stacked layers thereof.

[0041] For example, a pixel structure PX may include active elements (not shown) and pixel electrodes (not shown) electrically connected to each other, wherein the active elements are also electrically connected to a data line DL and a scan line GL. When the active elements are turned on, the pixel electrodes electrically connected to them can receive drive signals (e.g., voltage or current) from the circuit board 300 via the data line DL to enable the display medium layer. By individually controlling these pixel structures PX, different parts of the display medium layer can be enabled to the same or different degrees, resulting in different light emission intensities or phase delay modulation, thereby achieving the purpose of displaying images. It should be noted that the components of the pixel structure PX (or pixel circuit) and their configuration may vary depending on the type of display medium layer, and the present invention is not limited thereto.

[0042] In this embodiment, the circuit board 300 is electrically bonded within the second non-display area NDA2. Specifically, the second non-display area NDA2 is provided with a plurality of bonding pads BP, which are arranged along direction D2 in the region of the second non-display area NDA2 closer to the edge of the substrate. The circuit board 300 may include a driver chip 350 and a plurality of signal channels CH, wherein each signal channel CH electrically connected to the driver chip 350 may be bonded to a corresponding bonding pad BP via solder (not shown), but is not limited thereto.

[0043] The multiple pixel structures PX include multiple first pixel structures PX1 and multiple second pixel structures PX2. These first pixel structures PX1 are disposed on one side of the aperture 100h along direction D1. These second pixel structures PX2 are disposed on the other side of the aperture 100h along direction D1, and are located between the aperture 100h (or the first non-display area NDA1) and the second non-display area NDA2. It is particularly noteworthy that these first pixel structures PX1 and second pixel structures PX2 overlap the first non-display area NDA1 along direction D1. Therefore, multiple data lines DL electrically connecting the multiple first pixel structures PX1 or the multiple second pixel structures PX2 cannot extend from one side of the first non-display area NDA1 along direction D1 to the other side of the first non-display area NDA1 along direction D1. That is, any first pixel structure PX1 and any second pixel structure PX2 arranged along direction D1 are electrically independent of each other.

[0044] In this embodiment, to electrically connect these first pixel structures PX1 to the circuit board 300 located in the second non-display area NDA2, the first non-display area NDA1 of the display panel 10 is also provided with multiple connection traces WR1 and multiple first multiplexers 151. These first multiplexers 151 are disposed between the aperture 100h and the multiple first pixel structures PX1. The multiple first pixel structures PX1 arranged along the direction D1 can be electrically connected to a corresponding first multiplexer 151 via the connected data line DL.

[0045] For example, in this embodiment, each first multiplexer 151 can be electrically connected to one connection trace WR1 and three data lines DL connecting multiple first pixel structures PX1, and each connection trace WR1 can be electrically connected to two first multiplexers 151. That is, the number of connection traces WR1 set in the first non-display area NDA1 and the number of data lines DL set in the display area DA and electrically connected to the first pixel structures PX1 correspond to a one-to-six relationship, but this is not a limitation. By setting the first multiplexers 151, the number of connection traces WR1 can be effectively reduced, which helps to reduce the configuration space required for the first non-display area NDA1. In other words, the width of the inner bezel of the display panel 10 can be effectively reduced, thereby improving its screen-to-body ratio.

[0046] It is particularly noteworthy that, in this embodiment, the multiple connection traces WR1 disposed in the first non-display area NDA1 do not overlap with the encapsulation pattern 210 in the direction perpendicular to the surface of the substrate 100. This avoids the connection traces WR1 from peeling off due to high temperatures during the encapsulation process, thus preventing encapsulation failure and improving the encapsulation yield and reliability of the display panel 10.

[0047] Similarly, to electrically connect the multiple second pixel structures PX2 to the circuit board 300 located in the second non-display area NDA2, the second non-display area NDA2 of the display panel 10 is also provided with multiple connection traces WR2 and multiple second multiplexers 152. The multiple second pixel structures PX2 are located between the aperture 100h and these second multiplexers 152. The multiple second pixel structures PX2 arranged along the direction D1 can be electrically connected to a corresponding second multiplexer 152 via the connected data line DL.

[0048] For example, in this embodiment, each second multiplexer 152 can electrically connect one connection trace WR2 and three data lines DL connecting multiple second pixel structures PX2, and each connection trace WR2 can electrically connect two second multiplexers 152. That is, the number of connection traces WR2 set in the second non-display area NDA2 and the number of data lines DL set in the display area DA and electrically connected to the second pixel structures PX2 correspond to a one-to-six relationship, but this is not a limitation. By setting the second multiplexers 152, the number of connection traces WR2 can be effectively reduced, which helps to reduce the configuration space required for the second non-display area NDA2. In other words, the outer bezel width of the display panel 10 can be effectively reduced, thereby improving its screen-to-body ratio.

[0049] For conductivity considerations, the materials used for connecting traces WR1 and WR2 are generally metallic materials, such as aluminum, copper, molybdenum, chromium, palladium, or alloys thereof, or stacked layers thereof.

[0050] In this embodiment, multiple first multiplexers 151 are electrically connected to a portion of the signal channel CH of the circuit board 300 via multiple connection traces WR1, while multiple second multiplexers 152 are electrically connected to another portion of the signal channel CH of the circuit board 300 via multiple connection traces WR2. The multiple connection traces WR1 disposed in the first non-display area NDA1 also extend through portions of the second pixel structures PX2 to the second non-display area NDA2 to electrically connect to the circuit board 300.

[0051] For example, in this embodiment, the connection traces WR1 do not overlap with the second pixel structures PX2 in a direction perpendicular to the surface of the substrate 100. Therefore, the arrangement pitch of the plurality of second pixel structures PX2 along direction D2 is different from the arrangement pitch of the plurality of first pixel structures PX1 along direction D2. Specifically, the plurality of first pixel structures PX1 are arranged into a plurality of pixel rows PXC1 along direction D1, and these pixel rows PXC1 are arranged along direction D2. The plurality of second pixel structures PX2 are arranged into a plurality of pixel rows (e.g., pixel rows PX2a, PXC2b, PXC2c, PXC2d, and PXC2e) along direction D1, and these pixel rows are arranged along direction D2.

[0052] In this embodiment, pixel rows PXC2a and PXC2b have an arrangement pitch P2a along direction D2, and any two adjacent pixel rows PXC1 have an arrangement pitch P1 along direction D2, and the arrangement pitch P1 is different from the arrangement pitch P2a. Furthermore, a connecting trace WR1 is provided between pixel rows PXC2b and PXC2c located between the first non-display area NDA1 and the second non-display area NDA2. Therefore, pixel rows PXC2b and PXC2c have an arrangement pitch P2b along direction D2, and this arrangement pitch P2b is different from the arrangement pitch P2a between pixel rows PXC2a and PXC2b and the arrangement pitch P1 between multiple pixel rows PXC1.

[0053] On the other hand, two connecting traces WR1 are provided between pixel row PXC2d and pixel row PXC2e. Therefore, pixel row PXC2d and pixel row PXC2e have an arrangement pitch P2c along direction D2, and this arrangement pitch P2c is different from the arrangement pitch P2a between pixel row PXC2a and pixel row PXC2b, the arrangement pitch P2b between pixel row PXC2b and pixel row PXC2c, and the arrangement pitch P1 between multiple pixel rows PXC1.

[0054] However, the present invention is not limited thereto. According to other embodiments, the connecting trace WR1 may overlap with a plurality of second pixel structures PX2 in a direction perpendicular to the surface of the substrate 100. Therefore, the arrangement pitch of the plurality of first pixel structures PX1 along direction D2 may be equal to the arrangement pitch of the plurality of second pixel structures PX2 along direction D2.

[0055] Figure 3 This is a top view schematic diagram of a display panel according to another embodiment of the present invention. Please refer to... Figure 3 The display panel 10A in this embodiment and Figure 2 The difference between the display panels 10 and 10A lies in the number of connecting traces. In this embodiment, the number of connecting traces in both the first non-display area NDA1 and the second non-display area NDA2 of the display panel 10A is [number missing]. Figure 2 The number of connection traces is half of the total number of traces. For example, the number of connection traces WR1-A in the first non-display area NDA1 of display panel 10A is half of the total number of traces. Figure 2 The four lines shown are reduced to two, and the number of WR2-A connection traces in the second non-display area NDA2 is reduced from... Figure 2 The six lines shown have been reduced to three.

[0056] To further reduce the number of connection traces, each connection trace is electrically connected to four multiplexers. In other words, the number of connection traces WR1-A located in the first non-display area NDA1 corresponds to the number of data lines DL located in the display area DA and electrically connected to the first pixel structure PX1 in a one-to-twelve relationship. Similarly, the number of connection traces WR2-A located in the second non-display area NDA2 corresponds to the number of data lines DL located in the display area DA and electrically connected to the second pixel structure PX2 in a one-to-twelve relationship. Accordingly, the configuration space required for the first non-display area NDA1 and the second non-display area NDA2 can be further reduced, which helps to improve the screen-to-body ratio of the display panel 10A.

[0057] Figure 4 This is a top view schematic diagram of a display panel according to another embodiment of the present invention. Please refer to... Figure 4 The display panel 10B in this embodiment and Figure 1 The difference in display panel 10 lies in the different configuration of the holes. Unlike... Figure 1 The hole 100h of the display panel 10 is a closed hole, while the hole 100h” of the display panel 10B in this embodiment is an open hole. For example, the hole 100h” of the substrate 100A disconnects the display area DA” on one side along the direction D1. That is, the display area DA”, the first non-display area NDA1” and the second non-display area NDA2” in this embodiment are not arranged around the hole 100h”.

[0058] In detail, in this embodiment, the first non-display area NDA1” is connected to the second non-display area NDA2” and surrounds the display area DA”. Therefore, the encapsulation pattern 210A disposed in the first non-display area NDA1” is connected to the encapsulation pattern 220A disposed in the second non-display area NDA2” and surrounds the display area DA”.

[0059] Since the multiplexer and connection wiring configuration in this embodiment are similar to those in other embodiments... Figure 2 For a detailed description of the display panel 10, please refer to the relevant paragraphs and corresponding figures in the foregoing embodiments, which will not be repeated here.

[0060] In summary, in a display panel according to an embodiment of the present invention, a hole is provided in the display area, and a non-display area is provided between the hole and the display area. Multiple pixel structures located on one side of the hole are electrically connected to a circuit board located on the other side of the hole via multiple connection traces disposed in the non-display area. Multiple multiplexers connecting these pixel structures and these connection traces are provided in the non-display area located on one side of the hole. The arrangement of these multiplexers effectively reduces the number of connection traces and reduces the configuration space required in the non-display area.

Claims

1. A display panel, comprising: A substrate has a display area, a hole disposed in the display area, a first non-display area located between the hole and the display area, and a second non-display area located on the side of the display area away from the hole, wherein the first non-display area is adjacent to the hole. Multiple pixel structures are disposed within the display area, including multiple first pixel structures and multiple second pixel structures. The first pixel structures are disposed on one side of the hole along the first direction, and the second pixel structures are disposed on the other side of the hole along the first direction. The first pixel structures and the second pixel structures overlap the first non-display area along the first direction. Multiple first multiplexers are disposed within the first non-display area and are electrically connected to the first pixel structures; Multiple second multiplexers are disposed within the second non-display area and are electrically connected to the second pixel structures; The circuit board is electrically bonded to the second non-display area and electrically connected to the first multiplexers and the second multiplexers; and Multiple connection traces are disposed within the first non-display area and electrically connect the first multiplexers and the circuit board. Each of the connection traces has multiple branch portions, curved portions, and straight portions that are closer to the second non-display area than the first multiplexers in the first direction. The curved portion is located between the branch portions and the straight portion in the first direction, and the connection point between the straight portion and the curved portion has a first turning point located within the first non-display area. This first turning point is located on the side of the hole closest to the second non-display area and overlaps the hole along the first direction. The connection point between the branch portions and the curved portion has a second turning point located within the first non-display area. Each branch portion is directly connected to the second turning point and one of the first multiplexers.

2. The display panel as claimed in claim 1, wherein the first pixel structures are arranged in a plurality of first pixel rows along the first direction, the second pixel structures are arranged in a plurality of second pixel rows along the first direction, the arrangement pitch of the first pixel rows along the second direction is different from the arrangement pitch of the second pixel rows along the second direction, and the second direction intersects the first direction.

3. The display panel of claim 1, wherein the circuit board has a driver chip and a plurality of signal channels, a portion of the signal channels being electrically connected to the second multiplexers and the driver chip, and another portion of the signal channels being electrically connected to the first multiplexers and the driver chip.

4. The display panel as claimed in claim 1, further comprising an encapsulation pattern disposed within the first non-display area and surrounding the hole.

5. The display panel of claim 4, wherein the connection traces do not overlap the encapsulation pattern.

6. The display panel of claim 1, wherein the first multiplexers are located between the aperture and the first pixel structures, and the second pixel structures are located between the aperture and the second multiplexers.

7. The display panel of claim 1, wherein the connection traces extend to the second non-display area via portions of the second pixel structures.

8. The display panel of claim 7, wherein the connection traces do not overlap the second pixel structures.

9. The display panel of claim 7, wherein the second pixel structures are arranged in a plurality of pixel rows along a first direction, the pixel rows are arranged between the first non-display area and the second non-display area along a second direction, the pixel rows include a first pixel row, a second pixel row and a third pixel row that are adjacent to each other, and the first arrangement pitch between the first pixel row and the second pixel row is different from the second arrangement pitch between the second pixel row and the third pixel row.

10. The display panel of claim 9, wherein the pixel rows further include a fourth pixel row and a fifth pixel row adjacent to each other, the third arrangement pitch between the fourth pixel row and the fifth pixel row being different from the first arrangement pitch and the second arrangement pitch.

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