Gate driver and display device using the same

Abstract

Gate driver and display device using the same. Disclosed are a gate driver according to an embodiment and a display device using the same. The gate driver according to an embodiment includes a plurality of signal transmission units cascaded via a carry line, and a carry signal is applied to the carry line from a preceding signal transmission unit, wherein an nth signal transmission unit (where n is a positive integer) includes a circuit unit configured to receive a carry signal from a preceding signal transmission unit to charge or discharge a first control node and a second control node, an output unit configured to output a carry signal and a gate signal based on the potentials of the first control node and the second control node, and a row selection unit configured to charge an M node to a high potential voltage according to a display mode, and to charge the first control node to a high potential voltage based on the charged voltage of the M node and a sensing start signal according to a sensing mode after the display mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0090010, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0186054, filed on December 23, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a gating driver and a display device using the gating driver. Background Technology

[0004] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDP), etc.

[0005] Electroluminescent display devices are classified into inorganic and organic light-emitting display devices based on the material of their light-emitting layer. Active-matrix organic light-emitting display devices use self-emissive elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs") to reproduce input images. The advantages of organic light-emitting display devices include fast response time, high luminous efficiency, brightness, and wide viewing angle.

[0006] Some display devices (such as liquid crystal displays or organic light-emitting displays) include: a display panel having multiple sub-pixels; a driver that outputs drive signals for driving the display panel; and a power supply that generates power to provide power to the display panel or the driver. Drivers include gating drivers that provide scan signals or gating signals to the display panel, and data drivers that provide data signals to the display panel.

[0007] In such a display device, when drive signals such as scan signals, EM signals and data signals are provided to multiple sub-pixels formed in the display panel, the selected sub-pixels transmit light or emit light directly, thereby displaying an image.

[0008] Each subpixel includes a driving thin-film transistor (TFT) that controls the current flowing through the light-emitting element and one or more switching TFTs that switch the current. In this case, degradation may occur due to prolonged driving of the driving TFTs, and a current-sensing-based compensation method is applied to compensate for this degradation. However, the current-sensing-based compensation method is performed when the user is not viewing the image, but it has the drawback of identifying the organic light-emitting diode (OLED) as a light-emitting structure. Summary of the Invention

[0009] This disclosure aims to address all the aforementioned necessities and problems.

[0010] This disclosure aims to provide a gating driver configured to prevent light emission from a light-emitting element in sensing mode, and a display device using the gating driver.

[0011] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0012] The gating driver according to this disclosure includes a plurality of signal transmission units cascaded via carry lines, applying a carry signal from a preceding signal transmission unit to a carry line, wherein the nth signal transmission unit (where n is a positive integer) includes: a circuit unit configured to receive the carry signal from the preceding signal transmission unit to charge or discharge a first control node and a second control node; an output unit configured to output a carry signal and a gating signal based on the potentials of the first control node and the second control node; and a row selection unit configured to charge an M node to a high potential voltage according to a display mode, and to charge the first control node to a high potential voltage based on the charging voltage of the M node and a sensing start signal according to a sensing mode following the display mode.

[0013] In another aspect, a display device according to the present disclosure includes: a display panel having a plurality of data lines, a plurality of gating lines intersecting the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels; a data driver configured to provide a data voltage for pixel data to the data lines; and a gating driver configured to provide gating signals to the gating lines, wherein the gating driver includes a plurality of signal transmission units cascaded via carry lines, applying a carry signal from a preceding signal transmission unit to the carry line, wherein the nth signal transmission unit (where n is a positive integer) includes: a circuit unit configured to receive the carry signal from the preceding signal transmission unit to charge or discharge a first control node and a second control node; an output unit configured to output the carry signal and the gating signal based on the potentials of the first control node and the second control node; and a row selection unit configured to charge an M node to a high potential voltage according to a display mode, and to charge the first control node to a high potential voltage based on the charging voltage of the M node and a sensing start signal according to a sensing mode following the display mode.

[0014] In this disclosure, multiple scan lines can be selected simultaneously by charging the M node of the signal transmission unit connected to the scan line to be selected to a high potential voltage before driving in sensing mode.

[0015] In this disclosure, when driven in sensing mode, a high-voltage scanning signal is output to sense the current flowing through the pixel drive voltage line, and a current path is formed by using a path that bypasses the light-emitting element, thereby suppressing the light emission of the light-emitting element.

[0016] In this disclosure, when driven in sensing mode, the visibility problem is solved because the light emission of the light-emitting element is suppressed.

[0017] The effects of the present invention are not limited to those described above, and those skilled in the art will clearly understand other unmentioned effects through the description of the claims. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0020] Figure 2 This is an example Figure 1 A diagram showing the cross-sectional structure of the display panel;

[0021] Figure 3 This is a circuit diagram illustrating a pixel circuit connected to an external compensation circuit according to the present disclosure;

[0022] Figures 4 to 8 This is a diagram used to illustrate the operating principle of the sensing circuit according to the embodiment;

[0023] Figure 9 This is a diagram illustrating a driving method according to a pattern based on an embodiment of this disclosure;

[0024] Figure 10 This is a diagram illustrating a shift register of a strobe driver according to an embodiment of the present disclosure;

[0025] Figure 11 This is a diagram illustrating a gating driver according to a first embodiment of the present disclosure;

[0026] Figure 12A and Figure 12B It is used for comparative explanation Figure 11 A diagram showing the construction of a line selection unit;

[0027] Figure 13 This is an example Figure 11 The waveforms of the input / output signals and voltages of the control node of the gating driver are shown.

[0028] Figures 14A to 14D This is a diagram illustrating the selection of pixel rows using a row selection signal;

[0029] Figure 15 This diagram illustrates the principle of selecting a sensing area from rows of pixels.

[0030] Figure 16 It is used to explain how to prevent Figure 10 The diagram shows the principle of leakage current in the line selection unit.

[0031] Figure 17 A diagram illustrating a gating driver according to a second embodiment of the present disclosure; and

[0032] Figure 18 It is used to explain how to prevent Figure 17 The diagram shows the principle of leakage current in the row selection unit. Detailed Implementation

[0033] The advantages and features of this disclosure and its implementation methods will become clearer from the following description of embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope. This disclosure is limited only by the scope of the appended claims.

[0034] The shapes, dimensions, scales, angles, quantities, etc., illustrated in the accompanying drawings for the purpose of describing embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally refer to similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0035] Terms such as “comprising,” “including,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0036] Even if not explicitly mentioned, the component is interpreted as including the normal tolerance range.

[0037] When using terms such as “above,” “over,” “below,” and “under,” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used in conjunction with the terms “close to” or “directly.”

[0038] The terms “first”, “second”, etc. can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding it.

[0039] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0040] The following implementation methods can be combined or integrated with each other in part or in whole, and can be linked and operated in various ways. These implementation methods can be performed independently or in relation to each other.

[0041] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 2 This is an example Figure 1 The diagram shows the cross-sectional structure of the display panel.

[0043] Reference Figure 1 and Figure 2 The display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0044] Display panel 100 may be a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. Display panel 100 includes a pixel array AA for displaying an input image. Pixel array AA includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. Display panel 100 may also include power lines commonly connected to the pixels. Power lines may include a power line applying a pixel driving voltage ELVDD, a power line applying an initial voltage Vinit, a power line applying a reference voltage Vref, and a power line applying a low-potential power supply voltage ELVSS. These power lines are commonly connected to the pixels.

[0045] The pixel array AA comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Subpixels arranged along the data line direction Y share the same data line 102. A horizontal time period 1H is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0046] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device that displays images on a screen and allows the actual background to be seen.

[0047] The display panel 100 can be a flexible display panel. The flexible display panel can be made of a plastic OLED panel. An organic thin film can be disposed on the back of the plastic OLED panel, and the pixel array AA and the light-emitting elements can be formed on the organic thin film.

[0048] To achieve color, each pixel 101 can be divided into red subpixels (hereinafter referred to as "R subpixels"), green subpixels (hereinafter referred to as "G subpixels"), and blue subpixels (hereinafter referred to as "B subpixels"). Each pixel may also include a white subpixel. Each subpixel includes pixel circuitry. The pixel circuitry is connected to data lines, gating lines, and power lines.

[0049] Pixels can be arranged as true-color pixels and pentile pixels. Pentile pixels can achieve higher resolution than true-color pixels by using a preset pixel rendering algorithm to drive two sub-pixels of different colors as a single pixel 101. The pixel rendering algorithm can use the colors of light emitted from neighboring pixels to compensate for insufficient color reproduction in each pixel.

[0050] A touch sensor can be located on the display panel 100. Touch input can be sensed using a separate touch sensor, or it can be sensed by pixels. The touch sensor can be configured as an on-cell or add-on type on the screen of the display panel, or implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0051] like Figure 2 As shown, when viewed in cross-section, the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0052] Circuit layer 12 may include pixel circuitry connected to wiring such as data lines, gating lines, and power lines, gating drivers (GIPs) connected to gating lines, etc. The wiring and circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers, and active layers comprising semiconductor materials.

[0053] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a protective layer comprising an organic film and a passivation film.

[0054] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating structure in which organic and inorganic films are alternately stacked. Inorganic films block the penetration of moisture and oxygen. Organic films planarize the surface of inorganic films. When organic and inorganic films are stacked in multiple layers, the movement path of moisture or oxygen becomes longer compared to a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0055] A touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wiring pattern forming the capacitor of the touch sensor and an insulating layer. The capacitor of the touch sensor may be formed between the metal wiring patterns. A polarizer may be disposed on the touch sensor layer. The polarizer can improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and circuit layer 12. The polarizer may be implemented as a polarizer in which a linear polarizer and a phase retardation film are bonded, or a circular polarizer. A cover glass may be adhered to the polarizer.

[0056] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include a red color filter, a green color filter, a blue color filter, and a black matrix pattern. The color filter layer can replace a polarizer and increases color purity by absorbing certain wavelengths of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a filter layer 20 with higher transmittance than a polarizer to the display panel, the transmittance of the display panel PNL can be improved, as can the thickness and flexibility of the display panel PNL. A cover glass may be adhered to the color filter layer.

[0057] Power supply 140 generates the DC power required to drive the pixel array AA and display panel driver of display panel 100 via a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 140 can adjust the DC input voltage from a host system (not shown) and thereby generate DC voltages such as gamma reference voltage VGMA, gate on-state voltages VGH and VEH, gate off-state voltages VGL and VEL, pixel drive voltage EVDD, pixel low-level supply voltage EVSS, reference voltage Vref, initial voltage Vinit, anode voltage Vano, etc. Gamma reference voltage VGMA is provided to data driver 110. Gate on-state voltages VGH and VEH, and gate off-state voltages VGL and VEL are provided to gating driver 120. Pixel drive voltage EVDD, pixel low-level supply voltage EVSS, reference voltage Vref, initial voltage Vinit, anode voltage Vano, etc., are collectively provided to the pixels.

[0058] The display panel driver, under the control of the timing controller (TCON) 130, writes the pixel data (digital data) of the input image into the pixels of the display panel 100.

[0059] The display panel driver includes a data driver 110 and a strobe driver 120. The display panel driver may also include a demultiplexer array 112 disposed between the data line 102 and the data driver 110.

[0060] The demultiplexer array 112 uses multiple demultiplexers (DEMUX) to sequentially supply data voltages output from the channels of the data driver 110 to the data lines 102. The demultiplexers may include multiple switching elements disposed on the display panel 100. When the demultiplexers are disposed between the output of the data driver 110 and the data lines 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0061] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The touch sensor driver can be integrated into a single driver integrated circuit (IC). In mobile or wearable devices, the timing controller 130, power supply 140, data driver 110, touch sensor driver, etc., can be integrated into a single driver integrated circuit (IC).

[0062] The display panel driver can operate in a low-speed drive mode under the control of the timing controller (TCON) 130. The low-speed drive mode can be configured to reduce the power consumption of the display device when there is no change in the input image for a preset number of frames during input image analysis. In low-speed drive mode, when an input still image persists for a predetermined time or longer, the power consumption of the display panel driver circuit and the display panel 100 can be reduced by decreasing the pixel refresh rate. The low-speed drive mode is not limited to the case of an input still image. For example, the display panel driver can operate in low-speed drive mode when the display device is operating in standby mode, or when no user command is input to the display panel driver or an input image persists for a predetermined time or longer.

[0063] Data driver 110 generates a data voltage Vdata by converting pixel data of the input image received from timing controller 130 using a digital-to-analog converter (DAC) with a gamma compensation voltage in each frame period. The gamma reference voltage VGMA is divided for each grayscale level by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of data driver 110. The data voltage Vdata is output through the output buffer AMP in each channel of data driver 110.

[0064] The gate driver 120 can be implemented as an in-panel gate (GIP) circuit directly formed on the circuit layer 12 of the display panel 100 along with the TFT array of the pixel array AA. The in-panel gate (GIP) circuit can be disposed on the bezel area BZ, which is a non-display area of ​​the display panel 100, or distributed among the pixel array that reproduces the input image. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the gate line 103. The gate driver 120 can sequentially provide gate signals to the gate line 103 by shifting the gate signals using a shift register. The gate signals may include scan pulses, light emission control pulses (hereinafter referred to as "EM pulses"), initial pulses, and sensing pulses.

[0065] The shift register of the strobe driver 120 responds to the start pulse and shift clock from the timing controller 130, outputs a strobe signal pulse, and shifts the pulse according to the shift clock timing.

[0066] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with it from the host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal time period (1H).

[0067] The host system can be any of a television (TV) system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, or vehicle system. The host system can scale the image signal from the video source according to the resolution of the display panel 100 and send the image signal along with a timing signal to the timing controller 130.

[0068] The timing controller 130 multiplies the input frame rate by i, using a frame rate of input frame rate × i (where i is a positive integer greater than 0) Hz to control the timing of the display panel driver circuit. The input frame rate is 60Hz in the NTSC (National Television Standards Committee) scheme and 50Hz in the PAL (Phase Alternating Horizontal Inversion) scheme. In low-speed drive mode, the timing controller 130 can reduce the drive frequency of the display panel driver by lowering the frame rate to a frequency between 1Hz and 30Hz, thereby reducing the pixel refresh rate.

[0069] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gating timing control signal for controlling the operation timing of the gating driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gating driver 120.

[0070] The voltage level of the gating timing control signal output from the timing controller 130 can be converted into gate on-state voltages VGH and VEH and gate off-state voltages VGL and VEL by a level shifter (not shown), and then provided to the gating driver 120. That is, the level shifter converts the low-level voltage of the gating timing control signal into the gate off-state voltages VGL and VEL, and the high-level voltage of the gating timing control signal into the gate on-state voltages VGH and VEH. The gating timing signal includes a start pulse and a shift clock.

[0071] Due to process variations and device characteristic variations during the manufacturing of the display panel 100, differences in the electrical characteristics of the driving elements may exist between pixels, and these differences can increase over time as the pixels are driven. Internal or external compensation techniques can be applied to organic light-emitting diode (OLED) displays to compensate for these variations in the electrical characteristics of the driving elements between pixels. Internal compensation techniques use an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage of the driving element for each sub-pixel, compensating for the gate-source voltage Vgs of the driving element as much as the threshold voltage. External compensation techniques use an external compensation circuit to sense in real-time the current or voltage of the driving element that varies according to its electrical characteristics. External compensation techniques compensate for these variations in the electrical characteristics of the driving elements in each pixel in real-time by modulating the pixel data (digital data) of the input image as much as the sensed variations (or changes) in the electrical characteristics of the driving element for each pixel. The display panel driver can use external or internal compensation techniques to drive the pixels.

[0072] Figure 3 This is a circuit diagram illustrating the pixel circuit of the present disclosure connected to an external compensation circuit.

[0073] Reference Figure 3 The pixel circuit includes a light-emitting element EL, a driving element DT that provides current to the light-emitting element EL, a first switching element M01 that connects to the data line 40 in response to the scan pulse SCAN, a capacitor Cst connected to the gate of the driving element DT, and a second switching element M02 that connects to the reference voltage line 43 in response to the sensing pulse SENSE.

[0074] The pixel driving voltage EVDD is applied to the first electrode of the driving element DT through the first power supply line 41. The driving element DT drives the light-emitting element OLED by providing current to the light-emitting element OLED according to the gate-source voltage Vgs. When the forward voltage between the anode and cathode is greater than or equal to the threshold voltage, the light-emitting element OLED turns on and emits light. A low-potential power supply voltage ELVSS is applied to the cathode of the light-emitting element EL. A capacitor Cst is connected between the gate and the second electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0075] The first switching element M01 is turned on according to the gate turn-on voltage of the scan pulse SCAN applied from the gate line, and connects the data line 40 to the gate of the drive element DT and the capacitor Cst.

[0076] The second switching element M02 applies a reference voltage Vref in response to a scan pulse SCAN or a separate sensing pulse SENSE. The reference voltage Vref is applied to the pixel circuit through reference voltage line 43.

[0077] The light-emitting element (EL) can be implemented as an OLED. An OLED includes an organic compound layer formed between the anode and cathode. This organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The switching elements M01 and M02 can be implemented as n-channel oxide thin-film transistors (TFTs).

[0078] Organic light-emitting diodes (OLEDs) used as light-emitting elements can have a series structure with multiple light-emitting layers stacked on top of each other. OLEDs with a series structure can improve pixel brightness and lifespan.

[0079] In sensing mode, the current flowing through the channel of the driving element DT, or the voltage between the driving element DT and the light-emitting element OLED, is sensed via reference voltage line 43. The current flowing through reference voltage line 43 is converted into voltage by an integrator and then into digital data by an analog-to-digital converter (ADC). This digital data is sensing data that includes threshold voltage or mobility information of the driving element DT. The sensing data is sent to the data operation unit. The data operation unit can receive the sensing data from the ADC to compensate for pixel drive deviations and degradation by adding or multiplying a compensation value selected based on the sensing data to the pixel data.

[0080] Figures 4 to 8 This is a diagram used to illustrate the operating principle of the sensing circuit according to the embodiment.

[0081] Reference Figure 4The chip-on-film (COF) can be adhered to the display panel PNL. The COF includes a driver IC (SIC) and connects the source PCB (SPCB) to the display panel PNL. The driver IC (SIC) includes a data driver.

[0082] The timing controller 130 and the power supply unit 150 can be mounted on the control PCB CPCB. The control PCB CPCB can be connected to the source PCB SPCB via a flexible circuit film (e.g., flexible printed circuit (FPC)).

[0083] The timing controller 130 can adjust the reference voltage Vref output from the power supply unit 150 based on the result of comparing the reference voltage Vref_sensed from the display panel PNL with the reference voltage Vref output from the power supply unit 150, including the aforementioned reference voltage controller.

[0084] The reference voltage Vref output from the power supply unit 150 can be supplied to the display panel PNL via the FPC, source PCB SPCB, and COF. Therefore, in the display panel PNL, the input portion IN of the reference voltage Vref is close to the driver IC SIC.

[0085] Reference voltage lines REFL on the display panel PNL can be connected to the power supply unit 150 via COF, SPCB, and FPC. Reference voltage lines REFL can be grouped by shorting bars SB. The shorting bars can be formed on one side of the display panel PNL and can be formed as lines on the display panel instead of the glass overlay (LOG) in the driver IC SIC. Reference voltage lines REFL connected to all pixels on the display panel PNL can be connected to the shorting bars.

[0086] When the sensing unit 160 is driven in sensing mode after the power is off, it senses the current flowing through the pixel power line to which a high potential voltage EVDD is applied. The sensing unit 160 provides the sensed current to the timing controller 130.

[0087] Reference Figure 5 The sensing unit may include a resistor connected to the pixel power line and an analog-to-digital converter (ADC) connected to the resistor. The sensing unit may also include a switch connected between the pixel power line and the resistor. The switch is off in display mode and on in sensing mode.

[0088] When switch SW is off in display mode, a high-potential voltage EVDD is applied to pixel PXL through the pixel power line. When switch SW is on in sensing mode, a high-potential voltage is applied to the pixel through the pixel power line and resistor R, and the current flowing through the resistor is sensed.

[0089] Reference Figure 6The sensing unit senses current in units of blocks comprising a predetermined number of pixels. Here, the block can be a square shape in which the number of pixels in the row direction X and the number of pixels in the column direction Y are the same, for example, a square shape of 30 pixels × 30 pixels. The block is not limited to a square shape and can be implemented in various shapes.

[0090] The sensing unit senses current in blocks, and senses the current flowing through each block in a predetermined order. Different currents are sensed depending on the characteristics and degradation level of the pixels included in each block.

[0091] Compared to methods that sense current on a pixel-by-pixel basis, methods that sense current on a block-by-block basis can reduce the overall sensing time and can be implemented with a simpler structure.

[0092] Reference Figure 7A In this embodiment, when driven in sensing mode, the gate-on voltage of the scan pulse SCAN is applied to the first switching element M01 and the second switching element M02. The first and second switching elements turn on after the applied gate-on voltage to form a current path through which the current flowing through the pixel driving voltage line 41 flows to the reference voltage line 43 instead of to the light-emitting element. Therefore, current sensing can be performed without light being emitted from the light-emitting element.

[0093] Reference Figure 7B In a comparative example, in sensing mode, the gate cutoff voltage of the scan pulse SCAN is applied to the first switching element M01 and the second switching element M02. Since the first and second switching elements are turned off when the gate cutoff voltage is applied, the current flowing through the pixel drive voltage line 41 is applied to the light-emitting element, which emits light. When the light-emitting element emits light after power is off, the user can identify the light.

[0094] Therefore, in this embodiment, the current flowing through the pixel power line can be measured by driving both the first and second switching elements and changing the current path when driven in sensing mode, without causing the light-emitting element to emit light.

[0095] Reference Figure 8 This embodiment illustrates a pixel structure for sensing current on a block-by-block basis. Reference voltage lines and high-potential voltage lines are connected to all pixels on the display panel for sharing, and data voltage lines are connected to each pixel in the column direction Y.

[0096] Therefore, even when both the reference voltage and the high-potential voltage are applied to all pixels on the display panel, the block to be sensed can be selected based on whether data is applied. For example, white data can be applied to all pixels in the first block ONBLK where sensing is performed, and black data can be applied to all pixels in the second block OFFBLK where sensing is not performed.

[0097] Here, white data is applied to one block on the display panel, and black data is applied to the remaining blocks.

[0098] When white data is applied to all pixels in the first block to be sensed, the sensing unit senses the current flowing through the pixel drive voltage lines. In this case, since the current flowing through the pixel drive voltage lines has a large value on a block-by-block basis, an integrator is not required in the sensing unit.

[0099] Figure 9 This is a diagram used to describe a pattern-based driving method according to an embodiment of the present disclosure.

[0100] Reference Figure 9 When driven in display mode, the strobe driver can sequentially output scan signals, and the data driver can output image data to display the image.

[0101] When driven in sensing mode after power failure, the gating driver outputs a high-voltage scan pulse to the sensing area and a low-voltage scan pulse to the non-sensing area. The data driver outputs white data or sensing data to the block to be sensed (i.e., the sensing area) and black data to the block not being sensed (i.e., the non-sensing area) to sense current without causing the block to be sensed to emit light.

[0102] Figure 10 This is a view illustrating the shift register of a strobe driver according to an embodiment of the present disclosure.

[0103] Reference Figure 10 According to the embodiment, the gating driver 120 includes a plurality of signal processing units ST1, ST2, ST3, ST4 and ST5 cascaded via carry lines, which transmit carry signals via carry lines.

[0104] The timing controller 130 can use the start pulse Vst input to the gating driver 120 to adjust the width and multiple outputs of the gating driver's output signal SC_OUT.

[0105] Each of the signal processing units ST1, ST2, ST3, ST4, and ST5 receives clock signals CLK1, CLK2, CLK3, and CLK4, as well as a start pulse or a carry signal output from the preceding odd-numbered or even-numbered signal processing unit. The first signal processing unit ST1 is driven starting from the start pulse Vst, and the other signal processing units ST2, ST3, ST4, and ST5 receive the carry signals from the preceding odd-numbered or even-numbered signal processing units and begin to be driven.

[0106] Each of the signal processing units ST1, ST2, ST3, ST4, and ST5 outputs scan signals sequentially by shifting the carry signal output by the starting pulse or the odd- or even-numbered signal processing unit preceding it, according to the timing of the clock signal.

[0107] Figure 11 This is a diagram illustrating a gating driver according to a first embodiment of the present disclosure. Figure 12A and Figure 12B It is used for comparative description Figure 11 The diagram shows the construction of the row selection unit, and Figure 13 This is an example Figure 11 The waveforms of the input / output signals and voltages of the control node of the gating driver are shown.

[0108] Reference Figure 11 and Figure 12A and Figure 12B The gating driver according to the first embodiment of the present disclosure may include a first control node for pulling up the output voltage (hereinafter referred to as the "Q node"), a second control node for pulling down the output voltage (hereinafter referred to as the "Qb node"), a row selection unit 61, a circuit unit 62, and an output unit 63.

[0109] The row selection unit 61 charges the M node to a high potential voltage GVDD according to the display mode, and according to the sensing mode after the display mode, the Q node Q can be charged to a high potential voltage based on the charging voltage of the M node and the sensing start signal RESET.

[0110] The row selection unit 61 may include a first transistor TV1, a second transistor TA, a third transistor TV2, a fourth transistor T1B, a fifth transistor T1C, and a first capacitor C1.

[0111] The first transistor TV1 is turned on by the carry signal C(n) and, together with the second transistor TA, charges node M to the high potential voltage of the high potential voltage line GVDD. The first transistor TV1 includes a first electrode connected to the high potential voltage line GVDD, a gate to which the carry signal C(n) is applied, and a second electrode connected to the first electrode of the second transistor TA.

[0112] The second transistor TA is turned on by a row selection signal (row selection pulse, LSP) and, together with the first transistor TV1, charges the M node to the high potential voltage of the high potential voltage line GVDD. The second transistor TA includes a first electrode connected to the second electrode of the first transistor TV1, a gate to which the row selection signal is applied, and a second electrode connected to the M node.

[0113] The third transistor TV2 is turned on by the start signal VST and discharges node M to the low potential voltage of the second low potential voltage line GVSS2. The third transistor TV2 includes a first electrode connected to node M, a gate to which the start signal is applied, and a second electrode connected to the low potential voltage line GVSS2.

[0114] The fourth transistor T1B is turned on through the M node and, together with the fifth transistor T1C, charges the Q node Q to the high potential voltage of the high potential voltage line GVDD. The fourth transistor T1B includes a first electrode connected to the high potential voltage line GVDD, a gate connected to the M node, and a second electrode connected to the first electrode of the fifth transistor T1C.

[0115] The fifth transistor T1C is turned on by sensing the start signal RESET, and together with the fourth transistor T1B, charges the Q node Q to the high potential voltage of the high potential voltage line GVDD. The fifth transistor T1C includes a first electrode connected to the second electrode of the fourth transistor T1B, a gate to which the sensing start signal RESET is applied, and a second electrode connected to the Q node Q.

[0116] The first capacitor C1 is connected between the high-potential voltage line GVDD and node M, and stores the high-potential voltage applied to node M.

[0117] In this embodiment, the M node is charged to a high potential voltage, and the M node being charged to a high potential voltage allows multiple rows to be selected when driven in sensing mode.

[0118] In other words, referencing Figure 12A and Figure 12B ,exist Figure 12A In the implementation, when a carry signal and a row selection signal are applied simultaneously, since the M node is charged to a high potential voltage GVDD, when the next row is selected, the charging voltage of the M node is maintained regardless of whether the carry signal is at a high voltage level or a low voltage level, when both the carry signal and the row selection signal are applied.

[0119] However, in Figure 12BIn the comparative example, when the row selection signal is applied, since node M is charged to the high voltage level of the carry signal, when the next row is selected, the charging voltage of node M is not maintained and it is discharged due to the low voltage level of the carry signal.

[0120] The circuit unit 62 may include a first circuit unit 62-1 and a second circuit unit 62-2.

[0121] The first circuit unit 62-1 is used to control the charging and discharging of Q node Q and Qb node Qb. The first circuit unit 62-1 includes the eighth transistor T1, the ninth transistor T1A, the tenth transistor T3, the eleventh transistor T3A, the twelfth transistor T3n, the thirteenth transistor T3nA, the fourteenth transistor T3q, the fifteenth transistor T3nB, and the sixteenth transistor T3nC.

[0122] The eighth transistor T1 is turned on by the (N-2)th carry signal applied via the (N-2)th carry signal line C(n-2), and transmits the (N-2)th carry signal to node Qh. In the eighth transistor T1, the gate and the first electrode are connected to the (N-2)th carry signal line C(n-2), while the second electrode is connected to node Qh.

[0123] The ninth transistor T1A is turned on by the (N-2)th carry signal applied via the (N-2)th carry signal line C(n-2), and charges the Q node Q based on the (N-2)th carry signal. In the ninth transistor T1A, the gate is connected to the (N-2)th carry signal line C(n-2), the first electrode is connected to the second electrode of the eighth transistor T1, and the second electrode is connected to the Q node Q.

[0124] The tenth transistor T3 is turned on through node Qb and, together with the eleventh transistor T3A, discharges node Q to the second low potential voltage of the second low potential voltage line GVSS2. In the tenth transistor T3, the gate is connected to node Qb, the first electrode is connected to node Q, and the second electrode is connected to the first electrode of the eleventh transistor T3A.

[0125] The eleventh transistor T3A is turned on through node Qb and, together with the tenth transistor T3, discharges node Q to the second low potential voltage of the second low potential voltage line GVSS2. In the eleventh transistor T3A, the gate is connected to node Qb, the first electrode is connected to the second electrode of the tenth transistor T3, and the second electrode is connected to the second low potential voltage line GVSS2.

[0126] The twelfth transistor T3n is turned on by the N+2 carry signal applied via the N+2 carry signal line C(n+2), and together with the thirteenth transistor T3nA, discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS2. In the twelfth transistor T3n, the gate is connected to the N+2 carry signal line C(n+2), the first electrode is connected to the Q node Q, and the second electrode is connected to the first electrode of the thirteenth transistor T3nA.

[0127] The thirteenth transistor T3nA is turned on by the N+2 carry signal applied via the N+2 carry signal line C(n+2), and together with the twelfth transistor T3n, discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS2. In the thirteenth transistor T3nA, the gate is connected to the N+2 carry signal line C(n+2), the first electrode is connected to the second electrode of the twelfth transistor T3n, and the second electrode is connected to the second low potential voltage line GVSS2.

[0128] The fourteenth transistor T3q is turned on through node Q and transmits the high-potential voltage of the high-potential voltage line GVDD to node Qh. In the fourteenth transistor T3q, the gate is connected to node Q, the first electrode is connected to the high-potential voltage line GVDD, and the second electrode is connected to node Qh.

[0129] The fifteenth transistor T3nB is turned on by the start pulse VST and, together with the sixteenth transistor T3nC, discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS2. The fifteenth transistor T3nB includes a first electrode connected to the Q node Q, a gate to which the start pulse VST is applied, and a second electrode connected to the first electrode of the sixteenth transistor T3nC.

[0130] The sixteenth transistor T3nC is turned on by the start pulse VST and, together with the fifteenth transistor T3nB, discharges the Q node Q to the second low potential voltage of the second low potential voltage line GVSS2. The sixteenth transistor T3nC includes a first electrode connected to the second electrode of the fifteenth transistor T3nB, a gate to which the start pulse VST is applied, and a second electrode connected to the second low potential voltage line GVSS2.

[0131] The second circuit unit 62-2 includes the seventeenth transistor T4, the eighteenth transistor T41, the nineteenth transistor T4q, the twentieth transistor T5q, and the twenty-first transistor T5.

[0132] The seventeenth transistor T4 is turned on by the voltage of the first node 70 and provides a high potential voltage to the Qb node Qb. The seventeenth transistor T4 includes a first electrode connected to a high potential voltage line to which the high potential voltage is applied, a gate connected to the first node 70, and a second electrode connected to the Qb node Qb.

[0133] The eighteenth transistor T41 is turned on by a high potential voltage and provides a high potential voltage to the first node 70. The eighteenth transistor T41 includes a first electrode connected to the high potential voltage line, a gate, and a second electrode connected to the first node.

[0134] The nineteenth transistor T4q is turned on by the voltage of the Q node and discharges the first node 70 to the second low potential voltage of the second low potential voltage line GVSS2. The nineteenth transistor T4q includes a first electrode connected to the first node 70, a gate connected to the Q node Q, and a second electrode connected to the second low potential voltage line GVSS2.

[0135] The twentieth transistor T5q is turned on by the voltage of the Q node and discharges the Qb node Qb to the second low potential voltage of the second low potential voltage line GVSS2. The twentieth transistor T5q includes a first electrode connected to the Qb node Qb, a gate connected to the Q node Q, and a second electrode connected to the second low potential voltage line GVSS2.

[0136] The twenty-first transistor T5 is turned on by the voltage of the carry signal line C(n-2) from the preceding signal transmission unit, and discharges the Qb node Qb to the second low potential voltage of the second low potential voltage line GVSS2. The twenty-first transistor T5 includes a first electrode connected to the Qb node, a gate for applying the carry signal from the preceding signal transmission unit, and a second electrode to which the second low potential voltage of the second low potential voltage line GVSS2 is applied.

[0137] The output unit 63 may include a first output unit 63-1 and a second output unit 63-2.

[0138] The first output unit 63-1 can output a scan signal SCOUT(n) to the first output node based on the potentials of Q node Q and Qb node Qb. The first output unit 63-1 may include a first pull-up transistor T6 and a first pull-down transistor T7.

[0139] The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of Q node Q and Qb node Qb, to output a scan signal SCOUT(n). The first pull-up transistor T6 includes a gate connected to Q node Q, a first electrode to which a first clock signal SCCLK(n) is applied, and a second electrode connected to the first output node. The first pull-down transistor T7 is connected to the first pull-up transistor T6, and the first output node is located between them. The first pull-down transistor T7 includes a gate connected to Qb node Qb, a first electrode connected to the first output node, and a second electrode connected to a first low-potential voltage line GVSS0.

[0140] The second output unit 63-2 can output a carry signal COUT(n) to the second output node based on the potentials of the Q node Q and the Qb node Qb. The second output unit 63-2 may include a second pull-up transistor T6cr and a second pull-down transistor T7cr.

[0141] The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of node Q and node Qb to output a carry signal COUT(n). The second pull-up transistor T6cr includes a gate connected to node Q, a first electrode to which a second clock signal CRCLK(n) is applied, and a second electrode connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr, and the second output node is located between them. The second pull-down transistor T7cr includes a gate connected to node Qb, a first electrode connected to the second output node, and a second electrode connected to the second low-potential voltage line GVSS2.

[0142] Reference Figure 13 According to the embodiment, when the gating driver is driven in display mode, that is, before driving the sensing mode, a row selection signal is applied to the row of pixels to be selected according to the output timing of the carry signal to charge the M node.

[0143] When driven in sensing mode, a pixel row is selected by applying a sensing start signal RESET, and a scan signal is output by the sensing start signal and the charging voltage of the M node.

[0144] Figures 14A to 14D This is a diagram illustrating the case where pixel rows are selected using a row selection signal.

[0145] Reference Figure 14A and Figure 14B This illustrates the case where two pixel rows are selected via row selection signals in two signal transmission units ST(n) and ST(n+1). Figure 14AAs shown, since the M nodes are charged to a high potential voltage, when the row selection signal is applied before driving the sensing mode, the M nodes M(n) and M(n+1) of each signal transmission unit are charged sequentially, and when the sensing start signal RESET is applied when driving in sensing mode, the pixel row can be selected simultaneously by outputting a scan signal based on the sensing start signal and the charging voltage of the M nodes M(n) and M(n+1).

[0146] Here, an example of selecting two pixel rows is described, but this disclosure is not limited thereto, and three or more pixel rows can be selected.

[0147] Reference Figure 14C According to the embodiment, the signal transmission unit can apply the row selection signal LSP according to the timing of the carry signal COUT(n) of the pixel row to be sensed before driving the sensing mode.

[0148] This section illustrates a case where the row selection signal is applied in time with the output of some carry signals, and 12 carry signals are output sequentially. It also illustrates a case where the row selection signal is applied in time with the output of carry signals six through ten.

[0149] Reference Figure 14D ,like Figure 14C As shown, since the M-node is charged by the row selection signal applied according to the output timing of the carry signal, when driven in sensing mode, the scan signal SCOUT(n) is applied at a high voltage level to the corresponding pixel row through the five signal transmission units of the M-node that are charged, thereby selecting the corresponding pixel row, and the scan signal SCOUT(n) is applied at a low voltage level to the remaining pixel rows through the seven signal transmission units of the M-node that are not charged, so the corresponding pixel row may not be selected.

[0150] Figure 15 This diagram illustrates the principle of selecting a sensing area from rows of pixels.

[0151] Reference Figure 11 and Figure 15 When the row selection signal LSP is applied before driving the sensing mode, the signal transmission unit according to the embodiment charges the M node to a high potential voltage, and when driving in sensing mode, the pixel row can be selected by applying a scan pulse with a high voltage level according to the sensing start signal RESET to the pixel row.

[0152] However, since the signal transmission unit may not charge the M node unless a row selection signal is applied before driving the sensing mode, a scan pulse with a low-level voltage is applied to the pixel row by the sensing start signal when driving in sensing mode, so the corresponding pixel row may not be selected.

[0153] As described above, in this embodiment, the row of pixels to be sensed can be selected by a row selection signal.

[0154] The sensing region can be selected from the pixel row selected by the row selection signal (①), and the sensing region can be selected by applying sensing data. Sensing data is applied to the sub-pixels located on the pixel row, and the region including the sub-pixel to which the sensing data is applied is selected as the sensing region. Since the driving elements are turned on by the sensing data, current can flow through the pixel driving voltage line. In this case, since all switching elements are turned on by a high-voltage scan pulse, the current path is not formed by the light-emitting elements, but bypasses the light-emitting elements, so no light is emitted in sensing mode.

[0155] Therefore, the current flowing through the pixel driving voltage line can be sensed in the sensing area (①).

[0156] Furthermore, since black data instead of sensing data is applied to the sub-pixel located in the non-sensing region (②) instead of the sensing region (①) in the pixel row selected by the row selection signal, the driving element is turned off and no current flows through the pixel driving voltage line.

[0157] Therefore, it is impossible to sense the current flowing through the pixel drive voltage line in the non-sensing region (②).

[0158] On the other hand, when a pixel row that is not selected by the row selection signal is connected to a data line passing through the sensing area (①)(③), since the switching element is turned off by a low-level scanning signal even when sensing data is applied to a sub-pixel located in the sensing area (①), no current flows through the pixel drive voltage line.

[0159] Therefore, it is impossible to sense the current flowing through the pixel drive voltage line in the non-sensing region (③).

[0160] Furthermore, when a pixel row that is not selected by the row selection signal is connected to a data line passing through the non-sensing area (②) (④), it is treated as a black pixel like a sub-pixel located in the non-sensing area (②), and no current flows through the pixel drive voltage line.

[0161] Therefore, it is impossible to sense the current flowing through the pixel drive voltage line in the non-sensing area (④).

[0162] As above, in this implementation, the sensing area in a row of pixels can be selected by applying sensing data.

[0163] Figure 16 It is used to explain how to prevent Figure 10The diagram illustrates the principle of leakage current in the row selection unit. All transistors used in the gating driver according to the embodiment are oxide TFTs, and due to the characteristics of oxide TFTs, a circuit stability margin is required based on the negative threshold voltage offset. The circuit stabilization method based on the negative threshold voltage offset will be described below.

[0164] Reference Figure 16 The row selection unit according to the first embodiment of the present disclosure may include a first transistor TV1, a second transistor TA, a third transistor TV2, a fourth transistor T1B, and a fifth transistor T1C.

[0165] After selecting a scan line or pixel line using the line selection signal LSP, a pre-charge state should be maintained in the M node. This prevents leakage current in the M node even when the third transistor TV2 is negatively offset using a low voltage level lower than the second low potential voltage as the start pulse.

[0166] For example, the high potential voltage can be 20V, the low voltage level of the starting pulse can be -18V, and the second low potential voltage can be -12V.

[0167] When both the low voltage level of the starting pulse and the second low potential voltage are -12V, abnormal circuit driving may occur because leakage current is generated in the third transistor TV2, where the voltage of node M leaks to the second low potential voltage even when there is a slight negative shift due to light or dispersion.

[0168] However, when using a low voltage level for the start pulse of -18V, which is lower than the second low potential voltage, the threshold voltage of the third transistor TV2 has a 6V margin, and it can be robust against leakage.

[0169] Figure 17 This is a diagram illustrating a gating driver according to a second embodiment of the present disclosure.

[0170] Reference Figure 17 The gating driver according to the second embodiment of the present disclosure may include a first control node for pulling up the output voltage (hereinafter referred to as the "Q node"), a second control node for pulling down the output voltage (hereinafter referred to as the "Qb node"), a row selection unit 61, a circuit unit 62, and an output unit 63.

[0171] Because the gating driver according to the second embodiment and according to Figure 11 The gating drivers of the first embodiment shown have the same construction and function, and only the row selection unit has a different construction, so only this will be described.

[0172] The row selection unit 61 may include a first transistor TV1, a second transistor TA, a third transistor TV2, a fourth transistor T1B, a fifth transistor T1C, a sixth transistor TV3, a seventh transistor T3qA, and a first capacitor C1.

[0173] The first transistor TV1 is turned on by the carry signal C(n) and, together with the second transistor TA, charges node M to the high potential voltage of the high potential voltage line GVDD. The first transistor TV1 includes a first electrode connected to the high potential voltage line GVDD, a gate to which the carry signal C(n) is applied, and a second electrode connected to the first electrode of the second transistor TA.

[0174] The second transistor TA is turned on by a row selection signal (row selection pulse, LSP) and, together with the first transistor TV1, charges the M node to the high potential voltage of the high potential voltage line GVDD. The second transistor TA includes a first electrode connected to the second electrode of the first transistor TV1, a gate to which the row selection signal is applied, and a second electrode connected to the M node.

[0175] The third transistor TV2 is turned on by the start signal VST and, together with the sixth transistor TV3, discharges the M node to the low potential voltage of the second low potential voltage line GVSS2. The third transistor TV2 includes a first electrode connected to the M node, a gate to which the start signal is applied, and a second electrode connected to the first electrode of the sixth transistor TV3.

[0176] The fourth transistor T1B is turned on through the M node and, together with the fifth transistor T1C, charges the Q node Q to the high potential voltage of the high potential voltage line GVDD. The fourth transistor T1B includes a first electrode connected to the high potential voltage line GVDD, a gate connected to the M node, and a second electrode connected to the first electrode of the fifth transistor T1C.

[0177] The fifth transistor T1C is turned on by sensing the start signal RESET, and together with the fourth transistor T1B, charges the Q node Q to the high potential voltage of the high potential voltage line GVDD. The fifth transistor T1C includes a first electrode connected to the second electrode of the fourth transistor T1B, a gate to which the sensing start signal RESET is applied, and a second electrode connected to the Q node Q.

[0178] The sixth transistor TV3 is turned on by the start signal VST and, together with the third transistor TV2, discharges node M to the low potential voltage of the second low potential voltage line GVSS2. The sixth transistor TV3 includes a first electrode connected to the second electrode of the third transistor TV2, a gate to which the start signal VST is applied, and a second electrode connected to the second low potential voltage line GVSS2.

[0179] The seventh transistor T3qA can be turned on by the voltage of the M node, and a high potential voltage can be applied to the second electrode of the third transistor TV2 and the first electrode of the sixth transistor TV3.

[0180] The first capacitor C1 is connected between the high-potential voltage line GVDD and node M, and stores the high-potential voltage applied to node M.

[0181] Figure 18 It is used to explain how to prevent Figure 17 The diagram shows the principle of leakage current in the row selection unit.

[0182] Reference Figure 18 According to the second embodiment of this disclosure, the row selection unit may include a first transistor TV1, a second transistor TA, a third transistor TV2, a fourth transistor T1B, a fifth transistor T1C, a sixth transistor TV3, a seventh transistor T3qA, and a first capacitor C1.

[0183] After selecting a scan line or pixel line using the row selection signal, the M node should remain in a pre-charged state. Since the gating driver according to the second embodiment additionally incorporates a sixth transistor TV3 and a seventh transistor T3qA, leakage current will not occur, even when a negative offset occurs in the third transistor TV2, preventing leakage current from the M node voltage to the second low-potential voltage line GVSS2.

[0184] For example, the high potential voltage can be 20V, the low voltage level of the starting pulse can be -12V, and the second low potential voltage can be -12V.

[0185] When node M is charged, the source node voltage of the third transistor TV2 increases due to the seventh transistor T3qA. Thus, even when the third transistor TV2 is negatively offset due to light or dispersion, the gate-source voltage Vgs of the third transistor TV2 remains sufficiently negative due to the increased source node voltage. Therefore, there is no leakage current to the second low potential voltage line GVSS2, and it is therefore robust against leakage.

[0186] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all respects and are not intended to limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be understood to fall within the scope of protection of the present disclosure.

Claims

1. A gate driver comprising a plurality of signal transmission units cascaded via a carry line, a carry signal being applied to the carry line from a preceding signal transmission unit, wherein an nth signal transmission unit comprising: a circuit unit configured to receive the carry signal from the preceding signal transmission unit to charge or discharge a first control node and a second control node; an output unit configured to output the carry signal and a gate signal based on potentials of the first control node and the second control node; and a row selection unit configured to charge an M node to a high potential voltage according to a display mode, and to charge the first control node to the high potential voltage based on a charging voltage of the M node and a sensing start signal according to a sensing mode subsequent to the display mode, wherein n is a positive integer, wherein the row selection unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor, wherein the first transistor comprises a first electrode connected to a first power line to which the high potential voltage is applied, a gate to which the carry signal is applied, and a second electrode connected to a first electrode of the second transistor, the second transistor comprises the first electrode connected to the second electrode of the first transistor, a gate to which a row selection signal is applied, and a second electrode connected to the M node, the third transistor comprises a first electrode connected to the M node, a gate to which a start signal is applied, and a second electrode connected to a second power line to which a low potential voltage is applied, the fourth transistor comprises the first electrode connected to the first power line, a gate connected to the M node, and a second electrode connected to a first electrode of the fifth transistor, the fifth transistor comprises a first electrode connected to the second electrode of the fourth transistor, a gate to which the sensing start signal is applied, and a second electrode connected to the first control node, and the capacitor is connected between the first power line to which the high potential voltage is applied and the M node, and stores the high potential voltage applied to the M node.

2. The gate driver of claim 1, wherein, A low voltage level of the start signal is lower than the low potential voltage.

3. The gated driver of claim 1, wherein, the row selection unit further comprises a sixth transistor and a seventh transistor, wherein the sixth transistor comprises a first electrode connected to the second electrode of the third transistor, a gate to which the start signal is applied, and a second electrode connected to the second power line, and the seventh transistor comprises a first electrode connected to the first power line, a gate connected to the M node, and a second electrode connected to the second electrode of the third transistor and the first electrode of the sixth transistor.

4. The gated driver of claim 3, wherein, A low voltage level of the start signal is the same as the low potential voltage.

5. The gated driver of claim 1, wherein, The row selection signal is applied according to an output timing of the carry signal of the nth signal transmission unit.

6. A display device comprising: A display panel on which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver configured to supply a data voltage of pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, wherein the gate driver includes a plurality of signal transmission units cascaded via a carry line, and a carry signal is applied to the carry line from a preceding signal transmission unit, wherein an nth signal transmission unit includes: a circuit unit configured to receive the carry signal from the preceding signal transmission unit to charge or discharge a first control node and a second control node; an output unit configured to output the carry signal and a gate signal based on potentials of the first control node and the second control node; and a row selection unit configured to charge an M node to a high potential voltage according to a display mode, and to charge the first control node to the high potential voltage based on a charging voltage of the M node and a sensing start signal according to a sensing mode subsequent to the display mode, wherein n is a positive integer, wherein the row selection unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor, wherein the first transistor includes a first electrode connected to a first power line to which the high potential voltage is applied, a gate to which the carry signal is applied, and a second electrode connected to a first electrode of the second transistor, the second transistor includes the first electrode connected to the second electrode of the first transistor, a gate to which a row selection signal is applied, and a second electrode connected to the M node, the third transistor includes a first electrode connected to the M node, a gate to which a start signal is applied, and a second electrode connected to a second power line to which a low potential voltage is applied, the fourth transistor includes a first electrode connected to the first power line, a gate connected to the M node, and a second electrode connected to a first electrode of the fifth transistor, the fifth transistor includes the first electrode connected to the second electrode of the fourth transistor, a gate to which the sensing start signal is applied, and a second electrode connected to the first control node, and the capacitor is connected between the first power line to which the high potential voltage is applied and the M node, and stores the high potential voltage applied to the M node.

7. The display device of claim 6, wherein, The low voltage level of the start signal is lower than the low potential voltage.

8. The display device of claim 6, wherein, The row selection unit further includes a sixth transistor and a seventh transistor, wherein the sixth transistor includes a first electrode connected to the second electrode of the third transistor, a gate to which the start signal is applied, and a second electrode connected to the second power line, and the seventh transistor includes the first electrode connected to the second electrode of the sixth transistor, a gate to which the sensing start signal is applied, and a second electrode connected to the first control node. The seventh transistor includes a first electrode connected to the first power supply line, a gate connected to the M node, and a second electrode connected to the second electrode of the third transistor and the first electrode of the sixth transistor.

9. The display device of claim 8, wherein, The low voltage level of the start signal is the same as the low potential voltage.

10. The display device of claim 6, wherein, The row selection signal is applied in accordance with the output timing of the carry signal of the nth signal transmission unit.

11. The display device of claim 6, wherein, Each of the subpixels includes: a driving element including a first electrode to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode to which a data voltage is applied, a gate to which a scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to the second node, a gate to which the scan pulse is applied, and a second electrode to which a reference voltage is applied; a light emitting element including an anode connected to the second node and a cathode to which a low potential power supply voltage is applied; and a capacitor connected between the first node and the second node.

12. The display device of claim 11, wherein, The data voltage includes a sensing data voltage and a black data voltage, and In a case where a sensing region of a pixel row is selected in accordance with a sensing mode, the first switching element and the second switching element are turned on, and the sensing data voltage is applied.

13. The display device of claim 12, wherein, In a case where a pixel row is not selected in accordance with the sensing mode and is connected to a data line passing through the sensing region, the first switching element and the second switching element are turned off, and the sensing data voltage is applied.

14. The display device of claim 12, wherein, In a case where a non-sensing region of the pixel row is selected in accordance with the sensing mode, the first switching element and the second switching element are turned on, and the black data voltage is applied.

15. The display device of claim 14, wherein, In a case where a pixel row is not selected in accordance with the sensing mode and is connected to a data line passing through the non-sensing region, the first switching element and the second switching element are turned off, and the black data voltage is applied.

16. The display device of claim 6, wherein, All transistors in a panel including the data driver, the gate driver, and the subpixels are implemented by oxide thin film transistors (TFTs) including n-channel oxide semiconductors.

17. The display device of claim 6, wherein, Before driving in the sensing mode, a plurality of scan lines are simultaneously selected by charging M nodes of signal transmission units connected to the scan lines to be selected to the high potential voltage.

18. The display device of claim 11, wherein, When driving in the sensing mode, light emission of the light emitting element is suppressed by outputting a scan signal of a high voltage level to sense a current flowing through a pixel driving voltage line while forming a current path using a path bypassing the light emitting element.

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