Display panel and electronic device

Abstract

A display panel and an electronic device capable of making the frequency of a signal output from a control switch higher than the frequency of a signal output from a pixel switch are provided. The display panel includes a first control switch (W1a) having a plurality of first control switch elements (SWc). The first control switch elements are formed of transistors, and have gate electrodes (Eg), source electrodes (Es), and drain electrodes (Ed). A plurality of scan lines to which the plurality of gate electrodes (Eg) are electrically connected are different from each other. The plurality of drain electrodes (Ed) are electrically aggregated into one, and connected to a power supply voltage output terminal (POUT).

Description

[0001] This application is based on Japanese Patent Application 2021-106649 (filed on June 28, 2021), and enjoys priority based on that application. This application incorporates the entire contents of that application. Technical Field

[0002] Embodiments of the present invention relate to display panels and electronic devices. Background Technology

[0003] A known display device is a liquid crystal display (LCD). The LCD includes a liquid crystal display panel as a display panel. The liquid crystal display panel includes multiple pixels, multiple scan lines, multiple signal lines, and signal line driving circuitry connected to the signal lines. Multiple pixels are disposed in the display area. Each pixel includes a thin-film transistor (TFT) and a pixel electrode connected to the TFT.

[0004] The signal line driving circuit is a driver IC formed using an IC (integrated circuit) chip. The signal line driving circuit outputs image signals to the signal lines. By turning on the TFT in each pixel, the signal line driving circuit can write the image signal to the pixel electrode via the signal lines and the TFT.

[0005] The control signal used to operate the signal line driving circuit is a low-voltage signal. Therefore, the signal line driving circuit outputs a low-voltage image signal to the signal line, for example, an image signal with a voltage value in the range of -5V to +5V. By using the aforementioned signal line driving circuit, multiple pixels can be driven using polarity reversal driving, enabling the liquid crystal display panel to display multiple grayscale levels in the display area.

[0006] In addition, as shown in Patent Document 1, the liquid crystal display panel may include electrodes other than pixel electrodes. Summary of the Invention

[0007] This embodiment provides a display panel capable of making the frequency of the signal output by the control switch higher than the frequency of the signal output by the pixel switch, and an electronic device including the display panel.

[0008] In one embodiment of the display panel, there are: a plurality of scan lines; a plurality of signal lines; pixel switching elements; pixel electrodes; and a first control switch having a plurality of first control switching elements, each pixel switching element being formed of a transistor and having: a gate electrode electrically connected to a corresponding scan line of the plurality of scan lines; a source electrode electrically connected to a corresponding signal line of the plurality of signal lines; and a drain electrode electrically connected to the pixel electrode. Each first control switching element is formed of a transistor and has: a gate electrode electrically connected to a corresponding scan line of the plurality of scan lines; a source electrode electrically connected to a corresponding signal line of the plurality of signal lines; and a drain electrode. The plurality of scan lines electrically connected to the gate electrodes of the plurality of first control switching elements are different from each other, and the plurality of drain electrodes of the plurality of first control switching elements are electrically combined into one and connected to a power supply voltage output terminal of the first control switch.

[0009] Additionally, in one embodiment of the electronic device, the device includes: a display panel having a plurality of scan lines, a plurality of signal lines, pixel switching elements, pixel electrodes, an incident light control region, a first control switch having a plurality of first control switching elements, a control electrode located in the incident light control region, a first level shifting circuit, and a first charge pump; and a camera device for acquiring information about light transmitted through the incident light control region of the display panel. The pixel switching elements are formed by transistors and have: a gate electrode electrically connected to a corresponding scan line of the plurality of scan lines; a source electrode electrically connected to a corresponding signal line of the plurality of signal lines; and a drain electrode electrically connected to the pixel electrode. Each of the first control switching elements is formed by a transistor and has: a gate electrode electrically connected to a corresponding signal line of the plurality of scan lines; a source electrode electrically connected to a corresponding signal line of the plurality of signal lines; and a drain electrode electrically connected to the pixel electrode. The plurality of first control switching elements are electrically connected to a gate electrode corresponding to a scan line; a source electrode electrically connected to a corresponding signal line among the plurality of signal lines; and a drain electrode. The plurality of scan lines to which the gate electrodes of the plurality of first control switching elements are electrically connected are different from each other. The plurality of drain electrodes of the plurality of first control switching elements are electrically combined into one and connected to the power supply voltage output terminal of the first control switch. The first control switch outputs a first power supply voltage input from the signal line to the power supply voltage output terminal. The first level shifting circuit outputs the first power supply voltage to the first charge pump. The first charge pump generates a first output voltage and outputs the first output voltage to the control electrode. The absolute value of the first output voltage is greater than the absolute value of the first power supply voltage. Attached Figure Description

[0010] Figure 1 This is an exploded perspective view showing a structural example of an electronic device according to the first embodiment.

[0011] Figure 2 This is a cross-sectional view showing the area around the camera of the aforementioned electronic device.

[0012] Figure 3 It means Figure 2 The plan view shown, which includes the configuration of the liquid crystal display panel and multiple cameras, is a diagram that also represents the equivalent circuit of a pixel.

[0013] Figure 4 This is a plan view showing the pixel arrangement in the aforementioned liquid crystal display panel.

[0014] Figure 5 This is a plan view representing one unit pixel of the aforementioned liquid crystal display panel, and it shows the scan lines, signal lines, pixel electrodes, and light-shielding parts.

[0015] Figure 6 This is a plan view showing the main pixel, which differs from the above-described embodiment. It is a diagram showing the scan lines, signal lines, pixel electrodes, and light-shielding parts.

[0016] Figure 7 It means including Figure 5 The image shows a cross-sectional view of the liquid crystal display panel with the indicated pixels.

[0017] Figure 8 This is a plan view showing the light-shielding layer in the incident light control area of ​​the aforementioned liquid crystal display panel.

[0018] Figure 9 This is a plan view showing the multiple control electrodes of the aforementioned liquid crystal display panel.

[0019] Figure 10 This is a cross-sectional view showing the incident light control area of ​​the aforementioned liquid crystal display panel.

[0020] Figure 11 This diagram shows the equivalent circuit of the multiple control switch groups, multiple level shifting units, multiple charge pumps, first control electrode structure, scan lines, and signal lines of the aforementioned liquid crystal display panel. It also shows multiple pixels, scan line driving circuits, and signal line driving circuits.

[0021] Figure 12 It means Figure 11 The circuit diagram shown is a part of a control switch, and also represents an example of the signal waveform output by the control switch.

[0022] Figure 13 This is a circuit diagram showing the electrical system used to generate the first output voltage. Figure 11 The diagram shows two control switches, two level shifting circuits, and one charge pump.

[0023] Figure 14 It means and Figure 11 The multiple control switches shown are different from one part of a control switch and Figure 11 and Figure 13 The circuit diagram of the charge pump is a diagram showing the connection state between the power supply voltage output terminal of the control switch and the power supply terminal of the charge pump.

[0024] Figure 15 It means Figure 11 and Figure 13 The circuit diagram of a single level shifter circuit.

[0025] Figure 16 This is a circuit diagram showing the electrical system used to generate the second output voltage. It shows two control switches, two level shifting circuits, one charge pump, etc.

[0026] Figure 17 It means Figure 13 The timing diagram of the multiple output signals is shown.

[0027] Figure 18A It means Figure 13 The circuit diagram of the modified example 1 of the electrical system shown is a diagram that represents 2 control switches, 2 level shifting circuits, 1 charge pump, etc.

[0028] Figure 18B It means Figure 13 The circuit diagram of the modified example 2 of the electrical system shown is a diagram that represents 2 control switches, 2 level shifting circuits, 1 charge pump, etc.

[0029] Figure 18C It means Figure 13 The circuit diagram of the modified example 3 of the electrical system shown is a diagram that represents 2 control switches, 2 level shifting circuits, 1 charge pump, etc.

[0030] Figure 19 This is a circuit diagram showing a part of the electronic device of the second embodiment, a diagram showing the electrical system for generating the first output voltage, and a diagram showing a control switch, multiple inverters, a logic AND circuit, a logic NOR circuit, a level shifter, a charge pump, etc.

[0031] Figure 20 It means Figure 19 The timing diagram of the multiple output signals is shown.

[0032] Figure 21 This is a circuit diagram of a modified example 1 of the electronic device of the second embodiment described above, a diagram of an electrical system for generating a first output voltage, and a diagram showing a control switch, multiple inverters, a logic XOR circuit, a level shifter, a charge pump, etc.

[0033] Figure 22 It means Figure 21 The timing diagram of the multiple output signals is shown.

[0034] Figure 23 This is a circuit diagram of a modified example 2 of the electronic device of the second embodiment described above, a diagram of an electrical system for generating the first output voltage, and a diagram showing a control switch, multiple inverters, an RC circuit, a logic XOR circuit, a level shifter, a charge pump, etc.

[0035] Figure 24 This is a circuit diagram showing a part of the electronic device according to the third embodiment. It shows a control switch group, a level shifter, a charge pump, a first control electrode structure, a third control electrode structure, a fifth control electrode structure, and multiple switches. Detailed Implementation

[0036] The various embodiments of the present invention will now be described with reference to the accompanying drawings. Furthermore, the disclosures herein are merely illustrative, and appropriate modifications that will readily conceive by those skilled in the art while maintaining the spirit of the invention are, of course, within the scope of the invention. In addition, to make the description clearer, some of the widths, thicknesses, shapes, etc., of the various parts are schematically shown compared to the actual forms; however, these are at most examples and do not limit the interpretation of the invention. Furthermore, in this specification and the accompanying drawings, elements identical to those described in the existing figures are marked with the same reference numerals, and detailed descriptions of some parts are appropriately omitted.

[0037] (First Implementation)

[0038] The first embodiment will be described first. Figure 1 This is an exploded perspective view showing a structural example of the electronic device 100 of this embodiment.

[0039] like Figure 1 As shown, directions X, Y, and Z are orthogonal to each other, but can also intersect at angles other than 90 degrees.

[0040] The electronic device 100 includes a liquid crystal display device (DSP) as a display device and a camera 1 as a camera device. The liquid crystal display device (DSP) includes a liquid crystal display panel (PNL) as a display panel and an illumination device (backlight) (IL). The camera 1 has a camera (camera module) 1a as a first camera. In this embodiment, although not all cameras 1b as second cameras are illustrated, the electronic device 100 also includes two cameras 1b. Alternatively, the camera 1 may include only camera 1a.

[0041] The lighting device IL includes a light guide LG1, a light source EM1, and a housing CS. Such a lighting device IL is used, for example, for illumination. Figure 1 The liquid crystal display panel (PNL) is simplified and represented by dashed lines.

[0042] The light guide LG1 is formed as a flat plate parallel to the XY plane defined by directions X and Y. The light guide LG1 faces the liquid crystal display panel PNL. The light guide LG1 has a side surface SA, a side surface SB opposite to side surface SA, and a through-hole h1 surrounding the camera 1a. The light guide LG1 faces multiple cameras 1b. Side surfaces SA and SB extend in direction X. For example, side surfaces SA and SB are surfaces parallel to the XZ plane defined by directions X and Z. The through-hole h1 penetrates the light guide LG1 in direction Z. In direction Y, the through-hole h1 is located between side surfaces SA and SB, closer to side surface SB than side surface SA.

[0043] Multiple light sources EM1 are arranged at intervals in direction X. Each light source EM1 is mounted on a wiring board F1 and electrically connected to the wiring board F1. The light source EM1 is, for example, a light-emitting diode (LED) that emits white illumination light. The illumination light emitted by the light source EM1 enters the light guide LG1 from side SA and travels from side SA to side SB inside the light guide LG1.

[0044] The housing CS houses the light guide LG1 and the light source EM1. The housing CS has sidewalls W1-W4, a base plate BP, a through hole h2, a protrusion PP, and another through hole h3. Sidewalls W1 and W2 extend in the X direction and are opposite each other in the Y direction. Sidewalls W3 and W4 extend in the Y direction and are opposite each other in the X direction. Through hole h2 overlaps with through hole h1 in the Z direction. The protrusion PP is fixed to the base plate BP. The protrusion PP protrudes from the base plate BP towards the liquid crystal display panel PNL in the Z direction and surrounds the through hole h2.

[0045] In this embodiment, the housing CS has the same number of through holes h3 as the camera 1b. The through holes h3 are formed by penetrating the base plate BP in the Z direction. In top view, the multiple through holes h3 are distributed together with the through holes h2. Furthermore, if the base plate BP is made of a material that transmits infrared light, it is not necessary to form the through holes h3 on the base plate BP. Additionally, from the viewpoint of reducing the thickness of the electronic device 100 in the Z direction, it is preferable to form the through holes h3 on the base plate BP and surround the camera 1b with the through holes h3.

[0046] The light guide LG1 overlaps with the liquid crystal display panel PNL.

[0047] Cameras 1a and 1b are mounted on wiring board F2 and electrically connected to wiring board F2. Camera 1a passes through through hole h2, the interior of protrusion PP, and through hole h1, and is opposite to liquid crystal display panel PNL. Camera 1b passes through through hole h3 and is opposite to light guide LG1.

[0048] Figure 2 This is a cross-sectional view showing the area around the camera 1a of the electronic device 100.

[0049] like Figure 2 As shown, the lighting device IL also includes a light reflector RS, a light diffuser SS, and prism sheets PS1 and PS2.

[0050] A light reflector RS, a light guide LG1, a light diffuser SS, a prism sheet PS1, and a prism sheet PS2 are arranged sequentially in the Z direction and housed within a housing CS. The housing CS comprises a metal housing CS1 and a resin light-shielding wall CS2 as a peripheral component. The light-shielding wall CS2 is adjacent to the camera 1 and forms a protrusion PP together with the housing CS1. The light-shielding wall CS2 is located between the camera 1 and the light guide LG1 and is cylindrical in shape. The light-shielding wall CS2 is formed of a light-absorbing resin such as black resin. Each of the light diffuser SS, prism sheet PS1, and prism sheet PS2 has a through-hole overlapping with a through-hole h1. The protrusion PP is located inside the through-hole h1.

[0051] The liquid crystal display panel PNL also includes polarizers PL1 and PL2. The liquid crystal display panel PNL and the protective glass CG, serving as a protective component, are arranged in the Z-direction to form a liquid crystal element LCD that optically switches light traveling in the Z-direction. The liquid crystal element LCD is attached to the lighting device IL using tape TP1. Tape TP1 is attached to the protrusion PP, the prism sheet PS2, and the polarizer PL1.

[0052] A liquid crystal display panel (PNL) may include any structure corresponding to the following display modes: a display mode utilizing a lateral electric field along the main surface of the substrate, a display mode utilizing a longitudinal electric field utilizing a normal to the main surface of the substrate, a display mode utilizing a tilted electric field obliquely inclined relative to the main surface of the substrate, and a display mode utilizing the above-mentioned lateral electric field, longitudinal electric field, and tilted electric field in a suitable combination. Here, the main surface of the substrate is a surface parallel to the XY plane.

[0053] A liquid crystal display panel (PNL) includes a display area DA for displaying an image, a non-display area NDA outside the display area DA, and a circular incident light control area PCA surrounded by the display area DA. The PNL includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC, and a sealing member SE. The sealing member SE is located in the non-display area NDA and bonds the first substrate SUB1 and the second substrate SUB2. The liquid crystal layer LC is located between the display area DA and the incident light control area PCA and is held between the first substrate SUB1 and the second substrate SUB2. The liquid crystal layer LC is formed in the space surrounded by the first substrate SUB1, the second substrate SUB2, and the sealing member SE.

[0054] An image is displayed in the display area DA by controlling the amount of light transmitted from the illumination device IL using the liquid crystal display panel PNL. The user of the electronic device 100 is located on the Z side (upper side in the figure) of the protective glass CG and views the emitted light from the liquid crystal display panel PNL as an image.

[0055] In response, the amount of light transmitted is also controlled by the liquid crystal display panel PNL in the incident light control area PCA, but the light will pass through the liquid crystal display panel PNL from the Z side of the protective glass CG and enter the camera 1.

[0056] In this specification, the light that travels from the lighting device IL through the liquid crystal display panel PNL to the protective glass CG side is called the emitted light, and the light that travels from the protective glass CG side through the liquid crystal display panel PNL to the camera 1 is called the incident light.

[0057] Here, the main parts of the first substrate SUB1 and the second substrate SUB2 will be described.

[0058] The first substrate SUB1 includes an insulating substrate 10 and an alignment film AL1. The second substrate SUB2 includes an insulating substrate 20, a color filter CF, a light-shielding layer BM, a transparent layer OC, and an alignment film AL2.

[0059] Insulating substrate 10 and insulating substrate 20 are transparent substrates such as glass substrates or flexible resin substrates. Alignment films AL1 and AL2 are in contact with the liquid crystal layer LC.

[0060] The color filter CF, the light-shielding layer BM, and the transparent layer OC are located between the insulating substrate 20 and the liquid crystal layer LC. In the example shown, the color filter CF is disposed on the second substrate SUB2, but it can also be disposed on the first substrate SUB1. The color filter CF is located in the display area DA.

[0061] The incident light control region PCA has at least: a first light-shielding region LSA1 in the shape of a ring located at the outermost periphery; and a first incident light adjustment region TA1 that is surrounded by the first light-shielding region LSA1 and contacts the first light-shielding region LSA1.

[0062] The light-shielding layer BM includes: a light-shielding portion located in the display area DA and dividing pixels; and a frame-shaped light-shielding portion BMB located in the non-display area NDA. In the incident light control area PCA, the light-shielding layer BM includes at least a first light-shielding portion BM1 in a circular shape located in the first light-shielding area LSA1, and a first opening OP1 located in the first incident light adjustment area TA1.

[0063] The boundary between the display area DA and the non-display area NDA is defined, for example, by the inner end of the light-shielding part BMB (the end on the side of the display area DA). The sealing member SE overlaps with the light-shielding part BMB.

[0064] The transparent layer OC contacts the color filter CF in the display area DA, contacts the light-shielding portion BMB in the non-display area NDA, contacts the first light-shielding portion BM1 in the first light-shielding area LSA1, and contacts the insulating substrate 20 in the first incident light adjustment area TA1. Alignment films AL1 and AL2 are disposed throughout the display area DA, the incident light control area PCA, and the non-display area NDA.

[0065] Details regarding the color filter CF are omitted here; however, the color filter CF includes a red coloring layer with red pixels, a green coloring layer with green pixels, and a blue coloring layer with blue pixels. Additionally, the color filter CF sometimes also includes a transparent resin layer with white pixels. A transparent layer OC covers the color filter CF and the light-shielding layer BM. The transparent layer OC is, for example, a transparent organic insulating layer.

[0066] Camera 1 is located inside the through hole h2 of the housing CS. Camera 1 overlaps with the protective glass CG and the liquid crystal display panel PNL in the Z direction. Furthermore, the liquid crystal display panel PNL may include optical elements other than polarizers PL1 and PL2 in the incident light control area PCA. Examples of such optical elements include phase retardation plates, light scattering layers, and anti-reflection layers. In the electronic device 100 having the liquid crystal display panel PNL, camera 1a, etc., from the user's perspective, camera 1a appears to be located on the inside of the liquid crystal display panel PNL.

[0067] The camera 1a, for example, has an optical system 2 including at least one lens, an image sensor 3, and a housing 4. The image sensor 3 includes an image-facing surface 3a facing the liquid crystal display panel (PNL). The optical system 2 is opposite to the incident light control area (PCA) of the liquid crystal display panel (PNL). The optical system 2 is located between the image-facing surface 3a and the liquid crystal display panel (PNL), and includes a light-incident surface 2a facing the liquid crystal display panel (PNL). The light-incident surface 2a overlaps with the incident light control area (PCA). The optical system 2 is located at a position separated from the liquid crystal display panel (PNL) by a gap. The housing 4 houses the optical system 2 and the image sensor 3.

[0068] The upper part of the housing 4 is equipped with a light source EM2 as a first light source and a light source EM3 as a second light source. The light source EM2 is configured to emit infrared light toward the liquid crystal display panel PNL side. The light source EM3 is configured to emit visible light toward the liquid crystal display panel PNL side. The purpose of setting up the light sources EM2 and EM3 is to illuminate the subject captured by the camera 1a.

[0069] Camera 1a acquires information about the light after it passes through the incident light control area PCA of the liquid crystal display panel PNL. The imaging element 3 of camera 1a receives light via the protective glass CG, the liquid crystal display panel PNL, and the optical system 2. The imaging element 3 is configured to convert the light after it passes through the incident light control area PCA of the liquid crystal display panel PNL, the optical system 2, etc., into image data. For example, camera 1a receives visible light (e.g., light in the wavelength range of 400nm to 700nm) after it passes through the protective glass CG and the liquid crystal display panel PNL. Additionally, it can also simultaneously receive infrared light (e.g., light in the wavelength range of 800nm ​​to 1500nm) along with visible light.

[0070] Additionally, camera 1b differs from camera 1a in that it does not have a light source EM3. Camera 1b passes through the through-hole h3. Figure 1 Opposite to the light reflector RS, camera 1b can receive infrared light through the protective glass CG, liquid crystal display panel PNL, prism sheet PS2, prism sheet PS1, light diffuser SS, light guide LG1, light reflector RS, and optical system 2. The light reflector RS has an opening at the position overlapping with the IR sensor. However, if the light reflector is a thin film capable of transmitting IR, it is possible not to have an opening in the light reflector, and instead, the IR sensor can receive the infrared light transmitted through the light reflector. In this case, the adverse effects on image recognizability can be reduced. Furthermore, camera 1b can be housed in the through-hole h1 of light guide LG1 and the through-hole h2 of base plate BP, similar to camera 1a.

[0071] Polarizer PL1 is bonded to insulating substrate 10. Polarizer PL2 is bonded to insulating substrate 20. Protective glass CG is attached to polarizer PL2 via transparent adhesive layer AD.

[0072] In addition, to protect the liquid crystal layer LC from external electric fields, a transparent conductive layer is sometimes provided between the polarizer PL2 and the insulating substrate 20. This transparent conductive layer is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0073] Furthermore, polarizer PL1 or polarizer PL2 may include a super birefringent film. Super birefringent films are known to convert transmitted light into unpolarized light (natural light) when linearly polarized light is incident, allowing for photography without a sense of dissonance even if the subject includes an object emitting polarized light. For example, when an electronic device 100 is captured in the subject of camera 1a, since linearly polarized light is emitted from the electronic device 100, the brightness of the electronic device 100 incident on the subject, depending on the angles of polarizer PL1, polarizer PL2, and the polarizer of the electronic device 100, may change, potentially causing a sense of dissonance during photography. However, by equipping polarizer PL1 and polarizer PL2 with super birefringent films, the brightness variation that causes a sense of dissonance can be suppressed.

[0074] As a thin film capable of exhibiting super birefringence, cosmoshine (registered trademark) from Toyobo Co., Ltd. can be used appropriately, for example. Here, super birefringence refers to an in-plane optical path difference of 800 nm or more for visible light, such as light at 500 nm.

[0075] The liquid crystal display panel PNL has a first surface S1 on the image display side and a second surface S2 on the side opposite to the first surface S1. In this embodiment, the polarizer PL2 has the first surface S1 and the polarizer PL1 has the second surface S2.

[0076] The light sources EM2 and EM3 are located on the second side S2 of the liquid crystal display panel PNL.

[0077] The display area DA and the incident light control area PCA are each regions that overlap with the first substrate SUB1, the second substrate SUB2, and the liquid crystal layer LC.

[0078] Figure 3 It means Figure 2 The plan view shown, including the configuration of the liquid crystal display panel PNL and multiple cameras 1a, 1b, is a diagram illustrating the equivalent circuit of a single pixel PX. Figure 3 In the diagram, the liquid crystal layer LC and the sealing component SE are indicated by different slashes.

[0079] like Figure 3 As shown, the display area DA is essentially a quadrilateral area, with rounded corners, or it can be a polygon or a circle other than a quadrilateral. The display area DA is surrounded by a sealing component SE.

[0080] The liquid crystal display panel (PNL) has a pair of short sides E11 and E12 extending along the X direction and a pair of long sides E13 and E14 extending along the Y direction. The PNL includes a plurality of pixels PX arranged in a matrix in the X and Y directions within the display area DA. Each pixel PX in the display area DA has the same circuit structure. For example... Figure 3 As shown in the magnified diagram, each pixel PX includes a pixel switching element SWp, a pixel electrode PE, a common electrode CE, and a liquid crystal layer LC.

[0081] The pixel switching element SWp is, for example, composed of a thin-film transistor (TFT). The pixel switching element SWp has a gate electrode electrically connected to a corresponding scan line G among a plurality of scan lines G, a source electrode electrically connected to a corresponding signal line S among a plurality of signal lines S, and a drain electrode electrically connected to the pixel electrode PE. A control signal for controlling the pixel switching element SWp is provided to the scan lines G. An image signal, such as an image signal, is provided to the signal lines S as a different signal from the control signal. A common voltage is provided to the common electrode CE. The liquid crystal layer LC is driven by the voltage (electric field) generated between the pixel electrode PE and the common electrode CE. A capacitor Cp is formed, for example, between an electrode at the same potential as the common electrode CE and an electrode at the same potential as the pixel electrode PE.

[0082] The electronic device 100 also includes a wiring board 5 and an IC chip 6.

[0083] Wiring board 5 is mounted on and connected to the extension Ex of the first substrate SUB1. IC chip 6 is mounted on and electrically connected to wiring board 5. Alternatively, IC chip 6 can also be mounted on and electrically connected to the extension Ex. IC chip 6 has a built-in display driver or similar component for outputting signals required for image display. Wiring board 5 can be a flexible printed circuit board that can be bent.

[0084] Figure 3 In the display area DA, the electronic device 100 includes three cameras 1. An incident light control area PCA is formed, overlapping with the camera 1a at the upper center of the figure. The incident light control area PCA includes an outer periphery that contacts the display area DA. The other cameras 1b overlap with normal pixels PX, and normal display is performed on the pixels PX overlapping with the cameras 1b.

[0085] Polarizers PL1 and PL2 have high transmittance in the infrared band, allowing infrared light to pass through. Therefore, even if pixel PX overlaps with cameras 1a and 1b, cameras 1a and 1b can still receive infrared light. By displaying normally on the pixel PX overlapping with camera 1b, users can use electronic device 100 without realizing the location of camera 1b. Furthermore, since the area of ​​display area DA is not reduced, a large number of cameras 1b can be configured. Moreover, users will not be aware of the presence of a large number of cameras 1b. In particular, when electronic device 100 is used in the form of an automatic teller machine (ATM), by placing the cameras 1b in a fixed black area, it becomes even more difficult for users to notice their presence.

[0086] Marker 300 is an indicator that visually informs the user of the status of cameras 1a and 1b. For example, in situations such as fingerprint authentication, indicator 300 can indicate the optimal finger position to the user. Additionally, arrow 400 is a mark (symbol) displayed to intentionally inform the user of the position of camera 1b. The displayed graphic can be more than just arrow 400; appropriate shapes can be selected, such as surrounding camera 1b with a circle.

[0087] Figure 4 It is a plan view showing the arrangement of pixels PX in a liquid crystal display panel (PNL).

[0088] like Figure 4 As shown, each master pixel (MPX) is composed of multiple pixels (PX). These master pixels (MPX) are classified into two categories: master pixels (MPXa) and MPXb. Two adjacent master pixels (MPXa) and MPXb in the Y direction constitute a unit pixel (UPX). Each master pixel (MPXa) and MPXb corresponds to the smallest unit for displaying a color image. Master pixel (MPXa) includes pixels PX1a, PX2a, and PX3a. Master pixel (MPXb) includes pixels PX1b, PX2b, and PX3b. Furthermore, the shape of the aforementioned pixels (PX) is approximately a parallelogram, as shown in the illustration.

[0089] Each of the main pixels MPXa and MPXb comprises multiple pixels PX of different colors arranged in the X direction. Pixels PX1a and PX1b are pixels of a first color and include a coloring layer CF1 for that first color. Pixels PX2a and PX2b are pixels of a second color, different from the first color, and include a coloring layer CF2 for that second color. Pixels PX3a and PX3b are pixels of a third color, different from the first and second colors, and include a coloring layer CF3 for that third color.

[0090] The main pixels MPXa and MPXb are each repeatedly arranged in direction X. Rows of main pixels MPXa arranged along direction X and rows of main pixels MPXb arranged along direction X are alternately and repeatedly arranged in direction Y. Each pixel PX of main pixel MPXa extends in a first extension direction d1, and each pixel PX of main pixel MPXb extends in a second extension direction d2. Furthermore, the first extension direction d1 is a direction different from both direction X and direction Y. The second extension direction d2 is a direction different from direction X, direction Y, and the first extension direction d1. Figure 5 In the example shown, the first extension direction d1 is the right diagonal downward direction, and the second extension direction d2 is the left diagonal downward direction.

[0091] When the shape of pixel PX is approximately a parallelogram as shown in the diagram, multiple domains with different rotation directions of the pointer can be set within a unit pixel UPX. That is, by combining two principal pixels MPXa and MPXb, multiple domains can be formed even for pixels of each color, enabling compensation for viewing angle characteristics. Therefore, when viewing angle characteristics are a concern, one unit pixel UPX obtained by combining principal pixels MPXa and MPXb is equivalent to the smallest unit for displaying a color image.

[0092] Figure 5 This is a plan view representing one unit pixel UPX of a liquid crystal display panel (PNL), and it shows the scan line G, signal line S, pixel electrode PE, and light-shielding part BMA. Figure 5 The illustrations only show the structures necessary for the description, omitting illustrations of pixel switching elements SWp, common electrode CE, color filter CF, etc.

[0093] like Figure 5 As shown, the plurality of pixels PX have a structure corresponding to the FFS (Fringe Field Switching) mode, one of the display modes utilizing a lateral electric field. Scan lines G and signal lines S are disposed on the first substrate SUB1, and a light-shielding portion BMA (light-shielding layer BM) is disposed on the second substrate SUB2. The scan lines G and signal lines S extend intersectingly in the display area (DA). The plurality of scan lines G extend in the X direction and are arranged in the Y direction. The plurality of signal lines S extend in the Y direction and are arranged in the X direction. Furthermore, the light-shielding portion BMA is a grid-like light-shielding portion located in the display area DA and dividing the pixels PX, indicated by a double-dotted line in the figure.

[0094] The light-shielding part BMA has the function of at least blocking light emanating from the aforementioned lighting device (IL). The light-shielding part BMA is formed of a material with high light absorption, such as black resin. The light-shielding part BMA is formed in a lattice shape. In the light-shielding part BMA, a plurality of light-shielding parts BMA1 extending in the X direction and a plurality of light-shielding parts BMA2 extending while bending along the first extension direction d1 and the second extension direction d2 are formed integrally.

[0095] Each scan line G extends in direction X. Each scan line G is opposite to its corresponding light-shielding portion BMA1 and extends along the corresponding light-shielding portion BMA1. The light-shielding portion BMA1 is opposite to the ends of the scan line G and the pixel electrode PE, etc. Each signal line S extends while bending along direction Y, the first extension direction d1, and the second extension direction d2. Each signal line S is opposite to its corresponding light-shielding portion BMA2 and extends along the corresponding light-shielding portion BMA2.

[0096] The light-shielding layer BM has multiple opening regions AP. The opening regions AP are defined by light-shielding portions BMA1 and BMA2. The opening region AP of the main pixel MPXa extends in a first extending direction d1. The opening region AP of the main pixel MPXb extends in a second extending direction d2.

[0097] The pixel electrode PE of the main pixel MPXa includes multiple linear pixel electrodes PA located in the opening region AP. The multiple linear pixel electrodes PA extend linearly in a first extending direction d1 and are spaced apart in an orthogonal direction dc1 orthogonal to the first extending direction d1. The pixel electrode PE of the main pixel MPXb includes multiple linear pixel electrodes PB located in the opening region AP. The multiple linear pixel electrodes PB extend linearly in a second extending direction d2 and are spaced apart in an orthogonal direction dc2 orthogonal to the second extending direction d2.

[0098] In the display area DA, the aforementioned alignment films AL1 and AL2 have an alignment axis AA parallel to the direction Y. The alignment direction AD1 of alignment film AL1 is parallel to the direction Y, and the alignment direction AD2 of alignment film AL2 is parallel to the alignment direction AD1.

[0099] When a voltage is applied to the liquid crystal layer (LC), the rotational state (or orientation state) of the liquid crystal molecules in the aperture region AP of the main pixel MPXa is different from that in the aperture region AP of the main pixel MPXb. Therefore, the viewing angle characteristics can be compensated.

[0100] As mentioned above, in Figure 4 and Figure 5 The document describes a structure for compensating for viewing angle characteristics within a single unit pixel (UPX). However, unlike this embodiment, the viewing angle characteristics can also be compensated within a single main pixel (MPX). Figure 6 This is a plan view showing the main pixel MPX, which differs from this embodiment. It is a diagram showing the scan line G, signal line S, pixel electrode PE, and light-shielding part BMA.

[0101] like Figure 6 As shown, each opening region AP extends in the second extending direction d2 and bends midway to extend in the first extending direction d1. Each opening region AP has the shape of a "<" symbol and has a first opening region AP1 and a second opening region AP2. The first opening region AP1 extends in the first extending direction d1, and the second opening region AP2 extends in the second extending direction d2.

[0102] The pixel electrode PE extends in the second extending direction d2 and bends midway to extend in the first extending direction d1. The pixel electrode PE includes multiple linear pixel electrodes PA and multiple linear pixel electrodes PB. The multiple linear pixel electrodes PA are located in the first opening region AP1, extend linearly in the first extending direction d1, and are spaced apart in the orthogonal direction dc1. The multiple linear pixel electrodes PB are located in the second opening region AP2, extend linearly in the second extending direction d2, and are spaced apart in the orthogonal direction dc2. A consecutive linear pixel electrode PA and a linear pixel electrode PB have a "<" symbol shape.

[0103] Alternatively, in a top view where pixel PX1 is on the left and pixel PX3 is on the right, a continuous linear pixel electrode PA and a linear pixel electrode PB have the shape of a ">" symbol, and the opening region AP has the shape of a ">" symbol.

[0104] When a voltage is applied to the liquid crystal layer (LC), the rotational states of the liquid crystal molecules in the first opening region AP1 are different from those in the second opening region AP2. Each opening region AP has four domains with different director rotation directions. Therefore, the liquid crystal display panel PNL can achieve good viewing angle characteristics.

[0105] In addition, in this first embodiment, the pixel electrode PE functions as a display electrode, and the linear pixel electrode PA and the linear pixel electrode PB function as linear display electrodes.

[0106] Figure 7 It means including Figure 5 The diagram shows a cross-sectional view of the liquid crystal display panel PNL of pixels PX1 and PX2. The liquid crystal display panel PNL has a structure corresponding to the FFS (Fringe Field Switching) mode, one of the display modes that utilizes a lateral electric field.

[0107] like Figure 7As shown, the first substrate SUB1 includes an insulating layer 11, a signal line S, an insulating layer 12, a common electrode CE, a metal layer ML, an insulating layer 13, and a pixel electrode PE between the insulating substrate 10 and the alignment film AL1. Additionally, a polarizer PL1 is formed on the outer side of the first substrate SUB1.

[0108] An insulating layer 11 is disposed on the insulating substrate 10. Furthermore, the aforementioned scan line (G), the gate electrode of the pixel switching element SWp, a semiconductor layer, and other insulating layers are disposed between the insulating substrate 10 and the insulating layer 11, but these will not be described in detail here. A signal line S is formed on the insulating layer 11. An insulating layer 12 is disposed on the insulating layer 11 and the signal line S.

[0109] A common electrode CE is disposed on the insulating layer 12. A metal layer ML is disposed on the common electrode CE and is in contact with the common electrode CE. The metal layer ML is located directly above the signal line S. Alternatively, in the illustrated example, although the first substrate SUB1 includes the metal layer ML, the metal layer ML can be omitted. An insulating layer 13 is disposed on the common electrode CE and the metal layer ML.

[0110] Pixel electrodes PE are formed on insulating layer 13. Each pixel electrode PE is located between adjacent signal lines S, opposite to the common electrode CE. Furthermore, each pixel electrode PE has a gap at a position opposite to the common electrode CE (opening region AP). The common electrode CE and pixel electrodes PE are formed of a transparent conductive material such as ITO or IZO. Insulating layer 13 is sandwiched between the pixel electrodes PE and the common electrode CE. Alignment film AL1 is disposed on insulating layer 13 and pixel electrodes PE, covering the pixel electrodes PE.

[0111] On the other hand, the second substrate SUB2 has a light-shielding layer BM including a light-shielding portion BMA2, a color filter CF including coloring layers CF1, CF2, and CF3, a transparent layer OC, and an alignment film AL2 on the side of the insulating substrate 20 opposite to the first substrate SUB1. The light-shielding portion BMA2 is formed on the inner surface of the insulating substrate 20. The light-shielding portion BMA2 is located directly above the signal line S and the metal layer ML. The coloring layers CF1 and CF2 are formed on the inner surface of the insulating substrate 20, and a portion of them overlaps with the light-shielding portion BMA2. The transparent layer OC covers the color filter CF. The alignment film AL2 covers the transparent layer OC. In addition, a polarizer PL2 is formed on the outer side of the second substrate SUB2.

[0112] Alternatively, the liquid crystal display panel PNL can also be configured such that the display area DA does not have light-shielding portions BMA2 and BMA1. Figure 6 In this case, the metal layer ML can be formed into a grid shape in the display area DA, replacing the light-shielding parts BMA1 and BMA2 to give the metal layer ML a light-shielding function.

[0113] The liquid crystal layer LC has a display liquid crystal layer LCI located in the display area DA. For example, the transmission axes of polarizers PL1 and PL2 are orthogonal. In pixel PX1, in the off (OFF) state where no voltage (electric field) is generated between the pixel electrode PE and the common electrode CE, and no voltage is applied to the display liquid crystal layer LCI, the liquid crystal molecules contained in the display liquid crystal layer LCI are initially aligned in the direction of the transmission axis of polarizer PL1 between alignment films AL1 and AL2. Therefore, no phase difference is generated in the liquid crystal layer LC. Since the transmission axes of polarizers PL1 and PL2 are orthogonal, pixel PX1 has minimum transmittance and displays black. That is, in pixel PX1, the liquid crystal display panel PNL performs a light-shielding function.

[0114] On the other hand, in pixel PX1a, when the liquid crystal layer LCI is in the ON state (voltage (electric field) generated between the pixel electrode PE and the common electrode CE is applied), the liquid crystal molecules align in a direction different from the initial alignment direction, and this alignment direction is controlled by the electric field. That is, a phase difference is generated in the liquid crystal layer LC, and in pixel PX1, the liquid crystal display panel PNL performs its light-transmitting function. Therefore, pixel PX1 in the ON state displays the color corresponding to the color layer CF1.

[0115] The PNL method of the LCD panel is the so-called "normally black" method, which displays black when the LCD is off, but it can also be the so-called "normally white" method, which displays black when the LCD is on (and white when the LCD is off).

[0116] Of the pixel electrode PE and the common electrode CE, the electrode closer to the liquid crystal layer LCI (liquid crystal layer LC) is the pixel electrode PE, which functions as a display electrode as described above. However, the electrode closer to the liquid crystal layer LCI (liquid crystal layer LC) among the pixel electrode PE and the common electrode CE can also be the common electrode CE. In this case, the common electrode CE has a slit located in the opening region AP, functions as a display electrode as described above, and has a linear display electrode instead of the pixel electrode PE.

[0117] Figure 8 This is a plan view showing the light-shielding layer BM in the incident light control area PCA of the liquid crystal display panel (PNL). The light-shielding layer BM is marked with dotted patterns in the figure. Figure 8 As shown, the incident light control region PCA includes a second incident light adjustment region TA2 at its center, and from the outside to the center includes a first shading region LSA1, a first incident light adjustment region TA1, a third shading region LSA3, a third incident light adjustment region TA3, a second shading region LSA2, and a second incident light adjustment region TA2.

[0118] The first light-shielding region LSA1 is located at the outermost periphery of the incident light control region PCA and is in the shape of a ring. The first light-shielding region LSA1 has an outer periphery that contacts the display region DA. The first incident light adjustment region TA1 is surrounded by the first light-shielding region LSA1 and has an outer periphery that contacts the first light-shielding region LSA1, and is in the shape of a ring. The second incident light adjustment region TA2 is located at the center of the incident light control region PCA and has an outer periphery that contacts the second light-shielding region LSA2, and is in the shape of a circle.

[0119] The second light-shielding region LSA2 has an inner periphery that contacts the second incident light adjustment region TA2, surrounding the second incident light adjustment region TA2 in a ring shape. The third light-shielding region LSA3 is surrounded by the first incident light adjustment region TA1, and has an outer periphery that contacts the first incident light adjustment region TA1, also in a ring shape. The third incident light adjustment region TA3 is surrounded by the third light-shielding region LSA3, and has an outer periphery that contacts the third light-shielding region LSA3 and an inner periphery that contacts the second light-shielding region LSA2, also in a ring shape.

[0120] The first light-blocking region LSA1, the second light-blocking region LSA2, and the third light-blocking region LSA3 can be referred to as an annular light-blocking region. The first incident light adjustment region TA1 and the third incident light adjustment region TA3 can be referred to as an annular incident light adjustment region. The second incident light adjustment region TA2 can be referred to as a circular incident light adjustment region. The first incident light adjustment region TA1, the second incident light adjustment region TA2, and the third incident light adjustment region TA3 are regions where the amount of light transmitted can be adjusted.

[0121] In the incident light control region PCA, the light-shielding layer BM includes a first light-shielding portion BM1, a first opening OP1, a second light-shielding portion BM2, a second opening OP2, a third light-shielding portion BM3, and a third opening OP3. The first light-shielding portion BM1 is located in the first light-shielding region LSA1 and is annular in shape. The second light-shielding portion BM2 is located in the second light-shielding region LSA2 and is annular in shape. The third light-shielding portion BM3 is located in the third light-shielding region LSA3 and is annular in shape.

[0122] The light-shielding portions of the first light-shielding portion BM1, the second light-shielding portion BM2, and the third light-shielding portion BM3 are each referred to as annular light-shielding portions. The first opening OP1 and the third opening OP3 are annular in shape, and the second opening OP2 is circular in shape.

[0123] In addition, the first light-shielding part BM1, the second light-shielding part BM2 and the third light-shielding part BM3 can be formed on the same layer as the light-shielding layer BM formed in the display area DA through the same process and the same material.

[0124] The outer circumferences of the first light-shielding part BM1, the first incident light adjustment area TA1, the second light-shielding part BM2, the second incident light adjustment area TA2, the third light-shielding part BM3, and the third incident light adjustment area TA3 are concentric circles.

[0125] The liquid crystal display panel PNL can also be configured without the third light-shielding region LSA3, the third light-shielding part BM3, and the third incident light adjustment region TA3. In this case, the inner periphery of the first incident light adjustment region TA1 only needs to contact the second light-shielding region LSA2.

[0126] Figure 9 The electrode structure representing the incident light control area PCA of the PNL (Parallel Light Layer) in a liquid crystal display panel is a planar diagram showing multiple control electrode structures RE. For example... Figure 9 and Figure 8 As shown, the liquid crystal display panel PNL includes a first control electrode structure RE1, a second control electrode structure RE2, a third control electrode structure RE3, a fourth control electrode structure RE4, a fifth control electrode structure RE5, and a sixth control electrode structure RE6.

[0127] in addition, Figure 9 A schematic diagram is shown in the incident light control region PCA, illustrating the case where the electrodes have a structure corresponding to the IPS (In-Plane-Switching) mode.

[0128] The first control electrode structure RE1 includes a first power supply wiring CL1 and a first control electrode RL1.

[0129] The first power supply wiring CL1 is located in the first light-shielding area LSA1 and includes the first wiring WL1. In this embodiment, the first wiring WL1 is in the shape of a ring.

[0130] Multiple first control electrodes RL1 are located in the first light-shielding region LSA1 and the first incident light adjustment region TA1, are electrically connected to the first wiring WL1, extend linearly in the first extension direction d1, and are spaced apart in the orthogonal direction dc1. The first control electrodes RL1 are disposed inside the first wiring WL1.

[0131] The plurality of first control electrodes RL1 include a first control electrode RL1 connected to a first wiring WL1 at both ends, and a first control electrode RL1 connected to the first wiring WL1 at one end and not connected to the first wiring WL1 at the other end.

[0132] The second control electrode structure RE2 includes a second power supply line CL2 and a second control electrode RL2. The second power supply line CL2 includes a second line WL2. The second control electrode structure RE2 has the same structure as the first control electrode structure RE1. The second line WL2 is located inside the first line WL1, but it can also be located outside the first line WL1.

[0133] Multiple first control electrodes RL1 and multiple second control electrodes RL2 are alternately arranged in the orthogonal direction dc1.

[0134] The third control electrode structure RE3 and the fourth control electrode structure RE4 are located in the second light-shielding region LSA2 and the second incident light conditioning region TA2. Each of the third control electrode structure RE3 and the fourth control electrode structure RE4 is represented as a semicircle with a side parallel to the first extending direction d1. The aforementioned side of the third control electrode structure RE3 and the aforementioned side of the fourth control electrode structure RE4 are spaced apart in the orthogonal direction dc1. Furthermore, the shapes of the third control electrode structure RE3 and the fourth control electrode structure RE4 can be varied.

[0135] The fifth control electrode structure RE5 includes the fifth power supply wiring CL5 and the fifth control electrode RL5. The fifth power supply wiring CL5 includes the fifth wiring WL5. The fifth power supply wiring CL5 is located in the third light-shielding area LSA3 and is in a ring shape.

[0136] Multiple fifth control electrodes RL5 are located in the third light-shielding region LSA3 and the third incident light conditioning region TA3, and are electrically connected to the fifth wiring WL5. They extend linearly in the first extension direction d1 and are spaced apart in the orthogonal direction dc1. The fifth wiring WL5 and the fifth control electrodes RL5 are formed as a single unit. The fifth control electrodes RL5 are disposed inside the fifth wiring WL5.

[0137] The plurality of fifth control electrodes RL5 include a fifth control electrode RL5 connected to a fifth wiring WL5 at both ends, and a fifth control electrode RL5 connected to a fifth wiring WL5 at one end but not connected to a fifth wiring WL5 at the other end.

[0138] The sixth control electrode structure RE6 includes a sixth power supply wiring CL6 and a sixth control electrode RL6. The sixth power supply wiring CL6 includes a sixth wiring WL6. The sixth control electrode structure RE6 has the same structure as the fifth control electrode structure RE5. The sixth wiring WL6 is located inside the fifth wiring WL5, but it can also be located outside the fifth wiring WL5.

[0139] Multiple fifth control electrodes RL5 and multiple sixth control electrodes RL6 are arranged alternately in the orthogonal direction dc1.

[0140] In addition, the first power supply line CL1, the second power supply line CL2, the fifth power supply line CL5 and the sixth power supply line CL6 can be composed of a laminate of a transparent conductive layer and a metal layer.

[0141] If already used Figure 7 As explained, the pixel electrode PE and common electrode CE of the display area DA are formed of a transparent conductive material (transparent conductive film), and the pixel PX has two different transparent conductive films. The first wiring WL1 to the sixth wiring WL6 are formed from one of the two transparent conductive films, and the first control electrode RL1 to the sixth control electrode RL6 are formed from the other transparent conductive film. The first control electrode RL1 to the sixth control electrode RL6 can be formed in the same layer. Alternatively, the first wiring WL1 to the sixth wiring WL6 can also be formed from a multilayer film of transparent conductive film and metal film.

[0142] The liquid crystal display panel (PNL) has a structure in the incident light control area (PCA) corresponding to the IPS mode, one of the display modes utilizing a lateral electric field. The first control electrodes RL1 to the sixth control electrodes RL6 each have a shape different from the shape of the pixel electrode PE corresponding to the FFS mode.

[0143] A voltage is supplied to the control electrodes, which are alternately arranged, represented by the first control electrode RL1 and the second control electrode RL2, and the liquid crystal molecules are driven by the potential difference generated between the electrodes.

[0144] In the incident light control region PCA, the alignment films AL1 and AL2 have an alignment axis AA parallel to the direction Y. That is, the alignment axis AA of the alignment films AL1 and AL2 is parallel in the display region DA and in the incident light control region PCA. In the incident light control region PCA, the alignment direction AD1 of the alignment film AL1 is parallel to the direction Y, and the alignment direction AD2 of the alignment film AL2 is parallel to the alignment direction AD1.

[0145] When no voltage is applied to the liquid crystal layer LC, the initial orientation direction of the liquid crystal molecules in the display area DA is the same as the initial orientation direction of the liquid crystal molecules in the incident light control area PCA. The aforementioned linear pixel electrode (linear display electrode) PA extends parallel to the control electrode RL. In the XY plane, the first extension direction d1 and the second extension direction d2 are each tilted by 10° relative to direction Y. Therefore, the rotation direction of the liquid crystal molecules can be unified in both the display area DA and the incident light control area PCA. The tilting has been explained above based on the linear pixel electrode PA. However, the same applies when the tilt of the linear pixel electrode PA is replaced by the tilt of the gap of the common electrode.

[0146] Figure 10 This is a cross-sectional view of the incident light control area PCA of the PNL (Parallel Light Layer) of a liquid crystal display panel. Figure 10 The diagrams of signal lines S, scan lines G, etc., are omitted.

[0147] like Figure 10 As shown, one of the two conductors formed with an insulating layer 13 is disposed in the same layer as one of the pixel electrode PE and the common electrode CE, and is formed of the same material as the aforementioned electrode. The other conductor of the two conductors is disposed in the same layer as the other electrode of the pixel electrode PE and the common electrode CE, and is formed of the same material as the aforementioned other electrode.

[0148] exist Figure 10 In this structure, the second wiring WL2, the second control electrode RL2, the fourth control electrode structure RE4, the sixth wiring WL6, and the sixth control electrode RL6 are disposed on the insulating layer 12 and covered by the insulating layer 13. The second wiring WL2, the second control electrode RL2, the fourth control electrode structure RE4, the sixth wiring WL6, and the sixth control electrode RL6 are disposed on the same layer as the common electrode CE and are formed of the same transparent conductive material as the common electrode CE.

[0149] The first wiring WL1, the first control electrode RL1, the third control electrode structure RE3, the fifth wiring WL5, and the fifth control electrode RL5 are disposed on the insulating layer 13 and covered by the alignment film AL1. The first control electrode RL1, the third control electrode structure RE3, the fifth wiring WL5, and the fifth control electrode RL5 are disposed on the same layer as the pixel electrode PE and are formed of the same transparent conductive material as the pixel electrode PE.

[0150] For example, the insulating layer 13 is sandwiched between the first control electrode RL1 (first control electrode structure RE1) and the second control electrode RL2 (second control electrode structure RE2). Furthermore, the first control electrode RL1, the second control electrode RL2, the third control electrode structure RE3, the fourth control electrode structure RE4, the fifth control electrode RL5, and the sixth control electrode RL6 can be formed in the same layer.

[0151] In the incident light control region PCA, the alignment film AL1 covers the first wiring WL1, the first control electrode RL1, the second wiring WL2, the second control electrode RL2, the third control electrode structure RE3, the fourth control electrode structure RE4, the fifth wiring WL5, the fifth control electrode RL5, the sixth wiring WL6, and the sixth control electrode RL6, and is in contact with the liquid crystal layer LC.

[0152] In the second substrate SUB2, no color filter CF is provided in the incident light control region PCA.

[0153] The liquid crystal layer LC has a first control liquid crystal layer LC1 located in the first incident light conditioning region TA1, a second control liquid crystal layer LC2 located in the second incident light conditioning region TA2, and a third control liquid crystal layer LC3 located in the third incident light conditioning region TA3.

[0154] The first control liquid crystal layer LC1 is subjected to a voltage generated by the first control electrode RL1 and the second control electrode RL2. The second control liquid crystal layer LC2 is subjected to a voltage generated by the third control electrode structure RE3 and the fourth control electrode structure RE4. The third control liquid crystal layer LC3 is subjected to a voltage generated by the fifth control electrode RL5 and the sixth control electrode RL6.

[0155] Here, we focus on driving the first control electrode structure RE1 and the second control electrode structure RE2 among the multiple control electrodes RL, which are used to apply a voltage to the first control liquid crystal layer LC1. A first control voltage is provided to the first control electrode structure RE1, and a second control voltage is provided to the second control electrode structure RE2.

[0156] Alternatively, one of the first control voltage and the second control voltage may be fixed to the same reference voltage as the common electrode, and the other of the first control voltage and the second control voltage may switch between the reference voltage, a first output voltage that is positive relative to the reference voltage, and a second output voltage that is negative relative to the reference voltage.

[0157] Alternatively, during any given period, one of the first control voltage and the second control voltage may be the first output voltage, and the other of the first control voltage and the second control voltage may be the second output voltage.

[0158] By setting the first control voltage and the second control voltage as described above, polarity reversal drive can be facilitated, for example. Furthermore, the driving of the first control electrode structure RE1 and the second control electrode structure RE2 described above can also be applied to the driving of the third control electrode structure RE3 and the fourth control electrode structure RE4, as well as the driving of the fifth control electrode structure RE5 and the sixth control electrode structure RE6.

[0159] Next, as representatives of the first control electrode structures RE1 to the sixth control electrode structures RE6, the circuit structure for driving the first control electrode structure RE1 and the second control electrode structure RE2 will be described. The content described here is also applicable to the circuit structure for driving the group of third control electrode structures RE3 and fourth control electrode structures RE4, as well as the circuit structure for driving the group of fifth control electrode structures RE5 and sixth control electrode structures RE6.

[0160] First, the first control electrode structure RE1 and the second control electrode structure RE2, as well as their peripheral circuits, will be described. Figure 11This diagram shows the equivalent circuit of multiple control switch groups Wa and Wb, multiple level shifters SIa and SIb, multiple charge pumps CP1 and CP2, first control electrode structure RE1, scan line G, and signal line S of a liquid crystal display panel PNL. It also shows multiple pixels PX, scan line drive circuit GD, and signal line drive circuit SD.

[0161] like Figure 11 As shown, the liquid crystal display panel (PNL) includes a scan line driving circuit GD and a signal line driving circuit SD. The scan line driving circuit GD is connected to multiple scan lines G. The signal line driving circuit SD is connected to multiple signal lines S. Additionally, a portion of the scan line driving circuit GD and the signal line driving circuit SD can be disposed outside the liquid crystal display panel (PNL).

[0162] The liquid crystal display panel (PNL) also includes multiple control switch groups Wa and Wb, multiple level shifters SIa and SIb, and multiple charge pumps CP1 and CP2. Control switch group Wa includes control switch W1a and control switch W2a. Control switch group Wb includes control switch W1b and control switch W2b. Each of the control switches W1a, W2a, W1b, and W2b is electrically connected to one corresponding signal line S from among the multiple scan lines G and multiple signal lines S.

[0163] For example, the multiple scan lines G electrically connected to control switch W1a are the same as the multiple scan lines G electrically connected to control switch W2a. The multiple scan lines G electrically connected to control switch W1b are the same as the multiple scan lines G electrically connected to control switch W2b. Control switches W1a and W1b are electrically connected to different signal lines respectively. Control switches W2a and W2b are electrically connected to different signal lines respectively.

[0164] The control switches W1a, W2a, W1b, and W2b are respectively provided with control signals SG from the scan line drive circuit GD via the scan line G, and with the first power supply voltage vdd and the second power supply voltage vss from the signal line drive circuit SD via the signal line S.

[0165] The voltage level of the control signal SG switches between a gate high voltage VGH and a gate low voltage VGL. In this embodiment, VGH = +8V and VGL = -8V.

[0166] The voltage level output by the signal line driver circuit SD is within the range between the first power supply voltage Vdd and the second power supply voltage Vss. For example, the level of the first power supply voltage Vdd is positive compared to the level of the reference voltage (gnd) (ground level), and the level of the second power supply voltage Vss is negative compared to the level of the reference voltage. Additionally, the voltage level of the image signal Vsig output by the signal line driver circuit SD for a typical pixel PX is within the range between the first power supply voltage Vdd and the second power supply voltage Vss. In this embodiment, Vdd = +5V, and Vss = -5V.

[0167] Control switches W1a and W2a are electrically connected to level shifting unit SIa. Level shifting unit SIa includes level shifting circuit LS1a and level shifting circuit LS2a. In this embodiment, control switch W1a is electrically connected to level shifting circuit LS1a, and control switch W2a is electrically connected to level shifting circuit LS2a. The signal output from control switch W1a is input to level shifting circuit LS1a, and the signal output from control switch W2a is input to level shifting circuit LS2a.

[0168] The level shifting unit SIa is electrically connected to the charge pump CP1. In this embodiment, level shifting circuits LS1a and LS2a are respectively electrically connected to the charge pump CP1. The signals output from level shifting circuit LS1a and level shifting circuit LS2a are respectively input to the charge pump CP1. The charge pump CP1 generates a first output voltage gvdd based on the signal provided by the level shifting unit SIa. The absolute value of the first output voltage gvdd is greater than the absolute value of the first power supply voltage vdd. In this embodiment, the first output voltage gvdd is +10V. The first output voltage gvdd is either input to the first control electrode structure RE1 (first control electrode RL1) via the on-state switch SSW1, or input to the level shifting units SIa and SIb. The charge pump CP1 is connected, for example, to the first control electrode structure RE1 (first control electrode RL1) which serves as a load unit.

[0169] Control switches W1b and W2b are electrically connected to the level shifting unit SIb. The level shifting unit SIb includes level shifting circuits LS1b and LS2b. In this embodiment, control switch W1b is electrically connected to level shifting circuit LS1b, and control switch W2b is electrically connected to level shifting circuit LS2b. The signal output from control switch W1b is input to level shifting circuit LS1b, and the signal output from control switch W2b is input to level shifting circuit LS2b.

[0170] The level shifting unit SIb is electrically connected to the charge pump CP2. In this embodiment, level shifting circuits LS1b and LS2b are respectively electrically connected to the charge pump CP2. The signals output from level shifting circuit LS1b and level shifting circuit LS2b are respectively input to the charge pump CP2. The charge pump CP2 generates a second output voltage gvss based on the signal provided by the level shifting unit SIb. The absolute value of the second output voltage gvss is greater than the absolute value of the second power supply voltage vss. In this embodiment, the second output voltage gvss is -10V. The second output voltage gvss is either input to the first control electrode structure RE1 (first control electrode RL1) via the on-state switch SSW2, or input to the level shifting units SIa and SIb. Similarly, the charge pump CP2 is connected to the first control electrode structure RE1 (first control electrode RL1), which serves as a load unit, just like the charge pump CP1.

[0171] Each control switch W1a, W2a, W1b, and W2b is connected to a scan line G and a signal line S that are connected to multiple pixels PX. For example, the signal line S connected to control switch W1a is the same as the signal line S connected to the pixel switching element SWp of pixel PXα among the multiple pixels PX. Furthermore, a scan line G connected to control switch W1a is the same as the scan line G connected to the pixel switching element SWp of pixel PXβ among the multiple pixels PX.

[0172] A control signal SG is also provided to the pixel switching element SWp of pixel PX. The voltage level of the control signal SG switches between two values: gate low voltage VGL and gate high voltage VGH. The pixel switching element SWp of pixel PX toggles whether to output the image signal Vsig to the pixel electrode PE. In addition, multiple pixel switching elements SWp and multiple pixel electrodes PE are located in the display area DA.

[0173] The signal line drive circuit SD outputs a first power supply voltage vdd and a second power supply voltage vss to the signal lines S connected to each control switch W1a, W2a, W1b, and W2b, in addition to the image signal Vsig. Therefore, each control switch W1a, W2a, W1b, and W2b selectively outputs one of the first power supply voltage vdd and the second power supply voltage vss during each horizontal scan period.

[0174] Here, the positions of control switches W1a, W2a, W1b, W2b, level shifters SIa, SIb, and charge pumps CP1, CP2 in the incident light control region PCA are explained.

[0175] like Figure 8 , Figure 9 and Figure 11As shown, control switches W1a, W2a, W1b, W2b, level shifters SIa, SIb, and charge pumps CP1, CP2 are located in the light-shielding region LSA. In this embodiment, control switches W1a, W2a, W1b, W2b, level shifters SIa, SIb, and charge pumps CP1, CP2 are located in the first light-shielding region LSA1.

[0176] Furthermore, preferably, the control switch W, the level shifting unit SI, and the charge pump CP, which are electrically connected to each control electrode structure RE other than the first control electrode structure RE1, are also located in the light-shielding area LSA, such as the first light-shielding area LSA1. Since the control switch W, the level shifting unit SI, and the charge pump CP are not located in the incident light conditioning area TA, it is possible to prevent the area of ​​the incident light conditioning area TA from shrinking.

[0177] Next, control switch W1a will be described as a representative of control switches W1a, W2a, W1b, and W2b. The description herein is also applicable to the other control switches W. Figure 12 It means Figure 11 The circuit diagram shown is a part of a control switch W1a, and is also an example of the signal waveform output by the control switch W1a.

[0178] like Figure 11 and Figure 12 As shown, the control switch W1a has multiple control switch elements SWc. The control switch elements SWc are formed, for example, by an N-channel transistor (TFT). In this embodiment, the control switch elements SWc are configured similarly to the pixel switch elements SWp.

[0179] The control switch element SWc has a gate electrode Eg electrically connected to a corresponding scan line G among a plurality of scan lines G, a source electrode Es and a drain electrode Ed electrically connected to a corresponding signal line S among a plurality of signal lines S. The plurality of scan lines G electrically connected to the plurality of gate electrodes Eg of the plurality of control switch elements SWc of control switch W1a are different from each other. The plurality of drain electrodes Ed of the plurality of control switch elements SWc of control switch W1a are electrically combined into one and connected to the power supply voltage output terminal POUT of control switch W1a.

[0180] in addition, Figure 12 The diagram shows three control switch elements SWc, but the number of control switch elements SWc that the control switch W1a can have is not limited to three; it can have multiple elements.

[0181] In this embodiment, the multiple scan lines G electrically connected to the multiple gate electrodes Eg of the multiple control switching elements SWc of the control switch W1a are continuously arranged in the Y direction. Furthermore, the multiple source electrodes Es of the multiple control switching elements SWc of the control switch W1a are electrically connected to the same signal line S.

[0182] As described above, since control switch W1a includes multiple control switch elements SWc, it can freely generate signals with different voltage levels in units of one horizontal scan period (1H). Therefore, control switch W1a can make the voltage level of the signal output from the power supply voltage output terminal POUT either fixed or vary between -5V and +5V within one vertical scan period (one frame period). Figure 12 In the example shown, the voltage level of the signal output by the control switch W1a alternately switches every 1H between the first power supply voltage Vdd and the second power supply voltage VSS. Additionally, the reference voltage Gnd is at ground level, which is essentially 0V.

[0183] On the other hand, the voltage level of the image signal Vsig output from the pixel switching element SWp to the pixel electrode PE remains unchanged during one vertical scan period (one frame period). Furthermore, the pixel electrode PE can be referred to as a load portion different from the first control electrode structure RE1 (first control electrode RL1).

[0184] Next, regarding Figure 11 The circuit structure of the PNL liquid crystal display panel shown is explained. Figure 13 This is a circuit diagram showing the electrical system used to generate the first output voltage gvdd. Figure 11 The diagram shows two control switches W1a and W2a, two level shift circuits LS1a and LS2a, and a charge pump CP1.

[0185] like Figure 13 As shown, control switch W1a outputs the first power supply voltage vdd and the second power supply voltage vss, which are input from signal line S, to its own power supply voltage output terminal POUT in a time-division manner. The power supply voltage output terminal POUT of control switch W1a is electrically connected to the input terminal IN of level shifting circuit LS1a. Between control switch W1a and level shifting circuit LS1a, one electrode of capacitor (smoothing capacitor) C1 is electrically connected. The other electrode of capacitor C1 is electrically connected, for example, to a common electrode CE, and is electrically fixed to a common voltage Vcom.

[0186] The level shifting circuit LS1a outputs the signal Sig1 to the charge pump CP1.

[0187] Control switch W2a outputs the first power supply voltage Vdd and the second power supply voltage Vss, input from signal line S, in a time-division manner to its own power supply voltage output terminal POUT. The power supply voltage output terminal POUT of control switch W2a is electrically connected to the input terminal IN of level shifting circuit LS2a. Between control switch W2a and level shifting circuit LS2a, one electrode of capacitor (smoothing capacitor) C2 is electrically connected. The other electrode of capacitor C2 is electrically connected, for example, to the common electrode CE, and is electrically fixed to the common voltage Vcom.

[0188] The level shifting circuit LS2a outputs the signal Sig2 to the charge pump CP1.

[0189] The charge pump CP1 includes multiple switches SW1, SW2, SW3, SW4, a capacitor Cn, a charge pump capacitor Ccg, a capacitor (smoothing capacitor) Ct, a power input terminal Tc1, and an output terminal OUT. Switches SW1, SW2, SW3, and SW4 are formed by transistors (TFTs). In this embodiment, switches SW1, SW3, and SW4 are formed by P-channel TFTs, and switch SW2 is formed by an N-channel TFT. One electrode of capacitor Cn and one electrode of capacitor Ct are electrically connected to ground (gnd).

[0190] The output signal Sig1 from the level shift circuit LS1a is provided to the control terminal (gate electrode) of switch SW2 on one hand, and to the control terminal (gate electrode) of switch SW1 via inverter IV on the other hand. The output signal Sig2 from the level shift circuit LS2a is provided to the control terminal (gate electrode) of switch SW3 on one hand, and to the control terminal (gate electrode) of switch SW4 via inverter IV on the other hand.

[0191] During the initial drive period before charge pump CP1 generates the first output voltage gvdd and charge pump CP2 generates the second output voltage gvss, the first power supply voltage vdd is precharged to the first power supply terminal T1 of the level shift circuits LS1a and LS2a and the inverter IV, and the second power supply voltage vss is precharged to the second power supply terminal T2 of the level shift circuits LS1a and LS2a and the inverter IV.

[0192] During the period after charge pump CP1 generates the first output voltage gvdd and charge pump CP2 generates the second output voltage gvss, the first output voltage gvdd is supplied from charge pump CP1 to the first power supply terminal T1 of level shift circuits LS1a and LS2a and inverter IV, and the second output voltage gvss is supplied from charge pump CP2 to the second power supply terminal T2 of level shift circuits LS1a and LS2a and inverter IV.

[0193] Here, the operation during the initial driving period before charge pump CP1 generates the first output voltage gvdd and charge pump CP2 generates the second output voltage gvss will be explained.

[0194] First, control switch W1a outputs a first power supply voltage vdd to level shift circuit LS1a, and control switch W2a outputs a second power supply voltage vss to level shift circuit LS2a. Therefore, level shift circuit LS1a outputs the first power supply voltage vdd as output signal Sig1, and level shift circuit LS2a outputs the second power supply voltage vss as output signal Sig2. The first power supply voltage vdd (output signal Sig1) is inverted by inverter IV to become the second power supply voltage vss, and the second power supply voltage vss (output signal Sig2) is inverted by inverter IV to become the first power supply voltage vdd.

[0195] Therefore, in charge pump CP1, switches SW1 and SW2 are in the ON state, and switches SW3 and SW4 are in the OFF state. Current flows from the power input terminal Tc1 to the charge pump capacitor Ccg via switch SW1. The voltage level of electrode EL1 of charge pump capacitor Ccg is set to the first power supply voltage vdd, and the voltage level of electrode EL2 of charge pump capacitor Ccg is set to the reference voltage (gnd) level. By providing the first power supply voltage vdd to charge pump CP1 from the signal line, charge pump capacitor Ccg is charged.

[0196] Subsequently, control switch W1a outputs a second power supply voltage, vss, to level shift circuit LS1a, and control switch W2a outputs a first power supply voltage, vdd, to level shift circuit LS2a. Thus, level shift circuit LS1a outputs the second power supply voltage, vss, as output signal Sig1, and level shift circuit LS2a outputs the first power supply voltage, vdd, as output signal Sig2. The second power supply voltage, vss (output signal Sig1), is inverted by inverter IV to become the first power supply voltage, vdd, and the first power supply voltage, vdd (output signal Sig2), is inverted by inverter IV to become the second power supply voltage, vss.

[0197] Therefore, in charge pump CP1, switches SW1 and SW2 are switched to the off state, and switches SW3 and SW4 are switched to the on state. Current flows from the power input terminal Tc1 to electrode EL2 of charge pump capacitor Ccg via switch SW3. The voltage level of electrode EL2 of charge pump capacitor Ccg rises from the reference voltage (gnd) level (essentially 0V) to the level of the first power supply voltage vdd (+5V). Consequently, due to the electrostatic coupling of charge pump capacitor Ccg, the voltage level of electrode EL1 also rises to +5V. The voltage level of electrode EL1 is set to +10V, which is the first output voltage gvdd.

[0198] As described above, by providing a first power supply voltage vdd to the charge pump CP1 from the signal line, the charge pump capacitor Ccg is further charged, and the charge pump capacitor Ccg maintains the first output voltage gvdd. As described above, the first output voltage gvdd generated by the charge pump CP1 is output to the output terminal OUT via the switch SW4. The charge pump CP1 outputs the first output voltage gvdd to the first control electrode structure RE1 (first control electrode RL1), etc.

[0199] The charge pump CP1 is capable of outputting a first output voltage gvdd that depends on the voltage (first power supply voltage vdd) input to the power input terminal Tc1. In other words, the charge pump CP1 can boost the first power supply voltage vdd input to the power input terminal Tc1 to the first output voltage gvdd.

[0200] Next, a method for providing a first power supply voltage vdd to the power input terminal Tc1 of the charge pump CP1 will be described. Figure 14 It means and Figure 11 The multiple control switches W1a, W2a, W1b, W2b shown are different from a portion of one control switch W3a, and Figure 11 and Figure 13 The circuit diagram of charge pump CP1 shows the connection between the power supply voltage output terminal POUT of control switch W3a and the power supply input terminal Tc1 of charge pump CP1.

[0201] like Figure 14 As shown, control switch W3a has multiple control switching elements SWc. The multiple gate electrodes Eg of the multiple control switching elements SWc of control switch W3a are electrically connected to multiple scan lines G, which are different from each other. The multiple drain electrodes Ed of the multiple control switching elements SWc of control switch W3a are electrically combined into one and connected to the power supply voltage output terminal POUT of control switch W3a. The power supply voltage output terminal POUT of control switch W3a is electrically connected to the power supply input terminal Tc1 of charge pump CP1.

[0202] in addition, Figure 14 The diagram shows three control switching elements SWc, but the number of control switching elements SWc in control switch W3a is preferably the same as or greater than the number of control switching elements SWc in control switch W1a. Therefore, during the ON / OFF switching of the switch SW of charge pump CP1, control switch W3a can continuously provide a first power supply voltage vdd to the power input terminal Tc1 of charge pump CP1. For example, control switch W3a may have 100 control switching elements SWc.

[0203] In this embodiment, the multiple scan lines G electrically connected to the multiple gate electrodes Eg of the multiple control switching elements SWc of the control switch W3a are continuously arranged in the Y direction. Furthermore, the multiple source electrodes Es of the multiple control switching elements SWc of the control switch W3a are electrically connected to the same signal line S. As described above, since the control switch W3a includes multiple control switching elements SWc, it is possible to continuously output the first power supply voltage Vdd throughout multiple horizontal scans.

[0204] Control switch W3a is a different control switch from the control switches W1a, W2a, W1b, and W2b mentioned above. For example, the multiple scan lines G electrically connected to control switch W1a can all be included within the multiple scan lines G electrically connected to control switch W3a. Alternatively, several of the multiple scan lines G electrically connected to control switch W1a can be included within the multiple scan lines G electrically connected to control switch W3a.

[0205] As described above, for the charge pump capacitor Ccg, by inputting a first power supply voltage vdd from the level shifting circuit LS1a, the voltage input from the power supply voltage output terminal POUT of the control switch W3a (the first power supply voltage vdd) can be charged. Then, the voltage input from the power supply voltage output terminal POUT of the control switch W3a is further applied to the charge pump capacitor Ccg. The charge pump CP1 generates a first output voltage gvdd that depends on the voltage input from the power supply voltage output terminal POUT of the control switch W3a, and maintains the first output voltage gvdd in the charge pump capacitor Ccg.

[0206] Next, we will describe the level shift circuit LS1a as a representative of the level shift circuits LS1a and LS2a. The content described here is also applicable to other level shift circuits LS. Figure 15 It means Figure 11 and Figure 13 The circuit diagram of a level shifter circuit LS1a.

[0207] like Figure 15 As shown, the level shifting circuit LS1a has a front stage P1a, a rear stage P1b, and a main body P1c.

[0208] The input terminal IN of the preamplifier P1a is electrically connected to the control switch W1a. The preamplifier P1a consists of a single inverter IT. The output terminal OUT of the power amplifier P1b is electrically connected to the charge pump CP1. The power amplifier P1b consists of three inverters IT connected in series. The number of stages of the inverters IT in both the preamplifier P1a and the power amplifier P1b can vary.

[0209] The inverter in the front stage P1a is not limited to one stage, but can be an odd number of stages other than one. In this case, the inverter in the rear stage P1b is not limited to three stages, but can be an odd number of stages other than three.

[0210] The level shifting circuit LS1a can also be configured without a preceding stage P1a (the inverter stage P1a has 0 stages). Alternatively, the inverter stage P1a can have an even number of stages. In this case, the inverter stage P1b can also have an even number of stages.

[0211] The main body P1c is electrically connected between the front stage P1a and the rear stage P1b. The main body P1c has one inverter IT, multiple N-channel TFTs trn and multiple P-channel TFTs trp.

[0212] Next, regarding Figure 11 The circuit structure of the PNL liquid crystal display panel shown is explained. Figure 16 This is a circuit diagram showing the electrical system used to generate the second output voltage gvss. Figure 11 The diagram shows two control switches W1b and W2b, two level shift circuits LS1b and LS2b, and a charge pump CP2. Additionally, Figure 16 The electrical system, except for the aspects described below, is related to Figure 13 Their electrical systems are the same.

[0213] like Figure 16 As shown, the power supply voltage output terminal POUT of control switch W1b is electrically connected to the input terminal IN of level shifting circuit LS1b. Control switch W1b outputs the first power supply voltage vdd and the second power supply voltage vss input from signal line S to its own power supply voltage output terminal POUT. The power supply voltage output terminal POUT of control switch W2b is electrically connected to the input terminal IN of level shifting circuit LS2b. Control switch W2b outputs the first power supply voltage vdd and the second power supply voltage vss input from signal line S to its own power supply voltage output terminal POUT.

[0214] The charge pump CP2 includes multiple switches SW1, SW2, SW3, SW4, capacitor Cn, charge pump capacitor Ccg, capacitor (smoothing capacitor) Ct, power input terminal Tc1, and output terminal OUT. In this embodiment, switches SW1, SW3, and SW4 are formed by N-channel TFTs, and switch SW2 is formed by P-channel TFTs.

[0215] The output signal Sig1 from the level shift circuit LS1b is provided to the control terminal (gate electrode) of switch SW2 via inverter IV, and to the control terminal (gate electrode) of switch SW1 without inverter IV. The output signal Sig2 from the level shift circuit LS2b is provided to the control terminal (gate electrode) of switch SW3 and switch SW4 without inverter IV.

[0216] During the initial drive period before charge pump CP1 generates the first output voltage gvdd and charge pump CP2 generates the second output voltage gvss, the first power supply voltage vdd is precharged to the first power supply terminal T1 of the level shift circuits LS1b and LS2b and the inverter IV, and the second power supply voltage vss is precharged to the second power supply terminal T2 of the level shift circuits LS1b and LS2b and the inverter IV.

[0217] During the period after charge pump CP1 generates the first output voltage gvdd and charge pump CP2 generates the second output voltage gvss, the first output voltage gvdd is supplied from charge pump CP1 to the first power supply terminal T1 of level shift circuits LS1b and LS2b and inverter IV, and the second output voltage gvss is supplied from charge pump CP2 to the second power supply terminal T2 of level shift circuits LS1b and LS2b and inverter IV.

[0218] Here, the operation during the initial driving period before charge pump CP1 generates the first output voltage gvdd and charge pump CP2 generates the second output voltage gvss will be explained.

[0219] First, control switch W1b outputs a first power supply voltage vdd to level shift circuit LS1b, and control switch W2b outputs a first power supply voltage vdd to level shift circuit LS2b. Then, level shift circuit LS1b outputs the first power supply voltage vdd as output signal Sig1, and level shift circuit LS2b outputs the second power supply voltage vss as output signal Sig2. The first power supply voltage vdd (output signal Sig1) is inverted by inverter IV to become the second power supply voltage vss.

[0220] Therefore, in charge pump CP2, switches SW1 and SW2 are in the ON state, and switches SW3 and SW4 are in the OFF state. Current flows from charge pump capacitor Ccg to power input terminal Tc1 via switch SW1. The voltage level of electrode EL1 is set to the second power supply voltage VSS, and the voltage level of electrode EL2 is set to the reference voltage (GND) level. As described above, by outputting the first power supply voltage Vdd from the level shifting circuit LS1b to charge pump CP2, charge pump capacitor Ccg is charged.

[0221] Subsequently, control switch W1b outputs a second power supply voltage, vss, to level shift circuit LS1b, and control switch W2b outputs a first power supply voltage, vdd, to level shift circuit LS2b. Thus, level shift circuit LS1b outputs the second power supply voltage, vss, as output signal Sig1, and level shift circuit LS2b outputs the first power supply voltage, vdd, as output signal Sig2. The second power supply voltage, vss (output signal Sig1), is inverted by inverter IV to become the first power supply voltage, vdd.

[0222] Therefore, in charge pump CP2, switches SW1 and SW2 are switched to the off state, and switches SW3 and SW4 are switched to the on state. Current flows through switch SW3 from electrode EL2 of charge pump capacitor Ccg to power input terminal Tc1. The voltage level of electrode EL2 of charge pump capacitor Ccg drops from the reference voltage (gnd) level (actually 0V) to the level of the second power supply voltage vss (-5V). Consequently, due to the electrostatic coupling of charge pump capacitor Ccg, the voltage level of electrode EL1 also drops to -5V. The voltage level of electrode EL1 is set to -10V, which is the second output voltage gvss.

[0223] As described above, by outputting the first power supply voltage vdd from the level shifting circuit LS2b to the charge pump CP2, the charge pump capacitor Ccg is further charged, and the charge pump capacitor Ccg maintains the second output voltage gvss. As described above, the second output voltage gvss generated by the charge pump CP2 is output to the output terminal OUT via the switch SW4. The charge pump CP2 outputs the second output voltage gvss to the first control electrode structure RE1 (first control electrode RL1), etc.

[0224] The charge pump CP2 is capable of outputting a second output voltage gvss that depends on the voltage input to the power input terminal Tc1 (the second power supply voltage vss). In other words, the charge pump CP2 can step down the second power supply voltage vss input to the power input terminal Tc1 to the second output voltage gvss.

[0225] As a method of providing a second power supply voltage vss to the power input terminal Tc1 of charge pump CP2, it is possible to utilize with Figure 14 The control switch W3a shown also controls the switch W. By utilizing the control switch with the control switch element, a second power supply voltage vss can be continuously output to the power input terminal Tc1 of the charge pump CP2 throughout multiple horizontal scans.

[0226] The control switch used to provide the second power supply voltage vss to the power input terminal Tc1 of the charge pump CP2 is a different control switch from the control switches W1a, W2a, W1b, W2b, and W3a described above. For example, all the scan lines G electrically connected to the control switch W1a can be included within the multiple scan lines G electrically connected to the control switch used to provide the second power supply voltage vss to the power input terminal Tc1 of the charge pump CP2. Alternatively, several of the multiple scan lines G electrically connected to the control switch W1a can be included within the multiple scan lines G electrically connected to the control switch used to provide the second power supply voltage vss to the power input terminal Tc1 of the charge pump CP2.

[0227] As described above, for the charge pump capacitor Ccg, by inputting a first power supply voltage vdd from the level shifting circuit LS1b, the voltage input to the power supply input terminal Tc1 (the second power supply voltage vss) can be charged. Then, the voltage input to the power supply input terminal Tc1 is further applied to the charge pump capacitor Ccg. The charge pump CP2 generates a second output voltage gvss that depends on the voltage input to the power supply input terminal Tc1, and maintains the second output voltage gvss in the charge pump capacitor Ccg.

[0228] in addition, Figure 16 The level shifting circuits LS1b and LS2b can also be used with Figure 15 The level shifting circuit LS1a shown is similarly constructed.

[0229] Next, examples will be provided. Figure 13 The multiple output signals Sig1 and Sig2 are shown. Figure 17 It means Figure 13 The timing diagrams for the multiple output signals Sig1 and Sig2 are shown.

[0230] like Figure 17 As shown, during any one horizontal scan period, the level shifting circuit LS1a outputs a first output voltage gvdd to the charge pump CP1 (initially the first power supply voltage vdd). This charges the charge pump capacitor Ccg. Furthermore, during a subsequent horizontal scan period, the level shifting circuit LS1a outputs a second output voltage gvss to the charge pump CP1 (initially the second power supply voltage vss). This keeps the charge pump capacitor Ccg in a charged state.

[0231] During the next horizontal scan period, following two horizontal scan periods in any of the aforementioned horizontal scan periods, the level shifting circuit LS2a outputs a first output voltage gvdd to the charge pump CP1 (initially the first supply voltage vdd). This further charges the charge pump capacitor Ccg. Additionally, during the next consecutive horizontal scan period, the level shifting circuit LS2a outputs a second output voltage gvss to the charge pump CP1 (initially the second supply voltage vss). This keeps the charge pump capacitor Ccg in a further charged state. The first output voltage gvdd is maintained at the charge pump capacitor Ccg.

[0232] One cycle of each of the output signals Sig1 and Sig2 corresponds to four horizontal scan periods. In other words, the cycle used to drive the charge pump CP1 is four horizontal scan periods.

[0233] According to the first embodiment of the above-described structure, the electronic device 100 includes a liquid crystal display device (DSP) and a camera 1a, etc. The liquid crystal display device (DSP) includes a liquid crystal display panel (PNL). The liquid crystal display panel (PNL) has an incident light control area (PCA) opposite to the camera 1a. Therefore, the liquid crystal display panel (PNL) can selectively transmit visible light from the outside to the camera 1a.

[0234] Control switches W1a, W2a, W1b, W2b, and W3a each include multiple control switch elements SWc. Therefore, the frequency of the signal output by each control switch W1a, W2a, W1b, W2b, and W3a is higher than the frequency of the signal output by the pixel switch element SWp (pixel switch).

[0235] The signal line driving circuit SD outputs an image signal Vsig to each signal line S. The voltage level applied by the signal line driving circuit SD to the signal line S is in the range of -5V to +5V. Therefore, the pixel electrode PE is driven by the -5V to +5V image signal Vsig.

[0236] To this end, the voltage levels applied to the control electrode RL (control electrode structure RE) are -10V and +10V. The control electrode RL (control electrode structure RE) is driven by a voltage level higher than the voltage level of the driving pixel electrode PE.

[0237] Therefore, insufficient writing to the control electrode RL (control electrode structure RE) can be suppressed. For example, when the incident light control area PCA of the liquid crystal display panel PNL is in a normally black mode, the problem of insufficient transmission amount when the incident light control area PCA of the liquid crystal display panel PNL is switched to a transmission state (white display state) can be solved.

[0238] When the incident light control area (PCA) of the PNL (Polymer Optical Light Control Area) in the liquid crystal display panel is set to a normally white mode, the problem of unclear images from pinhole cameras and IR cameras can be solved. Pinhole cameras refer to imaging where only the second incident light adjustment area (TA2) within the PCA is switched to a transmission state. IR cameras refer to imaging where the entire PCA is switched to a light-blocking state (blocking visible light).

[0239] The control electrode RL (control electrode structure RE) is connected to the signal line S via a control switch W, a level shifting circuit LS, a charge pump CP, etc. The control circuit for the control switch W, the level shifting circuit LS, the charge pump CP, etc., is located in the incident light control region PCA (shielding region LSA). The first output voltage gvdd and the second output voltage gvss supplied to the control electrode RL (control electrode structure RE) can be generated in the incident light control region PCA.

[0240] In the display area DA, it is not necessary to lay wiring that would be subject to high absolute values ​​of voltages such as the first output voltage gvdd and the second output voltage gvss. This allows for the suppression of interference to the pixels PX in the display area DA.

[0241] Next, several examples of variations of the circuit structure of the electrical system used to generate the first output voltage will be described. The circuit structure of the electrical system used to generate the first output voltage is not limited to... Figure 13 The example shown can be modified in various ways.

[0242] (Modification 1 of the first embodiment)

[0243] Next, a variation of the above-described implementation method will be described. Figure 18A It means Figure 13 The circuit diagram of Modified Example 1 of the electrical system shown is a diagram illustrating two control switches W1a and W2a, two level shifting circuits LS1a and LS2a, a charge pump CP1, etc. The electronic device 100 is configured similarly to the embodiment described above, except for the structure described in Modified Example 1.

[0244] like Figure 18A As shown, the multiple switches SW1, SW2, SW3, and SW4 of the charge pump CP1 can each be formed by a P-channel TFT or an N-channel TFT. Switches SW1, SW2, SW3, and SW4 can all be formed by P-channel TFTs.

[0245] In this case, the following adjustments can be made: whether to insert an inverter IV between the level shift circuit LS and the charge pump CP1, and if so, where to insert the inverter IV. In this example, the output signal Sig1 from the level shift circuit LS1a is provided to the control terminal (gate electrode) of switch SW1 and the control terminal (gate electrode) of switch SW2 via the inverter IV.

[0246] In the modified example 1 of the above structure, the same effect as the above embodiment can also be obtained.

[0247] use Figure 18A The techniques described can also be applied to Figure 16 The circuit diagram (the electrical system used to generate the second output voltage). For example, in Figure 16 In this circuit, switches SW1, SW2, SW3, and SW4 can all be formed using N-channel TFTs. The level shifting circuit LS1b can be electrically connected to the charge pump CP1 without going through inverter IV.

[0248] (Modification 2 of the first embodiment)

[0249] Next, a variation of the above-described implementation method will be described. Figure 18B It means Figure 13 The circuit diagram of Modified Example 2 of the electrical system shown is a diagram illustrating two control switches W1a and W2a, two level shifting circuits LS1a and LS2a, a charge pump CP1, etc. The electronic device 100 is configured similarly to the embodiment described above, except for the structure described in Modified Example 2.

[0250] like Figure 18B As shown, the multiple switches SW1, SW2, SW3, and SW4 of the charge pump CP1 can all be formed by N-channel TFTs. In this example, the output signals Sig1 and Sig2 from the level shift circuit LS1a and LS2a are inverted. Furthermore, either the level shift circuit LS1a or LS2a can be connected to the charge pump CP1 via inverter IV as needed.

[0251] In variation 2 of the above structure, the same effect as the above embodiment can also be obtained.

[0252] (Modification 3 of the first embodiment)

[0253] Next, a variation of the above-described implementation method, Example 3, will be described. Figure 18C It means Figure 13The circuit diagram of Modified Example 3 of the electrical system shown is a diagram illustrating two control switches W1a and W2a, two level shifting circuits LS1a and LS2a, a charge pump CP1, etc. The electronic device 100 is configured similarly to the embodiment described above, except for the structure described in Modified Example 3.

[0254] like Figure 18C As shown, charge pump CP1 replaces capacitor Cn and includes a power input terminal Tc2. Power input terminal Tc1 is electrically connected to switch SW1 of a plurality of switches SW1, SW2, SW3, and SW4. Power input terminal Tc2 is electrically connected to switch SW3 of a plurality of switches SW1, SW2, SW3, and SW4. A first output voltage gvdd is provided to power input terminal Tc2 from the charge pump CP of another electrical system.

[0255] Therefore, the charge pump CP1 does not generate a first output voltage gvdd that is twice the first power supply voltage vdd, but is instead able to generate a first output voltage gvdd1 that is three times the first power supply voltage vdd and +15V.

[0256] In variation 3 of the above structure, the same effect as the above embodiment can also be obtained.

[0257] use Figure 18C The techniques described can also be applied to Figure 16 The circuit diagram (the electrical system used to generate the second output voltage). For example, it can be found in... Figure 16 The capacitor Cn is replaced by a power input terminal Tc2, through which a second output voltage gvss is supplied from the charge pump CP of another electrical system.

[0258] (Second Implementation)

[0259] Next, the second embodiment will be described. Figure 19 This is a circuit diagram showing a portion of the electronic device 100 according to the second embodiment. It is a diagram showing the electrical system used to generate the first output voltage gvdd, and includes a control switch W1a, multiple inverters IV, a logic AND circuit AN, a logic NOR circuit NR, a level shifter SIa, a charge pump CP1, etc. The electronic device 100 is configured similarly to the embodiment described above, except for the structure described in this embodiment.

[0260] like Figure 19 As shown, the control switch group Wa includes control switch W1a but excludes control switch W2a. Multiple inverters IV, an AND circuit AN, and a NOR circuit NR are electrically connected between control switch W1a and level shifter SIa. The AND circuit AN is an AND circuit, and the NOR circuit NR is a NOR circuit.

[0261] The logic circuit AN has a first input terminal IN1 electrically connected to the power supply voltage output terminal POUT of the control switch W1a via two inverters IV, a second input terminal IN2 electrically connected to the power supply voltage output terminal POUT via four inverters IV, and a first output terminal OUT1 electrically connected to the level shifting circuit LS1a. The number of inverters IV connected to the second input terminal IN2 is two more than the number of inverters IV connected to the first input terminal IN1. Therefore, compared to the first input terminal IN1, the second input terminal IN2 can be said to be connected to the power supply voltage output terminal POUT via a delay circuit.

[0262] The logic NOR circuit NR has a third input terminal IN3 electrically connected to the power supply voltage output terminal POUT via two inverters IV, a fourth input terminal IN4 electrically connected to the power supply voltage output terminal POUT via four inverters IV, and a second output terminal OUT2 electrically connected to the level shifting circuit LS2a. Compared to the third input terminal IN3, the fourth input terminal IN4 can be said to be connected to the power supply voltage output terminal POUT via a delay circuit.

[0263] The output signal Sig1a is input to the first input terminal IN1 of the AND circuit AN and the third input terminal IN3 of the NOR circuit NR. The output signal Sig1b is input to the second input terminal IN2 of the AND circuit AN and the fourth input terminal IN4 of the NOR circuit NR.

[0264] Additionally, the output signal Sig3 is input from the AND logic circuit AN to the level shift circuit LS1a. The output signal Sig4 is input from the NOR logic circuit NR to the level shift circuit LS2a.

[0265] Multiple inverters IV, AND circuit AN, and OR circuit NR constitute a two-phase circuit. In each of the multiple inverters IV, AND circuit AN, and OR circuit NR, a first output voltage gvdd is provided from charge pump CP1 to the first power supply terminal, and a second output voltage gvss is provided from charge pump CP2 to the second power supply terminal T2.

[0266] Figure 20 It means Figure 19 The timing diagrams for the multiple output signals Sig1a, Sig1b, Sig3, and Sig4 are shown.

[0267] like Figure 19 and Figure 20 As shown, firstly, when the voltage level of the output signal Sig1a becomes the first output voltage gvdd, the voltage levels of the output signals Sig3 and Sig4 become the second output voltage gvss.

[0268] Next, slightly delayed from the output signal Sig1a, when the voltage level of the output signal Sig1b switches to the first output voltage gvdd, the voltage level of the output signal Sig3 also switches to the first output voltage gvdd. Therefore, the level shifting circuit LS1a outputs the first output voltage gvdd to the charge pump CP1. Consequently, the charge pump capacitor Ccg of the charge pump CP1 is charged.

[0269] Subsequently, when the voltage level of the output signal Sig1a switches to the second output voltage gvss, the voltage levels of the output signals Sig3 and Sig4 become the second output voltage gvss. Therefore, the charge pump capacitor Ccg remains in a charged state.

[0270] Next, slightly delayed from the output signal Sig1a, when the voltage level of the output signal Sig1b switches to the second output voltage gvss, the voltage level of the output signal Sig4 switches to the first output voltage gvdd. Therefore, the level shifting circuit LS2a outputs the first output voltage gvdd to the charge pump CP1. As a result, the charge pump capacitor Ccg is further charged.

[0271] Subsequently, when the voltage level of output signal Sig1a switches back to the first output voltage gvdd, the voltage levels of output signals Sig3 and Sig4 become the second output voltage gvss. Thus, the charge pump capacitor Ccg remains in a state of further charging. Furthermore, the first output voltage gvdd is maintained at the charge pump capacitor Ccg.

[0272] One cycle of each of the output signals Sig3 and Sig4 corresponds to two horizontal scan periods. In other words, the cycle used to drive the charge pump CP1 is two horizontal scan periods.

[0273] In the second embodiment of the above structure, the same effects as in the first embodiment can be obtained. Compared with the first embodiment, this embodiment can improve the frequency driving of the charge pump CP1. In the charge pump CP1, the boost voltage from the first power supply voltage vdd to the first output voltage gvdd can be performed more effectively. When the above technology is applied to the charge pump CP2, the buck voltage from the second power supply voltage vss to the second output voltage gvss can be performed more effectively.

[0274] Multiple inverters IV, an AND circuit AN, and a NOR circuit NR constitute a two-phase circuit. Therefore, a control switch group Wa can be formed without the need for a control switch W2a.

[0275] (Modification 1 of the second embodiment)

[0276] Next, a variation of the second embodiment described above will be described. Figure 21 This is a circuit diagram of a modified example 1 of the electronic device 100 of the second embodiment described above, a diagram of an electrical system for generating the first output voltage gvdd, and a diagram showing a control switch W1a, multiple inverters IV, a logic XOR circuit XO, a level shifter S1a, a charge pump CP1, etc. Figure 22 It means Figure 21 The timing diagrams for the multiple output signals Sig1a, Sig1b, and Sig5 are shown.

[0277] like Figure 21 As shown, on the first substrate SUB1 (liquid crystal display panel PNL), instead of the second embodiment described above ( Figure 19 The circuit consists of two inverters IV, an AND circuit AN, and a NOR circuit NR, including an XOR circuit XO. The XOR circuit XO includes a first input terminal IN5, a second input terminal IN6, and an output terminal OUT3. The first input terminal IN5 and the second input terminal IN6 are electrically connected to the power supply voltage output terminal POUT of the control switch W1a.

[0278] In detail, the first input terminal IN5 is electrically connected to the output terminal of the second inverter IV counting from the control switch W1a side. The second input terminal IN6 is electrically connected to the power supply voltage output terminal POUT via four inverters IV. Therefore, the two inverters IV on the side of the second input terminal IN6 can be referred to as a delay circuit. The second input terminal IN6 is electrically connected to the power supply voltage output terminal POUT via the delay circuit.

[0279] The output signal Sig1a is input to the first input terminal IN5 of the logic XOR circuit XO via two inverters IV. The output signal Sig1b is input to the second input terminal IN6 of the logic XOR circuit XO via four inverters IV. The output signal Sig5 from the logic XOR circuit XO is input to the level shifter SIa.

[0280] like Figure 21 and Figure 22 As shown, the period of the output signal Sig1b is the same as the period of the output signal Sig1a. The output signal Sig1b is delayed by one-quarter of the period of the output signal Sig1a. In this variation 1, the output signal Sig1b is delayed by one horizontal scan period (1H) relative to the output signal Sig1a.

[0281] One cycle of the output signal Sig5 corresponds to two horizontal scan periods. In other words, the cycle used to drive the charge pump CP1 is two horizontal scan periods.

[0282] In the modified example 1 of the above structure, the same effect as the second embodiment described above can also be obtained.

[0283] (Modification 2 of the second embodiment)

[0284] Next, a variation of the second embodiment described above will be described. Figure 23 This is a circuit diagram of a modified example 2 of the electronic device 100 of the second embodiment described above, a diagram of an electrical system for generating the first output voltage gvdd, and a diagram showing a control switch W1a, multiple inverters IV, an RC circuit RCC, a logic XOR circuit XO, a level shifter SIa, a charge pump CP1, etc.

[0285] like Figure 23 As shown, on the first substrate SUB1 (liquid crystal display panel PNL), instead of the above-described modified example 1 ( Figure 21 The two inverters IV of the circuit are connected in series with an RC circuit RCC to form a delay circuit. The second input terminal IN6 of the logic XO circuit is electrically connected to the power supply voltage output terminal POUT of the control switch W1a via the RC circuit RCC.

[0286] The RC circuit RCC includes a resistor RT and a capacitor C3. Resistor RT is electrically connected between the output terminal of the inverter IV (the last stage) and the second input terminal IN6, as viewed from the control switch W1a side. In capacitor C3, one electrode is electrically connected to the node between resistor RT and the second input terminal IN6, and the other electrode is electrically connected to ground (gnd).

[0287] The waveforms of the multiple output signals Sig1a, Sig1b, and Sig5 are similar to those in the above-mentioned variant 1 ( Figure 22 )same.

[0288] In the modified example 2 of the above structure, the same effect as the second embodiment described above can also be obtained.

[0289] (Third Implementation)

[0290] Next, the third embodiment will be described. Figure 24This is a circuit diagram showing a portion of the electronic device 100 according to the third embodiment. It illustrates a control switch group Wa, a level shifter SIa, a charge pump CP1, a first control electrode structure RE1 (first control electrode RL1), a third control electrode structure RE3 (third control electrode RL3), a fifth control electrode structure RE5 (fifth control electrode RL5), and multiple switches SSW1a, SSW1b, SSW1c, SSW3a, SSW3b, SSW3c, etc. The electronic device 100 is configured similarly to the first embodiment, except for the structure described in this embodiment.

[0291] like Figure 24 As shown, the third control electrode structure RE3 and the fifth control electrode structure RE5 are load portions other than the first control electrode structure RE1 and the pixel electrode PE. The first substrate SUB1 (liquid crystal display panel PNL) also includes multiple switches SSW1a, SSW1b, SSW1c, SSW3a, SSW3b, and SSW3c.

[0292] Switch SSW1a is electrically connected between charge pump CP1 and the first control electrode RL1, and is used to switch whether to output the first output voltage gvdd to the first control electrode RL1. Switch SSW1b is electrically connected between charge pump CP1 and the fifth control electrode RL5, and is used to switch whether to output the first output voltage gvdd to the fifth control electrode RL5. Switch SSW1c is electrically connected between charge pump CP1 and the third control electrode RL3, and is used to switch whether to output the first output voltage gvdd to the third control electrode RL3.

[0293] Multiple load units can be selectively driven using a single electrical system that generates the first output voltage gvdd.

[0294] The first control electrode RL1 is electrically connected to ground (gnd) via switch SSW3a. The fifth control electrode RL5 is electrically connected to ground (gnd) via switch SSW3b. The third control electrode RL3 is electrically connected to ground (gnd) via switch SSW3c.

[0295] Therefore, the potentials of the first control electrode RL1, the fifth control electrode RL5, and the third control electrode RL3 can be selectively initialized.

[0296] In the third embodiment of the above structure, the same effect as in the first embodiment can also be obtained.

[0297] Several embodiments and modifications of the present invention have been described above, but these embodiments and modifications are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the inventive spirit. These embodiments and modifications are included within the scope and inventive spirit of the invention, and are included within the scope of the claimed technical solutions and their equivalents.

[0298] For example, the above technology is not limited to the liquid crystal display panel PNL described above, but can be applied to other liquid crystal display panels, as well as various display panels with control switches.

[0299] Furthermore, the above-mentioned technology is not limited to the electronic device 100 described above, but can be applied to various electronic devices.

Claims

1. A display panel, characterized in that, include: Multiple scan lines; Multiple signal lines; Pixel switching element; Pixel electrode; A first control switch having multiple first control switching elements; First level shifting circuit; and First charge pump, The pixel switching element is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and the drain electrode electrically connected to the pixel electrode, Each of the first control switch elements is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and drain electrode, The plurality of scan lines electrically connected to the plurality of gate electrodes of the plurality of first control switching elements are different from each other. The multiple drain electrodes of the plurality of first control switch elements are electrically grounded into one and connected to the power supply voltage output terminal of the first control switch. The power supply voltage output terminal is electrically connected to the first level shifting circuit. The first level shifting circuit is electrically connected to the first charge pump. The first charge pump is electrically connected to a first load portion that is different from the pixel electrode.

2. The display panel as described in claim 1, characterized in that, The plurality of scan lines extend in the first direction. The plurality of signal lines extend in a second direction that intersects the first direction. The plurality of scan lines to which the gate electrodes of the plurality of first control switching elements are electrically connected are arranged continuously in the second direction.

3. The display panel as described in claim 1, characterized in that, The multiple source electrodes of the plurality of first control switching elements are electrically connected to the same signal line.

4. The display panel as described in claim 1, characterized in that: The first control switch outputs the first power supply voltage input from the signal line to the power supply voltage output terminal. The first level shifting circuit outputs the first power supply voltage to the first charge pump. The first charge pump generates a first output voltage and outputs the first output voltage to the first load section. The absolute value of the first output voltage is greater than the absolute value of the first power supply voltage.

5. The display panel as described in claim 4, characterized in that, Also includes: A second control switch having multiple second control switching elements; and Second level shifting circuit Each of the second control switching elements is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and drain electrode, The plurality of scan lines electrically connected to the plurality of gate electrodes of the plurality of second control switching elements are different from each other. The multiple drain electrodes of the plurality of second control switching elements are electrically grounded into one and connected to the power supply voltage output terminal of the second control switch. The first charge pump has a charge pump capacitor. The charge pump capacitor is charged by inputting the first power supply voltage from the first level shift circuit, and then further charged by inputting the first power supply voltage from the second level shift circuit, while maintaining the first output voltage.

6. The display panel as described in claim 4, characterized in that, Also includes: A second level shifting circuit that outputs the first power supply voltage to the first charge pump; Delay circuit; A logic circuit having a first input terminal electrically connected to the power supply voltage output terminal, a second input terminal electrically connected to the power supply voltage output terminal via the delay circuit, and a first output terminal electrically connected to the first level shifting circuit; and A logic NOR circuit having a third input terminal electrically connected to the power supply voltage output terminal, a fourth input terminal electrically connected to the power supply voltage output terminal via the delay circuit, and a second output terminal electrically connected to the second level shift circuit.

7. The display panel as described in claim 4, characterized in that, Also includes: Delay circuit; and A logic XOR circuit having a first input terminal electrically connected to the power supply voltage output terminal, a second input terminal electrically connected to the power supply voltage output terminal via the delay circuit, and a first output terminal electrically connected to the first level shifting circuit.

8. The display panel as described in claim 4, characterized in that, Also includes: Series-type RC circuit; and A logic XOR circuit having a first input terminal electrically connected to the power supply voltage output terminal, a second input terminal electrically connected to the power supply voltage output terminal via the RC circuit, and a first output terminal electrically connected to the first level shifting circuit.

9. The display panel as described in claim 4, characterized in that, Also includes: Display area; and The incident light control region has an incident light adjustment region and a light-blocking region that can adjust the amount of light transmitted. The pixel switching element and the pixel electrode are located in the display area. The first load portion is a control electrode located in the incident light adjustment region.

10. The display panel as claimed in claim 9, characterized in that, The first control switch, the first level shifting circuit, and the first charge pump are respectively located in the light-shielding area.

11. The display panel as claimed in claim 4, characterized in that, Also includes: A second control switch having multiple second control switching elements; Second level shifting circuit; and Second charge pump, Each of the second control switching elements is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and drain electrode, The plurality of scan lines electrically connected to the plurality of gate electrodes of the plurality of second control switching elements are different from each other. The multiple drain electrodes of the plurality of second control switching elements are electrically grounded into one and connected to the power supply voltage output terminal of the second control switch. The second control switch outputs the first power supply voltage input from the signal line to its own power supply voltage output terminal. The second level shift circuit outputs the first power supply voltage to the second charge pump. The second charge pump generates a second output voltage and outputs the second output voltage to the first load section.

12. The display panel as claimed in claim 4, characterized in that, Also includes: A second load portion other than the pixel electrode and the first load portion; A first drive switch is connected between the first charge pump and the first load section to switch whether to output the first output voltage to the first load section; and A second drive switch is connected between the first charge pump and the second load section to switch whether the first output voltage is output to the second load section.

13. The display panel as claimed in claim 4, characterized in that, It also includes a second control switch having multiple second control switching elements. Each of the second control switching elements is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and drain electrode, The plurality of scan lines electrically connected to the plurality of gate electrodes of the plurality of second control switching elements are different from each other. The multiple drain electrodes of the plurality of second control switching elements are electrically grounded into one and connected to the power supply voltage output terminal of the second control switch. The first charge pump has a power input terminal that is electrically connected to the power supply voltage output terminal of the second control switch; and charge pump capacitors, For the charge pump capacitor, the voltage input from the power supply voltage output terminal of the second control switch is applied by inputting the first power supply voltage from the first level shift circuit, and then the voltage input from the power supply voltage output terminal of the second control switch is applied to the charge pump capacitor to generate a first output voltage that depends on the voltage input from the power supply voltage output terminal of the second control switch, and the first output voltage is maintained.

14. An electronic device, characterized in that, include: The display panel has multiple scan lines, multiple signal lines, pixel switching elements, pixel electrodes, an incident light control area, a first control switch having multiple first control switching elements, a control electrode located in the incident light control area, a first level shifting circuit, and a first charge pump. and A camera device acquires information about the light after it has passed through the incident light control area of ​​the display panel. The pixel switching element is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and the drain electrode electrically connected to the pixel electrode, Each of the first control switch elements is formed of a transistor and has a gate electrode electrically connected to a corresponding scan line among the plurality of scan lines; The source electrode is electrically connected to one of the corresponding signal lines among the plurality of signal lines; and drain electrode, The plurality of scan lines electrically connected to the plurality of gate electrodes of the plurality of first control switching elements are different from each other. The multiple drain electrodes of the plurality of first control switch elements are electrically grounded into one and connected to the power supply voltage output terminal of the first control switch. The first control switch outputs the first power supply voltage input from the signal line to the power supply voltage output terminal. The first level shifting circuit outputs the first power supply voltage to the first charge pump. The first charge pump generates a first output voltage and outputs the first output voltage to the control electrode. The absolute value of the first output voltage is greater than the absolute value of the first power supply voltage.

15. The electronic device as claimed in claim 14, characterized in that, The plurality of scan lines extend in the first direction. The plurality of signal lines extend in a second direction that intersects the first direction. The plurality of scan lines to which the gate electrodes of the plurality of first control switching elements are electrically connected are arranged continuously in the second direction.

16. The electronic device as claimed in claim 14, characterized in that, The multiple source electrodes of the plurality of first control switching elements are electrically connected to the same signal line.

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