Adaptive word line underdrive control for in-memory compute operations
By employing adaptive power supply and bias voltage regulation technology, the data flipping problem caused by parallel access during memory computation operations is solved, improving computational accuracy and stability, and adapting to process and temperature variations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STMICROELECTRONICS INT NV
- Filing Date
- 2022-07-08
- Publication Date
- 2026-07-24
Smart Images
Figure CN115602227B_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to U.S. Patent Application No. 63 / 220,152, filed July 9, 2021, the disclosure of which is incorporated herein by reference. Technical Field
[0003] The embodiments relate to in-memory computing circuitry utilizing an array of static random access memory (SRAM), and more specifically, to performing adaptive word line underdrive control during simultaneous access of multiple rows of the SRAM array for in-memory computing operations. Background Technology
[0004] right Figure 1 For reference, a schematic diagram of in-memory computation circuitry 10 is shown. Circuitry 10 utilizes a static random access memory (SRAM) array 12 formed by standard 6T SRAM memory cells 14 arranged in a matrix format with N rows and M columns. Alternatively, standard 8T memory cells or SRAM with similar functionality and topology can be used instead. Each memory cell 14 is programmed to store bits of computational weights for in-memory computational operations. In this context, in-memory computational operations are understood as high-dimensional matrix-vector multiplication (MVM) supporting multi-bit weights stored in multiple bit cells of memory. (In the case of multi-bit weights) groups of bit cells can be considered as virtual synaptic elements. Each bit of the computational weight has a logic "1" or logic "0" value.
[0005] Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. An 8T-type SRAM cell will additionally include a read word line RWL and a read bit line RBT. Cells 14 in a common row of the matrix are connected to each other via a common word line WL (and via a common read word line RWL in the 8T-type implementation). Cells 14 in a common column of the matrix are connected to each other via a pair of common complementary bit lines BLT and BLC (and via a common read bit line RBL in the 8T-type implementation). Each word line WL, RWL is driven by a word line driver circuit 16, which can be implemented as a CMOS driver circuit (e.g., a series-connected pair of p-channel MOSFET transistors and n-channel MOSFET transistors forming a logic inverter circuit). The word line signals applied to the word lines and driven by the word line driver circuit 16 are generated from feature data input to the in-memory computing circuit 10 and controlled by the row controller circuit 18. Column processing circuit 20 senses analog signal voltages on complementary bit line pairs BLT and BLC (and / or read bit line RBL) of M columns and generates decision outputs for in-memory computation operations based on those analog signal voltages. Column processing circuit 20 can be implemented to support processing that first processes the voltages on the columns individually and then combines multiple column outputs.
[0006] Despite Figure 1 Although not explicitly shown, it should be understood that circuit 10 also includes conventional row decoding, column decoding, and read / write circuitry known to those skilled in the art, which are used to write the bits of the calculated weights into the SRAM cells 14 of the memory array 12 and to read the bits of the calculated weights from the SRAM cells 14 of the memory array 12.
[0007] Now for reference Figure 2Each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series-connected pair of p-channel MOSFET transistors and n-channel MOSFET transistors. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit with a real data storage node QT and a complementary data storage node QC, which stores the complementary logic states of the stored data bits. Cell 14 also includes two transmit (transmission gate) transistors 26 and 28, whose gate terminals are driven by word line WL. The source-drain path of transistor 26 is connected between the real data storage node QT and the node associated with the real bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., Vdd) at the high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at the low supply node. Although Figure 2 Specific to the use of 6T-type cells, but those skilled in the art will recognize that 8T-type cells are similarly configured and will also include a signal path coupled to one of the memory nodes, and include a transmit (transmission gate) transistor coupled to the read word line RWL and gate-driven by signals on the read word line RWL. The word line driver circuit 16 is also typically coupled to receive a high supply voltage (Vdd) at the high supply node and reference a low supply voltage (Gnd) at the low supply node.
[0008] The line controller circuit 18 selects the word line WL during in-memory computation operations. <0> To WL <n-1>The function determines which word lines will be accessed (or actuated) simultaneously and in parallel, and further performs the function of controlling the application of pulse signals to word lines based on characteristic data used for computational operations within the memory. Figure 1 The simultaneous actuation of all N word lines with pulse word line signals is illustrated by way of example only. It should be understood that in-memory computation operations can be performed using simultaneous actuation of fewer than all rows of the SRAM array. The analog signal voltage generated on a given pair of complementary bit lines BLT and BLC (or on the read bit line RBL in the 8T-type embodiment) depends on the logic state of the bits of the computation weights stored in the memory cells 14 of the corresponding columns and the width of one or more pulse word line signals used to apply the characteristic data to those memory cells 14.
[0009] Figure 1 The embodiment illustrated in the figure shows an example of applied word line signals for in-memory computation operations in the form of pulse width modulation (PWM). Using PWM or periodic pulse modulation (PTM) for applied word line signals is a common technique used for in-memory computation operations based on vector linearity of multiply-accumulate (MAC) operations. The pulse word line signal format can further evolve into coded pulse sequences to manage the block sparsity of characteristic data for in-memory computation operations. It should be recognized accordingly that when multiple word lines are driven simultaneously, any set of encoding schemes can be used for the applied word line signals. Furthermore, in a simpler implementation, it should be understood that all applied word line signals in a simultaneously actuated state can alternatively have the same pulse width.
[0010] Figure 3 This is a timing diagram illustrating the simultaneous application of example pulse-width modulated word line signals for feature data to multiple rows of memory cells 14 in SRAM array 12 for a given in-memory computation operation. Analog signal voltages Va,T and Va,C are generated over time on corresponding pairs of complementary bit lines BLT and BLC, respectively, in response to the pulse width(s) of those word line signals and the logic state of the bits of the computation weights stored in the memory cells 14. The representation of the analog voltage Va level shown is merely an example. After the computation cycle of the in-memory computation operation is completed, the analog voltage Va level returns to the bit line precharge Vdd level. It should be noted that there is a risk that the analog voltage on at least one of the bit lines BLT and BLC may drop from the Vdd voltage to a level that causes an undesirable data flip relative to the data bit value stored in one of the column memory cells 14. For example, a logic "1" state stored in the column cell 14 may be flipped to a logic "0" state. Such a data flip introduces data errors into the computation weights stored in the memory cells, thereby jeopardizing the accuracy of subsequent in-memory computation operations.
[0011] Undesirable data flips caused by excessively low bit line voltages are primarily due to the simultaneous parallel access of word lines in matrix-vector multiplication mode during in-memory computation operations. This problem differs from normal data flips in SRAM bit cells, which are caused by static noise margin (SNM) issues during serial bit cell accesses when the bit lines are close to the supply voltage Vdd. Normal data flips during serial access are caused by ground bounces at the data storage node QT or QC.
[0012] A known solution to this Serial Bit Cell Access (SNM) fault is to slightly reduce the word line voltage, which is typically achieved by using short-circuiting and bleed paths in the word line driver. However, parallel access to multiple word lines during in-memory computation operations requires Radical-WL downsampling / modulation (RWLM) techniques. Furthermore, a known solution to the aforementioned problem is to apply a fixed word line voltage reduction at all integrated circuit process corners (e.g., applying a voltage equal to Vdd / 2). WLUD This is done to ensure the worst-case integrated circuit process corner. However, this word line underdrive (WLUD) solution has a known drawback: a corresponding reduction in read current on the bit lines, which negatively impacts computational performance. Furthermore, using a fixed word line underdrive voltage increases the variability of read current across the array, leading to reduced accuracy of in-memory computational operations.
[0013] Another solution is to utilize a dedicated bit cell circuit design for each memory cell 14, which is less likely to suffer unwanted data flips during simultaneous (parallel) accesses of multiple rows in in-memory computation operations. One problem with this solution is the increased circuit area occupied by such bit cell circuitry. For some in-memory computation applications, it is preferable to retain the use of topologically similar bit cells or standard 6T SRAM cells in array 12. Figure 2 The advantages offered by 8T SRAM cells or 8T SRAM cells.
[0014] Therefore, there is a need in this field for in-memory computing circuitry that supports standard 6T (or 8T) SRAM cells while ensuring that no unwanted data flips occur during simultaneous row access. Summary of the Invention
[0015] In one embodiment, the in-memory computing circuitry includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells of that row, and each column including a pair of bit lines connected to the SRAM cells of that column; word line driving circuitry for each row having outputs connected to drive the word lines of that row, wherein the word line driving circuitry is powered by an adaptive supply voltage; row controller circuitry configured to simultaneously actuate a plurality of word lines by applying pulses to the word lines via the word line driver circuitry for in-memory computing operations; column processing circuitry connected to the bit line pairs of each column and configured to process analog voltages generated on the bit line pairs in response to the simultaneous actuation of the plurality of word lines to generate decision outputs for in-memory computing operations; and voltage generator circuitry configured to generate an adaptive supply voltage for powering the word line driving circuitry during the simultaneous actuation of the plurality of word lines for in-memory computing operations, the adaptive supply voltage having a level dependent on integrated circuit process and / or temperature conditions.
[0016] In one embodiment, the in-memory computing circuitry includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells of that row, and each column including a pair of bit lines connected to the SRAM cells of that column; word line driving circuitry for each row having outputs connected to drive the word lines of that row; row controller circuitry configured to simultaneously actuate multiple word lines by applying pulses to the word lines via the word line driver circuitry for in-memory computing operations; and column processing circuitry connected to each... Each column of bit line pairs is configured to process analog voltages generated on the bit line pairs in response to simultaneous actuation of multiple word lines to generate decision outputs for in-memory computation operations; a bleed transistor for each word line, wherein each bleed transistor has a source-drain path coupled between the word line and a reference voltage node and a gate configured to receive an adaptive bias voltage; and a voltage generator circuit configured to generate an adaptive bias voltage during simultaneous actuation of multiple word lines for in-memory computation operations, the adaptive bias voltage having a level dependent on integrated circuit process and / or temperature conditions.
[0017] In one embodiment, the in-memory computing circuitry includes: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including word lines connected to the SRAM cells in that row, and each column including a pair of bit lines connected to the SRAM cells in that column; word line driving circuitry for each row having outputs connected to drive the word lines of that row, wherein the word line driving circuitry is powered by an adaptive supply voltage; row controller circuitry configured to simultaneously actuate multiple word lines by applying pulses to the word lines via the word line driver circuitry for in-memory computing operations; and column processing circuitry. The circuit includes: a bit line pair connected to each column and configured to process analog voltages generated on the bit line pairs in response to simultaneous actuation of multiple word lines to generate decision outputs for in-memory computation operations; a replica circuit that replicates the transmission gate transistors and pull-down transistors of the SRAM cells; a current generator configured to apply a forced current to the replica circuit to generate a bias voltage; and a voltage circuit configured to use the bias voltage to generate an adaptive power supply voltage for powering the word line drive circuitry during simultaneous actuation of multiple word lines for in-memory computation operations, the adaptive power supply voltage having a level that depends on the integrated circuit process and / or temperature conditions. Attached Figure Description
[0018] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:
[0019] Figure 1 This is a schematic diagram of the computing circuitry within the memory;
[0020] Figure 2 yes Figure 1 The circuit diagram shown is of a standard 6T static random access memory (SRAM) cell used in the memory array of the in-memory computing circuitry.
[0021] Figure 3 It is a timing diagram illustrating computational operations within memory;
[0022] Figure 4 This is a schematic diagram of an in-memory computing circuit that uses adaptive power supply voltage for word line driving;
[0023] Figure 5 It's a flowchart;
[0024] Figure 6 This is a schematic diagram of an in-memory computing circuit that uses adaptive power supply voltage for word line driving;
[0025] Figure 7 This is a schematic diagram of an in-memory computing circuit that utilizes adaptive power supply voltage for word line driving; and
[0026] Figure 8 This is a schematic diagram of an in-memory computing circuit that utilizes adaptive word line underdrive bias voltage. Detailed Implementation
[0027] Now to Figure 4 For reference, a schematic diagram of an in-memory computing circuit 110 that uses an adaptive power supply voltage Vbias for word line driving is shown. Figure 1 and Figure 4 The same reference numerals in the figures refer to the same or similar components, and their description will not be repeated (see the description above). Circuit 110 differs from circuit 10 in that the power supply voltage for the word line drive circuit 16 is not fixed to Vdd (i.e., it is different from the array power supply voltage) nor is it set to a fixed word line undervoltage level (e.g., Vdd). WLUD =Vdd / 2). Conversely, the power supply voltage for the word line driver circuit 16 is an adaptive power supply voltage Vbias, which is modulated depending on the integrated circuit process and / or temperature conditions. This adaptive power supply voltage Vbias has a voltage level lower than the power supply voltage Vdd (e.g., used by memory cell 14) and is generated by the voltage generator circuit 112. In one embodiment, the voltage generator circuit 112 may include a voltage regulator, such as a low dropout (LDO) regulator, which is well known to those skilled in the art.
[0028] Voltage generator circuit 112 receives a power supply voltage Vdd and a control signal. In one embodiment, the control signal is a multi-bit digital control signal Vsel; however, it should be understood that the control signal can alternatively be implemented as an analog signal. The value of the control signal (specifically, the digital value of the bits in the control signal Vsel) selects the voltage level of the adaptive power supply voltage Vbias output by voltage generator circuit 112. The control signal Vsel is generated by control circuit 114 in response to integrated circuit process and / or temperature information, and therefore the voltage level of the adaptive power supply voltage Vbias is modulated in a manner dependent on the integrated circuit process and / or temperature information.
[0029] Integrated circuit process information is a digital code generated and stored in memory M within control circuitry 114. This digital code represents the center of the process batch and is generated by a circuit such as a ring oscillator (RO), whose output frequency varies depending on the integrated circuit process. Therefore, the output frequency of the RO circuit represents the process center and can be easily converted into a digital code (e.g., using a counter circuit). Process monitoring circuitry 116 within control circuitry 114 can generate a value for a control signal Vsel based on the stored digital code for the integrated circuit process. For example, process monitoring circuitry 116 may include a lookup table (LUT) that associates each digital code with a value for control signal Vsel to provide a specific voltage level for an adaptive supply voltage Vbias, which will generate an optimal word line underdrive level for the integrated process corner. Control circuitry 114 outputs the value of control signal Vsel associated with the stored digital code, and voltage generator circuitry 112 responds by generating a corresponding level for the adaptive supply voltage Vbias.
[0030] Temperature information is generated by temperature sensing circuit 118 and represents the current temperature of the integrated circuit. Temperature sensing circuit 118 can select, modify, or adjust the value of control signal Vsel based on the sensed temperature. For example, temperature sensing circuit 118 may include a lookup table (LUT) that specifies a (positive or negative) adjustment of the value of control signal Vsel to provide a corresponding tuning for a specific voltage level of adaptive power supply voltage Vbias, which will produce an optimal word line underdrive level given the integrated circuit process corner and current temperature conditions.
[0031] Now to Figure 5 For reference, this figure illustrates the use of Figure 4 The flowchart describes the operation of the control circuit 114 and the process monitoring circuit 116 of the circuit. In step 140, a stored digital code for the integrated circuit process is read from the memory M. In one embodiment, the digital code for the integrated circuit process is loaded into the memory M at the factory, and the digital code is based on the identified integrated circuit process characteristics (fast / slow angle, etc.) for the integrated circuit manufacturing batch (e.g., source wafer), from which the integrated circuit is obtained. Next, in step 142, it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOSFET device of the memory cell 12 is at a fast integrated circuit process angle (e.g., where NMOS is fast and PMOS is slow – the "FS" angle). If so, then in step 144, a value of the control signal Vsel is selected, which corresponds to the read digital code, and will cause the voltage generator circuit 112 to generate a higher degree of word line underdrive (i.e., the voltage level for the adaptive supply voltage Vbias will be lower than the nominal (or default) voltage level for word line underdrive). Setting the adaptive supply voltage Vbias below the nominal (or default) voltage level reduces the Multi-Row Access Write Margin (MRAWM), which is the maximum bit line voltage level required to write to a bit cell. Reducing the MRAWM results in a degradation of the bit cell's write capability and an increase in the data flip rate, which is of concern at fast NMOS corners. Those skilled in the art will understand that this is different from the nominal write margin of a bit cell. This voltage level below the nominal (or default) also provides higher headroom for bit line wobbling and therefore higher accuracy for bit line accumulation values in in-memory computation operations. If no in step 142, then in step 146 it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOSFET device of memory cell 12 is at a slow integrated circuit process corner (e.g., where NMOS is slow and PMOS is fast—the "SF" corner). If so, then in step 148, a value for the control signal Vsel is selected, corresponding to the read digital code, and this will cause the voltage generator circuit 112 to generate a lower degree of word line underdrive (i.e., the voltage level used for the adaptive supply voltage Vbias is higher than the nominal (or default) voltage level used for word line underdrive). Setting the adaptive supply voltage Vbias higher than the nominal (or default) voltage level increases the multi-row access write margin (MRAWM), resulting in increased cell current while still controlling the data toggle rate, which is less of a concern at the slow NMOS corner. This higher-than-nominal voltage level also reduces the localized effects of slow process corner variations.If no in step 146, then in step 150 a value for the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 112 to generate a voltage level for the adaptive power supply voltage Vbias, which is equal to the nominal (or default) voltage level for word line underdriving.
[0032] although Figure 5 The process envisions three levels of voltage control (above, below, and equal to nominal), but it should be understood that this is merely an example. Additional test steps can be added. Figure 5 During the process, other integrated circuit process corners or process-related conditions (e.g., fast-fast (FF) corners and / or slow-slow (SS) corners) are tested. Each test has an associated digital code and a value of the control signal Vsel to set the corresponding voltage level of the adaptive power supply voltage Vbias generated by the voltage generator circuit 112.
[0033] Now to Figure 6 For reference, a schematic diagram of an in-memory computing circuit 210 that uses an adaptive power supply voltage Vbias for word line driving is shown. Figure 1 and Figure 6 The same reference numerals in the figures refer to the same or similar components, and their description will not be repeated (see the description above). Circuit 210 differs from circuit 10 in that the power supply voltage for the word line drive circuit 16 is not fixed to Vdd (i.e., it is different from the array power supply voltage) nor is it set to a fixed word line undervoltage level (e.g., Vdd). WLUD =Vdd / 2). Conversely, the power supply voltage for word line driver circuit 16 is an adaptive power supply voltage Vbias, which is modulated depending on the integrated circuit process conditions. This adaptive power supply voltage Vbias has a voltage level lower than the power supply voltage Vdd (e.g., used by memory cell 14) and is generated by voltage generator circuit 212, its voltage level being proportional to the reference current Iref level (multiplied by a factor n). The reference current Iref has an amplitude defined by the fast NMOS process batch. As an example, the reference current Iref for a given location cell is the current when MRAWM is zero, while allowing the bit line to fully oscillate rail-to-rail at the worst process corner. The value of the scaling factor n is set by design and is based on the desired variability of the adaptive power supply voltage Vbias level (such that the number of copies n will effectively minimize Vbias variations due to localized changes).
[0034] Voltage generator circuit 212 includes current source 214, powered by supply voltage Vdd and generating output current Iout at node 216, wherein the current source is connected in series with a first n-channel MOSFET device 218 and a second n-channel MOSFET device 220. The output current Iout is applied (i.e., imposed) to a circuit having transistors 218 and 220 to generate bias voltage Vbias, wherein transistors 218 and 220 effectively replicate a transmission gate and pull-down transistor configuration that describes the read conditions of a memory cell. The first n-channel MOSFET device 218 has a drain coupled (preferably, directly connected) to node 216 and a source coupled (preferably, directly connected) to node 222. The gate of the first n-channel MOSFET device 218 is coupled (preferably, directly connected) to the drain of node 216, thereby configuring device 218 as a diode-connected transistor. The first n-channel MOSFET device 218 is a scaled copy of the n-channel transfer (transmission gate) transistors 26 and 28 within each memory cell 14, where the scaling factor is equal to n. In this context, "scaled copy" means that transistor 218 is fabricated using the same integrated circuit process materials and parameters (doping level, oxide thickness, gate material, etc.) as each of transistors 26 and 28, but is an n-fold repetition of a single transistor, thus providing a more efficient width. As an example, transistor 218 can be fabricated by connecting n identical (matching) transistors to each of transistors 26 and 28 in parallel. The second n-channel MOSFET device 220 has a drain coupled (preferably, directly connected) to node 222 and a source coupled (preferably, directly connected) to a ground power supply reference. The gate of the second n-channel MOSFET device 220 is coupled (preferably, directly connected) to receive a power supply voltage Vdd. The second n-channel MOSFET device 220 is a scaled copy of the n-channel pull-down transistors 34 and 36 within each memory cell 14, where the scaling factor is equal to n. As an example, transistor 220 can be manufactured by connecting n transistors that are the same (matching) each of transistors 34 and 36 in parallel.
[0035] The bias voltage Vbias generated at node 216 is equal to:
[0036] Vbias = n(Iref)(Rdson218+Rdson220),
[0037] Wherein: Rdson218 is the drain-to-source resistance of the diode-connected first n-channel MOSFET device 218, and Rdson220 is the drain-to-source resistance of the second n-channel MOSFET device 220 gate-biased by the power supply voltage Vdd. Under the operating condition that the transmission gate transistor and its pull-down transistor located on one side of the memory cell are both turned on during the read operation, the series-connected transistors 218 and 220 replicate the current path from the bit line (BLT or BLC) to ground in the memory cell 14 depending on the scaling factor n.
[0038] The differential amplifier circuit 224, configured as a unity-gain voltage follower, receives a Vbias voltage at its non-inverting input and generates a Vbias voltage at its output 226 with sufficient drive capability to power all word line driver circuits 16 used for simultaneous actuation of word lines during in-memory computation operations. The output of the differential amplifier circuit 224 is short-circuited to the inverting input.
[0039] Now to Figure 7 For reference, a schematic diagram of an in-memory computing circuit 310 that uses an adaptive power supply voltage Vbias for word line driving is shown. Figure 6 and Figure 7 The same reference numerals in the figures refer to the same or similar components and will not be described again (see the description above). Circuit 310 differs from circuit 210 in that it supports tuning the amplitude of the current Iout output by the current source 214 within the voltage generator circuit 212 based on a different integrated circuit process and / or temperature. In this context, the current source 214 is formed by a variable current source having a base (or nominal) current Innom amplitude equal to n(Iref), with a positive or negative adjustment amount adj from the base current amplitude level set by a control signal. In other words, the amplitude of the current output Iout of the current source 214 is equal to n(Iref) ± adj, where adj is the adjustment amount set by the control signal. In one embodiment, the control signal is a multi-bit digital control signal Vsel, but it should be understood that the control signal can alternatively be implemented as an analog signal. The value of the control signal (specifically, the digital value of the bits in the control signal Vsel) selects the degree of adjustment to the amplitude of the current output by the current source 214. The control signal Vsel is generated by the control circuit 114 in response to integrated circuit process and / or temperature information. Therefore, the level of the adaptive power supply voltage Vbias now additionally depends on this integrated circuit process and / or temperature information.
[0040] Integrated circuit process information is generated and stored in memory M within control circuitry 114 as digital codes. These digital codes represent the center of the process batch and are generated by circuitry such as a ring oscillator (RO), whose output frequency varies depending on the integrated circuit process. Therefore, the output frequency of the RO circuit represents the process center and can be easily converted into digital codes (e.g., using a counter circuit). Process monitoring circuitry 116 within control circuitry 114 can generate a value for a control signal Vsel based on the stored digital codes for the integrated circuit process. For example, process monitoring circuitry 116 may include a lookup table (LUT) that associates each digital code with the value of control signal Vsel for selecting a positive or negative adjustment amount adj of the nominal amplitude of the current generated by current source 214 to ensure that the voltage level of the adaptive power supply voltage Vbias will produce the optimal word line underdrive level for the integrated circuit process corner. Control circuitry 114 outputs the value of the control signal Vsel associated with the digital code, and voltage generator circuitry 212 responds by generating a corresponding voltage level for the adaptive power supply voltage Vbias.
[0041] Temperature information is generated by temperature sensing circuit 118 and represents the current temperature of the integrated circuit. Temperature sensing circuit 118 can modify or adjust the value of control signal Vsel based on the sensed temperature. For example, temperature sensing circuit 118 may include a lookup table (LUT) that specifies a certain adjustment to the value of control signal Vsel to provide a corresponding tuning to the amplitude of the current output by current source 214, ensuring that the level of adaptive power supply voltage Vbias produces an optimal word line underdrive level given the integrated circuit process corner and current temperature conditions.
[0042] Now to Figure 5 For reference, this figure illustrates the use of Figure 7 The flowchart illustrates the operation of the control circuit 114 and the process monitoring circuit 116 of the circuit. In step 140, the accessed digital code for the integrated circuit process is read from the memory M. In one embodiment, the digital code for the integrated circuit process is loaded into the memory M at the factory, and the digital code is based on the identified integrated circuit process characteristics (fast / slow angle, etc.) for the integrated circuit manufacturing batch (e.g., source wafer), from which the integrated circuit is obtained. Next, in step 142, it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOSFET device of the memory cell 12 is at a fast integrated circuit process angle (i.e., where NMOS is fast and PMOS is slow – the "FS" angle). If so, then in step 144, a value for the control signal Vsel is selected, corresponding to the read digital code, and this will cause a negative adjustment amount adj in the amplitude of the current output by current source 214, so that the voltage regulator circuit will produce a higher degree of word line underdrive (i.e., the level used for the adaptive power supply voltage Vbias will be lower than the nominal (or default) level of word line underdrive set by the nominal current amplitude n(Iref)). Setting the adaptive power supply voltage Vbias below the nominal (or default) voltage level has the effect of reducing the multi-row access write margin (MRAWM), which is the maximum bit line voltage level required to write to a bit cell. Reducing the MRAWM results in a degradation of the bit cell's write capability and an increase in the data flip rate, which is of concern at fast NMOS corners. This voltage level below the nominal (or default) also provides higher headroom for bit line wobbling and therefore higher accuracy for bit line accumulated values in in-memory computation operations. If no in step 142, then in step 146 it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOSFET device of memory cell 12 is at a slow integrated circuit process corner (i.e., where NMOS is slow and PMOS is fast – the "SF" corner). If yes, then in step 148 a value of the control signal Vsel is selected, which corresponds to the read digital code and will cause a positive adjustment amount adj in the amplitude of the current output by current source 214, so that the voltage regulator circuit will produce a lower degree of word line underdrive (i.e., the level of the adaptive supply voltage Vbias is higher than the nominal (or default) level of word line underdrive set by the nominal current amplitude n(Iref)). Setting the adaptive supply voltage Vbias higher than the nominal (or default) voltage level increases the multi-row access write margin (MRAWM), resulting in increased cell current while still controlling the data toggle rate, which is less of a concern at the slow NMOS corner. This higher-than-nominal voltage level also reduces the local variation effect of the slow process corner.If no in step 146, then in step 150 select the value of the control signal Vsel, which corresponds to the read digital code and will cause no adjustment to the amplitude n(Iref) in the current output by current source 214 (i.e., adj = 0), so that the voltage regulator circuit will generate the level of the adaptive supply voltage Vbias, which is equal to the nominal (or default) level of word line underdrive set by the nominal current Inom.
[0043] although Figure 5 The process envisions three levels of voltage control (above, below, and equal to nominal), but it should be understood that this is merely an example. Additional test steps can be added. Figure 5 During the process, other integrated circuit process corners or process-related conditions (e.g., fast-fast (FF) corners and / or slow-slow (SS) corners) are tested. Each test has an associated digital code and a value of the control signal Vsel to set the corresponding level of the current adjustment output by the current source 214 of the voltage generator circuit 212.
[0044] Now to Figure 8 For reference, a schematic diagram of an in-memory computing circuit 410 utilizing integrated circuit technology and / or temperature-dependent word line underdriving is shown. Figure 1 and Figure 8 The same reference numerals in the figures refer to the same or similar components and will not be described again (see the description above). Circuit 410 differs from circuit 10 in that, for each word line, it includes a bleeder (n-channel pull-down) MOSFET device 412 having a source-drain path coupled between the word line and a ground reference, and a gate coupled to receive an adaptive gate bias voltage Vgbias modulated depending on the integrated circuit process and / or temperature conditions to control the applied word line underdrive level. The adaptive gate bias voltage Vgbias is generated by a voltage generator circuit 112. In one embodiment, the voltage generator circuit 112 may include a voltage regulator, such as a low-dropout (LDO) voltage regulator, which is well known to those skilled in the art.
[0045] Voltage generator circuit 112 receives a power supply voltage Vdd and a control signal. In one embodiment, the control signal is a multi-bit digital control signal Vsel; however, it should be understood that the control signal may alternatively be implemented as an analog signal. The value of the control signal (specifically, the digital value of the bits of the control signal Vsel) selects the level of the adaptive gate bias voltage Vgbias output by voltage generator circuit 112. The control signal Vsel is generated by control circuit 114 in response to integrated circuit process and / or temperature information. The level of the adaptive gate bias voltage Vgbias controls the conductivity of bleed transistor 412, and therefore the applied word line underdrive level depends on the integrated circuit process and / or temperature information.
[0046] Integrated circuit process information is a digital code generated and stored in memory M within control circuitry 114. This digital code indicates the center of the process batch and is generated by circuitry such as a ring oscillator (RO), whose output frequency varies depending on the integrated circuit process. Therefore, the output frequency of the RO circuit indicates the process center and can be easily converted into a digital code (e.g., using a counter circuit). Process monitoring circuitry 116 within control circuitry 114 can generate a value for a control signal Vsel based on the stored digital code for the integrated circuit process. For example, process monitoring circuitry 116 may include a lookup table (LUT) that associates each digital code with a value for control signal Vsel to provide a specific voltage level for an adaptive gate bias voltage Vbias, which will generate an optimal word line underdrive level for the integrated circuit process corner. Control circuitry 114 outputs the value of the control signal Vsel associated with the digital code, and voltage generator circuitry 112 responds by generating a corresponding voltage level for the adaptive gate bias voltage Vgbias.
[0047] Temperature information is generated by temperature sensing circuit 118 and represents the current temperature of the integrated circuit. Temperature sensing circuit 118 can modify or adjust the value of control signal Vsel based on the sensed temperature. For example, temperature sensing circuit 118 may include a lookup table (LUT) that specifies an adjustment to the value of control signal Vsel to provide a corresponding tuning for a specific voltage level of adaptive gate bias voltage Vgbias, which will produce an optimal word line underdrive level given the integrated circuit process corner and current temperature conditions.
[0048] Now to Figure 5 For reference, this figure illustrates the use of Figure 8 The flowchart describes the operation of the control circuit 114 and the process monitoring circuit 116 of the circuit. In step 140, a stored digital code for the integrated circuit process is read from the memory M. In one embodiment, the digital code for the integrated circuit process is loaded into the memory M at the factory, and the digital code is based on the identified integrated circuit process characteristics (fast / slow angle, etc.) for the integrated circuit manufacturing batch (e.g., source wafer), from which the integrated circuit is obtained. Next, in step 142, it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOSFET device of the memory cell 12 is at a fast integrated circuit process angle (i.e., where NMOS is fast and PMOS is slow – the "FS" angle). If so, then in step 144, a value of the control signal Vsel is selected, which corresponds to the read digital code, and will cause the voltage generator circuit 112 to generate a higher degree of word line underdrive (i.e., the level for the adaptive gate bias voltage Vgbias will be higher than the nominal (or default) level for word line underdrive). If no in step 142, then in step 146 it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOSFET device of memory cell 12 is at a slow integrated circuit process corner (i.e., where NMOS is slow and PMOS is fast – the "SF" corner). If yes, then in step 148 a value of the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 112 to generate a lower degree of word line underdrive (i.e., the level for the adaptive gate bias voltage Vgbias is lower than the nominal (or default) level for word line underdrive). If no in step 146, then in step 150 a value of the control signal Vsel is selected, which corresponds to the read digital code and will cause the voltage generator circuit 112 to generate a level for the adaptive supply voltage Vgbias, which is equal to the nominal (or default) level for word line underdrive.
[0049] although Figure 5 The process envisions three levels of voltage control (above, below, and equal to nominal), but it should be understood that this is merely an example. Additional test steps can be added. Figure 5 During the process, other integrated circuit process corners or process-related conditions (e.g., fast-fast (FF) corners and / or slow-slow (SS) corners) are tested. Each test has an associated digital code and a value of the control signal Vsel to set the corresponding level of the adaptive gate bias voltage Vgbias generated by the voltage generator circuit 112.
[0050] The foregoing description has provided a complete and informative description of exemplary embodiments of the invention by way of exemplary and non-limiting examples. However, various modifications and alterations may become apparent to those skilled in the art when read in conjunction with the accompanying drawings and appended claims, given the foregoing description. Nevertheless, all such modifications and similar alterations to the teachings of the invention will still fall within the scope of the invention as defined in the appended claims.
Claims
1. An in-memory computing circuit, comprising: A memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the SRAM cells of the row, and each column comprising at least one bit line connected to the SRAM cells of the column; A word line driving circuit for each row, the word line driving circuit having an output connected to drive the word line of the row, wherein the word line driving circuit is powered by an adaptive power supply voltage; A row controller circuit configured to simultaneously actuate multiple word lines by applying pulses to the word lines via the word line drive circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line of each column, and configured to process analog voltages generated on the bit lines in response to simultaneous actuation of the plurality of word lines, to generate decision outputs for computational operations within the memory; as well as A voltage generator circuit configured to generate an adaptive power supply voltage for powering the word line drive circuit during simultaneous actuation of the multiple word lines used for computational operations within the memory, the adaptive power supply voltage having a level that depends on the integrated circuit process and / or temperature conditions. The voltage generator circuit includes a control circuit configured to generate a control signal. The control signal is configured to modulate the level of the adaptive power supply voltage away from the nominal level in response to the applicable integrated circuit process angle of the transistor device of the SRAM cell.
2. The in-memory computing circuit of claim 1, wherein the voltage generator circuit is an adjustable voltage regulator controlled to generate the level of the adaptive power supply voltage, and wherein the control signal is applied to the voltage generator circuit.
3. The in-memory computing circuit of claim 2, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit, and wherein the control circuit includes a lookup table (LUT) that associates the programming code with the value of the control signal.
4. The in-memory computing circuit of claim 2, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause temperature-dependent tuning of the level of the set adaptive power supply voltage in response to the applicable integrated circuit process corner.
5. The in-memory computing circuit of claim 4, wherein the control circuit includes a lookup table (LUT) that correlates the sensed integrated circuit temperature with a tuning level of the value of the control signal.
6. The in-memory computing circuit of claim 2, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to: in response to an integrated circuit temperature sensed by the temperature sensor, cause the level of the adaptive power supply voltage to be modulated away from the nominal level.
7. The in-memory computing circuit of claim 6, wherein the control circuit includes a lookup table (LUT) that associates the sensed integrated circuit temperature with the value of the control signal.
8. The in-memory computing circuit according to claim 1, wherein the voltage generator circuit comprises: A current source configured to generate a current applied to the first node; as well as The first transistor and the second transistor are connected in series between the first node and the reference node; The adaptive power supply voltage is generated at the first node; The first transistor is a copy of the transmission gate transistor within the SRAM cell; The second transistor is a copy of the pull-down transistor within the SRAM cell.
9. The in-memory computing circuit of claim 8, wherein the current generated by the current source has an amplitude set according to a reference current, the reference current representing the current flowing through the transmission gate transistor and the pull-down transistor for an applicable integrated circuit process corner.
10. The in-memory computing circuit of claim 9, wherein the amplitude of the current generated by the current source is scaled by a factor applied to the reference current.
11. The in-memory computing circuit of claim 10, wherein the first transistor is scaled by the factor for the copy of the transmission gate transistor, and wherein the second transistor is scaled by the factor for the copy of the pull-down transistor.
12. The in-memory computing circuit of claim 8 further includes an amplifier circuit having an input coupled to the first node and an output coupled to power the word line driving circuit.
13. The in-memory computing circuit of claim 8, wherein the current source is controlled to generate an adjustment amount to the current, and further comprising a control circuit configured to generate a control signal for applying to the current source.
14. The in-memory computing circuit of claim 13, wherein the control signal is configured to: in response to the applicable integrated circuit process angle of the transistor device of the SRAM cell, cause the level of the current to be modulated away from the nominal level.
15. The in-memory computing circuit of claim 14, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit; and wherein the control circuit includes a lookup table (LUT) that associates the programming code with the value of the control signal.
16. The in-memory computing circuit of claim 14, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause temperature-dependent tuning of the level of the current set in response to the applicable integrated circuit process corner.
17. The in-memory computing circuit of claim 16, wherein the control circuit includes a lookup table (LUT) that correlates the sensed integrated circuit temperature with a tuning level of the value of the control signal.
18. The in-memory computing circuit of claim 13, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to modulate the level of the current away from the nominal level in response to an integrated circuit temperature sensed by the temperature sensor.
19. The in-memory computing circuit of claim 18, wherein the control circuit includes a lookup table (LUT) that associates the sensed integrated circuit temperature with the value of the control signal.
20. An in-memory computing circuit, comprising: A memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the SRAM cells of the row, and each column comprising at least one bit line connected to the SRAM cells of the column; A word line driving circuit for each row, the word line driving circuit having an output connected to drive the word line of the row; A row controller circuit configured to simultaneously actuate multiple word lines by applying pulses to word lines via the word line drive circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line of each column, and configured to process analog voltages generated on the bit lines in response to simultaneous actuation of the plurality of word lines, to generate decision outputs for computational operations within the memory; A bleed transistor for each word line, wherein each bleed transistor has a source-drain path coupled between the word line and the reference voltage node and a gate configured to receive an adaptive gate bias voltage. as well as A voltage generator circuit configured to generate the adaptive gate bias voltage during simultaneous actuation of the multiple word lines used for computational operations within the memory, the adaptive gate bias voltage having a level that depends on the integrated circuit process and / or temperature conditions. The voltage generator circuit includes a control circuit configured to generate a control signal. The control signal is configured to modulate the level of the adaptive gate bias voltage away from the nominal level in response to the applicable integrated circuit process angle of the transistor device of the SRAM cell.
21. The in-memory computing circuit of claim 20, wherein the voltage generator circuit is an adjustable voltage regulator controlled to generate the level of the adaptive gate bias voltage, and wherein the control signal is applied to the voltage generator circuit.
22. The in-memory computing circuit of claim 21, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit, and wherein the control circuit includes a lookup table (LUT) that associates the programming code with the value of the control signal.
23. The in-memory computing circuit of claim 21, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause temperature-dependent tuning of the level of the set adaptive gate bias voltage in response to the applicable integrated circuit process angle.
24. The in-memory computing circuit of claim 23, wherein the control circuit includes a lookup table (LUT) that correlates the sensed integrated circuit temperature with a tuning level of the value of the control signal.
25. The in-memory computing circuit of claim 21, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to modulate the level of the adaptive gate bias voltage away from the nominal level in response to an integrated circuit temperature sensed by the temperature sensor.
26. The in-memory computing circuit of claim 25, wherein the control circuit includes a lookup table (LUT) that associates the sensed integrated circuit temperature with the value of the control signal.
27. An in-memory computing circuit, comprising: A memory array comprising a plurality of static random access memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the SRAM cells of the row, and each column comprising at least one bit line connected to the SRAM cells of the column; A word line driving circuit for each row, the word line driving circuit having an output connected to drive the word line of the row, wherein the word line driving circuit is powered by an adaptive power supply voltage; A row controller circuit configured to simultaneously actuate multiple word lines by applying pulses to the word lines via the word line drive circuit for in-memory computation operations; A column processing circuit, connected to the at least one bit line of each column, and configured to process analog voltages generated on the bit lines in response to simultaneous actuation of the plurality of word lines, to generate decision outputs for computational operations within the memory; A replica circuit that replicates the transmission gate transistor and pull-down transistor of the SRAM cell; A current generator configured to apply a forced current to the replica circuit to generate a bias voltage; as well as A voltage circuit configured to use the bias voltage to generate an adaptive power supply voltage for powering the word line drive circuit during simultaneous actuation of the multiple word lines used for computational operations within the memory, the adaptive power supply voltage having a level that depends on the integrated circuit process and / or temperature conditions. The current generator said therein includes control circuitry configured to generate control signals; The control signal is configured to modulate the level of the forced current away from the nominal level in response to the applicable integrated circuit process angle of the transistor device of the SRAM cell.
28. The in-memory computing circuit of claim 27, wherein the voltage circuit is a voltage buffer.
29. The in-memory computing circuit of claim 27, wherein the forced current generated by the current generator has an amplitude set according to a reference current, the reference current representing the current flowing through the transmission gate transistor and pull-down transistor of the SRAM cell for an applicable integrated circuit process corner.
30. The in-memory computing circuit of claim 29, wherein the amplitude of the current generated by the current generator is scaled by a factor applied to the reference current.
31. The in-memory computing circuit of claim 30, wherein the copy circuit is scaled according to the factor.
32. The in-memory computing circuit of claim 27, wherein the current generator is controlled to generate an adjustment amount for the forced current, and wherein the control signal is applied to the current generator.
33. The in-memory computing circuit of claim 32, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit, and wherein the control circuit includes a lookup table (LUT) that associates the programming code with the value of the control signal.
34. The in-memory computing circuit of claim 32, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause temperature-dependent tuning of the level of the set forced current in response to the applicable integrated circuit process corner.
35. The in-memory computing circuit of claim 34, wherein the control circuit includes a lookup table (LUT) that correlates the sensed integrated circuit temperature with a tuning level of the value of the control signal.
36. The in-memory computing circuit of claim 31, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to modulate the level of the forced current away from the nominal level in response to an integrated circuit temperature sensed by the temperature sensor.
37. The in-memory computing circuit of claim 36, wherein the control circuit includes a lookup table (LUT) that associates the sensed integrated circuit temperature with the value of the control signal.