A high-reliability anti-reverse connection circuit suitable for a redundant dual controller

Abstract

A kind of high reliability anti-reverse connection circuit suitable for redundant dual controller, increase high side MOS gate auxiliary circuit and sensor low side MOS control circuit.When power is connected, auxiliary circuit does not work;When power is reversed, triode T1, T2 is turned on, and then the gate voltage of MOS Q1, Q2 is pulled to the GND of reverse connection, so that the gate-source voltage of Q1, Q2 is lower than threshold value, to ensure the reliable and stable turn-off of MOS on power bus, at the same time, the gate voltage of MOS Q3, Q4 is also pulled to the GND of reverse connection, so that the gate-source voltage of Q3, Q4 is lower than threshold value, to ensure the reliable and stable turn-off of MOS on sensor ground wire.Diode D1 and D2 realize that this part of circuit does not conduct when power is connected, and only works when power is reversed, resistance RH and RL provide base bias voltage of triode and play the role of current limiting.This application realizes the high reliability anti-reverse protection of redundant dual controller system and external common ground sensor through the distributed configuration of high and low side MOS on the input end of automobile main load power supply and the backflow end of sensor ground wire and the design of targeted auxiliary circuit, and the anti-reverse circuit design scheme suitable for redundant dual controller can effectively realize the high reliability anti-reverse protection.

Description

Technical Field

[0001] This invention belongs to the field of electronic engineering technology, specifically relating to a highly reliable reverse connection protection circuit suitable for redundant dual controllers. Background Technology

[0002] In recent years, autonomous driving has become a hot topic, and the market prospects of automotive intelligence have brought unprecedented changes and opportunities to the automotive industry. The increasing intelligence of automotive electronic control units (ECUs) also places higher demands on product reliability. If automotive electronic equipment suddenly malfunctions, safety accidents can easily occur; therefore, redundant design of automotive ECUs is crucial. ECU redundancy is mainly achieved through full or partial backup of the ECU. A fully redundant ECU system typically consists of a master and a slave controller. When the master controller fails, the slave controller can take over in time to prevent the vehicle's equipment from going out of control, thereby improving the reliability and safety of autonomous driving. However, redundant systems also present new challenges to the vehicle's power supply polarity protection capabilities. Because of the presence of dual power supply interfaces, vehicles with redundant ECU systems are more prone to problems such as reverse wiring harness connections and reverse battery polarity connections during installation, testing, and maintenance than ordinary vehicles. Without reverse polarity protection, this can lead to ECU damage, causing economic losses and even endangering personal safety. Existing reverse connection protection designs are usually inherited from the traditional single ECU reverse connection protection design, without taking into account the special circumstances of redundant scenarios, especially the scenario where two ECUs under redundant power supply have one side connected to the positive power supply and the other side connected to the reverse power supply. This scenario is very likely to cause a short circuit accident between the positive and negative power supplies, damaging the power supply, ECU and grounding equipment. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a highly reliable reverse connection protection circuit suitable for redundant dual controllers. It can effectively protect power supplies and common ground sensors and other devices, and can realize reverse connection protection under the condition that one side is connected to the power supply in the positive direction and the other side is connected to the power supply in the reverse direction, and improve the reliability of the reverse connection protection.

[0004] The present invention provides a highly reliable reverse connection protection circuit suitable for redundant dual controllers, including a main control ECU (1), a secondary control ECU (6) and a sensor (5). The main control ECU (1) is connected to the first die chip of the sensor (5), and the secondary control ECU (2) is connected to the second die chip of the sensor (5). The ground lines of the first die chip and the second die chip are connected to the same ground.

[0005] The main control ECU (1) includes a main control gate auxiliary circuit (10), a main control NMOS tube drive circuit (2), a main control load circuit (3), a main control boost / buck circuit (4), and a sensor low-side first MOS control circuit (11). The sensor low-side first MOS control circuit (11) is located at the ground return terminal of the sensor (5).

[0006] The main control gate auxiliary circuit (10) includes a first transistor T1. The base of the first transistor T1 is divided into two paths. One path is connected to the main control power line through a resistor RH and a first diode D1, and the other path is grounded through a resistor RL. The emitter of the first transistor T1 is connected between the resistor RH and the first diode D1, and the collector of the first transistor T1 is connected to the main control NMOS transistor drive circuit (2).

[0007] The sensor low-side first MOS control circuit (11) includes a third NMOS transistor Q3. The gate of the third NMOS transistor Q3 is connected to the main control NMOS transistor drive circuit (2) through a resistor. One source of the third NMOS transistor Q3 is connected to the ground return terminal of the first die chip, and the other is connected to the gate of the third NMOS transistor Q3 through a reverse diode. The drain of the third NMOS transistor Q3 is connected to the main control load circuit.

[0008] The secondary control ECU (6) includes a secondary control gate auxiliary circuit (12), a secondary control NMOS transistor drive circuit (7), a secondary control load circuit (8), a secondary control boost / buck circuit (9), and a sensor low-side second MOS control circuit (13).

[0009] The second MOS control circuit (11) on the low side of the sensor is located at the ground return terminal of the sensor (5);

[0010] The auxiliary gate circuit (12) includes a second transistor T2. The base of the second transistor T2 is divided into two paths. One path is connected to the auxiliary power supply line through a resistor RH and a second diode D2, and the other path is grounded through a resistor RL. The emitter of the second transistor T2 is connected between the resistor RH and the second diode D2, and the collector of the second transistor T2 is connected to the auxiliary NMOS transistor drive circuit (7).

[0011] The sensor low-side second MOS control circuit (13) includes a fourth NMOS transistor Q4. The gate of the fourth NMOS transistor Q4 is connected to the sub-control NMOS transistor drive circuit (7) through a resistor. One source of the fourth NMOS transistor Q4 is connected to the ground return terminal of the second die chip, and the other is connected to the gate of the fourth NMOS transistor Q4 through a reverse diode. The drain of the fourth NMOS transistor Q4 is connected to the sub-control load circuit.

[0012] As a further technical solution of the present invention, the main control NMOS transistor driving circuit (2) includes a first NMOS transistor Q1. One of the gates of the first NMOS transistor Q1 is connected to the main control gate auxiliary circuit (10), one of the gates is connected to the main control boost circuit through a resistor, and the other of the gate is connected to the source of the first NMOS transistor Q1 through a resistor. The drain of the first NMOS transistor Q1 is connected to the main control boost circuit and the main control load circuit (3) respectively.

[0013] Furthermore, the secondary control NMOS transistor driving circuit (7) includes a second NMOS transistor Q2. One of the gates of the second NMOS transistor Q2 is connected to the secondary control gate auxiliary circuit (12), another is connected to the secondary control boost circuit through a resistor, and the other is connected to the source of the second NMOS transistor Q2 through a resistor. The drain of the second NMOS transistor Q2 is connected to the secondary control boost circuit and the secondary control load circuit (8) respectively.

[0014] Furthermore, the main control load circuit (3) and the secondary control load circuit (8) are respectively connected between the power supply bus and the ground wire.

[0015] The advantages of this invention are that,

[0016] 1. The high-side and low-side MOSFET circuits are distributed and coordinated to provide reverse connection protection, which covers complex reverse connection fault scenarios such as one side being connected to the positive power supply and the other side being connected to the reverse power supply, thus enhancing the system protection capability.

[0017] 2. A reliable turn-off circuit for the high-side MOSFET has been added, which avoids the problem of false turn-on of the high-side MOSFET under rapid reverse connection and improves the reliability of reverse protection;

[0018] 3. By using a low-side MOSFET anti-reverse circuit on a non-busbar, the problem of voltage deviation to ground plane caused by large current flowing through the MOSFET on the busbar can be avoided.

[0019] 4. All four MOSFETs used are common power NMOS transistors instead of PMOS transistors as switching devices, which improves the economics of the circuit and expands the range of device options available on the market. Attached Figure Description

[0020] Figure 1 This is the circuit diagram of the present invention. Detailed Implementation

[0021] Please see Figure 1 This embodiment provides a method of the present invention including a main control ECU1, a secondary control ECU6 and a sensor 5. The main control ECU1 is connected to the first die chip of the sensor 5, and the secondary control ECU6 is connected to the second die chip of the sensor 5. The first die chip and the second die chip are connected in a common manner.

[0022] The main control ECU1 includes a main control gate auxiliary circuit 10, a main control NMOS transistor drive circuit 2, a main control load circuit 3, a main control boost / buck circuit 4, and a sensor low-side first MOS control circuit 11. The sensor low-side first MOS control circuit 11 is located at the ground return terminal of the sensor 5.

[0023] The main control gate auxiliary circuit 10 includes a first transistor T1. The base of the first transistor T1 is divided into two paths. One path is connected to the main control power line through a resistor RH and a first diode D1, and the other path is grounded through a resistor RL. The emitter of the first transistor T1 is connected between the resistor RH and the first diode D1, and the collector of the first transistor T1 is connected to the main control NMOS transistor drive circuit 2.

[0024] The sensor low-side first MOS control circuit 11 includes a third NMOS transistor Q3. The gate of the third NMOS transistor Q3 is connected to the main control NMOS transistor drive circuit 2 through a resistor. One source of the third NMOS transistor Q3 is connected to the ground return terminal of the first die chip, and the other is connected to the gate of the third NMOS transistor Q3 through a reverse diode. The drain of the third NMOS transistor Q3 is connected to the main control load circuit.

[0025] The secondary control ECU6 includes a secondary control gate auxiliary circuit 12, a secondary control NMOS transistor drive circuit 7, a secondary control load circuit 8, a secondary control boost / buck circuit 9, and a sensor low-side second MOS control circuit 13.

[0026] The second MOS control circuit 11 on the low side of the sensor is located at the ground return terminal of the sensor 5;

[0027] The secondary control gate auxiliary circuit 12 includes a second transistor T2. The base of the second transistor T2 is divided into two paths. One path is connected to the secondary control power supply line through a resistor RH and a second diode D2, and the other path is grounded through a resistor RL. The emitter of the second transistor T2 is connected between the resistor RH and the second diode D2, and the collector of the second transistor T2 is connected to the secondary control NMOS transistor drive circuit 7.

[0028] The sensor low-side second MOS control circuit 13 includes a fourth NMOS transistor Q4. The gate of the fourth NMOS transistor Q4 is connected to the sub-control NMOS transistor drive circuit 7 through a resistor. One source of the fourth NMOS transistor Q4 is connected to the ground return terminal of the second die chip, and the other is connected to the gate of the fourth NMOS transistor Q4 through a reverse diode. The drain of the fourth NMOS transistor Q4 is connected to the sub-control load circuit.

[0029] The main control NMOS transistor driving circuit 2 includes a first NMOS transistor Q1. One gate of the first NMOS transistor Q1 is connected to the main control gate auxiliary circuit 10, another is connected to the main control boost circuit through a resistor, and the third is connected to the source of the first NMOS transistor Q1 through a resistor. The drain of the first NMOS transistor Q1 is connected to the main control boost circuit and the main control load circuit 3 respectively.

[0030] The secondary control NMOS transistor driving circuit 7 includes a second NMOS transistor Q2. One of the gates of the second NMOS transistor Q2 is connected to the secondary control gate auxiliary circuit 12, another is connected to the secondary control boost circuit through a resistor, and the third is connected to the source of the second NMOS transistor Q2 through a resistor. The drain of the second NMOS transistor Q2 is connected to the secondary control boost circuit and the secondary control load circuit 8, respectively.

[0031] The main control load circuit 3 and the secondary control load circuit 8 are respectively connected between the power bus and the ground wire.

[0032] The following is a detailed description of each part of this circuit;

[0033] Redundant controller: It consists of a main control ECU1 and a secondary control ECU6. The secondary control ECU6 mainly serves as a backup for the main control ECU1 and intervenes in control when the main control ECU1 fails to ensure the functional safety of the system.

[0034] Sensor: To meet the functional safety and data security requirements of redundant controller systems, sensor 5 contains dual dies (chips) for redundant backup and verification of the signals sensed and output by the sensor. Typically, due to signal consistency and data verification requirements, sensor 5 is designed with a common ground, with GND1 and GND2 connected internally.

[0035] The high-side reverse protection circuit includes NMOS transistors Q1 and Q2 and their driving circuits, as well as a gate auxiliary circuit. Compared to PMOS transistors of the same level, NMOS transistors have a smaller size, better cost-effectiveness, and lower on-resistance, reducing losses. However, they require a voltage higher than the sum of the source and turn-on threshold voltages through a charge pump or boost converter. When the power supply is connected in the correct direction, the boost converter operates, and MOS transistors Q1 and Q2 conduct, allowing the system to operate normally. When the power supply is connected in the reverse direction, the boost converter does not operate, and Q1 and Q2 are turned off, thus protecting the system from damage caused by reverse polarity voltage. The gate auxiliary circuit improves the reverse protection reliability under extreme operating conditions.

[0036] Load circuit: The main load circuit of the ECU is responsible for control and drive. A large current flows through the power bus to provide power to the load.

[0037] Boost / buck circuit: The boost / buck circuit converts the power bus voltage and outputs it to power external sensors;

[0038] Low-side reverse protection circuit section: In contrast to the high-side reverse protection circuit on the power supply side, this design adds a low-side reverse protection circuit located at the sensor's ground return terminal. When the power supply is connected in the correct direction, NMOS transistors Q3 and Q4 conduct normally. Since the large current of the main load ground line does not pass through these MOS transistors, the ground potential shift problem that usually accompanies low-side reverse protection will not occur. Therefore, MOS transistors with a much lower current-carrying capacity than the high-side bus power MOS transistors can be selected during the design process, reducing costs. When the power supply is connected in the reverse direction, the gate voltage is lower than the source voltage, the MOS transistors turn off, and the common ground line is cut off, realizing the reverse protection function. In particular, when the redundant controller's dual power supply is connected in the correct direction on one side and in the reverse direction on the other, this circuit can effectively protect the external common ground sensor and prevent the generation of a large current between the two grounds of the sensor from damaging the chip.

[0039] Compared to existing circuits, this embodiment specifically adds a high-side MOS gate auxiliary circuit and a sensor low-side MOS control circuit.

[0040] When the power supply is connected in the forward direction, the gate auxiliary circuit does not operate. When the power supply is connected in the reverse direction, transistors T1 and T2 conduct, thereby pulling the gate voltages of MOSFETs Q1 and Q2 to the reverse-connected GND. This ensures that the gate-source voltages of Q1 and Q2 are below the threshold, guaranteeing reliable and stable turn-off of the MOSFETs on the power bus. Simultaneously, the gate voltages of MOSFETs Q3 and Q4 are also pulled to the reverse-connected GND, ensuring that the gate-source voltages of Q3 and Q4 are below the threshold, guaranteeing reliable and stable turn-off of the MOSFETs on the sensor ground. Diodes D1 and D2 ensure that this part of the circuit does not conduct when the power supply is connected in the forward direction, but only conducts when the power supply is reversed. Resistors RH and RL provide the base bias voltage of the transistors and also limit current.

[0041] Taking a 12V automotive power system as an example, in this invention, MOSFETs Q1 and Q2 can be N-channel power MOSFETs with a drain-source withstand voltage of 40V, such as Infineon AUIRF8736M2TR; Q3 and Q4 can be N-channel general-purpose MOSFETs, such as Nexperia PMV130ENEAR; transistors T1 and T2 can be NPN transistors, such as Nexperia 2PC4081R-Q; diodes D1 and D2 can be 40V withstand voltage Schottky diodes, such as Nexperia 1PS76SB21-Q; resistors RH and RL can be 10kΩ resistors, such as Yageo AC0402FR-0710KL.

[0042] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the specific embodiments described above. The specific embodiments and descriptions in the specification are merely for further illustrating the principles of the invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A highly reliable reverse connection protection circuit suitable for redundant dual controllers, characterized in that, It includes a main control ECU (1), a secondary control ECU (6) and a sensor (5). The main control ECU (1) is connected to the first die chip of the sensor (5), and the secondary control ECU (2) is connected to the second die chip of the sensor (5). The ground wires of the first die chip and the second die chip are connected to the same ground. The main control ECU (1) includes a main control gate auxiliary circuit (10), a main control NMOS tube drive circuit (2), a main control load circuit (3), a main control boost / buck circuit (4), and a sensor low-side first MOS control circuit (11). The sensor low-side first MOS control circuit (11) is located at the ground return terminal of the sensor (5). The main control gate auxiliary circuit (10) includes a first transistor T1. The base of the first transistor T1 is divided into two paths. One path is connected to the main control power line through a resistor RH and a first diode D1, and the other path is grounded through a resistor RL. The emitter of the first transistor T1 is connected between the resistor RH and the first diode D1, and the collector of the first transistor T1 is connected to the main control NMOS transistor drive circuit (2). The sensor low-side first MOS control circuit (11) includes a third NMOS transistor Q3. The gate of the third NMOS transistor Q3 is connected to the main control NMOS transistor drive circuit (2) through a resistor. One source of the third NMOS transistor Q3 is connected to the ground return terminal of the first die chip, and the other is connected to the gate of the third NMOS transistor Q3 through a reverse diode. The drain of the third NMOS transistor Q3 is connected to the main control load circuit. The secondary control ECU (6) includes a secondary control gate auxiliary circuit (12), a secondary control NMOS transistor drive circuit (7), a secondary control load circuit (8), a secondary control boost / buck circuit (9), and a sensor low-side second MOS control circuit (13). The second MOS control circuit (11) on the low side of the sensor is located at the ground return terminal of the sensor (5); The auxiliary gate circuit (12) includes a second transistor T2. The base of the second transistor T2 is divided into two paths. One path is connected to the auxiliary power supply line through a resistor RH and a second diode D2, and the other path is grounded through a resistor RL. The emitter of the second transistor T2 is connected between the resistor RH and the second diode D2, and the collector of the second transistor T2 is connected to the auxiliary NMOS transistor drive circuit (7). The sensor low-side second MOS control circuit (13) includes a fourth NMOS transistor Q4. The gate of the fourth NMOS transistor Q4 is connected to the sub-control NMOS transistor drive circuit (7) through a resistor. One source of the fourth NMOS transistor Q4 is connected to the ground return terminal of the second die chip, and the other is connected to the gate of the fourth NMOS transistor Q4 through a reverse diode. The drain of the fourth NMOS transistor Q4 is connected to the sub-control load circuit.

2. The high-reliability reverse connection protection circuit suitable for redundant dual controllers according to claim 1, characterized in that, The main control NMOS transistor driving circuit (2) includes a first NMOS transistor Q1. One of the gates of the first NMOS transistor Q1 is connected to the main control gate auxiliary circuit (10), another is connected to the main control boost circuit through a resistor, and the other is connected to the source of the first NMOS transistor Q1 through a resistor. The drain of the first NMOS transistor Q1 is connected to the main control boost circuit and the main control load circuit (3) respectively.

3. The high-reliability reverse connection protection circuit suitable for redundant dual controllers according to claim 1, characterized in that, The secondary control NMOS transistor driving circuit (7) includes a second NMOS transistor Q2. One of the gates of the second NMOS transistor Q2 is connected to the secondary control gate auxiliary circuit (12), another is connected to the secondary control boost circuit through a resistor, and the other is connected to the source of the second NMOS transistor Q2 through a resistor. The drain of the second NMOS transistor Q2 is connected to the secondary control boost circuit and the secondary control load circuit (8) respectively.

4. A highly reliable reverse connection protection circuit suitable for redundant dual controllers according to claim 1, characterized in that, The main control load circuit (3) and the secondary control load circuit (8) are respectively connected between the power supply bus and the ground wire.

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