A circuit and method for implementing RTC reset based on power-on key
By designing an RTC reset circuit based on the power button, the cumbersome problem of clearing CMOS when a computer malfunctions in an industrial environment is solved, achieving stable CMOS clearing without disassembling the machine, thus reducing the difficulty and cost of operation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN REALBOM INTELLITECH CO LTD
- Filing Date
- 2022-11-07
- Publication Date
- 2026-06-26
AI Technical Summary
In industrial environments, when computers malfunction, they need to be returned to the factory for repair. Existing CMOS clearing methods are cumbersome, especially for computers that do not support on-site disassembly.
Design an RTC reset circuit based on the power button, including a power supply module, a button trigger module, a logic control module, and a CMOS clear module. By combining the button trigger signal and the logic control module, a stable CMOS clear can be achieved, avoiding physical disassembly.
It enables clearing the CMOS via a key while the computer is powered off, simplifying the operation process, reducing hardware costs and power consumption, and is widely adaptable and compatible with existing computers.
Smart Images
Figure CN115603724B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer error handling technology, and in particular to a circuit and method for resetting an RTC based on the power button. Background Technology
[0002] In the internal structure of a computer, CMOS (Complementary Metal Oxide Semiconductor) is a read / write parallel or serial FLASH chip on the motherboard, primarily used to store the motherboard BIOS hardware configuration settings and user-defined motherboard parameters. In practical applications, static electricity, power surges, unauthorized power outages, or improper user settings can all lead to CMOS parameter errors. Incorrect CMOS parameter settings may prevent the computer from booting properly, requiring manual clearing of the CMOS to restore normal operation.
[0003] Currently, clearing the CMOS is typically done using two methods: CMOS jumper setting and removing the motherboard battery. When using the CMOS jumper setting, the jumper needs to be moved from the Normal pin to the Clean pin corresponding to the CMOS clear operation. Afterward, the jumper should be left on the Clean pin for a period of time before being moved back to the Normal pin.
[0004] The aforementioned technologies are not applicable to computers used in industrial environments, which typically do not support on-site disassembly. When a computer malfunctions, it generally needs to be returned to the factory for repair, resulting in a cumbersome process for handling computer malfunctions. Summary of the Invention
[0005] To reduce the complexity of handling computer malfunctions, this application provides a circuit and method for resetting the RTC based on the power button.
[0006] In a first aspect, this application provides a circuit for RTC reset based on the power button, employing the following technical solution:
[0007] A circuit for resetting an RTC based on a power button includes:
[0008] The power supply module is connected to the motherboard power supply and the battery power supply. The power supply module is used to output the working voltage according to the connected motherboard power supply or battery power supply.
[0009] A button trigger module is connected to the power supply module. When the button trigger module receives the battery voltage and the power button is pressed, it outputs a clear trigger signal.
[0010] A logic control module is connected to both the power supply module and the button trigger module. After receiving a clear trigger signal, the logic control module outputs a reset sustain signal and a power supply sustain voltage.
[0011] The CMOS clearing module has its input terminals connected to the button triggering module and the logic control module, respectively. Its output terminal is connected to the Clean pin on the motherboard. The CMOS clearing module receives a reset sustain signal and a power supply sustain voltage and then outputs a clear signal to clear the CMOS.
[0012] By adopting the above technical solution, the entire circuit can be supplied with operating voltage through the power supply module regardless of whether the computer is powered on or off. When the computer is powered only by the battery, pressing the power button outputs a corresponding clear trigger signal. The logic control module holds the clear trigger signal, enabling the CMOS clearing module to output a clear signal to the Clean pin based on the reset hold signal and the power supply hold voltage output from the logic control module, thereby clearing the CMOS.
[0013] Optionally, the power supply module includes a motherboard power input terminal, a battery power input terminal, a first resistor R1, a second resistor R2, and a dual power input diode D1; the first resistor R1 is connected in series between the motherboard power input terminal and one input terminal of the dual power input diode D1; the second resistor R2 is connected in series between the battery power input terminal and one input terminal of the dual power input diode D1; the output terminal of the dual power input diode D1 is used to output the operating voltage.
[0014] By adopting the above technical solution, the dual power input diode D1 is used to select the power supply for the output. When there is no motherboard power supply, the battery power supply is used. When the motherboard power supply is present, the resistance values of the first resistor R1 and the second resistor R2 are used to preferentially conduct the diode where the motherboard power supply is located, thereby reducing battery consumption.
[0015] Optionally, the button triggering module includes a triggering unit and a suppression unit. The suppression unit is connected to the motherboard power supply and outputs a suppression signal when receiving motherboard voltage. The triggering unit and the suppression unit are connected. The triggering unit outputs a clear trigger signal when receiving battery voltage and the button is pressed. The triggering unit stops outputting the clear trigger signal when receiving both the suppression signal and battery voltage and the button is pressed.
[0016] By adopting the above technical solution, the suppression unit receives the motherboard voltage to limit the output signal of the trigger unit, thereby ensuring that after the system is powered on normally, pressing the power button will not cause the button trigger module to output a clear trigger signal, thus ensuring the normal use of the power button.
[0017] Optionally, the trigger unit includes a first MOSFET Q1, a third resistor R3, a fourth resistor R4, a Zener diode VD, a first capacitor C1, and a push-button switch K; the third resistor R3, the fourth resistor R4, and the push-button switch K are connected in series, and the third resistor R3 is connected to the source of the first MOSFET Q1, while the push-button switch K is grounded; the Zener diode VD is connected in series between the node between the third resistor R3 and the fourth resistor R4 and the ground line; the connection node between the fourth resistor R4 and the push-button switch K is connected to the output terminal of the power supply module; the gate of the first MOSFET Q1 is connected to the output terminal of the power supply module, the first capacitor C1 is connected in series between the gate of the first MOSFET Q1 and the ground line, and the drain of the first MOSFET Q1 outputs a clear trigger signal.
[0018] By adopting the above technical solution, when the push-button switch K is not pressed, the gate and source voltages of the first MOSFET Q1 are both at a high level, and the drain voltage of the first MOSFET Q1 has no output. After the push-button switch K is pressed, the gate voltage of the first MOSFET Q1 is directly pulled low, thereby turning on the first MOSFET Q1, and thus enabling the drain of the first MOSFET Q1 to output a low-level clear trigger signal.
[0019] Optionally, the suppression unit includes a second MOSFET Q2, a fifth resistor R5, a sixth resistor R6, a second capacitor C2, and a first Schottky diode SBD1; the fifth resistor R5 and the sixth resistor R6 are connected in series, the fifth resistor R5 is connected to the motherboard power supply, and the sixth resistor R6 is connected to ground; the first Schottky diode SBD1 and the fifth resistor R5 are connected in parallel, and the second capacitor C2 and the sixth resistor R6 are connected in parallel; the gate of the second MOSFET Q2 is connected to the connection node between the fifth resistor R5 and the sixth resistor R6, the source of the second MOSFET Q2 is grounded, and the drain of the second MOSFET Q2 is connected to the gate of the first MOSFET Q1.
[0020] By employing the above technical solution, when the computer is not powered on, there is no system power on the motherboard, and the gate of the second MOSFET Q2 is in a low-level state. After the computer is powered on, system power is present on the motherboard. At this time, the voltage divider circuit composed of the fifth resistor R5 and the sixth resistor R6 provides voltage to the gate of the second MOSFET Q2, thereby turning on the second MOSFET Q2. After the second MOSFET Q2 is turned on, its drain is connected to its gate, directly pulling down the gate level of the second MOSFET Q2, thus ensuring that the first MOSFET Q1 cannot be turned on, and therefore cannot output a trigger cancellation signal.
[0021] Optionally, the logic control module includes a third MOSFET Q3, a fourth MOSFET Q4, a fifth MOSFET Q5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and an XOR gate chip U1; the seventh resistor R7 is connected in series between the source and gate of the third MOSFET Q3, and the third capacitor C3 is connected in series between the drain and ground of the third MOSFET Q3; the eighth resistor R8 and the fourth capacitor C4 are connected in series, the ninth resistor R9 and the fifth capacitor C5 are connected in series, and both the eighth resistor R8 and the ninth resistor R9 are connected to the drain of the third MOSFET Q3; both the fourth capacitor C4 and the fifth capacitor C5 are connected to ground; the tenth resistor R10 is connected in series at the connection node between the eighth resistor R8 and the fourth capacitor C4, and at the fourth MOSFET Q5. Between the drain of MOSFET Q4, the eleventh resistor R11 is connected in series between the connection node between the ninth resistor R9 and the fifth capacitor C5 and the drain of the fifth MOSFET Q5. The sources of the fourth MOSFET Q4 and the fifth MOSFET Q5 are both connected to ground. The gates of the third MOSFET Q3, the fourth MOSFET Q4, and the fifth MOSFET Q5 are all connected to the output terminal of the button trigger module. The power supply terminal of the XOR gate chip U1 is connected to the drain of the third MOSFET Q3. The first input terminal of the XOR gate chip U1 is connected to the connection node between the eighth resistor R8 and the fourth capacitor C4. The second input terminal of the XOR gate chip U1 is connected to the connection node between the ninth resistor R9 and the fifth capacitor C5. The output terminal of the XOR gate chip U1 is used to output a reset holding signal. The fourth capacitor C4 and the fifth capacitor C5 have different capacitances.
[0022] By employing the above technical solution, the power supply sustaining voltage is provided by the conduction of the third MOSFET Q3. Two different RC charging circuits are formed, consisting of the eighth resistor R8 and the fourth capacitor C4, and the ninth resistor R9 and the fifth capacitor C5, with different charging speeds. By setting the fourth capacitor C4 and the fifth capacitor C5 to different capacitance values, a certain difference exists between the levels at the two input terminals of the XOR gate chip U1 at any given time, thus enabling the output terminal of the XOR gate chip U1 to output a sustaining signal for a certain period. After both the fourth capacitor C4 and the fifth capacitor C5 are fully charged, the levels at the input terminals of the XOR gate chip U1 are equal, thereby changing the output level. Furthermore, through the circuits containing the fourth MOSFET Q4 and the fifth MOSFET Q5, when the button trigger module does not output a clear trigger signal, the power supply module turns on the fourth MOSFET Q4 and the fifth MOSFET Q5, thereby quickly discharging the fourth capacitor C4 and the fifth capacitor C5.
[0023] Optionally, the CMOS clearing module includes a sixth MOSFET Q6, a seventh MOSFET Q7, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a sixth capacitor C6, a seventh capacitor C7, and a second Schottky diode SBD2. The twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are connected in series. The end of the twelfth resistor R12 furthest from the fourteenth resistor R14 is grounded. The end of the fourteenth resistor R14 furthest from the twelfth resistor R12 is used to receive the power supply sustaining voltage. The node between the twelfth resistor R12 and the thirteenth resistor R13 is used to receive the reset sustaining signal. The sixth capacitor C6 is connected in series between the thirteenth resistor R13 and the fourteenth resistor R14. The gate of the sixth MOSFET Q6 and the end of the sixth capacitor C6 furthest from ground are connected; the source of the sixth MOSFET Q6 is grounded; the fifteenth resistor R15 is connected to the drain of the sixth MOSFET Q6; the end of the fifteenth resistor R15 furthest from the drain of the sixth MOSFET Q6 is the output terminal of the clear CMOS module; the sixteenth resistor R16 is connected in series between the gate of the sixth MOSFET Q6 and the drain of the seventh MOSFET Q7; the source of the seventh MOSFET Q7 is grounded; the seventeenth resistor R17 is connected to the gate of the seventh MOSFET Q7; the second Schottky diode SBD2 is connected in parallel with the seventeenth resistor R17; the seventh capacitor C7 is connected in series between the ground and the gate of the seventh MOSFET Q7.
[0024] By adopting the above technical solution, the source of the sixth MOSFET Q6 is grounded to simulate the ground pin on the motherboard. When the sixth MOSFET Q6 is turned on, it corresponds to the grounding of the Clean pin on the motherboard. The CMOS is cleared by using the holding effect of the reset signal for a period of time.
[0025] Secondly, this application provides a method for resetting an RTC based on a power button, employing the following technical solution:
[0026] A method for resetting an RTC based on the power button includes the following steps:
[0027] Disconnect the power supply to the entire computer.
[0028] Based on the fact that the button switch K is pressed, it is determined that the state of the button switch K is maintained for more than a preset time threshold.
[0029] Based on the button holding time exceeding the preset time threshold, it is determined that the RTC has completed clearing and resetting.
[0030] By employing the above technical solution, after the computer's power supply is confirmed to be disconnected, pressing the power button will prevent the computer from starting, as the motherboard is powered only by the battery. When the computer has no system power supply, pressing the power button and holding it for more than a preset time threshold ensures that the Clean pin on the motherboard continuously receives a clear signal, thereby completing the CMOS clearing process.
[0031] In summary, this application includes at least one of the following beneficial technical effects:
[0032] 1. When the computer is powered off, the CMOS on the motherboard can be cleared by pressing a button, avoiding the cumbersome operation of opening the case.
[0033] 2. No other buttons are installed on the chassis, making it compatible with existing computers and more adaptable.
[0034] 3. This solution is implemented using pure hardware principles, resulting in low hardware cost and low power consumption. Attached Figure Description
[0035] Figure 1 This is a schematic diagram of a system module for clearing CMOS in a computer, as described in related technologies.
[0036] Figure 2 This is a system module diagram of a circuit for RTC reset based on the power button according to an embodiment of this application.
[0037] Figure 3This is a circuit diagram of the power supply module and the button triggering module in a circuit for RTC reset based on the power button according to an embodiment of this application.
[0038] Figure 4 This is a circuit diagram of the logic control module in a circuit that implements RTC reset based on the power button according to an embodiment of this application.
[0039] Figure 5 This is a circuit schematic diagram of the CMOS module clearing function in a circuit for RTC reset based on the power button according to an embodiment of this application.
[0040] Explanation of reference numerals in the attached diagram: 1. Power supply module; 2. Button trigger module; 21. Trigger unit; 22. Suppression unit; 3. Logic control module; 4. Clear CMOS module. Detailed Implementation
[0041] The following is in conjunction with the appendix Figure 1-5 This application will be described in further detail.
[0042] Reference Figure 1 In existing computer systems, the motherboard contains a CMOS chip, primarily used to store the motherboard's BIOS hardware configuration settings and user-defined parameters. When a user needs to restore the computer to factory settings or forgets their login password, they must clear the CMOS. There are generally two methods for clearing the CMOS.
[0043] Method 1: Use the CMOS discharge jumper. The CMOS discharge jumper usually has three pins. Pins 1-2 are in the "Normal" state, and pins 2-3 are in the "Clear CMOS" state. Move the jumper from pins 1-2 to pins 2-3, hold for one minute, and then return the jumper to the "Normal" state to complete the CMOS clearing process. Method 2: Remove the lithium battery from the motherboard.
[0044] Whether using jumpers or removing the lithium battery, both methods require opening the computer case and removing the motherboard. Disassembling and reassembling the computer case increases labor and time costs, and also increases the risk of motherboard damage.
[0045] In the description of this embodiment, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.
[0046] This application discloses a circuit for RTC reset based on the power button.
[0047] Reference Figure 2 A circuit for RTC reset based on the power button includes a power supply module 1, a button trigger module 2, a logic control module 3, and a CMOS clear module 4. The power supply module 1 is connected to the motherboard power supply and the battery power supply, providing the operating voltage for the entire circuit through either the motherboard power supply or the battery power supply.
[0048] The button trigger module 2 includes a power button and is connected to the power supply module 1. It outputs a signal when the power button is pressed. Specifically, in battery-powered mode, when the power button is pressed, the button trigger module 2 outputs a clear trigger signal. For CMOS clearing, the signal on the Clean pin needs to be maintained for a period of time. Therefore, to ensure signal stability, the logic control module 3 is connected to both the power supply module 1 and the button trigger module 2. The logic control module 3 obtains its operating voltage from the power supply module 1 and outputs a reset sustain signal and a power sustain voltage after receiving the clear trigger signal. By setting both the reset sustain signal and the power sustain voltage to maintain their positions for a certain period, subsequent CMOS clearing can be stably performed. The input terminals of the clear CMOS module 4 are connected to both the button trigger module 2 and the logic control module 3, while the output terminal of the clear CMOS module 4 is used to connect to the Clean pin on the motherboard. The CMOS clearing module 4 receives a reset sustain signal and a power supply sustain voltage, which enables the CMOS clearing module 4 to output a clear signal. By maintaining the reset sustain signal and the power supply sustain voltage, the clear signal is maintained for a period of time, thereby providing a stable clear signal to the Clean pin and clearing the CMOS.
[0049] Reference Figure 3 Power supply module 1 connects to both the motherboard power supply and the battery power supply. When the computer is powered on, it is powered by the motherboard power supply; when the computer is powered off, it is powered by the battery power supply. Specifically, power supply module 1 includes a motherboard power input terminal VAL, a battery power input terminal BAT, a first resistor R1, a second resistor R2, and a dual-power input diode D1. The motherboard power input terminal VAL is connected to the power supply terminals on the motherboard, generating a corresponding power supply voltage when the computer is powered on. The battery power input terminal BAT provides power output through a battery connection.
[0050] The first resistor R1 is connected in series between the motherboard power input terminal VAL and one input terminal of the dual power input diode D1; the second resistor R2 is connected in series between the battery power input terminal BAT and one input terminal of the dual power input diode D1. The output terminal of the dual power input diode D1 is used to output the operating voltage. By setting the first resistor R1 and the second resistor R2 to different impedance values, the battery power supply does not output a supply voltage when the motherboard power supply is present. Specifically, the resistance of the first resistor R1 is greater than the resistance of the second resistor R2.
[0051] When the button trigger module 2 is connected to the motherboard power supply, pressing the power button will not output a clear trigger signal. However, when the button trigger module 2 is powered only by the battery, pressing the power button will output a clear trigger signal. Specifically, the button trigger module 2 includes a trigger unit 21 and a suppression unit 22. The trigger unit 21 is connected to the power supply module 1 and can receive both motherboard power supply voltage and battery power supply voltage. When receiving battery voltage, the trigger unit 21 outputs a clear trigger signal when the power button is pressed. The suppression unit 22 is connected to the motherboard power supply and also to the trigger unit 21. When the suppression unit 22 receives motherboard voltage, it outputs a suppression signal. When the trigger unit 21 receives the suppression signal, it stops outputting the clear trigger signal.
[0052] Specifically, the trigger unit 21 includes a first MOSFET Q1, a third resistor R3, a fourth resistor R4, a Zener diode VD, a first capacitor C1, and a push-button switch K, where the push-button switch K is the power button on a computer. The third resistor R3, the fourth resistor R4, and the push-button switch K are connected in series. The end of the third resistor R3 furthest from the push-button switch K is connected to the source of the first MOSFET Q1, while the end of the push-button switch K furthest from the third resistor R3 is grounded.
[0053] A Zener diode VD is connected in series between the node between the third resistor R3 and the fourth resistor R4, and between the ground wire. The connection node between the fourth resistor R4 and the push-button switch K is connected to the output terminal of power supply module 1. Before the push-button switch K is turned on, the source of the first MOSFET Q1 is at a high level. The gate of the first MOSFET Q1 is connected to the output terminal of power supply module 1, and the first capacitor C1 is connected in series between the gate of the first MOSFET Q1 and the ground wire. When power supply module 1 outputs the supply voltage, the first MOSFET Q1 is turned on, and its drain outputs a high-level voltage signal. When the switch button is pressed, the drain output voltage of the first MOSFET Q1 changes from high to low, i.e., the clear trigger signal becomes a low-level voltage signal.
[0054] The suppression unit 22 includes a second MOSFET Q2, a fifth resistor R5, a sixth resistor R6, a second capacitor C2, and a first Schottky diode SBD1. The fifth resistor R5 and the sixth resistor R6 are connected in series to form a voltage divider circuit. The fifth resistor R5 is connected to the motherboard power supply, and the sixth resistor R6 is connected to ground. The first Schottky diode SBD1 is connected in parallel with the fifth resistor R5, and the second capacitor C2 is connected in parallel with the sixth resistor R6. The gate of the second MOSFET Q2 is connected to the connection node between the fifth resistor R5 and the sixth resistor R6. The source of the second MOSFET Q2 is grounded, and the drain of the second MOSFET Q2 is connected to the gate of the first MOSFET Q1.
[0055] When the suppression unit 22 is connected to the motherboard power supply, the voltage divider circuit controls the second MOSFET Q2 to turn on, thereby pulling down the gate voltage of the first MOSFET Q1 and turning off the first MOSFET Q1, so that a low-level clear trigger signal cannot be output when the motherboard power supply is on.
[0056] Reference Figure 2 and Figure 4 The logic control module 3 is connected to the button trigger module 2. After receiving the button trigger signal, the logic control module 3 outputs a stable reset sustain signal and a power supply sustain voltage. Specifically, the logic control module 3 includes a third MOSFET Q3, a fourth MOSFET Q4, a fifth MOSFET Q5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and an XOR gate chip U1. The seventh resistor R7 is connected in series between the source and gate of the third MOSFET Q3, and the source of the third MOSFET Q3 is used to connect to the output terminal of the power supply module 1. The third MOSFET Q3 is a P-channel MOSFET. The third capacitor C3 is connected in series between the drain of the third MOSFET Q3 and ground, and the drain of the third MOSFET Q3 outputs the power supply sustain voltage.
[0057] The eighth resistor R8 and the fourth capacitor C4 are connected in series to form an RC charging branch, as are the ninth resistor R9 and the fifth capacitor C5. Both the eighth resistor R8 and the ninth resistor R9 are connected to the drain of the third MOSFET Q3. The fourth capacitor C4 and the fifth capacitor C5 are both connected to ground. Because the capacitances of the fourth capacitor C4 and the fifth capacitor C5 are different, their charging speeds differ. The power supply terminal of the XOR gate chip U1 is connected to the drain of the third MOSFET Q3 to receive the operating voltage. The first input terminal of the XOR gate chip U1 is connected to the connection node between the eighth resistor R8 and the fourth capacitor C4, and the second input terminal is connected to the connection node between the ninth resistor R9 and the fifth capacitor C5. Due to the different capacitances of the fourth capacitor C4 and the fifth capacitor C5, their charging speeds also differ. When neither the fourth capacitor C4 nor the fifth capacitor C5 is fully charged, a voltage difference exists between the two input terminals of the XOR gate chip U1 at the same time. This causes the XOR gate chip U1 to output a high-level voltage signal, which is maintained until both capacitors C4 and C5 are fully charged. When both capacitors C4 and C5 are fully charged, the XOR gate chip U1 outputs a low-level voltage signal. In this embodiment, the reset holding signal is a high-level voltage signal. The voltage signal output by the XOR gate chip U1 ensures that the output signal remains stable.
[0058] The tenth resistor R10 is connected in series between the connection node between the eighth resistor R8 and the fourth capacitor C4, and between the drain of the fourth MOSFET Q4. The eleventh resistor R11 is connected in series between the connection node between the ninth resistor R9 and the fifth capacitor C5, and between the drain of the fifth MOSFET Q5. The sources of the fourth MOSFET Q4 and the fifth MOSFET Q5 are both connected to ground. When the fourth MOSFET Q4 and the fifth MOSFET Q5 are turned on, they discharge the fourth capacitor C4 and the fifth capacitor C5. The gates of the third MOSFET Q3, the fourth MOSFET Q4, and the fifth MOSFET Q5 are all connected to the output terminal of the button trigger module 2. The capacitors are discharged by the button trigger module 2 outputting a high-level voltage signal.
[0059] Reference Figure 2 and Figure 5The CMOS clear module 4 outputs a stable clear signal to the Clean pin based on the received reset sustain signal and power sustain signal. Specifically, the CMOS clear module 4 includes a sixth MOSFET Q6, a seventh MOSFET Q7, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a sixth capacitor C6, a seventh capacitor C7, and a second Schottky diode SBD2. The twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are connected in series. The end of the twelfth resistor R12 furthest from the fourteenth resistor R14 is grounded, and the end of the fourteenth resistor R14 furthest from the twelfth resistor R12 is connected to the logic control module 3 to obtain the power sustain voltage. The node between the twelfth resistor R12 and the thirteenth resistor R13 is connected to the logic control module 3 to receive the reset sustain signal.
[0060] The sixth capacitor C6 is connected in series between the node between the thirteenth resistor R13 and the fourteenth resistor R14, and between the capacitor and ground. The gate of the sixth MOSFET Q6 is connected to the end of the sixth capacitor C6 furthest from ground, and the source of the sixth MOSFET Q6 is grounded. Upon receiving the reset hold signal, the voltage at the gate of the sixth MOSFET Q6 is slowly increased via the sixth capacitor C6. The fifteenth resistor R15 is connected to the drain of the sixth MOSFET Q6, and the end of the fifteenth resistor R15 furthest from the drain of the sixth MOSFET Q6 is the output terminal of the CMOS clear module 4. Through the XOR gate chip U1 and the sixth capacitor C6, it is ensured that the CMOS clearing operation is completed after a preset time. This also ensures that when only battery power is connected, the CMOS is not accidentally cleared due to accidental power-on triggering caused by human error or other reasons.
[0061] The sixteenth resistor is connected in series between the gate of the sixth MOSFET Q6 and the drain of the seventh MOSFET Q7, with the source of the seventh MOSFET Q7 grounded. The seventeenth resistor R17 is connected to the gate of the seventh MOSFET Q7. In this embodiment, the CMOS clearing module 4 also includes a second Schottky diode SBD2 and a seventh capacitor C7. The second Schottky diode SBD2 and the seventeenth resistor R17 are connected in parallel, and the seventh capacitor C7 is connected in series between the ground line and the gate of the seventh MOSFET Q7. Through the second Schottky diode SBD2 and the seventh capacitor C7, the gate voltage of the seventh MOSFET Q7 is stably increased while maintaining the gate voltage value.
[0062] The implementation principle of this application embodiment is as follows: Different voltage signals are generated by the power button when the motherboard power is connected and when the battery power is connected. The voltage signal output when the battery power is connected drives the logic control module 3 to work, enabling the XOR gate chip U1 in the logic control module 3 to output a stable clear signal. Furthermore, using only the power button to clear the CMOS significantly reduces the difficulty of handling computer malfunctions.
[0063] This application also discloses a method for resetting an RTC based on a power button. The method for resetting an RTC based on a power button includes the following steps.
[0064] S1. Disconnect the power supply to the computer.
[0065] In a computer, once the power button is pressed, the internal hardware starts up, causing the power supply to output various voltage control signals or power supply signals. Therefore, when clearing and resetting the RTC (Real-Time Control) using the power button, it's crucial to ensure the power button is intact while preventing the computer from immediately starting up. Disconnecting the computer's power supply prevents it from booting up when the power button is pressed, thus ensuring normal computer operation.
[0066] S2. Based on the fact that the button switch K is pressed, determine that the state of the button switch K is maintained for more than a preset time threshold.
[0067] For different motherboard manufacturers, the internal CMOS clearing time is fixed before the motherboard leaves the factory. The clearing time corresponding to the current motherboard is determined by the motherboard information. When the computer's power button is pressed, the pressed button needs to be held for an extended period, exceeding a preset time threshold. In this embodiment, the preset time threshold is the time difference between the inputs of the XOR gate chip U1.
[0068] S3. Based on the button holding time exceeding the preset time threshold, determine that the RTC has completed clearing and resetting.
[0069] Specifically, when the button is pressed and held for more than a preset time, it ensures that the long press reset of the power button is effective. That is, at this time, the Clean pin on the motherboard can receive a long-term clear signal to complete the CMOS clearing.
[0070] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A circuit for resetting an RTC based on a power-on button, characterized in that, include: Power supply module (1), which is connected to the motherboard power supply and the battery power supply, and is used to output the working voltage; A button trigger module (2) is connected to the power supply module (1). The button trigger module (2) outputs a clear trigger signal when it receives the battery voltage and the power button is pressed. The logic control module (3) is connected to the power supply module (1) and the key trigger module (2) respectively. After receiving the clear trigger signal, the logic control module (3) outputs a reset sustain signal and a power supply sustain voltage. The CMOS clearing module (4) has its input terminals connected to the button trigger module (2) and the logic control module (3) respectively. The output terminal of the CMOS clearing module (4) is used to connect to the Clean pin on the motherboard. The CMOS clearing module (4) receives the reset sustain signal and the power supply sustain voltage and then outputs a clear signal to clear the CMOS. The button trigger module (2) includes a trigger unit (21) and a suppression unit (22). The suppression unit (22) is connected to the motherboard power supply and outputs a suppression signal when receiving the motherboard voltage. The trigger unit (21) and the suppression unit (22) are connected. The trigger unit (21) outputs a clear trigger signal when receiving the battery voltage and the button is pressed. The trigger unit (21) stops outputting the clear trigger signal when receiving the suppression signal and the battery voltage and the button is pressed. The trigger unit (21) includes a first MOSFET Q1, a third resistor R3, a fourth resistor R4, a Zener diode VD, a first capacitor C1, and a push-button switch K; the third resistor R3, the fourth resistor R4, and the push-button switch K are connected in series, and the third resistor R3 is connected to the source of the first MOSFET Q1, while the push-button switch K is grounded; the Zener diode VD is connected in series between the node between the third resistor R3 and the fourth resistor R4 and the ground line; the connection node between the fourth resistor R4 and the push-button switch K is connected to the output terminal of the power supply module (1); the gate of the first MOSFET Q1 is connected to the output terminal of the power supply module (1), the first capacitor C1 is connected in series between the gate of the first MOSFET Q1 and the ground line, and the drain of the first MOSFET Q1 outputs a clear trigger signal.
2. The circuit for RTC reset based on the power button according to claim 1, characterized in that: The power supply module (1) includes a motherboard power input terminal, a battery power input terminal, a first resistor R1, a second resistor R2, and a dual power input diode D1; the first resistor R1 is connected in series between the battery power input terminal and one input terminal of the dual power input diode D1; the second resistor R2 is connected in series between the motherboard power input terminal and one input terminal of the dual power input diode D1; the output terminal of the dual power input diode D1 is used to output the working voltage.
3. The circuit for RTC reset based on the power button according to claim 1, characterized in that: The suppression unit (22) includes a second MOSFET Q2, a fifth resistor R5, a sixth resistor R6, a second capacitor C2, and a first Schottky diode SBD1; the fifth resistor R5 and the sixth resistor R6 are connected in series, the fifth resistor R5 is connected to the motherboard power supply, and the sixth resistor R6 is connected to the ground; the first Schottky diode SBD1 and the fifth resistor R5 are connected in parallel, and the second capacitor C2 and the sixth resistor R6 are connected in parallel; the gate of the second MOSFET Q2 is connected to the connection node between the fifth resistor R5 and the sixth resistor R6, the source of the second MOSFET Q2 is grounded, and the drain of the second MOSFET Q2 is connected to the gate of the first MOSFET Q1.
4. The circuit for RTC reset based on the power button according to claim 1, characterized in that: The logic control module (3) includes a third MOSFET Q3, a fourth MOSFET Q4, a fifth MOSFET Q5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and an XOR gate chip U1; the seventh resistor R7 is connected in series between the source and gate of the third MOSFET Q3, and the third capacitor C3 is connected in series between the drain and ground of the third MOSFET Q3; the eighth resistor R8 and the fourth capacitor C4 are connected in series, the ninth resistor R9 and the fifth capacitor C5 are connected in series, and both the eighth resistor R8 and the ninth resistor R9 are connected to the drain of the third MOSFET Q3, and both the fourth capacitor C4 and the fifth capacitor C5 are connected to ground; the tenth resistor R10 is connected in series at the connection node between the ninth resistor R9 and the fifth capacitor C5 and the fourth MOSFET Q3. Between the drain of transistor Q4, the eleventh resistor R11 is connected in series between the connection node between the eighth resistor R8 and the fourth capacitor C4 and between the drain of the fifth MOS transistor Q5. The sources of the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are both connected to ground. The gates of the third MOS transistor Q3, the fourth MOS transistor Q4, and the fifth MOS transistor Q5 are all connected to the output terminal of the button trigger module (2). The power supply terminal of the XOR gate chip U1 is connected to the drain of the third MOS transistor Q3. The first input terminal of the XOR gate chip U1 is connected to the connection node between the eighth resistor R8 and the fourth capacitor C4. The second input terminal of the XOR gate chip U1 is connected to the connection node between the ninth resistor R9 and the fifth capacitor C5. The output terminal of the XOR gate chip U1 is used to output a reset sustain signal. The fourth capacitor C4 and the fifth capacitor C5 have different capacitances.
5. The circuit for RTC reset based on the power button according to claim 1, characterized in that: The CMOS clearing module (4) includes a sixth MOSFET Q6, a seventh MOSFET Q7, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a sixth capacitor C6, a seventh capacitor C7, and a second Schottky diode SBD2. The twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are connected in series. The end of the twelfth resistor R12 furthest from the fourteenth resistor R14 is grounded. The end of the fourteenth resistor R14 furthest from the twelfth resistor R12 is used to receive the power supply sustaining voltage. The node between the twelfth resistor R12 and the thirteenth resistor R13 is used to receive the reset sustaining signal. The sixth capacitor C6 is connected in series between the thirteenth resistor R13 and the thirteenth resistor R14. The nodes between the fourteen resistors R14 and the ground line; the gate of the sixth MOS transistor Q6 and the end of the sixth capacitor C6 away from ground are connected, the source of the sixth MOS transistor Q6 is grounded, the fifteenth resistor R15 and the drain of the sixth MOS transistor Q6 are connected, and the end of the fifteenth resistor R15 away from the drain of the sixth MOS transistor Q6 is the output terminal of the clear CMOS module (4); the sixteenth resistor R16 is connected in series between the gate of the sixth MOS transistor Q6 and the drain of the seventh MOS transistor Q7, and the source of the seventh MOS transistor Q7 is grounded; the seventeenth resistor R17 is connected to the gate of the seventh MOS transistor Q7; the second Schottky diode SBD2 and the seventeenth resistor R17 are connected in parallel, and the seventh capacitor C7 is connected in series between the ground line and the gate of the seventh MOS transistor Q7.
6. A circuit for RTC reset based on the power button as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Disconnect the power supply to the entire computer. Based on the fact that the button switch K is pressed, it is determined that the state of the button switch K is maintained for more than a preset time threshold. Based on the button holding time exceeding the preset time threshold, it is determined that the RTC has completed clearing and resetting.