Scalable queue

Abstract

An extensible queue is disclosed. The network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to send packets to and receive packets from the network. The queue management circuitry is configured to: store a queue in memory for queuing data related to packet processing, the queue including a main buffer and an overflow buffer; select between a normal mode and an overflow mode based on defined conditions; queue data only in the main buffer when operating in normal mode; and queue data in concatenation of the main buffer and the overflow buffer when operating in overflow mode.

Description

Technical Field

[0001] This invention relates generally to computer systems, and more particularly to methods and systems for managing circular buffers in computer systems. Background Technology

[0002] Computer systems frequently use queues for communication between processes. Queues can be implemented as circular memory buffers.

[0003] U.S. Patent 5,873,089 describes a data processing system in which a circular queue formed in a paged memory is used to buffer data item transfers between producer and consumer entities. The producer entity maintains a tail pointer in the queue to indicate the next memory location to be written; similarly, the consumer entity maintains a head pointer to indicate the next memory location to be read. Since the head and tail pointers can point to different memory pages that may not yet have been assigned to the circular queue in a contiguous block, deriving queue state information using the head and tail pointers is complex. To simplify this task, the producer and consumer entities maintain producer and consumer indices for the next write and read locations based on a logical view of the queue as a circular contiguous block of memory locations.

[0004] PCT International Publication WO 1998 / 036534 describes a separate queue architecture and a method for queuing entries into a three-part queue. The first part of the queue is the write side, where entries are received. The second part of the queue is the read side, from which entries leave the queue after flowing through it. Entries typically flow from the write side to the read side. When the read side no longer has the capacity to receive more entries from the write side, an overflow area located off-chip in external memory forms part of the queue as needed to store entries from the write side. When the read side regains the capacity to accept more entries, the overflow area transfers its entries to the read side. Summary of the Invention

[0005] The embodiments of the invention described herein provide a network device including packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to send packets to and receive packets from the network. The queue management circuitry is configured to: store a queue in memory for queuing data related to packet processing; the queue includes a main buffer and an overflow buffer; select between a normal mode and an overflow mode based on defined conditions; queue data only in the main buffer when operating in normal mode; and queue data in a concatenation of the main buffer and the overflow buffer when operating in overflow mode.

[0006] In some embodiments, the queue is a circular queue, and the queue management circuitry is configured to: queuing data cyclically in the main buffer when operating in normal mode; and queuing data cyclically in a concatenation of the main buffer and the overflow buffer when operating in overflow mode.

[0007] In some embodiments, the queue management circuitry is configured to use zero-copy storage to queue data in both normal and overflow modes. In another embodiment, the queue management circuitry is configured to select between normal and overflow modes in response to a fill measurement of the main buffer.

[0008] In some embodiments, when transitioning from normal mode to overflow mode, the queue management circuitry is configured to insert an overflow transition flag after the most recently written data unit in the queue, the overflow transition flag indicating that the next data unit will be accessed in the overflow buffer. In embodiments, the queue management circuitry is configured to maintain a write pointer pointing to the location where the next data unit will be written, including advancing the write pointer from the main buffer to the overflow buffer upon encountering an overflow transition flag. In the disclosed embodiments, the queue management circuitry is configured to maintain a read pointer pointing to the location from which the next data unit will be read, including advancing the read pointer from the main buffer to the overflow buffer upon encountering an overflow transition flag.

[0009] In another embodiment, the network device further includes a cache for caching at least some of the queued data, wherein the cache capacity is at least as large as the main buffer, but smaller than the concatenation of the main buffer and the overflow buffer. In some embodiments, the queue is an ingress queue for queuing packets received from the network. In other embodiments, the queue is an egress queue for queuing packets to be sent to the network.

[0010] According to embodiments of the present invention, a method is also provided, comprising: sending packets to a network and receiving packets from a network in a network device. A queue, including a main buffer and an overflow buffer, is stored in memory for queuing data related to packet processing within the network device. The queue is selected between a normal mode and an overflow mode based on defined conditions. When operating in normal mode, data is queued only in the main buffer. When operating in overflow mode, data is queued in a concatenation of the main buffer and the overflow buffer. Attached Figure Description

[0011] Figure 1 This is a block diagram schematically depicting a network device (ND) according to an embodiment of the present invention;

[0012] Figure 2AThis is a schematic diagram illustrating the operation mode of the main buffer (PB) and overflow buffer (OFB) in shallow mode according to an embodiment of the present invention;

[0013] Figure 2B This is a schematic diagram illustrating the operation mode of overflow detection according to an embodiment of the present invention;

[0014] Figure 2C This is a schematic diagram illustrating the operation mode of PB and OFB in deep mode according to an embodiment of the present invention;

[0015] Figure 2D This schematically illustrates an operational mode diagram of the return to shallow mode conditions according to an embodiment of the present invention; and

[0016] Figure 3 This is a flowchart illustrating a method for managing a variable-size circular buffer according to an embodiment of the present invention. Detailed Implementation

[0017] Overview

[0018] Computer systems typically use queues for communication between processes, where, for example, the first process writes data to the queue and the second process reads the data.

[0019] Typically, queues are implemented as buffers; the first process writes to the buffer at the position pointed to by the write pointer, while the second process reads from the buffer at the position pointed to by the read pointer. Read and write operations are accompanied by the incrementing of the write / read pointer, which, after reaching the end of the buffer, circles back to the beginning of the buffer (i.e., the buffer is circular).

[0020] In the following text, we will refer to the process that writes data to the queue as the producer and the process that reads data as the consumer. Therefore, we sometimes call the write pointer the producer index (PI) and the read pointer the consumer index (CI).

[0021] On average, the rate at which consumers read data from the queue should match the rate at which producers write data; when the average read rate is higher than the write rate, the queue will be empty and consumer reads will fail; when the average write rate is higher than the read rate, the queue will be full and further writes will fail.

[0022] However, data bursts may occur, where large amounts of data are written to (or read from) a queue at a rate higher than average within a short period of time. For example, a network device (ND) may include a packet processing circuit (PPC) and a processor that communicates packets over the network; the PPC may be configured to publish incoming packets to a queue, and the processor may be configured to read from the queue and process packets. Shortly after arrival, the data rate of packets processed by the processor may be low for most of the time (e.g., due to low packet rates and / or small packet sizes); therefore, the queue size is small (or empty) most of the time. However, occasionally, the PPC may receive data bursts (e.g., longer packets and / or higher packet rates), causing the queue size to grow sharply within a short period. Furthermore, the queue emptying rate may also change, for example, due to variations in processor availability.

[0023] To avoid data loss, queues should be designed to accommodate the maximum expected size, such as when receiving the largest data burst (in some real-world scenarios, the maximum size corresponds to a burst or a set of bursts that coincides with the time period when the CPU is busy with higher-priority tasks and cannot process incoming packets). Therefore, when the queue is a circular buffer, the buffer size is preferably greater than or equal to the maximum expected data volume.

[0024] Most of the time, the read pointer will closely follow the write pointer (the difference between the write pointer and the read pointer is the queue size). Occasionally, such as when a burst of data arrives, the distance between the write queue and the read queue increases, and then gradually decreases as the producer's write rate decreases.

[0025] In some embodiments, the processor includes one or more cache memories configured to store the contents of frequently accessed locations in memory. Cache memories are typically fast but relatively small. When using a circular buffer large enough to accommodate data bursts as a queue, the buffer size can exceed the size of the cache memory, and therefore, queued data cannot be cached efficiently. This is also true for data bursts, but also for small groups, because the write pointer and read pointer, while closely following each other, span the entire depth of the circular buffer.

[0026] In other words, consider a large circular queue that is written to and read from at roughly the same rate. Even if the queue is relatively empty at any given time, the read and write pointers "crawl" across the entire circular queue and thus across a wide range of addresses. Since cache memory is accessed by address, the large queue degrades cache performance (increasing the likelihood of "cache misses") regardless of the actual fill level of the queue.

[0027] According to embodiments of the present invention, apparatus and methods are provided for resizing a buffer (typically a circular buffer), wherein the span between the read and write pointers is small when the queue size is small, and the span is large when the queue size increases. Therefore, the performance of caching data in the queue is greatly enhanced.

[0028] In this context, the terms "buffer" and "queue" are used interchangeably, as are the terms "circular buffer" and "circular queue." The embodiments described herein relate primarily to circular queues, but the disclosed techniques are similarly applicable to other types of queues and buffers, which are not necessarily circular.

[0029] In this embodiment, the circular buffer includes a primary buffer (PB), a secondary buffer (SB) (also known as an overflow buffer - OFB), and a queue management circuit (QMC) configured to control writes to and reads from the PB and OFB. The PB is large enough to store an average number of packets, assuming these packets are suitable for a cache memory. When the packets are small, the QMC operates the queue in shallow mode, where only the PB is used, allowing for efficient cache operations. As the queue size increases, the QMC enters deep mode, where the OFB is cascaded onto the PB, forming a large circular buffer. This reduces cache efficiency, but no data loss occurs. When the queue size decreases again, the QMC gradually reverts to the shallow mode, using only the PB. The QMC typically switches seamlessly between the two modes without data loss.

[0030] System Description

[0031] In the following description of the embodiments, we will primarily refer to network devices (ND); however, embodiments of the invention are not limited to network devices and may include many other applications. Some examples include wireless communication, video processing, graphics processing, and distributed computing.

[0032] In the embodiments described below, we will refer to a circular buffer with two operating modes: a shallow mode, in which a relatively small main buffer is used; and a deep mode, in which a secondary buffer (“overflow buffer”) is appended to the main buffer. The shallow mode and the deep mode are also referred to herein as “normal mode” and “overflow mode”, respectively.

[0033] Figure 1 This is a block diagram schematically illustrating a network device (ND) 102 according to an embodiment of the present invention. ND 102 may include, for example, a network adapter (such as an Ethernet interface controller (NIC) or an Infiniband host channel adapter (HCA)), a data processing unit (DPU – sometimes also called a “smart NIC”), a network switch or router, a network-enabled graphics processing unit (GPU), or any other suitable type of network device.

[0034] ND 102 includes a central processing unit (CPU) 104 (also referred to as a “processor”) configured to communicate packets over a communication network 108 via a packet processor 106 (also referred to as a “packet processing circuit”).

[0035] according to Figure 1 In the example embodiment shown, the CPU communicates packets to the packet processor via memory 107, which includes buffers for temporarily storing inbound and outbound packets. The CPU 104 can write outbound packets into an outbound queue buffer 110, which the packet processor then forwards to the network. The following description focuses on the inbound direction, and the outbound direction will not be discussed in detail. However, the disclosed techniques are not limited to inbound queues and are equally applicable to outbound queues and other suitable queue types.

[0036] In the ingress direction, as determined by the queue management circuitry (QMC) 118, the packet processor writes the received packet into either the primary buffer 114 or the secondary buffer 116. The QMC 118 includes a write pointer pointing to a location in the primary buffer 114 or secondary buffer 116 where the next data item will be written in a buffer-write operation. Similarly, the QMC includes a read pointer pointing to a location in the primary or secondary buffer where the next buffer-read operation will occur. In this example, both the primary buffer 114 and the secondary buffer 116 reside in memory 107, and the locations pointed to by the write and read pointers are addresses within memory 107.

[0037] According to an embodiment, when the main buffer 114 is large enough to contain queued data, the QMC 118 is in "shallow mode," directing only buffer read and write operations to the main buffer and performing wrap-around only within the main buffer. When the packet processor receives a data burst and there is no space in the main buffer for the burst, the QMC enters "deep mode," in which data is written to the network port and the CPU reads data from the concatenation of the main and secondary buffers. In shallow mode, the write and read pointers point only to positions in the main buffer. In deep mode, the pointers can point to positions in either the main or secondary buffer, and wrap-around is performed across the concatenation of the main and secondary buffers.

[0038] Network device 102 also includes a cache memory 120 coupled to CPU 104. The cache memory is configured to store frequently accessed memory locations of memory 107. When the QMC is in deep mode, write and read pointers traverse (“crawl”) beyond the cache capacity, resulting in low cache efficiency. However, most of the time the QMC is in shallow mode; write and read pointers only traverse the depth of the main buffer, which in this embodiment fits perfectly in the cache; therefore, the entire queue will remain in the cache (e.g., will not be written to the main buffer), and cache efficiency will increase. In other words, the cache capacity is chosen to be at least as large as the main buffer, but smaller than the concatenation of the main buffer and the secondary (overflow) buffer.

[0039] Therefore, according to Figure 1 The exemplary embodiment shown allows for efficient data caching by dividing the data into a primary buffer active in shallow mode and a secondary buffer added in the rare case of deep mode when most packets are short, where complete packets can fit into the cache.

[0040] It should be understood that, Figure 1 The configuration of ND 102, including packet processor 106, main buffer 114, secondary buffer 116, and QMC 118, shown and described above, is an example configuration depicted purely for conceptual clarity. Other suitable configurations may be used in alternative embodiments of the invention.

[0041] For example, the auxiliary buffer 116 may be in external memory coupled to the packet processor and CPU (e.g., a peripheral memory card accessed via a high-speed peripheral component interconnect - PCIe bus). In embodiments, a shallow mode for short packets, a medium-deep mode for medium-sized packets, and a deep mode for large packets may exist, and the ingress queue may include a main buffer for short packets, an auxiliary buffer for medium-sized packets, and a three-level buffer for large packets (more levels may be used in other embodiments). In embodiments, there may be more than one CPU; in other embodiments, CPU 104 may be a graphics processing unit (GPU).

[0042] In various embodiments, the disclosed technique can be implemented for the exit buffer, which is divided into a main buffer and an auxiliary buffer controlled by queue management circuitry. In some embodiments, the technique is implemented for both the exit queue and the entry queue.

[0043] Figure 2AThis diagram schematically illustrates the operation mode of PB 202 and OFB 204 in shallow mode according to an embodiment of the present invention. The write pointer (WP) 206 points to a write location in PB and increments during each write cycle, wrapping back to the first address after reaching the last address of PB 202. Similarly, the read pointer (RP) 208 points to a read location in PB and increments when a read occurs, wrapping back to the first address after reaching the last address. OFB is not used, and the maximum size of the queue is equal to the depth of PB 202, which in this embodiment is suitable for use in cache memory 120 (…). Figure 1 )middle.

[0044] Figure 2B This diagram schematically illustrates the operational mode of overflow detection according to an embodiment of the present invention. Although in shallow mode, the producer process needs to write data to the circular buffer, the read and write pointers are equal, and new data can overwrite old data in the PB that the consumer process has not yet read. This situation, which may occur in response to a data burst, is called overflow detection. Figure 2B In the example embodiment shown, the producer writes data to the first address of OFB 204 in response to an overflow detection, and sets WP 206 to point to the first address of OFB 204. In some embodiments, the producer adds a marker to the data at the last WP position in PB, thereby indicating to the consumer that the next address to read after reaching this position is the first address of OFB 204. The buffer now enters deep mode.

[0045] Figure 2C This schematically illustrates the operation mode diagram of PB 202 and OFB 204 in deep mode according to an embodiment of the present invention. PB 202 and OFB 204 are now concatenated to form a large circular buffer. WP 206 and RP 208 increment from the last address of PB 202 to the first address of OFB 204, and wrap around to the first address of PB 202 upon reaching the last address of OFB 204. The concatenated buffer contains large bursts of data without data loss; however, cache 116 ( Figure 1 It cannot accommodate a larger address space, and the cache performance is reduced.

[0046] Figure 2DThis diagram schematically illustrates the operational mode of returning to shallow mode according to an embodiment of the invention. PB and OFB are in deep mode, but the data burst ends and the queue narrows. At some point, WP 206 points to a position in PB 202, and RP 204 wraps around to the first position in PB 202 (after reading from the last address of OFB 204). The queue size is now small enough to be handled by PB, and the buffer can re-enter narrow mode.

[0047] according to Figure 2D In the example embodiment shown, when the queue narrows, both WP 206 and RP 204 point to PB 202 before re-entering shallow mode; if the queue narrows while WP points to a location in OFB, deep mode remains active until both WP and RP point to PB. In some embodiments, this condition is not required—if the queue narrows while the write pointer points to OFB, shallow mode can be entered immediately by setting WP 206 to the first address of PB 202 and optionally marking that address in OFB, such that when RP reaches that location, RP will wrap around to the first address of PB.

[0048] Therefore, QMC manages the write pointer and the read pointer; in shallow mode, the queue is contained in the main buffer, and in the deep mode described in this paper, the queue is contained in a concatenation of the main buffer and the overflow buffer, where there is seamless switching between modes.

[0049] As can be understood from the above description, in some embodiments, the QMC 118 uses full “zero-copy” storage to queue data. The term “zero-copy” means that queued data does not flow along the queue to be available at the output. Instead, read and write pointers move to point to the appropriate read and write positions. In some embodiments, zero-copy storage is used in shallow and deep modes and during transitions between them.

[0050] It should be understood that Figures 2A to 2D The operation mode diagram shown is an example operation mode referenced by way of example. Other operation modes may be used in alternative embodiments. For example, in some embodiments, the QMC is configured to support overflow in deep mode, for example, by overwriting the entry data.

[0051] Figure 3 This is a flowchart 300 schematically illustrating a method for a variable-size circular buffer according to an embodiment of the present invention. The process is based on QMC 118 (…). Figure 1 )implement.

[0052] The process begins with a Get New Entry step 302, where the QMC indicates that a new data entry is to be written to the queue. Then, in a Check Mode step 304, the QMC checks if the current mode is shallow. If so, the QMC proceeds to a Check-PB-Full step 306, and checks if the PB is full (e.g., the address (WP) used to write data to the PB is equal to the next read address (RP)). If so, the QMC proceeds to a Write-OFB-0 step 308, directing the data entry to the first address of the OFB buffer, and then enters deep mode in a Enter-Deep-Mode step 310.

[0053] In step 306, if the buffer is not full, the QMC proceeds to the Write-in-PB step 312, where the QMC directs the data entry to the next PB address, and then WP increments, wrapping back to the first PB address if the last address has been reached.

[0054] In step 304, if the QMC is in deep mode, the QMC proceeds to the Check-WP-Buffer step 314 and checks if WP points to an address in the OFB. If so, the QMC proceeds to the Write-OFB step 316, directing the data entry to the location pointed to by WP (in the OFB) and incrementing WP (if the end of the OFB is reached, it wraps back to the first address of PB).

[0055] In step 314, if WP points to a location in PB, then QMC proceeds to the Check-RP-in-PB step 318; if RP does not point to PB, then QMC proceeds to the Write-in-PB step 320, where QMC directs the data entry to the location pointed to by WP, and then increments WP from the last PB address to the first OFB address.

[0056] In step 318, if both WP and RP point to PB, the queue has shrunk and can enter shallow mode. QMC proceeds to write to PB step 322, where QMC routes the data entry to the next PB address, and then WP increments, wrapping back to the first PB address if the last address has been reached. QMC then enters shallow mode in step 324, which is the Enter Shallow-Mode step.

[0057] The flowchart ends after steps 310, 312, 316, 320, and 324.

[0058] It should be understood that Figure 3 The flowcharts shown and described above are exemplary embodiments referenced by way of example. Other flowcharts may be used in alternative embodiments. For example, in some embodiments, deep mode may be exited when the queue narrows and when WP points to OFB. In other embodiments, some of the steps described above may be performed in a different order and / or simultaneously.

[0059] Determine the next RP value

[0060] In the above discussion, we described in detail how WP is incremented, the length spanned across PB in shallow mode, and the length spanned across the combined PB-OFB in deep mode. RP is incremented in a similar manner, except that after entering deep mode, RP should continue reading entries from PB until RP reaches the point where PB is filled, at which point QMC sets WP to the first OFB address (we will refer to the value of WP when entering deep mode as the jump address).

[0061] In an embodiment, when the QMC enters deep mode, the QMC writes an indication associated with a jump address into the PB. In some embodiments, the PB includes an additional jump field (e.g., bits) in each entry that indicates the jump address; when the RP reads an entry with the jump field set, the QMC sets the RP to the first OFB address.

[0062] In other embodiments, the jump address (and sometimes a deep mode indicator) is stored in a dedicated register in the QMC; the register is updated accordingly when entering deep mode and cleared when entering shallow mode. The QMC is configured to set RP to the first address of OFB when RP reaches the address indicated in the register.

[0063] In other embodiments, instead of using flags, an RP pattern is defined, which can be shallow or deep, and responds to queue reads:

[0064] i) If the RP mode is shallow and WP points to OFB, then QMC sets RP to the first OFB address and sets the RP mode to deep.

[0065] ii) If both RP and WP point to addresses in PB, then QMC sets RP mode to shallow mode;

[0066] iii) Otherwise, RP increments; if RP is in shallow mode, it wraps around from the last PB address to the first PB address; if RP is in deep mode, it jumps from the last PB address to the first OFB address and from the last OFB address to the first PB address.

[0067] In the embodiment where WP points to a position in OFB, shallow mode can be entered (as described above), with necessary modifications, and the techniques described above for determining the next RP value can also be used.

[0068] exist Figures 1 to 3 The configuration of ND 102 shown and described above includes packet processor 106, main buffer 114, secondary buffer 116, and queue management circuitry 118; the operating modes of the main and secondary buffers and flowchart 300 are illustrated as example configurations, operating modes, and flowcharts purely for conceptual clarity. Any other suitable configuration, operating mode, and flowchart may be used in alternative embodiments. ND 102 may be replaced by any other suitable computing device that communicates with external devices using one or more queues. The different sub-units of ND 102 may be implemented using suitable hardware (such as in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), using software, using hardware, or using a combination of hardware and software elements.

[0069] CPU 104 ( Figure 1 The processor may include a general-purpose processor that is software-programmed to perform the functions described herein. For example, the software may be downloaded to the processor electronically via a network or from a host, or alternatively or additionally, the software may be provided and / or stored on a non-transitory tangible medium, such as magnetic memory, optical memory, or electronic memory.

[0070] While the embodiments described herein primarily address scalable queues in computing systems, the methods and systems described herein can also be used in other applications, such as communication and delivery systems.

[0071] Therefore, it should be understood that the above embodiments are cited by way of example, and the invention is not limited to what is specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications thereof that would occur to those skilled in the art upon reading the above description and which are not disclosed in the prior art. Except to the extent that any terms are defined in these incorporated documents in a manner that conflicts with the definitions expressly or implicitly made in this specification, references to documents incorporated in this patent application shall be considered an integral part of this application, and the definitions in this specification shall be considered only.

Claims

1. A network device, comprising: Packet processing circuitry configured to send packets to the network and receive packets from the network; as well as The queue management circuit is configured as follows: A queue for queuing data related to the processing of the group is stored in memory, the queue including a main buffer and an overflow buffer; Maintain a write pointer pointing to the next position to be written in the queue and a read pointer pointing to the next position to be read in the queue; The system selects between normal mode and overflow mode based on defined conditions. When operating in the normal mode, the queue is set to include only the main buffer, and the data is queued in the queue by restricting the write pointer and the read pointer to increment only in the main buffer; as well as When operating in the overflow mode, the queue is configured to include concatenation of the main buffer and the overflow buffer, and the data is queued in the queue by allowing the write pointer and the read pointer to increment on both the main buffer and the overflow buffer.

2. The network device of claim 1, wherein the queue is a circular queue, and wherein the queue management circuitry is configured to: restrict the write pointer and the read pointer to increment cyclically only in the main buffer when operating in the normal mode; and allow the write pointer and the read pointer to increment cyclically in both the main buffer and the overflow buffer when operating in the overflow mode.

3. The network device of claim 1, wherein the queue management circuit is configured to queue the data using zero-copy storage in both the normal mode and the overflow mode.

4. The network device of claim 1, wherein the queue management circuitry is configured to select between the normal mode and the overflow mode in response to a fill measurement of the main buffer.

5. The network device of claim 1, wherein when transitioning from the normal mode to the overflow mode, the queue management circuitry is configured to insert an overflow transition flag after the most recently written data unit in the queue, the overflow transition flag indicating that the next data unit will be accessed in the overflow buffer.

6. The network device of claim 5, wherein the queue management circuitry is configured to advance the write pointer from the main buffer to the overflow buffer upon encountering the overflow transition flag.

7. The network device of claim 5, wherein the queue management circuitry is configured to advance the read pointer from the main buffer to the overflow buffer upon encountering the overflow transition flag.

8. The network device of claim 1, further comprising a cache for caching at least some of the queued data, wherein the capacity of the cache is at least as large as the main buffer, but smaller than the concatenation of the main buffer and the overflow buffer.

9. The network device of claim 1, wherein the queue is an ingress queue for queuing packets received from the network.

10. The network device of claim 1, wherein the queue is an exit queue for queuing packets to be sent to the network.

11. A method for managing a circular buffer, comprising: In network devices, packets are sent to the network and received from the network; A queue for queuing data related to the processing of the packets in the network device is stored in memory, the queue including a main buffer and an overflow buffer; Maintain a write pointer pointing to the next position to be written in the queue and a read pointer pointing to the next position to be read in the queue; Based on the defined conditions, the queue is selected between normal mode and overflow mode; When operating in the normal mode, the queue is set to include only the main buffer, and the data is queued in the queue by restricting the write pointer and the read pointer to increment only in the main buffer; as well as When operating in the overflow mode, the queue is configured to include concatenation of the main buffer and the overflow buffer, and the data is queued in the queue by allowing the write pointer and the read pointer to increment on both the main buffer and the overflow buffer.

12. The method of claim 11, wherein the queue is a circular queue, and wherein queuing the data comprises: When operating in the normal mode, the write pointer and the read pointer are restricted to incrementing only cyclically in the main buffer; And when operating in the overflow mode, the write pointer and the read pointer are allowed to increment cyclically on both the main buffer and the overflow buffer.

13. The method of claim 11, wherein zero-copy storage is used to queue the data in both the normal mode and the overflow mode.

14. The method of claim 11, wherein in response to a fill measurement of the main buffer, selection is performed between the normal mode and the overflow mode.

15. The method of claim 11, further comprising: When transitioning from the normal mode to the overflow mode, an overflow transition flag is inserted after the most recently written data unit in the queue, the overflow transition flag indicating that the next data unit will be accessed in the overflow buffer.

16. The method of claim 15, wherein queuing the data comprises: When the overflow transition flag is encountered, the write pointer is advanced from the main buffer to the overflow buffer.

17. The method of claim 15, wherein queuing the data comprises: When the overflow transition flag is encountered, the read pointer is advanced from the main buffer to the overflow buffer.

18. The method of claim 11, further comprising: At least some of the queued data is cached in a cache, wherein the capacity of the cache is at least as large as the main buffer, but smaller than the concatenation of the main buffer and the overflow buffer.

19. The method of claim 11, wherein the queue is an ingress queue for queuing packets received from the network.

20. The method of claim 11, wherein the queue is an exit queue for queuing packets to be sent to the network.

21. A network device, comprising: Packet processing circuitry configured to send packets to the network and receive packets from the network; as well as The queue management circuit is configured as follows: A queue for queuing data related to the processing of the group is stored in memory, the queue including a main buffer and an overflow buffer; The system selects between normal mode and overflow mode based on defined conditions. When operating in the normal mode, the data is queued only in the main buffer; When operating in the overflow mode, the data is queued in the concatenation of the main buffer and the overflow buffer; as well as When transitioning from the normal mode to the overflow mode, an overflow transition flag is inserted after the most recently written data unit in the queue, the overflow transition flag indicating that the next data unit will be accessed in the overflow buffer.

22. A method for managing a circular buffer, comprising: In network devices, packets are sent to the network and received from the network; A queue for queuing data related to the processing of the packets in the network device is stored in memory, the queue including a main buffer and an overflow buffer; Based on the defined conditions, the queue is selected between normal mode and overflow mode; When operating in the normal mode, the data is queued only in the main buffer; When operating in the overflow mode, the data is queued in the concatenation of the main buffer and the overflow buffer; as well as When transitioning from the normal mode to the overflow mode, an overflow transition flag is inserted after the most recently written data unit in the queue, the overflow transition flag indicating that the next data unit will be accessed in the overflow buffer.

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