System for setting operating frequency of random access memory and operating method thereof

Abstract

Embodiments of the present disclosure relate to a system for setting an operating frequency of a random access memory and a method of operating the system. Based on some embodiments of the disclosed technology, the system can include a random access memory configured to include memory cells for storing data, a cache memory configured to cache at least a portion of the data, and a processor in communication with the random access memory and the cache memory to access at least a portion of the data from the random access memory or the cache memory. The system can determine a cache hit rate of the cache memory, and can set the operating frequency of the random access memory based on the cache hit rate.

Description

[0001] Cross-reference to related applications

[0002] This document claims priority and benefit to Korean patent application No. 10-2021-0092009, filed on July 14, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed embodiments relate to a system for setting the operating frequency of a random access memory based on cache hit rate and a method for operating the system. Background Technology

[0004] Memory systems include data storage devices that store data based on requests from hosts such as computers, servers, smartphones, tablets, or other devices. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory (UFS) devices, or embedded MMC (eMMC) devices.

[0005] A system is an interconnection of devices that perform specific operations. Such a system may include a memory device that stores data based on requests from a host computer, a mobile terminal (e.g., a smartphone or tablet), or various other devices. The system may store data in a disk (e.g., a hard disk drive (HDD)) or a semiconductor memory device such as volatile or non-volatile memory (e.g., a solid-state drive (SSD), a universal flash memory (UFS) device, or an embedded MMC (eMMC) device).

[0006] When performing logical operations and controlling various operations associated with the device, the system can store data in internal or external random access memory devices and access these random access memory devices to read the data. Summary of the Invention

[0007] The technology disclosed in this patent application can be implemented in various embodiments to provide a system and a method of operating the system that can minimize performance degradation while reducing the power consumption of a random access memory device.

[0008] In one aspect, embodiments of the present disclosure may provide a system comprising: a random access memory configured to include memory cells for storing data; a cache memory configured to cache at least a portion of the data; and a processor communicating with the random access memory and the cache memory to access at least a portion of the data in the random access memory or the cache memory.

[0009] The processor can determine the cache hit rate of the cache memory and set the random access memory operation frequency based on the cache hit rate.

[0010] For example, the system can determine the size of the data in the random access memory based on 1) the size of the data accessed by the processor in the random access memory or cache memory, and 2) the cache hit rate of the cache memory.

[0011] In addition, the system can set the operating frequency of the random access memory based on the size of the data accessed by the processor in the random access memory.

[0012] In another aspect, embodiments of this disclosure may provide a method of operating a system.

[0013] The system's operating method may include determining the cache hit rate of a cache memory configured to cache at least a portion of data to be stored in random access memory.

[0014] The system's operation method may include setting the random access memory operation frequency based on the cache hit rate of the cache memory.

[0015] As an example, setting the operating frequency of random access memory based on the cache hit rate of the cache memory can include determining the size of the data accessed in the random access memory based on 1) the size of the data accessed in the random access memory or the cache memory and (2) the cache hit rate of the cache memory.

[0016] In addition, setting the operating frequency of random access memory based on the cache hit rate of the cache memory can also be based on the size of the data accessed in the random access memory.

[0017] According to embodiments of this disclosure, the power consumption of random access memory can be reduced while minimizing performance degradation. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the configuration of a memory system based on an embodiment of the disclosed technology.

[0019] Figure 2 This is a block diagram schematically illustrating a memory device based on an embodiment of the disclosed technology.

[0020] Figure 3 The structure of word lines and bit lines of a memory device based on an embodiment of the disclosed technology is shown.

[0021] Figure 4Example configurations of systems based on some embodiments of the disclosed technology are shown.

[0022] Figure 5 This is a flowchart illustrating example operation of a system based on some embodiments of the disclosed technology.

[0023] Figure 6 An example method is shown for determining the cache hit rate of a cache based on some embodiments of the disclosed technology.

[0024] Figure 7 This is a flowchart illustrating an example of how a system based on some embodiments of the disclosed technology sets the operating frequency of a random access memory.

[0025] Figure 8 Example configurations of caches based on some embodiments of the disclosed technology are shown.

[0026] Figure 9 It shows about Figure 8 The flowchart illustrates an example of the operation described in the document to determine whether a cache hit has occurred.

[0027] Figure 10 An example method for setting the operating frequency of a random access memory based on some embodiments of the disclosed technology is shown.

[0028] Figure 11 Showing data size period and Figure 10 Examples of the relationship between the frequency of operations corresponding to data size segments are described in the text.

[0029] Figure 12 Show data size ranges and Figure 10 Another example of the relationship between the frequency of operations corresponding to data size segments, as described in the text.

[0030] Figure 13 The present invention illustrates a method of operating a system based on some embodiments of the disclosed technology.

[0031] Figure 14 Example configurations of computing systems based on some embodiments of the disclosed technology are shown. Detailed Implementation

[0032] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., are not necessarily limited to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. The term "embodiment" as used herein does not necessarily refer to all embodiments.

[0033] Various embodiments of the technology disclosed in this disclosure are described in more detail below with reference to the accompanying drawings. However, it should be noted that the disclosed technology can be implemented in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided as examples and variations of the disclosed embodiments, and other embodiments can be made based on the disclosure. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the invention.

[0034] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0035] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0036] Figure 1 This is a diagram illustrating a schematic configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0037] In some embodiments, memory system 100 may include memory device 110 configured to store data and memory controller 120 configured to control operations performed by memory device 110.

[0038] Memory device 110 may include multiple memory blocks, each memory block including multiple memory cells for storing data. Memory device 110 may be configured to operate in response to control signals received from memory controller 120. Operation of memory device 110 may include, for example, read operations, programming operations (also referred to as "write operations"), and erase operations.

[0039] The memory cells in memory device 110 are used to store data and can be arranged in an array of memory cells. The array of memory cells can be divided into blocks of memory cells, and each block includes pages of different memory cells. In a typical implementation of a NAND flash memory device, a page of a memory cell is the smallest unit of memory that can be programmed or written, and the data stored in a memory cell can be erased at the block level.

[0040] In some implementations, the memory device 110 can be implemented as various types, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM).

[0041] The memory device 110 can be implemented in a three-dimensional array structure. Some embodiments of the disclosed technology can be applied to any type of flash memory device having a charge storage layer. In one embodiment, the charge storage layer can be formed of a conductive material, and such a charge storage layer can be referred to as a floating gate. In another embodiment, the charge storage layer can be formed of an insulating material, and such a flash memory device can be referred to as charge-fetch flash (CTF).

[0042] The memory device 110 can be configured to receive commands and addresses from the memory controller 120 to access a region of the memory cell array selected using that address. In other words, the memory device 110 can perform operations on a memory region of the memory device corresponding to the received commands, the memory region having a physical address corresponding to the address received from the memory controller 120.

[0043] In some implementations, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to the region selected by the address. During a reading operation, the memory device 110 can read data from the memory region selected by the address. During an erasing operation, the memory device 110 can erase the data stored in the memory region selected by the address.

[0044] The memory controller 120 can control write operations (programming operations), read operations, erase operations, and background operations performed on the memory device 110. Background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0045] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs such background operation of the memory device, it can control the operation of the memory device 110 even without a request from the host.

[0046] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, the memory controller 120 and the host are discussed as separate devices by way of example.

[0047] Reference Figure 1 The memory controller 120 may include a memory interface 122, a control circuit 123, and a host interface 121.

[0048] Host interface 121 can be configured to provide an interface for communicating with a host.

[0049] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and perform operations to process the received command.

[0050] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120, so that the memory controller 120 can perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0051] The control circuit 123 can be configured to control the operation of the memory device 110 via the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126, etc.

[0052] Processor 124 can control all operations of memory controller 120. Processor 124 can perform logical operations. Processor 124 can communicate with host via host interface 121. Processor 124 can communicate with memory device 110 via memory interface 122.

[0053] Processor 124 can be used to perform operations associated with the Flash Translation Layer (FTL) to efficiently manage memory operations on memory system 100. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive an LBA and translate it into a PBA using a mapping table.

[0054] Based on the mapping unit, there are various address mapping methods that the FTL can use. Typical address mapping methods can include page mapping, block mapping, and hybrid mapping.

[0055] Processor 124 can be configured to randomize data received from the host to write the randomized data into the memory cell array. For example, processor 124 can randomize data received from the host by using a randomization seed. The randomized data is provided to memory device 110 and written into the memory cell array.

[0056] Processor 124 can be configured to derandomize data received from memory device 110 during a read operation. For example, processor 124 can derandomize data received from memory device 110 by using a derandomization seed. The derandomized data can then be output to the host.

[0057] The processor 124 can run firmware (FW) to control the operation of the memory controller 120. In other words, the processor 124 can control all operations of the memory controller 120, and in order to perform logical operations, it can run (drive) the firmware loaded into the working memory 125 during startup.

[0058] Firmware refers to a program or software stored on a non-volatile memory and running inside the memory system 100.

[0059] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of the following: a flash translation layer (FTL) configured to translate a logical address in a host request into a physical address of the memory device 110; a host interface layer (HIL) configured to interpret commands issued by the host to a data storage device such as the memory system 100 and pass the commands to the FTL; and a flash interface layer (FIL) configured to pass commands issued by the FTL to the memory device 110.

[0060] For example, firmware can be stored in memory device 110 and then loaded into working memory 125.

[0061] The working memory 125 may store firmware, program code, commands, or multiple data entries required to operate the memory controller 120. The working memory 125 may include at least one of, for example, static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memory.

[0062] Error detection / correction circuitry 126 can be configured to detect and correct one or more error bits in data using error detection and correction codes. In some embodiments, the error-detected and corrected data may include data stored in working memory 125 and data retrieved from memory device 110.

[0063] The error detection / correction circuit 126 can be implemented to decode data using an error correction code. The error detection / correction circuit 126 can be implemented using various decoding schemes. For example, a decoder that performs non-system code decoding or a decoder that performs system code decoding can be used.

[0064] In some implementations, the error detection / correction circuit 126 can detect one or more error bits based on sectors. That is, each read data entry can include multiple sectors. In this patent application, a sector can refer to a data unit smaller than a read unit (i.e., a page) of flash memory. The sectors constituting each read data entry can be mapped based on addresses.

[0065] In some implementations, the error detection / correction circuit 126 can calculate the bit error rate (BER) sector by sector and determine whether the number of erroneous bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable and mark the corresponding sector as "failed". If the BER is less than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable, or can mark the corresponding sector as "passed".

[0066] Error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data. When a sector in the read data is correctable, error detection / correction circuit 126 can proceed to the next sector to check if error correction is required for that sector. After completing error detection and correction operations on all read data in this way, error detection / correction circuit 126 can obtain information about which sector in the read data is considered uncorrectable. Error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to processor 124.

[0067] The memory system 100 may also include a bus 127 to provide a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transmitting various types of control signals and commands, and a data bus for transmitting various types of data.

[0068] As an example, Figure 1 The aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some of these constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 shown in the figures may be omitted, or some of these constituent elements may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0069] Figure 2 This is a block diagram schematically illustrating a memory device 110 based on an embodiment of the disclosed technology.

[0070] In some implementations, the memory device 110 based on the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0071] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0072] In multiple memory blocks BLK1 to BLKz, multiple word lines WL and multiple bit lines BL can be set by row and column, and multiple memory cells MC can be arranged.

[0073] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read / write circuit 230 via multiple bit lines BL.

[0074] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells are non-volatile memory cells. In some embodiments, such non-volatile memory cells may be arranged in a vertical channel configuration.

[0075] The memory cell array 210 can be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 210 can be arranged in a three-dimensional structure.

[0076] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array 210 can include a plurality of memory cells, each of which can be configured to store at least five bits of data per memory cell.

[0077] Reference Figure 2 The address decoder 220, read / write circuit 230, control logic 240, and voltage generation circuit 250 can operate as peripheral circuits configured to drive the memory cell array 210.

[0078] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0079] Address decoder 220 can be configured to operate in response to commands and control signals from control logic 240.

[0080] Address decoder 220 can receive addresses through input / output buffers within memory device 110. Address decoder 220 can be configured to decode block addresses within the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0081] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0082] During a read operation, address decoder 220 can apply a read voltage Vread to the selected word line WL inside the selected memory block and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0083] During the programming verification operation, the address decoder 220 can apply the verification voltage generated by the voltage generation circuit 250 to the selected word line WL inside the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0084] Address decoder 220 can be configured to decode the column address in a received address. Address decoder 220 can then transmit the decoded column address to read / write circuitry 230.

[0085] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0086] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read / write circuitry 230.

[0087] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0088] The read / write circuit 230 may include multiple page buffers PB. When the memory cell array 210 performs a read operation, the read / write circuit 230 can operate as a "read circuit", and when the memory cell array 210 performs a write operation, the read / write circuit 230 can operate as a "write circuit".

[0089] The aforementioned read / write circuit 230 is also referred to as a page buffer circuit including multiple page buffers PB, or a data register circuit. The read / write circuit 230 may include data buffers involved in data processing functions, and in some embodiments, may further include cache buffers for data caching.

[0090] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cell to detect changes in current proportional to the amount of current that varies according to the programming state of the corresponding memory cell at the sensing node, and the corresponding voltage can be stored or latched as sensing data.

[0091] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0092] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell, and this voltage value is read out as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include column select circuitry.

[0093] Control logic 240 can be connected to address decoder 220, read / write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory device 110.

[0094] Control logic 240 can be configured to control all operations of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals to adjust the voltage levels of the sensing nodes of multiple page buffers PB to precharge voltage levels.

[0095] Control logic 240 can control read / write circuit 230 to perform read operations in memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used during read operations in response to voltage generation circuit control signals output from control logic 240.

[0096] The memory block BLK included in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, and multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is coupled to one of the word lines WL, and each of the memory cell strings STR is coupled to one of the bit lines BL.

[0097] Within a storage block BLK, multiple word lines (WL) and multiple bit lines (BL) can be arranged in rows and columns. For example, each of the multiple word lines (WL) can be arranged along the row direction, and each of the multiple bit lines (BL) can be arranged along the column direction. As another example, each of the multiple word lines (WL) can be arranged along the column direction, and each of the multiple bit lines (BL) can be arranged along the row direction.

[0098] In some implementations, multiple word lines (WL) and multiple bit lines (BL) may intersect each other to address individual memory cells in an array of multiple memory cells (MC). In some implementations, each memory cell (MC) may include a transistor (TR) comprising a layer of material capable of storing charge.

[0099] For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of transistor TR may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of transistor TR may be connected directly or via another transistor TR to a source line (which may be ground). The gate of transistor TR may include a floating gate (FG) and a control gate (CG), wherein the floating gate is surrounded by an insulator, and a gate voltage is applied from word line WL to the control gate.

[0100] In each of the multiple memory blocks BLK1 to BLKz, the first select line (also referred to as the source select line or drain select line) may be additionally arranged outside the first outermost word line of the read / write circuit 230, and the second select line (also referred to as the drain select line or source select line) may be additionally arranged outside the other second outermost word line.

[0101] In some implementations, at least one additional dummy character line may be arranged between the first outermost character line and the first selection line. Additionally, at least one additional dummy character line may be arranged between the second outermost character line and the second selection line.

[0102] It can perform read and write operations on storage blocks one page at a time, and it can also perform erase operations on storage blocks one by one.

[0103] Figure 3 This is a diagram illustrating the structure of the word line WL and bit line BL of a memory device 110 based on an embodiment of the disclosed technology.

[0104] Reference Figure 3 The memory device 110 has a core region in which memory cells MC are arranged, and an auxiliary region (the remaining region other than the core region) including circuitry for performing operations of the memory cell array 210.

[0105] In the core region, a certain number of memory cells arranged in one direction can be called a "page" PG, and a certain number of memory cells coupled in series can be called a "memory cell string" STR.

[0106] Word lines WL1 to WL9 can be connected to row decoder 310. Bit line BL can be connected to column decoder 320. (Corresponding to...) Figure 2 The data register 330 of the read / write circuit 230 can exist between multiple bit lines BL and column decoder 320.

[0107] Multiple word lines WL1 to WL9 can correspond to multiple pages PG.

[0108] For example, each of the multiple word lines WL1 to WL9 can correspond to a page PG, such as Figure 3 As shown. When the size of each of the multiple word lines WL1 to WL9 is large, each of the multiple word lines WL1 to WL9 can correspond to at least two (e.g., two or four) pages PG. Each page PG is the smallest unit in programming and reading operations, and when programming and reading operations are performed, all memory cells MC within the same page PG can be operated on simultaneously.

[0109] Multiple bit lines BL can be connected to column decoder 320. In some implementations, the multiple bit lines BL can be divided into odd-numbered bit lines BL and even-numbered bit lines BL, such that a pair of odd-numbered bit lines and even-numbered bit lines are coupled together to column decoder 320.

[0110] When accessing a memory cell MC, the row decoder 310 and column decoder 320 can be used to locate the desired memory cell based on its address.

[0111] In some implementations, the data register 330 plays a crucial role because all data processing performed by the memory device 110, including programming and reading operations, occurs via the data register 330. If data processing by the data register 330 is delayed, all other areas must wait until the data register 330 has finished processing, which degrades the overall performance of the memory device 110.

[0112] Reference Figure 3 In the example shown, within a memory cell string STR, multiple transistors TR1 to TR9 can be connected to multiple word lines WL1 to WL9, respectively. In some embodiments, the multiple transistors TR1 to TR9 correspond to memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0113] Multiple word lines WL1 to WL9 include two outermost word lines, WL1 and WL9. A first select line DSL can be additionally positioned outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path compared to the other outermost word line WL9. A second select line SSL can additionally be positioned outside the other second outermost word line WL9.

[0114] The first selection transistor D-TR, controlled by the first selection line DSL to be turned on / off, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled by the second selection line SSL to be turned on / off, has a gate electrode connected to the second selection line SSL, but does not include a floating gate FG.

[0115] The first selection transistor D-TR serves as a switching circuit to connect the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR serves as a switching circuit to connect the corresponding memory cell string STR to the source line SL. In other words, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0116] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR to turn on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR to turn off the second selection transistor S-TR.

[0117] During a read or verify operation, the memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read or verify operation, current can flow through the corresponding memory cell string STR and to the source line SL corresponding to ground, allowing the voltage level of the bit line BL to be measured. However, during a read operation, there may be a time difference between the on / off timing of the first selection transistor D-TR and the second selection transistor S-TR.

[0118] During the erase operation, the memory system 100 can apply a predetermined voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, the memory system 100 applies a voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float. Therefore, the applied erase voltage can remove charge from the floating gate FG of the selected memory cell.

[0119] Figure 4 An example configuration of system 10 based on some embodiments of the disclosed technology is shown.

[0120] Reference Figure 4 System 10 (hereinafter referred to as the "system") may include random access memory 11, cache or cache memory 12, and processor 13 coupled to communicate with each other, such as Figure 4 The example is shown in the image.

[0121] Random access memory 11 can store data. In some embodiments, random access memory 11 can be used to store programs and data being used by processor 13. In one example, the data stored in random access memory 11 may include data loaded from a data storage device or another memory device (e.g., NAND flash memory, NOR flash memory, PRAM, MRAM, STT-RAM) located inside or outside system 10, or data created by processor 13 and / or used to perform logical operations.

[0122] In some implementations, cache 12 may cache a portion of data stored in random access memory 11. In one example, cache 12 may include memory (e.g., SRAM, TCM) that operates at a higher speed than random access memory 11 and has a smaller storage capacity. Additionally, system 10 may determine whether cached data in cache 12 has changed based on a dirty bit, thereby preventing potential data mismatches between cache 12 and random access memory 11. Here, the dirty bit may include a bit associated with a portion of cache 12 and indicating whether the corresponding portion of cache 12 has been modified.

[0123] In some implementations, the processor 13 may access a portion of the data stored in the random access memory 11 from the random access memory 11 or the cache 12.

[0124] As an example, when the data to be accessed is cached in cache 12 and successfully read from cache 12 (i.e., when a "cache hit" occurs), processor 13 can access the data from cache 12, such as... Figure 4 The marker in the text is "①". On the other hand, processor 13 may attempt to access specific data from cache 12, but that specific data is unavailable in cache 12 (i.e., when a "cache miss" occurs), such as... Figure 4 The marker in the text is "②". When such a cache miss occurs, the processor 13 can then access specific data from the random access memory 11.

[0125] System 10, based on some embodiments of the disclosed technology, can be implemented in various ways. As an example, system 10 can be implemented as a reference. Figure 1 The memory system 100 is described.

[0126] In some implementations, processor 13 may include references Figure 1 The processor 124 is described. The random access memory 11 may include references to... Figure 1The described working memory 125. The cache 12 may include a configuration arranged in reference... Figure 1 The volatile memory in the processor 124 or working memory 125 or any other memory device described.

[0127] In some implementations, the system 10 described above can operate as discussed below. As an example, the operation of the system 10 described below can be performed by the processor 13 or by separate arithmetic circuitry included in the system 10.

[0128] Figure 5 This illustrates some embodiments based on the disclosed technology. Figure 4 A flowchart of an example operation of System 10.

[0129] Reference Figure 5 The processor 13 of system 10 can determine the cache hit rate of cache 12 based on its operation of retrieving data from cache 12 (S510). In some embodiments, the cache hit rate may include a measure of how many content requests it can successfully deliver from its cache storage device compared to how many requests it receives.

[0130] In some implementations, at S520, the processor 13 of system 10 can set the operating frequency of random access memory 11 based on the cache hit rate of cache 12 determined at S510. The operating frequency of random access memory 11 can indicate the frequency of the clock fed into or input to random access memory 11.

[0131] In other words, the processor 13 of system 10 can dynamically update or change the operating frequency of random access memory 11 based on the cache hit rate of cache 12, instead of keeping the operating frequency of random access memory 11 at a fixed value.

[0132] As described below, system 10 can be configured to set the operating frequency of random access memory 11 based on the cache hit rate of cache 12 in specific cases as shown in the following specific examples.

[0133] In some implementations, the operating frequency of the random access memory 11 can be set to the operating frequency that supports the maximum performance of the random access memory 11, regardless of the frequency of use of the random access memory 11.

[0134] However, if the operating frequency of the random access memory 11 is fixed at the operating frequency that supports the maximum performance of the random access memory 11, the random access memory 11 may operate at a high operating frequency even if the processor 13 accesses the random access memory 11 at a very low frequency. In this case, it is difficult to maximize the performance of the random access memory 11 even at a high operating frequency.

[0135] On the other hand, the high operating frequency of the random access memory 11 during periods when it is not accessed by the processor 13 may unnecessarily increase the power consumption of the random access memory 11, since the operating frequency is one of the key factors determining power consumption.

[0136] The disclosed techniques can be implemented in some embodiments to determine the optimal value of the operating frequency of the random access memory 11 based on the frequency of access to the random access memory 11 by the processor 13.

[0137] The frequency of processor 13 accessing random access memory 11 can decrease as the frequency of processor 13 accessing cache 12 increases. When processor 13 can read data from cache 12, the performance of processor 13 can be improved because processor 13 can avoid accessing random access memory 11, which is slower than cache 12.

[0138] Therefore, systems implemented based on some embodiments of the disclosed technology can improve their performance by adjusting the operating frequency of random access memory 11 based on cache hit rate, thereby preventing unnecessary power consumption when the frequency of accessing random access memory 11 is low, where cache hit rate represents the frequency at which processor 13 accesses data in cache 12. Additionally, when the frequency of accessing random access memory 11 is high, processor 13 can increase the operating frequency of random access memory 11 to prevent potential performance degradation.

[0139] In some implementations, the cache hit rate of cache 12 is used to determine the operating frequency of random access memory 11, as will be discussed below.

[0140] Figure 6 An example method is shown for a system 10 to determine the cache hit rate of a cache 12 based on some embodiments of the disclosed technology.

[0141] In one implementation, system 10 can determine the cache hit rate based on the ratio of the size of data accessed by processor 13 in cache during a specific time period TP to the total size of data accessed by processor 13 in random access memory 11 or cache 12 during the specific time period TP. In another implementation, the cache hit rate can be determined based on the ratio of the number of requests processed by cache 12 to the total number of requests processed by random access memory 11 or cache 12.

[0142] Processor 13 may first check whether the requested data (the data to be accessed) is stored in cache 12. If the corresponding data is stored in cache 12, processor 13 may access cache 12 to read the data. If the corresponding data is not stored in cache 12, processor 13 may access random access memory 11 to read the data.

[0143] In some implementations, the total amount of data accessed by processor 13 from random access memory 11 or cache 12 during a specific time period TP can be referred to as the total bandwidth of the data accessed by processor 13.

[0144] exist Figure 6 In the context of the specific time period TP, the sizes of data accessed by the system 10 in the cache 12 are A, D, and E, and the sizes of data accessed by the system 10 in the random access memory 11 during the specific time period TP are B and C.

[0145] In this example, the cache hit rate of cache 12 can be (A+D+E) / (A+B+C+D+E), which is the ratio of the amount of data accessed from cache 12 (A+D+E) during a specific time period TP to the total amount of data accessed from random access memory 11 or cache 12 (A+B+C+D+E) during the specific time period TP.

[0146] As another example, when the amount of data accessed by system 10 from cache 12 each time is fixed, system 10 can determine the cache hit rate using the number of accesses to cache 12 and random access memory 11 during a specific time period TP. That is, system 10 can determine the cache hit rate of cache 12 based on the number of accesses to data in cache 12 during a specific time period TP and the total number of accesses to data in random access memory 11 or cache 12 during the specific time period TP.

[0147] As another example, system 10 can determine the cache hit rate of cache 12 based on the number of times data is accessed in cache 12 during a specific time period TP and the total number of times data is retrieved from cache 12 during the specific time period TP.

[0148] Figure 7 This is a flowchart illustrating an example of how a system 10, based on some embodiments of the disclosed technology, sets the operating frequency of a random access memory.

[0149] Reference Figure 7 System 10 can determine: (1) the size of the data accessed by processor 13 in random access memory 11 or cache 12; and (2) the cache hit rate of cache 12 (S710). In this example, the size of the data accessed by processor 13 in random access memory 11 or cache 12 can be the size of the data accessed by processor in random access memory 11 or cache 12 during a time period equal to a predetermined time period used to determine the cache hit rate of cache 12.

[0150] In addition, the system 10 may determine the size of the data accessed by the processor 13 in the random access memory 11 based on the following (S720): (1) the size of the data accessed by the processor 13 in the random access memory 11 or the cache 12 as determined in S710; and (2) the cache hit rate of the cache 12 as determined in S710.

[0151] As an example, the size of the data accessed by the processor 13 in cache 12 can be determined by the following product: (1) the size of the data accessed by the processor 13 in random access memory 11 or cache 12; and (2) the cache hit rate of cache 12. Alternatively, the size of the data accessed by the processor 13 in random access memory 11 can be obtained by subtracting the size of the data accessed by the processor 13 in cache 12 from the size of the data accessed by the processor 13 in random access memory 11 or cache 12.

[0152] System 10 can set the operating frequency of random access memory 11 based on the size of the data accessed by processor 13 in random access memory 11 (S730).

[0153] As discussed above, system 10 can set the operating frequency of random access memory 11 based on the cache hit rate of cache 12.

[0154] In some implementations, within a specific cache 12 structure, the operation of setting the operating frequency of the random access memory 11 will be described.

[0155] Figure 8 An example configuration of cache 12 based on some embodiments of the disclosed technology is shown.

[0156] Reference Figure 8Cache 12 may include L1 cache 21 and L2 cache 22. In this case, L1 cache 21 can operate at a higher speed than L2 cache 22 and can have a smaller storage capacity than L2 cache 22.

[0157] exist Figure 8 In the process, processor 13 can first search L1 cache 21 to determine whether the data to be accessed is stored in cache 12.

[0158] In the event of a cache hit in L1 cache 21, processor 13 can access the data stored in L1 cache 21, such as... Figure 8 The middle part is marked as "①".

[0159] If the data to be accessed is not stored in L1 cache 21 (i.e., if a cache miss occurs in L1 cache 21), then processor 13 can access L2 cache 22. If the data to be accessed is stored in L2 cache 22 (i.e., if a cache hit occurs in L2 cache 22), then processor 13 can access the data in L2 cache 22, such as... Figure 8 The middle part is marked as "②".

[0160] If the data to be accessed is neither stored in L1 cache 21 nor in L2 cache 22 (i.e., if both L1 cache 21 and L2 cache 22 experience cache misses), then processor 13 can access the data stored in random access memory 11, such as... Figure 8 The middle part is marked as "③".

[0161] In this case, system 10 can determine that cache 12 is hit under the circumstances described in “①” and “②” above.

[0162] The following section describes the operation of determining whether cache 12 is cache-hit when cache 12 determines L1 cache 21 and L2 cache 22.

[0163] Figure 9 It shows the determination about Figure 8 The flowchart illustrates an example of the operation described in [the document] to determine whether cache 12 is cache hit.

[0164] Reference Figure 9 The processor 13 of system 10 determines whether L1 cache 21 is hit (e.g., whether the data to be accessed is in L1 cache 21) (S910).

[0165] If the data to be accessed is hit in L1 cache 21 (e.g., if the data to be accessed is in L1 cache 21) (S910 - Yes), then processor 13 can determine that cache 12 has been hit (S920).

[0166] On the other hand, if the data to be accessed is not hit in L1 cache 21 (e.g., the data to be accessed does not exist in L1 cache 21) (S910 - No), then the processor 13 determines whether the data to be accessed is hit in L2 cache 22 (S930).

[0167] If the data to be accessed is hit in L2 cache 22 (S930 - Yes), then processor 13 can determine that cache 12 has been hit (S920).

[0168] If the data to be accessed is not found in L2 cache 22 (S930 - No), processor 13 can determine that cache 12 is not found (S940).

[0169] When processor 13 according to Figure 9 When determining whether cache 12 is cache hit, the cache hit rate CHR of cache 12 can be determined according to Equation 1, which is based on the cache hit rate CHR_L1 of L1 cache 21 and the cache hit rate CHR_L2 of L2 cache 22.

[0170] In some implementations, the cache hit rate CHR_L1 of L1 cache 21 and the cache hit rate CHR_L2 of L2 cache 22 can be determined in the same manner as the method described above for determining the cache hit rate of cache 12.

[0171] For example, the cache hit rate CHR_L1 of L1 cache 21 can be determined as the following ratio during a predetermined period: (1) the ratio of the size of data accessed by processor 13 in L1 cache 21 to the total size of data accessed by processor 13 in random access memory 11 or cache 12; (2) the ratio of the number of times processor 13 accesses data in L1 cache 21 to the total number of times processor 13 accesses data in random access memory 11 or cache 12; or (3) the ratio of the number of times processor 13 accesses data in L1 cache 21 to the total number of times processor 13 retrieves data from L1 cache 21.

[0172] For example, the cache hit rate CHR_L2 of L2 cache 22 can be determined as the following ratio during a predetermined period: (1) the ratio of the size of data accessed by processor 13 in L2 cache 22 to the total size of data accessed by processor 13 in random access memory 11 or cache 12; (2) the ratio of the number of times processor 13 accesses data in L2 cache 22 to the total number of times processor 13 accesses data in random access memory 11 or cache 12; or (3) the ratio of the number of times processor 13 accesses data in L2 cache 22 to the total number of times processor 13 retrieves data from L2 cache 22.

[0173] (CHR)=(CHR_L1)+(1-(CHR_L1))*(CHR_L2) (Equation 1)

[0174] In this case, the size of the data accessed by the processor 13 in the cache, DS_TOTAL, which represents the total size of the data in the random access memory 11 or cache 12, can be determined by the following:

[0175] (DS_TOTAL)*(CHR)=(DS_TOTAL)*(CHR_L1)+(DS_TOTAL)*(1-(CHR_L1))*(CHR_L2).

[0176] Therefore, the size of the data accessed by the processor 13 in the random access memory 11, DS_RAM, is the value obtained by subtracting the size of the data accessed by the processor 13 from the cache, (DS_TOTAL)*(CHR), from the total size of the data accessed by the processor 13 from the random access memory 11 or the cache 12, DS_TOTAL.

[0177] (DS_RAM)=(DS_TOTAL)–(DS_TOTAL)*(CHR)=(DS_TOTAL)-(DS_TOTAL)*(CHR_L1)-(DS_TOTAL)*(1–(CHR_L1))*(CHR_L2) (Equation 2)

[0178] Figure 10 An example method for setting the operating frequency of a system 10 based on some embodiments of the disclosed technology is shown.

[0179] Reference Figure 10The system 10 can set N data size segments DSP_1, DSP_2, ..., DSP_N (N is a natural number equal to or greater than 2) to set the operating frequency of the random access memory 11. In this case, the N data size segments DSP_1, DSP_2, ..., DSP_N correspond to different operating frequencies FREQ_1, FREQ_2, ..., FREQ_N.

[0180] The operating frequencies FREQ_1, FREQ_2, ..., FREQ_N corresponding to each of the N data size segments DSP_1, DSP_2, ..., DSP_N can be, for example, values ​​obtained by dividing a preset reference frequency by a specific coefficient. For instance, the operating frequency FREQ_1 can be 1 / 10 of the reference frequency, and the operating frequency FREQ_2 can be 1 / 2 of the reference frequency.

[0181] In addition, when the size of the data accessed by the processor 13 from the random access memory 11 belongs to any one of the above N data size segments DSP_1, DSP_2, ..., DSP_N, the system 10 can set the operating frequency of the random access memory 11 to the operating frequency corresponding to the target data size segment.

[0182] As an example, in Figure 10 In this context, it is assumed that the size of the data accessed by the processor 13 from the random access memory 11 belongs to the second data size segment DSP_2 among N data size segments DSP_1, DSP_2, ..., DSP_N. In this case, the system 10 can set the operating frequency of the random access memory 11 to the operating frequency FREQ_2 corresponding to the second data size segment DSP_2.

[0183] As another example, suppose the size of the data accessed by the processor 13 from the random access memory 11 belongs to the first data size segment DSP_1 among N data size segments DSP_1, DSP_2, ..., DSP_N. In this case, the system 10 can set the operating frequency of the random access memory 11 to the operating frequency FREQ_1 corresponding to the first data size segment DSP_1.

[0184] Figures 11 to 12 Show data size ranges and Figure 10 Examples of the relationship between the frequency of operations corresponding to data size segments are described in the text.

[0185] First, refer to Figure 11The first operating frequency FREQ_1 corresponds to the first data size segment DSP_1 among the N data size segments DSP_1, DSP_2, ..., DSP_N, and the second operating frequency FREQ_2 corresponds to the second data size segment DSP_2 among the N data size segments DSP_1, DSP_2, ..., DSP_N.

[0186] In this case, the size of the data included in the first data size segment DSP_1 is smaller than the size of the data included in the second data size segment DSP_2. Furthermore, the operating frequency corresponding to the first data size segment DSP_1 is lower than the operating frequency corresponding to the second data size segment DSP_2.

[0187] In other words, the operating frequency of the random access memory 11 decreases as the size of the data accessed by the processor 13 in the random access memory 11 decreases, and the operating frequency of the random access memory 11 increases as the size of the data in the random access memory 11 increases.

[0188] Additionally, refer to Figure 12 The second operating frequency FREQ_2 corresponds to the second data size segment DSP_2 among the N data size segments DSP_1, DSP_2, ..., DSP_N, and the third operating frequency FREQ_3 corresponds to the third data size segment DSP_3.

[0189] In this case, the size of the data included in the second data size segment DSP_2 is smaller than the size of the data included in the third data size segment DSP_3. Furthermore, the operating frequency corresponding to the second data size segment DSP_2 is lower than the operating frequency corresponding to the third data size segment DSP_3.

[0190] Therefore, the size of the data included in the first data size segment DSP_1 is smaller than the size of the data included in the third data size segment DSP_3. Furthermore, the operating frequency corresponding to the first data size segment DSP_1 is lower than the operating frequency corresponding to the third data size segment DSP_3.

[0191] Figure 13 The operation of system 10 based on some embodiments of the disclosed technology is shown.

[0192] Reference Figure 13 The system's operating method may include determining the cache hit rate of cache 12, which caches a portion of the data stored in random access memory 11 (S1310).

[0193] The operation method of system 10 may include setting the operating frequency of random access memory 11 based on the cache hit rate determined in S1310 (S1320).

[0194] In this case, operation S1320 may include, for example, determining the size of the data accessed by the processor 13 in the random access memory 11 based on (1) the size of the data accessed by the processor 13 in the random access memory 11 or the cache 12 and (2) the cache hit rate of the cache 12; and setting the operating frequency of the random access memory 11 based on the size of the data accessed by the processor 13 in the random access memory 11.

[0195] In some implementations, the cache 12 included in system 10 may include L1 cache 21 and L2 cache 22, and the cache hit rate of cache 12 may be determined by the cache hit rate of L1 cache 21 and the cache hit rate of L2 cache 22.

[0196] When the size of the data accessed by the processor 13 in the random access memory 11 belongs to any one of the target data size segments among a plurality of preset data size segments, the operating frequency of the random access memory 11 can be set to the operating frequency corresponding to the target data size segment.

[0197] In this scenario, for example, the first operating frequency may correspond to a first data size segment among multiple data size segments, and the second operating frequency may correspond to a second data size segment among multiple data size segments. Furthermore, the size of the data included in the first data size segment may be smaller than the size of the data included in the second data size segment, and the first operating frequency may be lower than the second operating frequency.

[0198] Furthermore, the third operating frequency can correspond to a third data size segment among multiple data size segments. In this case, the size of the data included in the second data size segment can be smaller than the size of the data included in the third data size segment, and the second operating frequency can be lower than the third operating frequency.

[0199] Figure 14 This is a diagram illustrating an example configuration of a computing system 1400 based on an embodiment of the disclosed technology.

[0200] Reference Figure 14The computing system 1400 based on the disclosed technology may include: a system 10 electrically connected to a system bus 1460; a CPU 1410 configured to control all operations of the computing system 1400; a RAM 1420 configured to store data and information related to the operation of the computing system 1400; a user interface / user experience (UI / UX) module 1430 configured to provide a user environment to a user; a communication module 1440 configured to communicate with external devices in wired and / or wireless manner; and a power management module 1450 configured to manage the power used by the computing system 1400.

[0201] The computing system 1400 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, tablet computer or various other devices.

[0202] The computing system 1400 may further include a battery for supplying operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art.

[0203] System 10 may include not only devices configured to store data on a disk, such as a hard disk drive (HDD), but also devices configured to store data in non-volatile memory, such as a solid-state drive (SSD), a general-purpose flash memory device, or an embedded MMC (eMMC) device. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, memory system 100 may be implemented as various types of storage devices and installed within various devices.

[0204] Based on the embodiments of the disclosed technology, the operation latency of the memory system can be advantageously reduced or minimized. Furthermore, based on the embodiments of the disclosed technology, the overhead incurred during the invocation of specific functions can be advantageously reduced or minimized.

[0205] Although various embodiments of the disclosed technology have been described in particular and different details for illustrative purposes, those skilled in the art will understand that various modifications, additions and substitutions may be made based on the content disclosed or shown in this disclosure without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A system comprising: Random access memory, which includes memory units for storing data; A cache memory that caches at least a portion of the data; as well as The processor communicates with the random access memory and the cache memory to access at least a portion of the data in the random access memory or the cache memory. The processor determines the cache hit rate of the cache memory and sets the operating frequency of the random access memory based on the cache hit rate. The system determines the size of the data accessed by the processor in the random access memory (RAM) based on the size of the data accessed by the processor in the RAM and the cache memory and the cache hit rate of the cache memory, and the system sets the operating frequency of the RAM based on the size of the data accessed by the processor in the RAM.

2. The system according to claim 1, wherein, The processor causes the cache hit rate of the cache memory to include at least one of the following: during a preset time period, (1) the ratio of the size of the data accessed by the processor in the cache memory to the total size of the data accessed by the processor in the random access memory or the cache memory; (2) the ratio of the number of times the processor accesses the data in the cache memory to the total number of times the processor accesses the data in the random access memory or the cache memory; (3) The ratio of the number of times the processor accesses data in the cache memory to the total number of times data is retrieved from the cache memory.

3. The system according to claim 1, wherein, The cache memory includes an L1 cache and an L2 cache, and the system determines the cache hit rate of the cache memory based on the cache hit rate of the L1 cache and the cache hit rate of the L2 cache.

4. The system according to claim 1, wherein, When the size of the data accessed by the processor in the random access memory belongs to any one of a plurality of data size segments, the system sets the operating frequency of the random access memory to an operating frequency corresponding to the target data size segment.

5. The system according to claim 4, wherein, The first operating frequency corresponds to the first data size segment among the plurality of data size segments, and the second operating frequency corresponds to the second data size segment among the plurality of data size segments. The data size included in the first data size segment is smaller than the data size included in the second data size segment, and the first operation frequency is lower than the second operation frequency.

6. The system according to claim 5, wherein, The third operating frequency corresponds to the third data size segment among the plurality of data size segments, where the data size included in the second data size segment is smaller than the data size included in the third data size segment, and the second operating frequency is lower than the third operating frequency.

7. A method comprising: Determine the cache hit rate of the cache memory, which caches at least a portion of the data to be stored in the random access memory; and The operating frequency of the random access memory is set based on the cache hit rate of the cache memory. Setting the operating frequency of the random access memory based on the cache hit rate of the cache memory includes: The size of the data accessed in the random access memory and the cache memory is determined based on the size of the data accessed in the random access memory and the cache hit rate of the cache memory; and The operating frequency of the random access memory is set based on the size of the data accessed in the random access memory.

8. The method according to claim 7, wherein, The cache hit rate of the cache memory is determined based on at least one of the following: (1) the ratio of the size of the data accessed in the cache memory during a preset period to the total size of the data accessed in the random access memory or the cache memory during the preset period; (2) the ratio of the number of times the data in the cache memory is accessed during the preset period to the total number of times the data in the random access memory or the cache memory is accessed during the preset period. (3) The ratio of the number of times data is accessed to the cache memory during the preset time period to the total number of times data is retrieved from the cache memory during the preset time period.

9. The method according to claim 7, wherein, The cache memory includes an L1 cache and an L2 cache, and the cache hit rate of the cache memory is determined based on the cache hit rate of the L1 cache and the cache hit rate of the L2 cache.

10. The method of claim 7, wherein, If the size of the data accessed in the random access memory belongs to any one of the target data size segments among multiple data size segments, the operating frequency of the random access memory is set to the operating frequency corresponding to the target data size segment.

11. The method according to claim 10, wherein, The first operating frequency corresponds to the first data size segment among the plurality of data size segments, and the second operating frequency corresponds to the second data size segment among the plurality of data size segments. The data size included in the first data size segment is smaller than the data size included in the second data size segment, and the first operation frequency is lower than the second operation frequency.

12. The method according to claim 11, wherein, The third operating frequency corresponds to the third data size segment among the plurality of data size segments, where the data size included in the second data size segment is smaller than the data size included in the third data size segment, and the second operating frequency is lower than the third operating frequency.

Images