Network device security protocol

Abstract

Network device security protocols are disclosed. In one embodiment, a network device includes packet processing circuitry including at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, in response to checking for missing sequence numbers among the assigned sequence numbers, to find missing packets in at least one corresponding subsequent stage of the packet processing, and to report the missing packets.

Description

TECHNICAL FIELD

[0001] The present invention relates to computing devices, and in particular, but not exclusively, to network devices. BACKGROUND

[0002] A network interface controller (NIC) located between a network and a local central processing unit (CPU) and / or graphics processing unit (GPU) manages traffic between the local CPU and / or GPU and the network. The CPU and / or GPU can exchange data with a remote CPU and / or GPU over the network via another NIC.

[0003] Communication channels typically check for corrupted, duplicated and dropped packets (e.g. via packet sequence numbers checks) and packet delays (e.g. via time-based signatures such as using timestamps or sending keep alive packets between two endpoints) using end-to-end security protocols including data integrity protection (e.g. cyclic redundancy check (CRC) checks) in order to protect the channel from failure modes. In this approach, both the source and the target need to support the end-to-end security protocol in both hardware and software.

[0004] This topology can be implemented in networks requiring a high level of reliability (e.g. automotive networks) to ensure that packets, especially those including sensitive data, are not lost on their way through the network (e.g. from a server to a car, or vice versa). Automotive safety applications typically comply with ISO-26262 which describes a security protocol to be used in end-to-end systems. SUMMARY

[0005] According to an embodiment of the present disclosure, there is provided a network device comprising packet processing circuitry comprising at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to allocate sequence numbers to the packets in at least one stage of packet processing, in response to checking for missing sequence numbers among the allocated sequence numbers, to find missing packets in at least one corresponding subsequent stage of the packet processing, and to report the missing packets.

[0006] Further according to an embodiment of the present disclosure, the device comprises a silicon chip comprising the packet processing circuitry, the at least one interface comprises a plurality of ports, a plurality of the ports are configured as input ports and other ones of the ports are configured as output ports, the silicon chip is configured to verify the integrity of the behaviour of the silicon chip from the input ports to the output ports.

[0007] Still further, according to embodiments of the present disclosure, the at least one interface comprises a plurality of ports, some of the ports are configured as input ports configured to receive the packets and to assign to the received packets input-port-specific sequence numbers, and the packet forwarding circuitry is configured to find missing ones of the received packets in response to checking for missing ones of the assigned input-port-specific sequence numbers.

[0008] Additionally, according to embodiments of the present disclosure, the at least one interface comprises a plurality of ports, some of the ports are configured as output ports to forward ones of the packets, the packet forwarding circuitry is configured to assign to the processed ones of the packets output-port-specific sequence numbers, and the output ports are configured to find missing ones of the processed packets in response to checking for missing ones of the assigned output-port-specific sequence numbers.

[0009] Furthermore, according to embodiments of the present disclosure, the at least one interface comprises a plurality of ports, some of the ports are configured as input ports to receive packets, and some of the ports are configured as output ports to forward ones of the packets, and the packet forwarding circuitry is configured to receive the respective packets from the input ports, make respective forwarding decisions on the respective packets to determine respective ones of the output ports to forward the respective packets to, forward the respective packets to the respective output ports, in response to respective input-output-port combinations of the respective packets, assign to the respective packets input-output-port-specific sequence numbers in a first stage of the packet processing, and find missing ones of the respective packets in a second stage of the packet processing in response to checking for missing ones of the assigned input-output-port-specific sequence numbers.

[0010] Further according to embodiments of the present disclosure, the input ports are configured to assign to the received packets input-port-specific sequence numbers, and the packet forwarding circuitry is configured to find missing ones of the received packets in response to checking for missing ones of the assigned input-port-specific sequence numbers.

[0011] Still further, according to embodiments of the present disclosure, the packet forwarding circuitry is configured to assign to the processed ones of the packets output-port-specific sequence numbers after the second stage of the packet processing, and the output ports are configured to find missing ones of the processed packets in response to checking for missing ones of the assigned output-port-specific sequence numbers.

[0012] Additionally, according to embodiments of the present disclosure, the input ports are configured to assign an ingress timestamp to the received packets, and the output ports are configured to find out, in the packet processing, delay packets of the packets that exceed a given processing delay in response to checking respective ones of the ingress timestamps against a current time, and to report the delay packets that exceed the given processing delay.

[0013] Furthermore, according to embodiments of the present disclosure, each of the received packets includes a respective integrity check code, the packet processing circuitry is configured to check the integrity check code of respective ones of the received packets, and to report packets of the packets that fail an integrity check.

[0014] Further, according to embodiments of the present disclosure, the at least one interface includes a plurality of ports, ones of the plurality of ports are configured as input ports to receive the packets and to assign an ingress timestamp to the received packets, ones of the plurality of ports are configured as output ports and to forward ones of the packets, the packet processing is found out, in the packet processing, delay packets of the packets that exceed a given processing delay in response to checking respective ones of the ingress timestamps against a current time, and the delay packets that exceed the given processing delay are reported.

[0015] Still further, according to embodiments of the present disclosure, the at least one interface is configured to connect to a packet network.

[0016] Additionally, according to embodiments of the present disclosure, the at least one interface includes a network interface configured to connect to a data packet network and a peripheral bus interface configured to connect to a host device.

[0017] According to another embodiment of the present disclosure, there is also provided a networking method, comprising receiving packets, making respective forwarding decisions for respective ones of the packets, assigning sequence numbers to the packets in at least one stage of packet processing, finding out, in response to checking for missing ones of the assigned sequence numbers, missing packets in at least one corresponding subsequent stage of the packet processing, and reporting the missing packets.

[0018] Furthermore, according to embodiments of the present disclosure, the assigning includes assigning input port specific sequence numbers to the received packets, and the finding out includes finding out, in response to checking for missing ones of the assigned input port specific sequence numbers, missing ones of the received packets.

[0019] Further in accordance with an embodiment of the present disclosure, the assigning includes assigning output-port-specific sequence numbers to processed ones of the packets, and the finding out includes finding out missing ones of the processed packets in response to checking the assigned output-port-specific sequence numbers for missing ones of the output-port-specific sequence numbers.

[0020] Still further in accordance with an embodiment of the present disclosure, the making out includes making out respective forwarding decisions for respective packets to determine respective output ports to forward the respective packets to, the assigning includes assigning input-output-port-specific sequence numbers to the respective packets in a first stage of the packet processing in response to respective input-output-port combinations of the respective packets, and the finding out includes finding out missing ones of the respective packets in a second stage of the packet processing in response to checking the assigned input-output-port-specific sequence numbers for missing ones of the input-output-port-specific sequence numbers.

[0021] Additionally in accordance with an embodiment of the present disclosure, the assigning includes assigning input-port-specific sequence numbers to the received packets, and the finding out includes finding out missing ones of the received packets in response to checking the assigned input-port-specific sequence numbers for missing ones of the input-port-specific sequence numbers.

[0022] Moreover in accordance with an embodiment of the present disclosure, the assigning includes assigning output-port-specific sequence numbers to processed ones of the packets after the second stage of the packet processing, and the finding out includes finding out missing ones of the processed packets in response to checking the assigned output-port-specific sequence numbers for missing ones of the output-port-specific sequence numbers.

[0023] Further in accordance with an embodiment of the present disclosure, the method includes assigning ingress timestamps to the received packets, finding out in the packet processing, in response to checking respective ones of the ingress timestamps for a current time, delayed ones of the packets that exceed a given processing delay, and reporting the delayed ones of the packets that exceed the given processing delay.

[0024] Still further in accordance with an embodiment of the present disclosure, each of the received packets includes a respective integrity check code, the method further includes checking the integrity check codes of respective ones of the received packets, and reporting ones of the packets that fail an integrity check.

[0025] Further, according to embodiments of the present disclosure, the method comprises assigning an entry timestamp to the received packets, forwarding some of the packets, in response to checking respective packets of the entry timestamps against a current time, finding out in the packet processing a delay packet of the packets that exceeds a given processing delay, and reporting the delay packet that exceeds the given processing delay. BRIEF DESCRIPTION OF DRAWINGS

[0026] The present application will be understood by the detailed description given below, in connection with the accompanying drawings, in which:

[0027] Figure 1 is a block diagram of a computer system constructed and operable in accordance with embodiments of the present application;

[0028] Figure 2 is a block diagram of a network device in a system for Figure 1 ;

[0029] Figure 3 is a flow diagram of steps in a security method comprising Figure 2 operation of a network device;

[0030] Figure 4 is a flow diagram of steps in a method comprising Figure 2 operation of an input port of a network device;

[0031] Figure 5 is a flow diagram of steps in a method comprising Figure 2 operation of a packet forwarding circuit of a network device; and

[0032] Figure 6 is a flow diagram of steps in a method comprising Figure 2 operation of an output port of a network device. DETAILED DESCRIPTION

[0033] SUMMARY

[0034] When one of the endpoint devices does not support or cannot support end-to-end security, one or more of the components along the route of the packet (e.g., CPU and / or GPU, NIC, and network) can implement independent security mechanisms without relying on adjacent components or devices. Implementing security concepts in a system-on-a-chip (SOC) design can include partitioning the SOC into independent units (e.g., CPU, interface controllers, bus matrix, memory, etc.), verifying the independence of each unit, and identifying failure modes for each unit. Security mechanisms can then be developed for each unit to address the corresponding identified failure modes. For network devices, such as smart NICs or switches, where the units of the network device are not neatly partitioned, the above solution is typically not possible to implement. For example, the design of a network device can include a mix of data-path, controller, and processing unit designs, and because each unit is deeply related to one or more adjacent units, it is difficult to analyze the failure modes of each unit independently. In such cases, security for the network device can be implemented using expensive power and area security mechanisms (e.g., lockstep or error checking and correction (ECC)).

[0035] Accordingly, embodiments of the present invention address the above problems by applying a security protocol from the input of a network device, such as a NIC or switch, to the output of the network device. In some embodiments, the network device includes a silicon chip that performs some or all of the functionality of the network device. The security protocol verifies the behavioral integrity of the silicon chip and avoids security violations due to random faults that can occur on data and logic control.

[0036] Packet duplication and loss are checked by assigning a sequence number to each received packet. The sequence number of each packet is then checked in the network device. Missing packets are identified based on a skip in the sequence numbers of the checked packets.

[0037] Packet integrity can also be checked by checking the CRC of each packet. Packet delay in the network device can also be checked by comparing the current time with the ingress timestamp assigned to each packet when received in the network device.

[0038] In some embodiments, different sequence numbers are assigned to each packet at respective different packet processing stages within the network device for checking at corresponding subsequent stages in packet processing. For example, a first sequence number is assigned to a packet at a first stage of packet processing for checking at a second stage of packet processing, and then a second sequence number is assigned to the packet at the second stage for checking at a third stage.

[0039] In some embodiments, the packets received by the network device can be assigned sequence numbers according to the input port from which the packet is received. For example, packets received by input port A can be assigned sequence numbers of series A, while packets received by input port B can be assigned sequence numbers of series B. In this way, there can be as many series of sequence numbers as there are input ports, such that each input port is able to assign sequence numbers to received packets according to its own series of sequence numbers, without having to be aware of the sequence numbers assigned by other input ports.

[0040] Each packet received by the network device typically includes a CRC for the packet that is computed by the originator of the packet (e.g., a local or remote CPU or GPU). The CRC can be used, for example, in subsequent stages of packet processing, to check packet integrity.

[0041] The packets received by the input ports are then forwarded to packet forwarding circuitry in the network device. The packet forwarding circuitry makes forwarding decisions as to which output port each packet should be forwarded to and performs the forwarding to the respective ports. The sequence number of each packet is examined by the packet forwarding circuitry (e.g., a switch circuit or a peripheral component interconnect (PCI) bridge) of the network device according to the series of assigned sequence numbers. For example, for series A sequence numbers, packets that are missing from input port A are identified, and so on.

[0042] The packet forwarding circuit then assigns each packet a new sequence number (replacing the existing sequence number) based on the input port from which it received the packet and the output port to which it will be assigned. For example, if a packet arrives from input port C and is assigned to output port E, the packet receives a sequence number from the C:E series, and if a packet arrives from input port C and is assigned to output port F, the packet receives a sequence number from the C:F series. Since each unique flow (e.g., input-output port combination) within the network device needs to be tracked, the sequence numbers assigned at this stage are specific to the input-output port. In this way, the packet forwarding circuit can easily track the sequence numbers, since packets from any input port can be assigned to any output port and treated as independent flows in the packet forwarding circuit. Then, just before the packet processing in the packet forwarding circuit is complete, the input-output port specific sequence number of each packet is checked. The reason for checking the sequence number at the end of the packet processing circuit is to ensure that the packet made it safely across the packet forwarding circuit, which performs many processes including managing queues and arbitration, among other tasks. The packet forwarding circuit then assigns each packet a new sequence number (replacing the existing sequence number) based on the output port to which it is assigned. For example, packets destined for output port D can be assigned sequence numbers from series D, while packets destined for output port F can be assigned sequence numbers from series F. In this way, there can be as many sequence number series as there are output ports, so that each output port can easily check the sequence number of a received packet based on its own sequence number series, without having to know the sequence numbers assigned to other output ports. The packets are then transmitted to the respective output ports, which check the sequence number of the received packet.

[0043] The different sequence number checks allow the network device to identify missing or duplicate packets at different stages in the packet processing based on missing or duplicate sequence numbers in the respective series. The network device can then report the missing or duplicate packets to a designated local or remote entity, such as an external safety microcontroller (MCU), for example, via an interrupt-based protocol.

[0044] The output ports can also check the integrity of the packets (e.g., based on a CRC for each respective packet). If the network device modifies a packet at any stage, a new CRC is typically generated and replaces the existing CRC.

[0045] The output ports can also check the latency of the packets in the network device based on an ingress timestamp (assigned to each packet by the respective input port) and a current time (e.g., based on an internal clock of the network device). The network device can report packets that fail the integrity check and / or are delayed too long in the network device to a designated local or remote entity.

[0046] In the above examples, the network device can be a NIC, where the input port can be configured on a PCI interface connecting the network device to a local CPU or GPU, and the output port can be configured on an Ethernet interface connecting the NIC to the network. In another example, the network device can be a NIC, where the input port can be configured on an Ethernet interface, and the output port can be configured on a PCI interface. In some examples, since a NIC typically handles two-way traffic, the input and output ports can be configured on both the PCI interface and the Ethernet interface. In yet another example, the network device can be a switch, where the input and output ports are configured on an Ethernet interface connecting the switch to the network.

[0047] System Description

[0048] Referring now Figure 1 , Figure 1 is a block diagram of a computer system 10 drawn and operable in accordance with embodiments of the present application. The computer system 10 includes two endpoint devices 12 that communicate with each other over a data packet network 14. Each endpoint device 12 can include a CPU and / or a GPU. The GPU can be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data provided by a central processing unit (CPU). GPUs are used to generate three-dimensional (3D) graphics objects and two-dimensional (2D) graphics objects for a variety of applications, including movies, computer games, virtual reality (VR) and augmented reality (AR) experiences, mechanical design, etc.

[0049] Each endpoint device 12 is connected to a network interface controller 16 to enable communication over the network 14. In some embodiments, each network interface controller 16 can serve one or more endpoint devices 12 and have one or more ports to the network 14. For example, each of the network interface controllers 16 can serve multiple endpoint devices 12, or one of the network interface controllers 16 can serve one endpoint device 12, while other network interface controllers 16 can serve multiple endpoint devices 12. Each network interface controller 16 can include packet processing circuitry 17, which can include a peripheral bus interface 20 (e.g., a PCI interface) configured to connect with a host device, e.g., a local endpoint device 12, a network interface 22 (e.g., an Ethernet interface) configured to connect to the network 14, and packet forwarding circuitry 24 that makes forwarding decisions for packets received from the peripheral bus interface 20 or the network interface 22. In some embodiments, the packet processing circuitry 17 can be included in a silicon chip 19 of the network interface controller 16.

[0050] Network 14 may include one or more switches 18. Each switch 18 may also include a network interface (not shown) and packet forwarding circuitry (not shown). One or more of the network interface controllers 16 and / or the switches 18 may implement as described in the reference. Figure 2 A more detailed description of the in-device security protocols. The computer system 10 also includes one or more entities 26 (e.g., a security microcontroller) that report security breaches.

[0051] Now for reference Figure 2 , Figure 2 It is used for Figure 1 A block diagram view of network device 30 in system 10. For simplicity, the following refers to... Figures 2 to 6 The provided description assumes that network device 30 is one of the network interface controllers 16. However, network device 30 can be implemented as one of the switches 18 or any suitable network device. For simplicity, see below. Figures 2 to 6 The provided description assumes that input port 32 is configured on peripheral bus interface 20 and output port 34 is configured on network interface 22. However, network device 30 may be configured with an input port on network interface 22 and an output port on peripheral bus interface 20, or with input and output ports on both peripheral bus interface 20 and network interface 22. In embodiments where network device 30 is implemented as one of switches 18, the input and output ports may be implemented on the same network interface.

[0052] Figure 2 Packets 36 received from endpoint device 12 or a peripheral device (e.g., a storage device) are shown (only some packets are labeled for simplicity). Input port 32 of peripheral bus interface 20 receives packets 36. In an embodiment where the input port is configured on network interface 22, packets 36 are received from network 14. See reference... Figure 4 In more detail, input port 32 assigns an input port-specific sequence number 38 to packet 36 and an entry timestamp. The input port-specific sequence number 38 is inserted into the header field of packet 36.

[0053] Packet forwarding circuit 24 receives packet 36 and makes a forwarding decision for packet 36 (e.g., which of the output ports 34 packet 36 should be forwarded to). Packet forwarding circuit 24 checks (box 46) the input port-specific sequence number 38 and assigns the input-output port-specific sequence number 40 to packet 36 based on the unique flow 42 of the corresponding input-output port combination of the corresponding packet 36 (only some unique flows are labeled for simplicity), as referenced. Figure 5The input-output port-specific sequence number 40 replaces the input port-specific sequence number 38 in the packet 36. The packet forwarding circuit 24 processes the packets 36 in their respective unique flows 42.

[0054] The input-output port-specific sequence number 40 is checked (block 48) at the end of packet processing in the packet forwarding circuit 24, and the output port-specific sequence number 44 is assigned by the packet forwarding circuit 24 to the packet 36 (replacing the input-output port-specific sequence number 40 in the packet 36). The packet 36 is then forwarded to its respective output port 34.

[0055] The respective output port 34 checks (block 50) the respective output port-specific sequence number 44, checks the delay of the packet 36 in the network device 30, and performs an integrity check of the packet 36, as described with reference to Figure 6 In more detail, the output port 34 forwards the packet over the network 14 (or to the end-point device 12 when the output port 34 is implemented on the peripheral bus interface 20).

[0056] The security protocol implemented using the sequence number check, and / or the integrity check of the packet, and / or the delay check, verifies the behavioral integrity of the silicon chip 19 of the network device 30 from the ingress to the egress of the silicon chip 19 (from the input port 32 to the output port 34), and protects the silicon chip 19 from security violations due to random faults that can occur on the data and the logic control.

[0057] In practice, part or all of the functionality of the packet forwarding circuit 24 can be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components can include hardwired devices or programmable devices, or a combination of both. In some embodiments, at least part of the functionality of the packet forwarding circuit 24 can be performed by a programmable processor under the control of suitable software. For example, the software can be downloaded into the device in electronic form over a network. Alternatively, or additionally, the software can be stored in a tangible, non-transitory computer-readable storage medium, such as an optical, magnetic, or electronic memory.

[0058] Reference is now made to Figure 3 which is a flowchart 300 of steps in a method of secure operation of the network device 30 including Figure 2 Reference is also made to Figure 2Peripheral bus interface 20 is configured to receive (box 302) packet 36. Generally, packet processing circuitry 17 is configured to assign (box 304) sequence numbers 38, 40, 44 to packet 36 in at least one stage of packet processing. Packet processing circuitry 17 is configured to check (box 306) for missing sequence numbers 38, 40, 44 among the assigned sequence numbers 38, 40, 44 in at least one corresponding subsequent stage of packet processing (i.e., sequence numbers are assigned in one stage and checked in a subsequent stage of packet processing). Packet processing circuitry 17 is configured to identify (box 308) the missing packet 36 in at least one corresponding subsequent stage of packet processing in response to the check for missing sequence numbers 38, 40, 44 among the assigned sequence numbers 38, 40, 44. Packet processing circuitry 17 is configured to report the missing packet 36 (box 310) to entity 26. Figure 1 One or more of them.

[0059] Now for reference Figure 4 , Figure 4 It includes Figure 2 The flowchart 400 shows the steps in the operation method of the input port 32 of the network device 30. See also: Figure 2 Input port 32 is configured to receive (box 402) packets 36. Each packet in the received packets 36 includes a corresponding integrity check code (e.g., CRC) calculated by the packet initiator (such as one of the endpoint devices 12, e.g., a local or remote CPU or GPU). The CRC can be used, for example, to check packet integrity in a later stage of packet processing. Input port 32 is configured to assign a corresponding inbound timestamp (box 404) to the received packets 36, for example, based on the current time of the clock running in network device 30. Input port 32 is configured to assign an input port-specific sequence number 38 (box 406) to the received packets 36. For example, packets 36 received by input port A may be assigned a sequence number of series A, while packets 36 received by input port B may be assigned a sequence number of series B. Series A and B are independent sequence number series. In this way, there can be as many sequence number series as input ports 32, so that each input port 32 (which typically processes packets 36 independently of other input ports 32) can assign a sequence number to the received packets 36 according to its own sequence number series, without needing to know the sequence numbers assigned by other input ports 32. The packets 36 received by input ports 32 are then forwarded to packet forwarding circuitry 24 in network device 30.

[0060] Now for reference Figure 5 , which includes Figure 2 Flowchart 500 shows the steps in the operation method of the packet forwarding circuit 24 of network device 30. See also:Figure 2 .

[0061] The packet forwarding circuit 24 is configured to receive (block 502) the respective packet 36 from the input port 32. The packet forwarding circuit 24 is configured to check (block 504) for missing input port specific sequence numbers 38 in the assigned input port specific sequence numbers 38. In other words, check for missing sequence numbers by sequence. For example, for missing series A sequence numbers, identify missing packets from input port A, and so on. The packet forwarding circuit 24 is configured to find (block 506) missing packets in the received packet 36 in response to the checking for missing input port specific sequence numbers 38 in the assigned input port specific sequence numbers 38. For example, if a packet with a series A sequence number of 10002 is received, and the next packet with a series A sequence number of 10004 is received, then the packet with a sequence number of 10003 is considered missing. The packet forwarding circuit 24 is configured to report (block 508) the missing packet 36 to the entity 26 in response to the finding and checking steps in blocks 506 and 504. Figure 1 ) one or more.

[0062] The packet forwarding circuit 24 is configured to make (block 510) a respective forwarding decision for a respective packet of the packets 36 to determine a respective one of the output ports 34 to which to forward the respective packet 36. The forwarding decision can be made according to the source IP address and the destination IP address in the packet header, among other factors. In response to making the forwarding decision (i.e., knowing the output port 34 for the packet 36), the packet forwarding circuit 24 is configured to assign (block 512) a input-output port specific sequence number 40 to the respective packet in a first stage of packet processing in the packet forwarding circuit 24 in response to the respective input-output port combination of the respective packet 36. For example, if a packet arrives from input port C and is assigned to output port E, the packet receives a sequence number in the C:E series of sequence numbers, and if a packet arrives from input port C and is assigned to output port F, the packet receives a sequence number in the C:F series of sequence numbers. Since each unique flow 42 (e.g., input-output port combination) within the network device 30 needs to be tracked, the input-output port specific sequence number 40 assigned in this stage is specific to the input-output port. In this way, the packet forwarding circuit 24 can easily track the sequence numbers, as packets 36 from any input port 32 can be assigned to any output port 34 and treated as a separate flow 42 in the packet forwarding circuit 24. In some embodiments, different hardware components in the packet forwarding circuit 24 can handle separate flows 42 and thus can not be aware of the sequence number series used by other flows 42. The input-output port specific sequence number 40 typically replaces the input port specific sequence number 38 in the respective packet 36.

[0063] The packet forwarding circuit 24 is configured to perform (block 514) packet processing of individual packets 36 in the respective flow 42 in a second stage of packet processing. The second stage can include one or more sub-stages, including management queues and arbitration. The packet forwarding circuit 24 is configured to check (block 516) for missing input-output port specific sequence numbers 40 in the assigned input-output port specific sequence numbers 40 in a third stage of packet processing. In other words, the missing sequence numbers 40 are checked in sequence. For example, for a missing series A:E sequence number, a missing packet from input port A that is to be forwarded to output port E is identified, and so on.

[0064] The packet forwarding circuit 24 is configured to find (block 518) missing packets in the respective packets 36 in the third stage of packet processing in response to the checking of missing input-output-port-specific sequence numbers 40 in the assigned input-output-port-specific sequence numbers 40 in the step of block 516. For example, if the sequence number of a packet having a sequence number of series A:E is 100010, and the sequence number of the next packet having a sequence number of series A:E is 100012, then the packet having a sequence number of 100011 is considered missing. The packet forwarding circuit 24 is configured to report (block 520) the missing packets 36 to one or more of the entities 26 in response to the finding and checking steps of blocks 516 and 518. Figure 1 One reason for checking the input-output-port-specific sequence numbers 40 of the packets 36 at the end of packet processing in the packet forwarding circuit 24 is to ensure that the packets 36 make it safely through the packet forwarding circuit 24, which performs many processes including managing queues and arbitration, among other tasks.

[0065] The packet forwarding circuit 24 is configured to assign (block 522) output-port-specific sequence numbers 44 to the packets 36 after the third stage of packet processing. For example, packets destined for output port D can be assigned sequence numbers of series D, while packets destined for output port F can be assigned sequence numbers of series F. In this way, there can be as many sequence number series as there are output ports 34, so that each output port 34 can easily check the sequence numbers of received packets 36 according to its own sequence number series, without having to know the sequence numbers assigned to other output ports 34. The packets 36 are then forwarded to the respective output ports 34.

[0066] Reference is now made to Figure 6 , Figure 6 is a flowchart 600 of steps in a method of operation of an output port 34 of the network device 30 including Figure 2 Reference is also made to Figure 2 .

[0067] The steps described below describe operations performed by the output port 34 with respect to the respective packet of the packets 36. In other words, each output port 34 performs the operations described below with respect to the packets 36 received by that output port 34 from the packet forwarding circuit 24.

[0068] The output port 34 is configured to check (block 602) for missing output-port-specific sequence numbers 44 in the assigned output-port-specific sequence numbers 44. In other words, the missing output-port-specific sequence numbers 44 are checked by sequence series. For example, for missing series D sequence numbers, missing packets for output port D are identified, and so on.

[0069] The output ports 34 are configured to find (block 604) missing packets in the processed packets 36 in response to checking for missing output port-specific sequence numbers 44 in the assigned output port-specific sequence numbers 44. For example, if the sequence number of a packet with a series E sequence number received by port E is 100006, and the sequence number of the next packet with a series E sequence number received by port E is 100008, then the packet with sequence number 100007 is considered missing. The output ports 34 are configured to report (block 606) the missing packets 36 to one or more of the entities 26( Figure 1 ) in response to one or more of the find and check steps in blocks 604 and 602.

[0070] The output ports 34 are configured to check (block 608) the respective ingress timestamps of the packets 36 for a respective packet against a current time at which the respective packet 36 was processed by the respective one of the output ports 34. The output ports 34 are configured to find (block 610) delayed packets in the packets 36 that exceed a given processing delay in packet processing in response to checking the respective ingress timestamps against the current time. In other words, a delayed packet is defined as a packet for which the assigned ingress timestamp is greater than the given processing delay. The output ports 34 are configured to report (block 612) the respective delayed packets in the delayed packets 36 that exceed the given processing delay to one or more of the entities 26( Figure 1 ).

[0071] The output ports 34 are configured to check (block 614) the integrity check codes (e.g., based on a CRC for each packet 36) of the respective received packets 36. If a packet is modified by the network device 30 at any stage, a new CRC for the packet is typically generated and replaces the existing CRC for the packet. The output ports 34 are configured to report (block 616) the packets 36 that fail the integrity check to one or more of the entities 26( Figure 1 ). The output ports 34 are configured to forward (block 618) the packets 36 (e.g., over the network 14 or a local end device in the end devices 12).

[0072] For the sake of clarity, the various features of the application described in the context of different embodiments can also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features of the application described in the context of a single embodiment can also be provided separately or in any appropriate

[0073] The above examples are cited by way of example, and the present application is not limited to the above described embodiments. Rather, the scope of the present application includes combinations and sub-combinations of various features described above, as well as variations and modifications which will occur to those skilled in the art upon reading the above description and which are not disclosed in the prior art.

Claims

1. A network device, comprising packet processing circuitry, the packet processing circuitry comprising: At least one interface is configured to receive packets; as well as A packet forwarding circuit configured to make a corresponding forwarding decision for a specific packet within the packet, wherein the packet processing circuit is configured to: In response to the various input-output port combinations in the corresponding packet, the packet processing circuit assigns a sequence number specific to the input-output port to the corresponding packet in the first stage of packet processing; After the first stage of packet processing, in which the packet processing circuit assigns serial numbers specific to the input-output ports, the second stage of packet processing checks for any missing serial numbers among the assigned serial numbers specific to the input-output ports. In response to the lost input-output port-specific sequence number, the lost packet in the corresponding packet is identified in the second stage of the packet processing; as well as The report describes the missing packets.

2. The device of claim 1, further comprising a silicon chip including the packet processing circuitry, the at least one interface including a plurality of ports, some of the ports being configured as input ports and other ports being configured as output ports, the silicon chip being configured to verify the integrity of the silicon chip's behavior from the input ports to the output ports.

3. The device according to claim 1, wherein: The at least one interface includes multiple ports, some of which are configured as input ports; The input port is configured to receive the packet and assign a specific input port sequence number to the received packet; as well as The packet forwarding circuit is configured to identify lost packets in the received packets in response to checking for missing input port-specific serial numbers in the assigned input port-specific serial numbers.

4. The device according to claim 1, wherein: The at least one interface includes multiple ports, some of which are configured as output ports for forwarding some of the packets; The packet forwarding circuit is configured to assign an output port-specific sequence number to the processed packets within the packet; as well as The output port is configured to identify missing packets in the processed packets in response to checking for missing output port-specific serial numbers in the assigned output port-specific serial numbers.

5. The device according to claim 1, wherein: The at least one interface includes a plurality of ports, some of which are configured as input ports for receiving the packets, and some of which are configured as output ports for forwarding some of the packets. as well as The packet forwarding circuit is configured as follows: Receive the corresponding packet from the input port; Make a forwarding decision for the corresponding packet to determine the corresponding output port to which the corresponding packet will be forwarded.

6. The device according to claim 5, wherein: The input port is configured to assign an input port-specific sequence number to the received packets; and The packet forwarding circuit is configured to identify lost packets in the received packets in response to checking for missing input port-specific serial numbers in the assigned input port-specific serial numbers.

7. The device according to claim 6, wherein: The packet forwarding circuit is configured to assign an output port-specific sequence number to the processed packets within the packet after the second stage of packet processing; as well as The output port is configured to identify missing packets in the processed packets in response to checking for missing output port-specific serial numbers in the assigned output port-specific serial numbers.

8. The device according to claim 7, wherein: The input port is configured to assign an entry timestamp to the received packets; and The output port is configured as follows: In response to checking the corresponding entry timestamp in the entry timestamps for the current time, delay packets exceeding a given processing delay are identified in the packet processing; and Report the delay group that exceeds the given processing delay.

9. The device according to claim 1, wherein: Each of the received packets includes a corresponding integrity check code; The packet processing circuit is configured to check the integrity check code of the corresponding packet in the received packets; and The report identifies the groups that failed the integrity check.

10. The device according to claim 1, wherein: The at least one interface includes multiple ports; Some of the ports are configured as input ports for receiving the packets and assigning entry timestamps to the received packets; Some of the ports are configured as output ports and are used for: Forward some of the packets in the aforementioned group; In response to checking the corresponding entry timestamp in the entry timestamps for the current time, delay packets exceeding a given processing delay are identified in the packet processing; and Report the delay group that exceeds the given processing delay.

11. The device of claim 1, wherein the at least one interface is configured to connect to a data packet network.

12. The device of claim 1, wherein the at least one interface comprises: A network interface configured to connect to a data packet network; And a peripheral bus interface, which is configured to connect to the host device.

13. A networking method, comprising: Receive packets; Make corresponding forwarding decisions for the corresponding packets in the aforementioned groups; In response to the individual input-output port combinations in the corresponding packet, the packet processing circuit assigns a sequence number specific to the input-output port to the corresponding packet in the first stage of packet processing; After the first stage of packet processing, in which the packet processing circuit assigns serial numbers specific to the input-output ports, the second stage of packet processing checks for any missing serial numbers among the assigned serial numbers specific to the input-output ports. In response to the lost input-output port-specific sequence number, the lost packet in the corresponding packet is identified in the second stage of the packet processing; as well as The report describes the missing packets.

14. The method of claim 13, wherein: The allocation includes assigning an input port-specific sequence number to the received packet; as well as The identification process includes: identifying lost packets in the received packets in response to checking for missing input port-specific serial numbers among the assigned input port-specific serial numbers.

15. The method according to claim 13, wherein: The allocation includes: assigning output port-specific sequence numbers to the processed packets within the packets; and The identification process includes: identifying missing output port-specific serial numbers in response to checking for missing output port-specific serial numbers among the assigned output port-specific serial numbers.

16. The method of claim 13, wherein: The making includes: making a corresponding forwarding decision for the corresponding packet to determine the corresponding output port to which the corresponding packet should be forwarded.

17. The method of claim 16, wherein: The allocation includes: assigning an input port-specific sequence number to the received packet; and The identification process includes: identifying lost packets in the received packets in response to checking for missing input port-specific serial numbers among the assigned input port-specific serial numbers.

18. The method of claim 17, wherein: The allocation includes: after the second stage of the packet processing, assigning an output port-specific sequence number to the processed packets within the packet; and The identification process includes: identifying missing output port-specific serial numbers in response to checking for missing output port-specific serial numbers among the assigned output port-specific serial numbers.

19. The method of claim 18, further comprising: Assign a timestamp to the received packet; In response to checking the corresponding entry timestamp in the entry timestamps for the current time, delay packets exceeding a given processing delay are identified in the packet processing; and Report the delay group that exceeds the given processing delay.

20. The method of claim 13, wherein each of the received packets includes a corresponding integrity check code, the method further comprising: Check the integrity check code of the corresponding packet in the received packets; as well as The report identifies the groups that failed the integrity check.

21. The method of claim 13, further comprising: Assign a timestamp to the received packet; Forward some of the packets in the aforementioned group; In response to checking the corresponding entry timestamp in the entry timestamp for the current time, delay packets in the packet processing that exceed a given processing delay are identified. as well as Report the delay group that exceeds the given processing delay.

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