Host, data processing system, method, electronic device and storage medium
By parsing and loading operators in the host, the problem of embedded processors being unable to efficiently process multiple operators in existing technologies is solved, thereby improving data processing performance and efficiency, reducing development complexity and cost, and enhancing flexibility and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-26
- Publication Date
- 2026-03-24
AI Technical Summary
In existing technologies, embedded processors are inefficient in the processes of operator loading, parsing, execution, and unloading, especially in that they cannot load multiple operators simultaneously, resulting in low data processing efficiency.
By setting up an operator parsing module and a loading module in the host, the parsing and loading functions of operators are transferred from the digital signal processor to the host. The digital signal processor focuses on data processing, while the host is responsible for the parsing and loading of operators and passes them to the digital signal processor for invocation through location information or identification information.
It improves the performance and efficiency of data processing, reduces the code complexity of digital signal processors, reduces development costs, improves development efficiency, and enhances flexibility and scalability through multi-operator loading.
Smart Images
Figure CN115629881B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of artificial intelligence, in particular, the present application relates to a host, a data processing system, a method, an electronic device and a storage medium. BACKGROUND
[0002] With the development of neural networks, there is an increasing demand for embedding processors in devices. Embedded processors can be used to perform various operators in neural network models. Common embedded processors, such as digital signal processors (DSPs), provide operator loading and operator execution functions.
[0003] In the prior art, operator loading, operator parsing, operator execution, and operator unloading are all processed by digital signal processors, resulting in low data processing efficiency. SUMMARY
[0004] The embodiments of the present application provide a host, a data processing system, a method, an electronic device and a storage medium, which can solve the problem of low data processing in the prior art.
[0005] The technical solution is as follows:
[0006] According to an aspect of an embodiment of the present application, a host is provided, which includes an operator parsing module and an operator loading module;
[0007] The operator parsing module is configured to parse a to-be-loaded operator to obtain a corresponding parsing result.
[0008] The operator loading module is configured to store the parsing result in a memory and send position information corresponding to the parsing result to a digital signal processor, so that the digital signal processor calls the corresponding parsing result from the memory based on the position information.
[0009] Optionally, the operator loading module includes a first interaction unit.
[0010] The position information includes an entry address. When the operator loading module sends the position information corresponding to the parsing result to the digital signal processor, so that the digital signal processor calls the corresponding parsing result from the memory based on the position information, it includes:
[0011] The first interaction unit sends the entry address corresponding to the parsing result to the digital signal processor, so that the digital signal processor calls the corresponding parsing result from the memory based on the entry address.
[0012] Optionally, the operator loading module includes a second interaction unit.
[0013] The location information includes a location index identifier. When the operator loading module sends the location information corresponding to the parsing result to the digital signal processor so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the location information, the following steps are included:
[0014] The second interaction unit sends the location index identifier corresponding to the parsing result to the digital signal processor, so that the digital signal processor can locate and retrieve the corresponding parsing result in the memory based on the location index identifier.
[0015] Optionally, the operator loading module includes a third interaction unit;
[0016] The third interaction unit is used to send the operator identification information of the operator to be executed to the digital signal processor, so that the digital signal processor can call and execute the corresponding parsing result from the memory based on the operator identification information; the operator to be executed is included in the operator to be loaded.
[0017] Optionally, the host also includes an operator unloading module, which includes an idle operator determination unit and an unloading unit;
[0018] The idle operator determination unit is used to determine idle operator information;
[0019] The unloading unit is used to send the idle operator information to the digital signal processor, so that the digital signal processor can release the memory resources of the corresponding idle operator based on the idle operator information.
[0020] The idle operator determination unit is used to receive idle operator information;
[0021] or
[0022] The system receives operator execution information sent by the digital signal processor and determines the idle operator information based on the operator execution information.
[0023] According to one aspect of the embodiments of this application, a data processing system is provided, the system including a digital signal processor and a memory, and further including a host as provided in the above embodiments, the memory being communicatively connected to the host and the digital signal processor.
[0024] According to one aspect of the embodiments of this application, a data processing method is provided, the method comprising:
[0025] The operator to be loaded is parsed to obtain the corresponding parsing result;
[0026] The parsing result is stored in a memory, and the location information corresponding to the parsing result is sent to a digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the location information.
[0027] According to another aspect of the embodiments of this application, an electronic device is provided, the electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above data processing methods.
[0028] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the data processing methods described above.
[0029] The beneficial effects of the technical solutions provided in this application are:
[0030] By having the host computer handle the parsing and loading of operators, the digital signal processor (DSP) can focus on data processing, thus improving the performance and efficiency of data processing. This also reduces the complexity of writing DSP code, lowers development costs, and increases development efficiency.
[0031] Furthermore, by setting multiple operators to be loaded, multiple operators can be loaded at once, which improves the efficiency, flexibility, and scalability of operator loading, and further enhances the efficiency of data processing. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.
[0033] Figure 1 A system architecture diagram of a data processing system provided in this application embodiment;
[0034] Figure 2 A schematic diagram of the structure of a host provided in an embodiment of this application;
[0035] Figure 3 A schematic diagram of the structure of a host provided in another embodiment of this application;
[0036] Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application;
[0037] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0038] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0039] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a,” “an,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”
[0040] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0041] Currently, in the field of artificial intelligence, embedded neural network processing units, in addition to performing convolution operations, typically rely on Xtensa Vision DSP (a type of processor) to process image data for other operations, including softmax (a function), argmax (a function), NMS (Non-Maximum Suppression), and other operators.
[0042] In existing technologies, the application layer code is provided on the HOST side to call the operator, and the driver layer code is provided to perform DSP memory allocation and mapping, DSP firmware loading, and interaction between the HOST and the DSP. On the DSP side, functional modules such as operator loading, operator unloading, and operator execution are provided.
[0043] During the loading phase of the neural network model, multiple operators need to be loaded in advance. The DSP needs to load these operators into local memory or system RAM in the preparation phase so that the processing functions of these operators can be directly accessed during the operator execution phase.
[0044] In existing technologies, operator loading, operator parsing, operator execution, and operator unloading are all handled by digital signal processors, resulting in low data processing efficiency.
[0045] Furthermore, due to the inherent software design of DSPs, DSPs only support loading a single operator, meaning that only one operator can be loaded at a time. This prevents the loading of multiple operators simultaneously. When executing multiple operators, multiple loading operations are required, further reducing data processing efficiency and failing to fully utilize the overall performance of the DSP in data processing.
[0046] The host, data processing system, method, electronic device and storage medium provided in this application are intended to solve the above-mentioned technical problems of the prior art.
[0047] The technical solutions of this application and their effects are described below through several exemplary embodiments. It should be noted that the following embodiments can be referenced, borrowed from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.
[0048] Figure 1 A system architecture diagram of a data processing system provided in this application embodiment is shown below. Figure 1 As shown, the system includes a host 101, a memory 102, and a digital signal processor 103. The memory 102 is communicatively connected to both the host 101 and the digital signal processor 103. The host parses the operator to be loaded, obtains the corresponding parsing result, stores the parsing result in the memory, and sends the position information corresponding to the parsing result to the digital signal processor for the digital signal processor to store the position information.
[0049] In the data processing system provided in this application embodiment, the parsing and loading of operators are completely delegated to the HOST, breaking through the traditional framework that limits the parsing and loading of operators to the DSP. This enables the simultaneous loading of various different operators in the same stage, saving DSP performance and allowing the DSP to focus on data processing. This saves subsequent development costs, improves development efficiency, enhances the flexibility of operator loading, the efficiency of the data processing stage, and subsequent scalability.
[0050] The data processing system provided in this application embodiment can process data such as audio, video, and images. Based on different algorithm models, specific settings can be made for the operators to be loaded, and it can be applied to scenarios such as smart education, security operation, intelligent manufacturing, and smart home.
[0051] Figure 2 A schematic diagram of the structure of a host provided in an embodiment of this application is shown below. Figure 2 As shown, the host includes:
[0052] Operator parsing module 111 is used to parse the operators to be loaded and obtain the corresponding parsing results;
[0053] The operator loading module 121 is used to store the parsing result in the memory and send the position information corresponding to the parsing result to the digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the position information.
[0054] Specifically, an operator can be a basic operational unit in an algorithm model. An algorithm model, such as a neural network model, can include multiple operators. The operator to be loaded can be the operator that needs to be loaded, and the operator to be loaded can include convolution operators, matrix multiplication operators, pooling operators, fully connected operators, etc.
[0055] The number of operators to be loaded can be one or more. When there are multiple operators to be loaded, multiple operators can be loaded simultaneously to improve the efficiency of operator loading. Furthermore, the type and number of operators to be loaded can be customized according to actual needs or specific algorithm models to enhance the flexibility and scalability of operator loading.
[0056] After identifying the operator to be loaded, the operator parsing module in the host (hereinafter referred to as HOST) can parse the operator to be loaded and obtain the corresponding parsing result. One parsing result corresponds to one operator to be loaded, and each parsing result can include the code segment and data segment of the corresponding operator. The code segment can be the program text lines that perform a certain function, and the data segment can be the data input to the program for processing.
[0057] After parsing is complete, the operator loading module in the host stores the parsing result in the memory and sends the corresponding location information of the parsing result to the digital signal processor (DSP). The DSP can then retrieve the corresponding parsing result from the memory based on the received location information for execution. The location information of the parsing result indicates its position in the memory, which can be a shared storage medium between the host and the DSP. The DSP can be an Xtensa Vision DSP.
[0058] Optionally, the host can copy the parsing results from DDR (Double Data Rate) to a specified System RAM or Instruction RAM (Random Access Memory).
[0059] In this embodiment, by having the HOST handle the parsing and loading of operators, the DSP no longer needs to participate in data preparation, but can focus on data processing and concentrate resources on operator execution, thereby improving the performance of operator execution and the efficiency of data processing.
[0060] By having the host handle operator parsing and loading, the DSP only needs to execute operators, reducing the complexity of DSP code writing. Since DSP program code is manufacturer-customized, developers need to learn relevant knowledge beforehand, including memory allocation, memory layout, dynamic library compilation principles, and firmware loading, if they want to design software functions based on this. Reducing the complexity of DSP code writing further reduces system development costs and improves system development efficiency.
[0061] In this embodiment, the parsing and loading of operators are completed by the host, allowing the digital signal processor to focus on data processing, thereby improving the performance and efficiency of data processing; it also reduces the complexity of writing digital signal processor code, reduces development costs, and improves development efficiency.
[0062] Furthermore, by setting multiple operators to be loaded, multiple operators can be loaded at once, which improves the efficiency, flexibility, and scalability of operator loading, and further enhances the efficiency of data processing.
[0063] As an optional embodiment, the operator loading module includes a first interaction unit;
[0064] The location information includes the entry address. The first interaction unit is used to send the entry address corresponding to the parsing result to the digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the entry address.
[0065] Specifically, the operator loading module may include a first interaction unit. When the location information includes an entry address, the first interaction unit can send the entry address corresponding to the parsing result to the digital signal processor. The digital signal processor can send the received entry address to the memory. The memory returns the parsing result stored at the entry address to the digital signal processor, so as to realize the digital signal processor's call to the parsing result.
[0066] The entry address can be the actual address where the parsed result is stored in memory, and the correspondence between the parsed result and the entry address can be represented as a data table. Since there is a one-to-one correspondence between the operator to be loaded and the parsed result, the operator identifier of the operator to be loaded can also be used to identify the corresponding parsed result. An operator identifier can be assigned to each operator to be loaded, and a relationship table between the operator identifier and the entry address can be established. The corresponding entry address can be found through the operator identifier.
[0067] The correspondence between the parsing result and the entry address can be stored in the host or in a designated memory. This application does not limit the comparison of the embodiments.
[0068] As an optional embodiment, the operator loading module includes a second interaction unit;
[0069] The location information includes a location index identifier. The second interaction unit is used to send the location index identifier corresponding to the parsing result to the digital signal processor, so that the digital signal processor can locate and retrieve the corresponding parsing result in the memory based on the location index identifier.
[0070] Specifically, the operator loading module may include a second interaction unit. When the position information includes a position index identifier, the second interaction unit can send the position index identifier corresponding to the parsing result to the digital signal processor. The digital signal processor can send the received position index identifier to the memory. The memory locates the storage location of the parsing result according to the position index identifier and then returns the parsing result to the digital signal processor so that the digital signal processor can call the parsing result.
[0071] The location index identifier can be the identifier corresponding to the storage address of the parsing result. A data table between the location index identifier and the storage address can be established in advance. The memory can look up the corresponding storage address in the data table based on the location index identifier, and then obtain the parsing result stored at that storage address.
[0072] The correspondence between the parsing result and the location index identifier is similar to the correspondence between the parsing result and the entry address. For details, please refer to the previous embodiment. This embodiment will not be repeated here.
[0073] The data length of the location index identifier is usually less than the length of the actual address. By calling the parsing result through the location index identifier, the amount of data transmitted can be reduced, the data transmission speed can be increased, and thus the efficiency of the entire data processing process can be improved.
[0074] As an optional embodiment, the operator loading module includes a third interaction unit;
[0075] The third interaction unit is used to send the operator identification information of the operator to be executed to the digital signal processor, so that the digital signal processor can call and execute the corresponding parsing result from the memory based on the operator identification information; the operator to be executed is contained in the operator to be loaded.
[0076] Specifically, the operator loading module may also include a third interaction unit, which is used to issue instructions to control the digital signal processor to execute the operator.
[0077] First, determine the operators to be executed. These operators can be any operators that need to be executed. To ensure that the operators to be executed have been loaded in advance, they can be determined from the already loaded operators to be loaded.
[0078] Then, the operator identification information of the operator to be executed is sent to the digital signal processor. The operator identification information includes the identifiers of all operators to be executed, and the identifier of the operator to be executed can be a UUID (Universally Unique Identifier).
[0079] After receiving the operator identifier information, the digital signal processor (DSP) can determine the position information corresponding to the operator to be executed based on the correspondence between the operator identifier and the position information, and send the corresponding position information to the memory. The memory returns the corresponding parsing result to the DSP based on the received position information. The DSP processes the parsing result to complete the execution of the operator to be executed. The position information can be an entry address or a position index identifier.
[0080] The correspondence between operator identifiers and location information can be represented as a data table. Since one operator corresponds to one operator identifier and one operator corresponds to one parsing result, and the operator identifier can also be used to identify the parsing result, the correspondence between operator identifiers and location information can be stored in a shared memory between the host and the digital signal processor. During the operator loading and execution phases, either the host or the digital signal processor can access this memory to obtain the correspondence between operator identifiers and location information.
[0081] In this embodiment of the application, during the operator execution stage, the operator to be executed has been loaded in advance. After receiving the operator identification information, the digital signal processor can retrieve the parsing result from the memory and execute it. The digital signal processor can concentrate its resources to execute the operator, giving full play to the processing power of the digital signal processor and improving the performance and efficiency of data processing.
[0082] As an optional embodiment, Figure 3 A schematic diagram of the structure of a host provided in an embodiment of this application is shown below. Figure 3 As shown, the host 101 also includes an operator unloading module 131, which includes an idle operator determination unit and an unloading unit;
[0083] The idle operator determination unit is used to determine idle operator information;
[0084] The unloading unit is used to send idle operator information to the digital signal processor, so that the digital signal processor can release the memory resources of the corresponding idle operators based on the idle operator information.
[0085] Specifically, the host may also include an operator unloading module, which is used to unload infrequently used operators. The operator unloading module includes an idle operator determination unit and an unloading unit. The idle operator determination unit is used to determine idle operator information. Idle operators can be operators with low usage frequency. The idle operator information may include the operator identifier of the idle operator.
[0086] The unloading unit is used to send idle operator information to the digital signal processor. After receiving the idle operator information, the digital signal processor can release the memory resources of the corresponding idle operator so that it can be used next time.
[0087] In this embodiment of the application, by releasing the memory resources of operators with low usage frequency, the resource occupation of operators with low usage frequency is avoided, so that the digital signal processor can allocate more resources to execute operators, which is beneficial to improving the performance and efficiency of data processing.
[0088] As an optional embodiment, the idle operator determination unit is used to receive idle operator information;
[0089] or
[0090] It receives operator execution information sent by a digital signal processor and determines idle operator information based on the operator execution information.
[0091] Specifically, the determination of idle operator information can be achieved by receiving externally inputted idle operator information, which can be user-defined; or it can be adaptively generated based on the operator's execution status. The digital signal processor can send operator execution information to the host, and the host's idle operator determination module can determine the idle operator information based on the operator execution information. The operator execution information can include the number of times the operator is executed, the memory resources occupied by the operator, and the execution time of the operator.
[0092] The method for determining idle operator information can be based on the execution time or the number of times the operator is executed, by sorting the operators and taking the last few operators as idle operators; or a threshold can be set to take operators whose execution time or number of executions is less than the threshold as idle operators. The embodiments of this application do not limit the method for determining idle operator information.
[0093] Figure 4 This is a flowchart illustrating a data processing method provided in an embodiment of this application, as shown below. Figure 4 As shown, the method includes:
[0094] S101, parse the operator to be loaded and obtain the corresponding parsing result;
[0095] S102, the parsing result is stored in the memory, and the location information corresponding to the parsing result is sent to the digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the location information.
[0096] As an optional embodiment, the location information includes an entry address. Sending the location information corresponding to the parsing result to a digital signal processor (DSP) so that the DSP can retrieve the corresponding parsing result from the memory based on the location information includes:
[0097] The entry address corresponding to the parsing result is sent to the digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the entry address.
[0098] As an optional embodiment, the location information includes a location index identifier. Sending the location information corresponding to the parsing result to a digital signal processor (DSP) so that the DSP can retrieve the corresponding parsing result from the memory based on the location information includes:
[0099] The location index identifier corresponding to the parsing result is sent to the digital signal processor, so that the digital signal processor can locate and retrieve the corresponding parsing result in the memory based on the location index identifier.
[0100] As an optional embodiment, the method further includes:
[0101] The operator identifier information of the operator to be executed is sent to the digital signal processor, so that the digital signal processor can call and execute the corresponding parsing result from the memory based on the operator identifier information; the operator to be executed is included in the operator to be loaded.
[0102] As an optional embodiment, the method further includes:
[0103] Determine idle operator information;
[0104] The idle operator information is sent to the digital signal processor so that the digital signal processor can release the memory resources of the corresponding idle operator based on the idle operator information.
[0105] As an optional embodiment, determining the idle operator information includes:
[0106] Receive idle operator information;
[0107] or
[0108] The system receives operator execution information sent by the digital signal processor and determines the idle operator information based on the operator execution information.
[0109] The steps in the methods of the various embodiments of this application correspond to the actions performed by the modules in the apparatus of the various embodiments of this application. For a detailed description of each step of the method, please refer to the processing flow of each module in the apparatus shown above, which will not be repeated here.
[0110] This application provides an electronic device including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of the data processing method described above. Compared with related technologies, this device achieves the following: operator parsing and loading are completed by the host computer, allowing the digital signal processor to focus on data processing, thus improving data processing performance and efficiency; the complexity of writing digital signal processor code is reduced, development costs are decreased, and development efficiency is improved. Furthermore, by setting multiple operators to be loaded, multiple operators can be loaded at once, improving the efficiency, flexibility, and scalability of operator loading, further enhancing data processing efficiency.
[0111] In one alternative embodiment, an electronic device is provided, such as Figure 5 As shown, Figure 5 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this application.
[0112] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.
[0113] Bus 4002 may include a pathway for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0114] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.
[0115] The memory 4003 stores computer programs that execute embodiments of this application, and its execution is controlled by the processor 4001. The processor 4001 executes the computer programs stored in the memory 4003 to implement the steps shown in the foregoing method embodiments.
[0116] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.
[0117] The terms "first," "second," "third," "fourth," "1," "2," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown in the figures or text.
[0118] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.
[0119] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.
Claims
1. A host computer, characterized in that, Includes an operator parsing module and an operator loading module; The operator parsing module is used to parse the operator to be loaded and obtain the corresponding parsing result; The operator loading module is used to store the parsing result in the memory and send the position information corresponding to the parsing result to the digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the position information; The operator loading module is further configured to determine the operator to be executed from the loaded operators, read the correspondence between the operator identifier and the position information from the memory, and determine the position information corresponding to the operator to be executed based on the correspondence between the operator identifier and the position information and the operator identifier information of the operator to be executed. The correspondence between the operator identifier and the location information is stored in the memory; When the operator loading module sends the position information corresponding to the parsing result to the digital signal processor (DSP) so that the DSP can retrieve the corresponding parsing result from the memory based on the position information, it is specifically used for: The operator loading module sends the position information corresponding to the operator to be executed to the digital signal processor, so that the digital signal processor can retrieve the parsing result corresponding to the operator to be executed from the memory based on the position information corresponding to the operator to be executed, and execute the corresponding parsing result.
2. The host computer according to claim 1, characterized in that, The operator loading module includes a first interaction unit; The location information includes an entry address. When the operator loading module sends the location information corresponding to the parsing result to the digital signal processor so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the location information, the following steps are included: The first interactive unit sends the entry address corresponding to the parsing result to the digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the entry address.
3. The host computer according to claim 1, characterized in that, The operator loading module includes a second interaction unit; The location information includes a location index identifier. When the operator loading module sends the location information corresponding to the parsing result to the digital signal processor so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the location information, the following steps are included: The second interaction unit sends the location index identifier corresponding to the parsing result to the digital signal processor, so that the digital signal processor can locate and retrieve the corresponding parsing result in the memory based on the location index identifier.
4. The host computer according to any one of claims 1 to 3, characterized in that, It also includes an operator unloading module, which includes an idle operator determination unit and an unloading unit; The idle operator determination unit is used to determine idle operator information; The unloading unit is used to send the idle operator information to the digital signal processor, so that the digital signal processor can release the memory resources of the corresponding idle operator based on the idle operator information.
5. The host computer according to claim 4, characterized in that, The idle operator determination unit is used to receive idle operator information; or The system receives operator execution information sent by the digital signal processor and determines the idle operator information based on the operator execution information.
6. A data processing system, characterized in that, It includes a digital signal processor and a memory, and further includes a host as described in any one of claims 1 to 5, wherein the memory is communicatively connected to the host and the digital signal processor is communicatively connected to the digital signal processor.
7. A data processing method, characterized in that, include: The operator to be loaded is parsed to obtain the corresponding parsing result; The parsing result is stored in a memory, and the location information corresponding to the parsing result is sent to a digital signal processor, so that the digital signal processor can retrieve the corresponding parsing result from the memory based on the location information; The method further includes: The operator to be executed is determined from the operators that have been loaded. The correspondence between the operator identifier and the position information is read from the memory. Based on the correspondence between the operator identifier and the position information and the operator identifier information of the operator to be executed, the position information corresponding to the operator to be executed is determined. The correspondence between the operator identifier and the position information is stored in the memory. The step of storing the parsing result in a memory and sending the location information corresponding to the parsing result to a digital signal processor (DSP) so that the DSP can retrieve the corresponding parsing result from the memory based on the location information includes: The position information corresponding to the operator to be executed is sent to the digital signal processor, so that the digital signal processor can retrieve the parsing result corresponding to the operator to be executed from the memory based on the position information corresponding to the operator to be executed, and execute the corresponding parsing result.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method of claim 7.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 7.
Citation Information
Patent Citations
Safety communication method and system based on dual-core processor
CN102999731A