Bfm-based simulation system, verification method, device and medium thereof

Abstract

The application discloses a simulation system based on BFM, a verification method, equipment and medium thereof, and belongs to the field of chip verification.The simulation system comprises a compiling module, a BFM module and a to-be-verified module.The compiling module is used for editing a test task required for verifying a to-be-verified code stored in a chip memory, and compiling the test task into a test instruction.The BFM module is used for reading the test instruction, generating a test vector according to the test instruction, and sending the test vector to the to-be-verified module.The to-be-verified module is used for verifying the to-be-verified code based on the received test vector, and generating a verification result.The simulation system based on BFM developed by the application is suitable for verifying all chip functions, the simulation system improves the chip verification speed, shortens the development cycle, the to-be-verified code stored in the chip memory is verified by using a preset development language to write a test task, a test vector required for verification is quickly and efficiently established, the verification difficulty of a super large scale chip is reduced, the real running environment of chip design verification is expanded, and the accuracy of the verification result is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip function verification technical field, and particularly relates to a simulation system based on BFM and a verification method, equipment and medium thereof. BACKGROUND

[0002] With the continuous improvement of chip product design rules and complexity, and the continuous acceleration of chip product update speed in the market, the electronic market is increasingly strict on the lead time required for the chip product to be listed on the market. In the entire life cycle of chip product development, verification accounts for a large part of the overall chip development cycle.

[0003] Nowadays, two methods are mainly used to verify the function of the chip product or the design code of the chip product. The first method is a simulation verification method based on simulation software (for example, ModelSim), which does not require the support of other hardware devices except the host computer, but the software simulation is slow and inefficient. The second method is a verification method based on FPGA (Field Programmable Gate Array, Field Programmable Gate Array) prototype board, which is fast in prototype verification, but in the hardware environment, DUV (Design Under Verification) needs the input of test vectors, and without the use of BFM (bus function module), it is difficult to generate test vectors, and the test efficiency is low and the difficulty is high. SUMMARY

[0004] The technical problem to be solved by the present application is to overcome the defects that the chip product verification method in the prior art cannot simultaneously meet the requirements of fast speed and low difficulty, and to provide a simulation system based on BFM and a verification method, equipment and medium thereof.

[0005] The present application solves the above technical problems by the following technical solutions:

[0006] In a first aspect, the present application provides a simulation system based on BFM, which comprises a compiling module, a BFM module and a to-be-verified module, the BFM module and the to-be-verified module are established on an FPGA verification platform.

[0007] The compiling module is configured to edit a test task required for verifying a to-be-verified code stored in a chip memory, and compile the test task into a test instruction.

[0008] The BFM module is configured to read the test instruction, generate a test vector according to the test instruction, and then send the test vector to the to-be-verified module.

[0009] The to-be-verified module is configured to verify the to-be-verified code based on the received test vector, and generate a verification result.

[0010] Preferably, the to-be-verified module comprises a plurality of to-be-verified units, and the compiling module comprises an instruction setting unit, a task setting unit and a code dividing unit.

[0011] The instruction setting unit is configured to set original instructions according to a preset language.

[0012] The task setting unit is configured to set a verification task for verifying the to-be-verified code according to the original instructions.

[0013] The code dividing unit is configured to divide the to-be-verified code into a plurality of sub-codes, and store each of the sub-codes in the to-be-verified units.

[0014] Preferably, the simulation system further comprises at least one storage module, which is in communication connection with the BFM module and the to-be-verified module.

[0015] The storage module is configured to store target data generated in a verification process of the to-be-verified code.

[0016] Preferably, the to-be-verified module is further configured to send the verification result to the BFM module.

[0017] The BFM module is further configured to store the verification result in the storage module after analyzing the verification result.

[0018] Preferably, the BFM module comprises a control unit and at least one BFM unit, and the control unit and the BFM unit are in communication connection.

[0019] The control unit is configured to generate and send verification data after analyzing the test instructions.

[0020] The BFM unit is configured to generate the test vector according to the verification data and a preset bus protocol, and send the test vector to the to-be-verified module.

[0021] Preferably, the BFM module and the to-be-verified module are in communication connection through at least one of an ultra-high-speed pin, a high-speed pin and a low-speed pin.

[0022] Preferably, the simulation system further comprises a monitoring module.

[0023] The monitoring module is configured to display state data in a verification process of the to-be-verified code and the verification result.

[0024] In a second aspect, the present application provides a verification method of a BFM-based simulation system, applied to the BFM-based simulation system of the first aspect, and the verification method comprises:

[0025] determining, on a software compiling platform, test instructions required for compiling a to-be-verified code stored in a verification chip;

[0026] reading the test instructions by using a BFM module, and generating test vectors according to the test instructions and sending the test vectors to a to-be-verified module; the BFM module and the to-be-verified module are established on an FPGA verification platform, and the BFM-based simulation system comprises the FPGA verification platform and the software compiling platform;

[0027] verifying the to-be-verified code according to the test vectors by using the to-be-verified module, and generating verification results.

[0028] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and capable of running on the processor, and the processor implements the verification method of the BFM-based simulation system of the second aspect when executing the computer program.

[0029] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the verification method of the BFM-based simulation system of the second aspect.

[0030] The positive progress effect of the present application is that the present application discloses a BFM-based simulation system and a verification method, device and medium thereof, the simulation system comprising a compiling module, a BFM module and a to-be-verified module; the compiling module is used for compiling test instructions required for a to-be-verified code stored in a verification chip; the BFM module is used for reading the test instructions, generating test vectors according to the test instructions, and sending the test vectors to the to-be-verified module; and the to-be-verified module is used for verifying the to-be-verified code based on the received test vectors, and generating verification results. The BFM-based simulation system developed by the present application is suitable for verification of all chip functions, and the simulation system improves the speed of chip verification and shortens the chip development cycle; the to-be-verified code stored in a chip is verified by using a preset development language to write test tasks, test vectors required for verification are quickly and efficiently established, and the verification difficulty of a super large scale chip is reduced; the real running environment of chip design verification is expanded, and the accuracy of verification results is improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 FIG. 1 is a module schematic diagram of the BFM-based simulation system of the first embodiment of the present application.

[0032] Figure 2This is a schematic diagram illustrating the application of the simulation system in Embodiment 1 of the present invention.

[0033] Figure 3 This is a schematic diagram of the architecture of the BFM-based simulation system according to Embodiment 1 of the present invention.

[0034] Figure 4 This is a flowchart of the verification method for the BFM-based simulation system according to Embodiment 2 of the present invention.

[0035] Figure 5 This is a simulation flowchart of the verification method of the BFM-based simulation system in Embodiment 2 of the present invention.

[0036] Figure 6 This is a schematic diagram of the hardware structure of the electronic device according to Embodiment 3 of the present invention. Detailed Implementation

[0037] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.

[0038] Example 1

[0039] like Figure 1 As shown, this embodiment provides a BFM-based simulation system, which includes a compilation module 110, a BFM module 120, and a module to be verified 130. The BFM module 120 and the module to be verified 130 are built on an FPGA verification platform.

[0040] The compilation module 110 is used to edit the test tasks required to verify the code to be verified stored in the chip, and compile the test tasks into test instructions;

[0041] BFM module 120 is used to read test instructions, generate test vectors based on the test instructions, and then send the test vectors to the module to be verified 130.

[0042] The module to be verified 130 is used to verify the code to be verified based on the received test vectors and generate verification results.

[0043] The BFM module 120 and the module to be verified 130 are connected via at least one of ultra-high speed pins, high speed pins, and low speed pins.

[0044] Specifically, the compiling module 110 sets the test instruction according to a preset high-level language. For example, the high-level language includes keywords such as always begin…End, which means that the statements in the keyword always are executed in sequence, the always is executed in parallel with the initial, and after the statements in the always are executed, the initial is executed again from the beginning. The keyword can also be initial begin…End, which means that the statements in the keyword initial are executed in sequence, the initial is executed in parallel with the always, and the statements in the initial are executed only once. The keyword can also be integer name value, which means that an integer variable name is defined, and the initial value is value.

[0045] The test instruction can include a clock generation instruction, a reset generation instruction, a register write instruction, a register read instruction, a bus write instruction, a bus read instruction, a start co-simulation instruction, a stop co-simulation instruction, a register read data comparison instruction, a bus read data comparison instruction, and a delay instruction. Specifically, the clock generation instruction is represented as clk_gen parameter1 parameter2, parameter1 represents a clock sequence number, which ranges from 0 to 31, and parameter2 represents a clock frequency, which is in Hz and ranges from 1 to 10^9. The reset generation instruction is represented as reset_gen parameter1 parameter2, parameter1 represents a reset sequence number, which ranges from 0 to 31, and parameter2 represents a level selection, 0 representing that the reset signal is 0, and 1 representing that the reset signal is 1. The register write instruction is represented as reg_wr parameter1 parameter2 parameter3, parameter1 represents a register write address, which is 64-bit addressing space, parameter2 represents register write data, which is 64-bit data, and parameter3 represents a bus selection, 0 representing SPI, 1 representing I2C, 2 representing PCI, 3 representing AXI, and a total of 1024 bus protocol selections. The register read instruction is represented as reg_rd parameter1 parameter2, parameter1 represents a register read instruction, which is 64-bit addressing space, and parameter2 represents a data storage location, which is 64-bit addressing space. Parameter3 represents a bus selection, 0 representing SPI, 1 representing I2C, 2 representing PCI, 3 representing AXI, and a total of 1024 bus protocol selections.

[0046] The BFM module 120 reads the test instructions, generates test vectors corresponding to a plurality of different test tasks, and sends the test vectors to the to-be-verified module 130 through one of the super-speed pins, the high-speed pins and the low-speed pins. The to-be-verified module 130 receives the test vectors and generates test results for each test task. In this way, large-scale chip code can be distributed and run on a limited number of FPGA verification platforms, and the comprehensive BFM module 120 can be downloaded to the FPGA verification platform at the same time and connected to the to-be-verified module 130 including the DUV. The BFM module 120 and the to-be-verified module 130 are integrated in the FPGA verification platform and run at the same time, which greatly improves the speed of chip code verification.

[0047] The to-be-verified module 130 includes a plurality of to-be-verified units 131, and the compiling module 110 includes an instruction setting unit 111, a task setting unit 112 and a code division unit 113.

[0048] The instruction setting unit 111 is configured to write original instructions according to a preset language.

[0049] The task setting unit 112 is configured to set verification tasks for verifying the to-be-verified code according to the original instructions.

[0050] The code division unit 113 is configured to divide the to-be-verified code into a plurality of sub-codes, and store each sub-code in the to-be-verified unit 131.

[0051] Specifically, the instruction setting unit 111 writes a plurality of original instructions such as clock generation instructions, reset generation instructions and write register instructions according to the written verification tasks, the BFM library, the properties of the FPGA verification platform and the verification data, and according to the preset language of the simulation system. The task setting unit 112 writes a plurality of verification tasks required for chip code verification according to the original instructions, and arranges the plurality of verification tasks in the form of a queue. After the to-be-verified code stored in the chip is segmented according to functions, a plurality of sub-codes are generated and downloaded to the to-be-verified unit 131.

[0052] The simulation system further includes at least one storage module 140, which is in communication connection with the BFM module 120 and the to-be-verified module 130.

[0053] The storage module 140 is configured to store target data generated in a verification process of the to-be-verified code.

[0054] Specifically, as Figure 1As shown, the simulation system can include 4 storage modules 140, 3 storage modules 140 are respectively connected with the to-be-verified unit 131 in communication, the storage module 140 can store the target data generated by the to-be-verified unit 131 in the verification process, and the code verification result of each to-be-verified unit. 1 storage module 140 is connected with the BFM module 120 in communication, and the storage module 140 can store the comparison result of the BFM module 120 comparing the verification data and the expected data. This way ensures that the target data generated by the to-be-verified code verification process, which helps users to monitor the verification process in real time, improves the verification efficiency of the chip code.

[0055] The to-be-verified module 130 is also configured to send the verification result to the BFM module 120.

[0056] The BFM module 120 is also configured to store the verification result in the storage module 140 after analyzing the verification result.

[0057] The BFM module 120 includes a control unit 121 and at least one BFM unit 122, and the control unit 121 and the BFM unit 122 are connected in communication.

[0058] The control unit 121 is configured to generate and send verification data after analyzing the test instruction.

[0059] The BFM unit 122 is configured to generate a test vector according to the verification data and a preset bus protocol, and send the test vector to the to-be-verified module 130.

[0060] Specifically, the control unit 121 automatically generates the code recognizable by the BFM FPGA, i.e. the verification data, after analyzing the test instruction.

[0061] The BFM unit 122 automatically calls the routing tool of the FPGA manufacturer, i.e. the preset bus protocol, to generate the test vector.

[0062] The simulation system further includes a monitoring module 150.

[0063] The monitoring module 150 is configured to display the state data and the verification result in the verification process of the to-be-verified code.

[0064] Specifically, the monitoring module 150 can obtain the verification result including the verification state and the verification data from the FPGA verification platform, and the cache data stored in the ILA in the verification process of the to-be-verified module 130 on the to-be-verified code, and the monitoring module 150 displays the verification result and the cache data in the form of text, numbers and waveform diagrams.

[0065] As Figure 2As shown, this is an existing pure software simulation system. This simulation system only includes a software task compiler, which includes multiple different tasks (TASK shown in the figure), a BFM module, and DUV (Design Under Verification). It does not set up a hardware verification platform, which makes the pure software simulation slow and inefficient when verifying large chips.

[0066] In one embodiment, such as Figure 3 As shown, the BFM-based simulation system comprises two parts: a software task compiler and a hardware verification platform. The software task compiler includes multiple different tasks (shown in the figure), each designed to verify a specific function of the DUV. Verification of a function can be achieved through the collaborative efforts of several tasks. The task is written using a predefined high-level language to express a specific transaction. For example, "reg_wr 0x0 0x5a PCI" means writing data 0x5a to address 0x0 using the PCI bus; "delay 0 1000" means a delay of 1000 nanoseconds; and "reset_gen 0 1" means setting the reset signal with sequence number 0 to 1. Based on all the tasks required for verifying a specific function, the system decomposes data and instructions according to the predefined high-level language's instruction set, generating data queues and instruction queues.

[0067] The host computer and the hardware verification platform communicate via Ethernet. The host computer sends data and instruction queues to the hardware verification platform, while the hardware verification platform uploads the DUV verification status and data to the host computer. The hardware verification platform consists of two parts: a BFM FPGA and a DUV FPGA. The BFM FPGA includes a BFM controller and multiple BFMs. Each BFM has a fixed and unified interface and BFM controller protocol, and all BFMs are connected in parallel. The BFM controller reads instructions and data from the DDR (data storage), parses the instructions, and sends the verification data to the corresponding BFM according to the instructions. The BFM compares the real-time received verification data with the expected data in the DDR and writes the final verification result back to the DDR. The BFM can also generate multiple test vectors from the data and instructions sent by the BFM controller according to a preset bus protocol and send them to the DUV FPGA. Furthermore, the BFM can receive test results from the DUV FPGA, parse the test results according to a preset bus protocol, and send the parsed data to the BFM controller.

[0068] The host computer software uses the algorithm and combines the structure of the hardware verification platform, can be stored in the chip memory according to the function of the code to be verified after the segmentation, respectively, in turn, download to the corresponding DUV-FPGA for storage. Figure 3 ILA (in-line logic analyzer) in the above is a Soft IP, used for saving necessary signals to generate waveforms, facilitating deeper debugging of each DUV.

[0069] In the embodiment, a simulation system based on BFM is provided, which is suitable for verification of all chip functions, and the simulation system improves the speed of chip verification and shortens the chip development cycle; the preset development language is used to compile the to-be-verified code stored in the chip memory, test vectors required for verification are quickly and efficiently established, and the verification difficulty of the super large scale chip is reduced; the real running environment of chip design verification is expanded, and the accuracy of the verification result is improved.

[0070] Embodiment 2

[0071] As shown in Figure 4 The embodiment provides a verification method of a simulation system based on BFM, and the control method is applied to the simulation system based on BFM in embodiment 1, and the verification method comprises the following steps of:

[0072] S11, determining a test instruction required for compiling and verifying the to-be-verified code stored in the chip memory;

[0073] S12, reading the test instruction by using the BFM module, and generating a test vector according to the test instruction and sending the test vector to a to-be-verified module; the BFM module and the to-be-verified module are established on an FPGA verification platform; the simulation system based on BFM comprises the FPGA verification platform and a software compiling platform;

[0074] S13, verifying the to-be-verified code according to the test vector by the to-be-verified module, and generating a verification result.

[0075] The test instruction can include a clock generation instruction, a reset generation instruction, a write register instruction, a register read instruction, a bus write instruction, a bus read command instruction, a start co-simulation instruction, a stop co-simulation instruction, a register read data comparison instruction, a bus read data comparison instruction and a delay instruction.

[0076] After reading the test instructions, the BFM module generates test vectors corresponding to multiple different test tasks. These test vectors are then sent to the module under test (DUT) via one of three pins: ultra-high-speed, high-speed, or low-speed. The DUT receives the test vectors, verifies them, and generates test results for each test task. This method allows large-scale chip code to be distributed and run across a limited number of FPGA verification platforms. The synthesized BFM module is simultaneously downloaded to the FPGA verification platform and connected to the DUT, including the DUV (Distributed Virtual Machine). Integrating the BFM module and the DUT within the FPGA verification platform and running them concurrently significantly improves the speed of chip code verification.

[0077] In one embodiment, such as Figure 5 As shown, task programming refers to writing verification tasks according to the keywords specified in the programming specification. This specification describes the instruction set and language used when performing chip verification using a BFM-based simulation system. During task compilation, based on the written verification task, combined with the BFM library, the attributes of the FPGA verification platform, and the verification data, the verification task is compiled according to the instruction set of the BFM-based simulation system, and is divided into sections. For example, the verification task can be divided into the instructions and data that the BFM controller can execute, the various corresponding BFMs of the BFM controller, the clock network and reset system, the pin configuration of all FPGAs on the FPGA verification platform, the segmentation of the chip code to be verified, the embedding of ILA IP, and the generation of monitoring window requirements.

[0078] The BFM command or data download operation indicates that various BFM commands and data generated during task compilation are downloaded via the network port to the DDR memory connected to the BFM-FPGA, allowing the BFM controller to read and use them. The "Start Verification" operation indicates that after receiving the command or data download completion instruction, the BFM controller reads the instructions to drive various transmitting BFM actions, and the BFM generates test vectors to drive DUV actions. Simultaneously, the DUV also sends test results to various receiving BFMs via ultra-high-speed pins, high-speed key pins, or low-speed pins for the BFM controller to judge and store.

[0079] After the test task is compiled, BFM-based instructions and test data are generated. The host computer software performs code segmentation on the DUV according to the test task. The host computer downloads the BFM-based instructions and test data to the FPGA verification platform. The FPGA verification platform performs real-time verification according to the BFM instructions and sends the running results to the host computer. The host computer monitors the received running results in real time.

[0080] The embodiment provides a verification method of a BFM-based simulation system, and the verification method is suitable for all chip functions in the developed BFM-based simulation system, the simulation system improves the chip verification speed and shortens the chip development cycle; the preset development language is used for writing a test task to verify the to-be-verified code stored in the chip memory, the test vector required for verification is quickly and efficiently established, and the verification difficulty of the super large scale chip is reduced; the real running environment of chip design verification is expanded, and the accuracy of the verification result is improved.

[0081] Embodiment 3

[0082] Figure 6 A structural schematic diagram of an electronic device is provided in the embodiment. The smart helmet includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the verification method of the BFM-based simulation system of embodiment 2 when implementing the program, Figure 6 The electronic device 60 shown is merely an example and should not impose any limitation on the functions and use range of the embodiment of the present application.

[0083] The electronic device 60 can be in the form of a general computing device, for example, it can be a server device. The components of the electronic device 60 can include but are not limited to: the above-mentioned at least one processor 61, the above-mentioned at least one memory 62, and a bus 63 connecting different system components including the memory 62 and the processor 61.

[0084] The bus 63 includes a data bus, an address bus and a control bus.

[0085] The memory 62 can include a volatile memory, such as a random access memory (RAM) 621 and / or a cache memory 622, and can further include a read-only memory (ROM) 623.

[0086] The memory 62 can further include programs / utilities 625 having a set of (at least one) program modules 624, such as an operating system, one or more application programs, other program modules, and program data, each of which or some combination of which can include the implementation of a network environment.

[0087] The processor 61 performs various function applications and data processing by running the computer program stored in the memory 62, such as the verification method of the BFM-based simulation system of embodiment 2.

[0088] The electronic device 60 can also communicate with one or more external devices 64 such as a keyboard or a pointing device, among others. This communication can occur via Input / Output (I / O) interface 65. Still yet, the model generation electronic device 60 can communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or the public network, such as the Internet) via network adapter 66. As depicted, network adapter 66 communicates with the other components of the model generation electronic device 60 via bus 63. It should be appreciated that although not shown, other hardware and / or software modules could be used in conjunction with the model generation electronic device 60. Such as, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0089] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the foregoing detailed description, such a division is merely exemplary and not mandatory. Indeed, according to embodiments of the application, the features and functionalities of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functionalities of one unit / module described above can be further divided into units / modules embodied by several units / modules.

[0090] Embodiment 4

[0091] The embodiment provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement or realize the verification method of the BFM-based simulation system of embodiment 2.

[0092] More specifically, the readable storage medium can include, but is not limited to, a portable disc, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0093] In possible embodiments, the application can also be implemented in the form of a program product, which includes program codes for causing terminal equipment to execute the verification method of the BFM-based simulation system of embodiment 2 when the program product is run on the terminal equipment.

[0094] The program codes for executing the application can be written in any combination of one or more programming languages, and can be executed entirely on the user equipment, partly on the user equipment and partly on a remote equipment, or entirely on a remote equipment, as a stand-alone software package, or partly on the user equipment and partly on a remote equipment.

[0095] Although the specific embodiments of the present application have been described above, it is understood by those skilled in the art that the present application is only illustrated by way of example, and the scope of protection of the present application is defined by the appended claims. Those skilled in the art can make various changes or modifications to the embodiments without departing from the principles and essence of the present application, and such changes and modifications fall within the scope of protection of the present application.

Claims

1. A BFM-based simulation system, characterized by, The simulation system comprises a compiling module, a BFM module and a to-be-verified module, and the BFM module and the to-be-verified module are established on an FPGA verification platform; The compiling module is configured to edit a test task required for verifying a to-be-verified code stored in a verification chip memory and compile the test task into a test instruction; the test instruction comprises a clock generation instruction, a reset generation instruction, a write register instruction, a register read instruction, a bus write instruction, a bus read instruction, a start co-simulation instruction, a stop co-simulation instruction, a register read data comparison instruction, a bus read data comparison instruction and a delay instruction; The BFM module is configured to read the test instruction, generate a test vector according to the test instruction, and send the test vector to the to-be-verified module; The to-be-verified module is configured to verify the to-be-verified code based on the received test vector and generate a verification result; The to-be-verified module comprises a plurality of to-be-verified units, and the compiling module comprises an instruction setting unit, a task setting unit and a code division unit; The instruction setting unit is configured to write an original instruction according to a preset language; The task setting unit is configured to set a verification task for verifying the to-be-verified code according to the original instruction; The code division unit is configured to divide the to-be-verified code into a plurality of sub-codes and store each sub-code in the to-be-verified unit.

2. The BFM-based simulation system of claim 1, wherein, The simulation system further comprises at least one storage module, which is in communication connection with the BFM module and in communication connection with the to-be-verified module; The storage module is configured to store target data generated in a verification process of a to-be-verified code.

3. The BFM-based simulation system according to claim 2, wherein The to-be-verified module is further configured to send the verification result to the BFM module; The BFM module is further configured to store the verification result in the storage module after analyzing the verification result.

4. The BFM-based simulation system of claim 1, wherein, The BFM module comprises a control unit and at least one BFM unit, and the control unit and the BFM unit are in communication connection; The control unit is configured to analyze the test instruction, generate and send verification data The BFM unit is configured to generate the test vector according to the verification data and a preset bus protocol and send the test vector to the to-be-verified module.

5. The BFM-based simulation system of claim 1, wherein, The BFM module and the to-be-verified module are in communication connection through at least one of an ultra-high-speed pin, a high-speed pin and a low-speed pin.

6. The BFM-based simulation system of claim 1, wherein, The simulation system further comprises a monitoring module; The monitoring module is configured to display state data in a verification process of the to-be-verified code and the verification result.

7. A method for verifying a BFM-based simulation system, the method comprising: The verification method is applied to the BFM-based simulation system according to any one of claims 1-6, and the verification method comprises: determining a test instruction required for verifying a to-be-verified code stored in a verification chip memory on a software compiling platform; The BFM module reads the test instruction and generates a test vector according to the test instruction and sends the test vector to a module to be verified; the BFM module and the module to be verified are established on an FPGA verification platform, and the BFM-based simulation system comprises the FPGA verification platform and the software compiling platform; The module to be verified verifies the code to be verified according to the test vector and generates a verification result; the test instruction comprises a clock generation instruction, a reset generation instruction, a write register instruction, a register read instruction, a bus write instruction, a bus read instruction, a start co-simulation instruction, a stop co-simulation instruction, a register read data comparison instruction, a bus read data comparison instruction and a delay instruction.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to realize the verification method of the BFM-based simulation system according to claim 7.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the verification method of the BFM-based simulation system according to claim 7.

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