GOA circuit and display panel

Abstract

The present application provides a GOA circuit and a display panel. The GOA circuit includes a plurality of cascaded GOA units, and the GOA unit includes a first node control module, a second node control module, a delay suppression module, and an output module. Among them, the delay suppression module outputs the stable potential of the second node to the third node. Compared with the existing GOA circuit, the GOA circuit of the present application uses the delay suppression module to output the stable potential of the second node to the third node, and then outputs it to the third node after the potential of the second node is stable, so that the signal output by the output module will not have a falling edge step.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a GOA circuit and a display panel. Background Art

[0002] The gate driver on array (GOA) technology integrates the gate driver circuit on the array substrate of the display panel to achieve a row-by-row scanning drive mode. This drive technology can save the gate driver, has the advantages of reducing production costs and realizing a narrow frame design of the panel.

[0003] However, the signal output by the existing GOA circuit has a falling edge step, and the threshold voltage of the transistor will shift during the operation of the GOA circuit; due to the falling edge characteristics of the signal output by the GOA circuit, the threshold voltage shift will affect the normal output of the falling edge, causing the falling edge step to change with the threshold voltage shift, thereby affecting the output stability of the GOA circuit. Summary of the invention

[0004] The present application provides a GOA circuit and a display panel, which can solve the technical problem that due to the falling edge characteristics of the signal output by the GOA circuit, the threshold voltage offset will affect the normal output of the falling edge, causing the falling edge step to change with the threshold voltage offset, thereby affecting the output stability of the GOA circuit.

[0005] In a first aspect, the present application provides a GOA circuit, which includes a plurality of cascaded GOA units, wherein the GOA units include a first node control module, a second node control module, a delay suppression module, and an output module; wherein:

[0006] The first node control module is electrically connected to the first node and to the second node control module, and the first node control module is used to control the potential of the first node;

[0007] The second node control module is electrically connected to the second node and to the first node control module, and the second node control module is used to control the potential of the second node;

[0008] The delay suppression module is electrically connected to the second node and the third node, and the delay suppression module is used to output the stable potential of the second node to the third node;

[0009] The output module is electrically connected to the first node, the third node and the signal output terminal of this stage, and is used to control the potential of the signal output terminal of this stage under the control of the potential of the first node and the potential of the third node.

[0010] In the GOA circuit provided in the present application, the first node control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor;

[0011] The gate of the first transistor is connected to a first clock signal, the source of the first transistor is connected to a first constant voltage signal, and the drain of the first transistor is electrically connected to the source of the second transistor, the drain of the fifth transistor, and the second node control module;

[0012] The gate of the second transistor is connected to the first constant voltage signal, and the drain of the second transistor is electrically connected to the gate of the third transistor and the first end of the first capacitor;

[0013] The source of the third transistor is connected to the second clock signal, and the drain of the third transistor is electrically connected to the source of the fourth transistor and the second end of the first capacitor;

[0014] The gate of the fourth transistor is connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the first node and the drain of the sixth transistor;

[0015] The gate of the fifth transistor is electrically connected to the second node control module, and the source of the fifth transistor is connected to the first clock signal;

[0016] The gate of the sixth transistor is electrically connected to the second node control module, and the source of the sixth transistor is connected to the second constant voltage signal.

[0017] In the GOA circuit provided in the present application, the second node control module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor;

[0018] The gate of the seventh transistor is connected to the first clock signal, the source of the seventh transistor is electrically connected to the previous stage signal output terminal, and the drain of the seventh transistor is electrically connected to the source of the eighth transistor and the first node control module;

[0019] The gate of the eighth transistor is connected to the first constant voltage signal, and the drain of the eighth transistor is electrically connected to the second node, the gate of the ninth transistor and the first end of the second capacitor;

[0020] The source of the ninth transistor is connected to the second clock signal, and the drain of the ninth transistor is electrically connected to the drain of the tenth transistor and the second end of the second capacitor;

[0021] The gate of the tenth transistor is electrically connected to the first node control module, and the source of the tenth transistor is connected to the second constant voltage signal.

[0022] In the GOA circuit provided in the present application, the second node control module also includes an eleventh transistor; the gate of the eleventh transistor is connected to the reset control signal, the source of the eleventh transistor is connected to the second constant voltage signal, and the drain of the eleventh transistor is electrically connected to the drain of the seventh transistor, the source of the eighth transistor and the first node control module.

[0023] In the GOA circuit provided in the present application, the delay suppression module includes a twelfth transistor; the gate of the twelfth transistor is connected to the clock signal, the source of the twelfth transistor is electrically connected to the second node, and the drain of the twelfth transistor is electrically connected to the third node.

[0024] In the GOA circuit provided in the present application, the seventh transistor and the twelfth transistor are both P-type transistors, and the first clock signal and the clock signal are signals with the same period and opposite phases.

[0025] In the GOA circuit provided in the present application, the seventh transistor is a P-type transistor, the twelfth transistor is an N-type transistor, and the first clock signal and the clock signal are the same signal.

[0026] In the GOA circuit provided in the present application, the delay suppression module also includes a third capacitor, a first end of the third capacitor is electrically connected to the third node, and a second end of the third capacitor is electrically connected to the signal output end of the current stage.

[0027] In the GOA circuit provided in the present application, the output module includes a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0028] The gate of the thirteenth transistor is electrically connected to the third node, the source of the thirteenth transistor is connected to the first constant voltage signal, and the drain of the thirteenth transistor is electrically connected to the current-stage signal output terminal;

[0029] The gate of the fourteenth transistor is electrically connected to the first node and the first end of the fourth capacitor, the source of the fourteenth transistor is connected to the second constant voltage signal and is electrically connected to the second end of the fourth capacitor, and the drain of the fourteenth transistor is electrically connected to the signal output end of this stage.

[0030] In a second aspect, the present application also provides a display panel, which includes the GOA circuit described above.

[0031] The present application provides a GOA circuit and a display panel. The GOA circuit includes a plurality of cascaded GOA units, and the GOA unit includes a first node control module, a second node control module, a delay suppression module, and an output module. Among them, the delay suppression module outputs the stable potential of the second node to the third node. Compared with the existing GOA circuit, the GOA circuit of the present application uses the delay suppression module to output the stable potential of the second node to the third node, and then outputs it to the third node after the potential of the second node is stable, so that the signal output by the output module will not have a falling edge step. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A first structural schematic diagram of a GOA unit in a GOA circuit provided in an embodiment of the present application;

[0033] Figure 2 for Figure 1 A circuit diagram of a first node control module in the GOA unit shown;

[0034] Figure 3 for Figure 1 A circuit diagram of a second node control module in the GOA unit shown;

[0035] Figure 4 for Figure 1 Another circuit diagram of the second node control module in the GOA unit shown;

[0036] Figure 5 for Figure 1 A circuit diagram of a delay suppression module in the GOA unit shown;

[0037] Figure 6 for Figure 1 Another circuit diagram of the delay suppression module in the GOA unit shown;

[0038] Figure 7 for Figure 1 The circuit diagram of the output module in the GOA unit shown;

[0039] Figure 8 for Figure 1 The complete circuit diagram of the GOA unit shown;

[0040] Fig. 9 for Figure 8 A timing diagram of the complete circuit of the GOA unit shown;

[0041] Fig.10 for Figure 1 Another complete circuit schematic diagram of the GOA unit shown;

[0042] Fig.11A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] In addition, the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish different objects rather than to describe a specific order. The terms "include", "have" and any variations thereof are intended to cover non-exclusive inclusions.

[0045] The present application provides a GOA circuit and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.

[0046] See also Figure 1 , Figure 1 Schematic diagram of a first structure of a GOA unit 100 in a GOA circuit provided in an embodiment of the present application. Figure 1 As shown, in the embodiment of the present application, the GOA circuit includes a multi-stage cascaded GOA unit 100. The GOA unit 100 includes a first node Q control module 101, a second node P control module 102, a delay suppression module 103 and an output module 104.

[0047] The first node Q control module 101 is electrically connected to the first node Q and to the second node P control module 102. The first node Q control module 101 is used to control the potential of the first node Q.

[0048] The second node P control module 102 is electrically connected to the second node P and to the first node Q control module 101. The second node P control module 102 is used to control the potential of the second node P.

[0049] The delay suppression module 103 is electrically connected to the second node P and the third node K. The delay suppression module 103 is used to output the stable potential of the second node P to the third node K.

[0050] The output module 104 is electrically connected to the first node Q, the third node K and the current signal output terminal OUT. The output module 104 is used to control the potential of the current signal output terminal OUT under the control of the potential of the first node Q and the potential of the third node K.

[0051] Compared with the existing GOA circuit, the GOA circuit of the embodiment of the present application uses the delay suppression module 103 to output the stable potential of the second node P to the third node K, and then outputs it to the third node K after the potential of the second node P is stabilized, so that the signal output by the output module 104 will not have a falling edge step.

[0052] For details, please refer to Figure 2 , Figure 2 for Figure 1 FIG. 1 is a circuit diagram of a first node Q control module 101 in a GOA unit 100. Figure 2 As shown, the first node Q control module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a first capacitor C1.

[0053] Among them, the gate of the first transistor T1 is connected to the first clock signal XCK, the source of the first transistor T1 is connected to the first constant voltage signal VGL, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2, the drain of the fifth transistor T5 and the second node P control module 102. The gate of the second transistor T2 is connected to the first constant voltage signal VGL, and the drain of the second transistor T2 is electrically connected to the gate of the third transistor T3 and the first end of the first capacitor C1. The source of the third transistor T3 is connected to the second clock signal CK, and the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4 and the second end of the first capacitor C1. The gate of the fourth transistor T4 is connected to the second clock signal CK, and the drain of the fourth transistor T4 is electrically connected to the first node Q and the drain of the sixth transistor T6. The gate of the fifth transistor T5 is electrically connected to the second node P control module 102, and the source of the fifth transistor T5 is connected to the first clock signal XCK. The gate of the sixth transistor T6 is electrically connected to the second node P control module 102, and the source of the sixth transistor T6 is connected to the second constant voltage signal VGH.

[0054] For details, please refer to Figure 3 , Figure 3 for Figure 1 FIG. 1 is a circuit diagram of the second node P control module 102 in the GOA unit 100. Figure 3 As shown, the second node P control module 102 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and a second capacitor C2.

[0055] Among them, the gate of the seventh transistor T7 is connected to the first clock signal XCK, the source of the seventh transistor T7 is electrically connected to the previous stage signal output terminal STV, and the drain of the seventh transistor T7 is electrically connected to the source of the eighth transistor T8 and the first node Q control module 101. The gate of the eighth transistor T8 is connected to the first constant voltage signal VGL, and the drain of the eighth transistor T8 is electrically connected to the second node P, the gate of the ninth transistor T9 and the first end of the second capacitor C2. The source of the ninth transistor T9 is connected to the second clock signal CK, and the drain of the ninth transistor T9 is electrically connected to the drain of the tenth transistor T10 and the second end of the second capacitor C2. The gate of the tenth transistor T10 is electrically connected to the first node Q control module 101, and the source of the tenth transistor T10 is connected to the second constant voltage signal VGH.

[0056] For details, please refer to Figure 4 , Figure 4 for Figure 1 Another circuit diagram of the second node P control module 102 in the GOA unit 100 is shown. Figure 3 , Figure 4 As shown, Figure 4 The second node P control module 102 is shown with Figure 3 The differences of the second node P control module 102 shown are: Figure 4 The second node P control module 102 shown further includes an eleventh transistor T11 .

[0057] Among them, the gate of the eleventh transistor T11 is connected to the reset control signal, the source of the eleventh transistor T11 is connected to the second constant voltage signal VGH, and the drain of the eleventh transistor T11 is electrically connected to the drain of the seventh transistor T7, the source of the eighth transistor T8 and the first node Q control module 101.

[0058] For details, please refer to Figure 5 , Figure 5 for Figure 1 FIG. 1 is a circuit diagram of the delay suppression module 103 in the GOA unit 100. Figure 5 As shown, the delay suppression module 103 includes a twelfth transistor T12. The gate of the twelfth transistor T12 is connected to the clock signal CK1, the source of the twelfth transistor T12 is electrically connected to the second node P, and the drain of the twelfth transistor T12 is electrically connected to the third node K.

[0059] For details, please refer to Figure 6 , Figure 6 for Figure 1 Another circuit diagram of the delay suppression module 103 in the GOA unit 100 is shown. Figure 5 , Figure 6 Show, Figure 6The second node P control module 102 is shown with Figure 5 The differences of the second node P control module 102 shown are: Figure 6 The delay suppression module 103 shown further includes a third capacitor C3.

[0060] The first end of the third capacitor C3 is electrically connected to the third node K, and the second end of the third capacitor C3 is electrically connected to the signal output terminal OUT of this stage.

[0061] For details, please refer to Figure 7 , Figure 7 for Figure 1 FIG. 1 is a circuit diagram of the output module 104 in the GOA unit 100. Figure 7 As shown, the output module 104 includes a thirteenth transistor T13, a fourteenth transistor T14 and a fourth capacitor C4.

[0062] Among them, the gate of the thirteenth transistor T13 is electrically connected to the third node K, the source of the thirteenth transistor T13 is connected to the first constant voltage signal VGL, and the drain of the thirteenth transistor T13 is electrically connected to the current-stage signal output terminal OUT. The gate of the fourteenth transistor T14 is electrically connected to the first end of the first-section fourth capacitor C4, the source of the fourteenth transistor T14 is connected to the second constant voltage signal VGH and is electrically connected to the second end of the fourth capacitor C4, and the drain of the fourteenth transistor T14 is electrically connected to the current-stage signal output terminal OUT.

[0063] It should be noted that Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 as well as Figure 7 The circuit diagrams of the modules shown are only one or two embodiments provided by the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0064] The following will be combined Figure 8 The complete circuit diagram is shown for detailed explanation. Figure 8 for Figure 1 A complete circuit diagram of the GOA unit 100 is shown.

[0065] in, Figure 8 The first node Q control module 101 in the GOA unit 100 shown is equivalent to Figure 2 The first node Q control module 101 in the GOA unit 100 is shown. Figure 8 The second node P control module 102 in the GOA unit 100 shown is equivalent to Figure 4The second node P control module 102 in the GOA unit 100 is shown. Figure 8 The delay suppression module 103 in the GOA unit 100 shown is equivalent to Figure 6 The delay suppression module 103 in the GOA unit 100 is shown. Figure 8 The output module 104 in the GOA unit 100 shown is equivalent to Figure 7 The output module 104 in the GOA unit 100 is shown.

[0066] Among them, Figure 8 In the GOA unit 100 shown, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are all P-type transistors.

[0067] Among them, Figure 8 In the GOA unit 100 shown, the first clock signal XCK and the second clock signal CK are signals with the same period and opposite phases, the clock signal CK1 and the second clock signal CK are the same signal, the first constant voltage signal VGL is a constant voltage low level signal, and the second constant voltage signal VGH is a constant voltage high level signal.

[0068] See also Fig. 9 , Fig. 9 for Figure 8 FIG. 1 is a timing diagram of the complete circuit of the GOA unit 100. Figure 8 , Fig. 9 As shown, in the first stage t1, the first clock signal XCK is at a low level, and the second clock signal CK is at a high level, thereby controlling the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 to be turned off, and the remaining transistors to be turned on.

[0069] Specifically, the first clock signal XCK is at a low level, so that the first transistor T1 and the seventh transistor T7 are turned on, the low level of the first constant voltage signal VGL is output to the node N2, the node N1 and the first end of the first capacitor C1, and the low level of the signal output by the previous signal output terminal STV is output to the node N3, the second node P and the first end of the second capacitor C2; because the node N3 is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the low level of the first clock signal XCK is output to the node N2, and the high level of the second constant voltage signal VGH is output to the first node Q. At this time, the third transistor T3 is turned on, and the high level of the second clock signal CK is output to the second end of the first capacitor C1. Because the node N2 is at a low level and the second node P is at a low level, the ninth transistor T9 and the tenth transistor T10 are turned on, and the high level of the second clock signal CK and the high level of the second constant voltage signal VGH are output to the second end of the second capacitor C2. At this time, because the twelfth transistor T12 is turned off, the third node K does not receive a signal.

[0070] Combination Figure 8 , Fig. 9 As shown, in the second stage t2, the first clock signal XCK is at a high level and the second clock signal CK is at a low level, thereby controlling the first transistor T1, the third transistor T3, the seventh transistor T7, the eleventh transistor T11, the twelfth transistor T12 and the fourteenth transistor T14 to be turned off, and the remaining transistors to be turned on.

[0071] Specifically, the second node P maintains the low level at the first stage t1 due to the existence of the second capacitor C2. At this time, the fifth transistor T5 and the sixth transistor T6 are turned on, and the high level of the first clock signal XCK is output to the node N2, the node N1 and the first end of the first capacitor C1, and the high level of the second constant voltage signal VGH is output to the first node Q and the second end of the first capacitor C1. Since the second node P is at a low level, the ninth transistor T9 is turned on, and the low level of the second clock signal CK is output to the second end of the second capacitor C2. At this time, the second end of the second capacitor C2 jumps from the high level at the first stage t1 to the low level, and the second capacitor C2 bootstraps to lower the potential of the second node P. At the same time, the twelfth transistor T12 is turned on, so that the level of the third node K is equal to the level of the second node P at this time, and the low level of the first constant voltage signal VGL is output to the signal output terminal OUT of this stage.

[0072] Combination Figure 8 , Fig. 9As shown, in the third stage t3, the first clock signal XCK is at a low level and the second clock signal CK is at a high level, thereby controlling the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 to be turned off, and the remaining transistors to be turned on.

[0073] Specifically, the first clock signal XCK is at a low level, so that the first transistor T1 and the seventh transistor T7 are turned on, the low level of the first constant voltage signal VGL is output to the node N2, the node N1 and the first end of the first capacitor C1, and the high level of the signal output by the previous level signal output terminal STV is output to the node N3, the second node P and the first end of the second capacitor C2; since the node N3 is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned off. Since the second clock signal CK is at a high level, the fourth transistor T4 is turned off, and the first node Q maintains the high level at the second stage t2. Since the node N1 is at a low level, the third transistor T3 is turned on, and the high level of the second clock signal CK is output to the second end of the first capacitor C1. Since the node N2 is at a low level and the second node P is at a high level, the ninth transistor T9 is turned off, the tenth transistor T10 is turned on, and the high level of the second constant voltage signal VGH is output to the second end of the second capacitor C2. At this time, since the twelfth transistor T12 is turned off, the third node K maintains the low level at the second stage t2, and the low level of the first constant voltage signal VGL is output to the signal output terminal OUT of this stage.

[0074] Combination Figure 8 , Fig. 9 As shown, in the fourth stage t4, the first clock signal XCK is at a high level and the second clock signal CK is at a low level, thereby controlling the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11 and the thirteenth transistor T13 to be turned off, and the remaining transistors to be turned on.

[0075] Specifically, the second node P maintains a high level at the third stage t3 due to the existence of the second capacitor C2, and the fifth transistor T5 and the sixth transistor T6 are turned off. Since the second clock signal CK is at a low level, the fourth transistor T4 is turned on. Since the node N1 is at a low level, the third transistor T3 is turned on, and the low level of the second clock signal CK is output to the second end of the first capacitor C1 and the first node Q. At this time, the second end of the first capacitor C1 jumps from the high level at the third stage t3 to the low level, and the first capacitor C1 bootstraps the potential of the node N1. Since the node N2 is at a low level, the second node P is at a high level, so that the ninth transistor T9 is turned off, the tenth transistor T10 is turned on, and the high level of the second constant voltage signal VGH is output to the second end of the second capacitor C2. At this time, since the twelfth transistor T12 is turned on, the third node K is at a high level, and the high level of the second constant voltage signal VGH is output to the signal output terminal OUT of this level.

[0076] Combination Figure 8 , Fig. 9 As shown, in the fifth stage t5, the first clock signal XCK is at a low level, and the second clock signal CK is at a high level, thereby controlling the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 to be turned off, and the remaining transistors to be turned on.

[0077] Specifically, the first clock signal XCK is at a low level, so that the first transistor T1 and the seventh transistor T7 are turned on, the low level of the first constant voltage signal VGL is output to the node N2, the node N1 and the first end of the first capacitor C1, and the low level of the signal output by the previous signal output terminal STV is output to the node N3, the second node P and the first end of the second capacitor C2. At this time, the twelfth transistor T12 is turned off, that is, the second node P is disconnected from the third node K, so that the second capacitor C2 can be charged at this time. After the second node P reaches a stable state, the potential of the second node P is output to the third node K, so that the output does not have a falling delay. The low level of the second node P is output to the first end of the second capacitor C2. The high level of the second clock signal CK and the high level of the second constant voltage signal VGH are output to the second end of the second capacitor C2.

[0078] It should be noted that, by adding the twelfth transistor T12, the present application can shield the influence of the charging of the second capacitor C2, and the gate of the twelfth transistor T12 is synchronized with the source of the seventh transistor T7, avoiding the use of the bootstrap effect of the second capacitor C2 to open the thirteenth transistor T13, thereby ensuring normal output. In addition, in terms of the width-to-length ratio setting of the transistor, the width-to-length ratio of the twelfth transistor T12 is similar to the width-to-length ratio of the ninth transistor T9, W / L=3.7u / 4.2u, where w represents the width of the transistor and L represents the length of the transistor. At the same time, special attention should be paid to the capacitance design of the fourth capacitor C4. When the RC load of the GOA unit load is small, for example, the RC load of the GOA unit is less than 10pF, and the capacitance value of the fourth capacitor C4 is 300fF; when the RC load of the GOA unit is greater than 10pF, or even reaches 30pF or 50pF, the capacitance value of the fourth capacitor C4 is less than 200fF, which can reduce the influence of the RC load on the third node K, avoid the voltage of the third node K being too high, and the third node K cannot normally open the thirteenth transistor T13.

[0079] See also Fig.10 , Fig.10 for Figure 1 Another complete circuit schematic diagram of the GOA unit 100 is shown. Fig.10 The circuit diagram of the GOA unit 100 shown is similar to Figure 8 The difference of the circuit diagram of the GOA unit 100 shown is that: Fig.10 The twelfth transistor T12 in the circuit diagram of the GOA unit 100 is an N-type transistor, and the first clock signal XCK and the clock signal CK1 are the same signal.

[0080] The embodiment of the present application can also shield the influence of charging of the second capacitor C2, and the gate of the twelfth transistor T12 is synchronized with the source of the seventh transistor T7, avoiding the use of the bootstrap effect of the second capacitor C2 to open the thirteenth transistor T13, thereby ensuring normal output.

[0081] Correspondingly, the present application also provides a display panel, which includes any of the GOA circuits described above. Fig.11 , Fig.11 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Fig.11As shown, the display panel 1000 includes a display area AA and a non-display area NA connected to the display area AA. The GOA circuit 200 is integrated in the non-display area NA. Among them, the structure and principle of the GOA circuit 200 are similar to those of the above-mentioned GOA circuit, which will not be repeated here. It should be noted that the display panel 1000 provided in the present application is introduced by taking the single-sided driving mode in which the GOA circuit 200 is set on one side of the display area AA as an example, but it should not be understood as a limitation of the present application. In some embodiments, double-sided driving or other driving modes may also be adopted according to the actual needs of the display panel 1000, and the present application makes specific limitations on this.

[0082] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of this application, or directly or indirectly used in other related technical fields, are similarly included in the patent protection scope of this application.

Claims

1. A GOA circuit, characterized in that: It includes a plurality of cascaded GOA units, wherein the GOA unit includes a first node control module, a second node control module, a delay suppression module and an output module; wherein, The first node control module is electrically connected to the first node and to the second node control module, and the first node control module is used to control the potential of the first node; The second node control module is electrically connected to the second node and to the first node control module, and the second node control module is used to control the potential of the second node; The delay suppression module is electrically connected to the second node and the third node, and the delay suppression module is used to output the stable potential of the second node to the third node; The output module is electrically connected to the first node, the third node and the current-stage signal output terminal, and the output module is used to control the potential of the current-stage signal output terminal under the control of the potential of the first node and the potential of the third node; The first node control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, the gate of the first transistor is connected to a first clock signal, the source of the first transistor is connected to a first constant voltage signal, the drain of the first transistor is electrically connected to the source of the second transistor, the drain of the fifth transistor and the second node control module, the gate of the second transistor is connected to the first constant voltage signal, the drain of the second transistor is electrically connected to the gate of the third transistor and the first end of the first capacitor, the source of the third transistor is connected to the second clock signal, the drain of the third transistor is electrically connected to the source of the fourth transistor and the second end of the first capacitor, the gate of the fourth transistor is connected to the second clock signal, the drain of the fourth transistor is electrically connected to the first node and the drain of the sixth transistor, the gate of the fifth transistor is electrically connected to the second node control module, the source of the fifth transistor is connected to the first clock signal, the gate of the sixth transistor is electrically connected to the second node control module, and the source of the sixth transistor is connected to the second constant voltage signal.

2. The GOA circuit according to claim 1, characterized in that: The second node control module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor; The gate of the seventh transistor is connected to the first clock signal, the source of the seventh transistor is electrically connected to the previous stage signal output terminal, and the drain of the seventh transistor is electrically connected to the source of the eighth transistor and the first node control module; The gate of the eighth transistor is connected to the first constant voltage signal, and the drain of the eighth transistor is electrically connected to the second node, the gate of the ninth transistor and the first end of the second capacitor; The source of the ninth transistor is connected to the second clock signal, and the drain of the ninth transistor is electrically connected to the drain of the tenth transistor and the second end of the second capacitor; The gate of the tenth transistor is electrically connected to the first node control module, and the source of the tenth transistor is connected to the second constant voltage signal.

3. The GOA circuit according to claim 2, characterized in that: The second node control module also includes an eleventh transistor; the gate of the eleventh transistor is connected to the reset control signal, the source of the eleventh transistor is connected to the second constant voltage signal, and the drain of the eleventh transistor is electrically connected to the drain of the seventh transistor, the source of the eighth transistor and the first node control module.

4. The GOA circuit according to claim 2 or 3, characterized in that: The delay suppression module includes a twelfth transistor; a gate of the twelfth transistor is connected to a clock signal, a source of the twelfth transistor is electrically connected to the second node, and a drain of the twelfth transistor is electrically connected to the third node.

5. The GOA circuit according to claim 4, characterized in that: The seventh transistor and the twelfth transistor are both P-type transistors, and the first clock signal and the clock signal are signals with the same period and opposite phases.

6. The GOA circuit according to claim 4, characterized in that: The seventh transistor is a P-type transistor, the twelfth transistor is an N-type transistor, and the first clock signal and the clock signal are the same signal.

7. The GOA circuit according to claim 4, characterized in that: The delay suppression module further includes a third capacitor, a first end of the third capacitor is electrically connected to the third node, and a second end of the third capacitor is electrically connected to the current-stage signal output end.

8. The GOA circuit according to claim 1, characterized in that: The output module includes a thirteenth transistor, a fourteenth transistor and a fourth capacitor; The gate of the thirteenth transistor is electrically connected to the third node, the source of the thirteenth transistor is connected to the first constant voltage signal, and the drain of the thirteenth transistor is electrically connected to the current-stage signal output terminal; The gate of the fourteenth transistor is electrically connected to the first node and the first end of the fourth capacitor, the source of the fourteenth transistor is connected to the second constant voltage signal and is electrically connected to the second end of the fourth capacitor, and the drain of the fourteenth transistor is electrically connected to the signal output end of this stage.

9. A display panel, characterized in that: The GOA circuit comprises the GOA circuit described in any one of claims 1 to 8.

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