A pulse signal detection method and system

Abstract

The embodiment of the present application relates to a kind of pulse signal detection method and system, the method includes receiving the target pulse signal of voltage being preset threshold value;The target pulse signal is split into multiple single-line pulse signals;Multiple the single-line pulse signal is respectively carried out rising edge detection, and the single-line pulse signal that appears rising edge is determined as valid pulse signal;The valid pulse signal, the channel number of the valid pulse signal is output to signal measurement unit, to make the signal measurement unit according to the channel number obtain the pulse parameter of the valid pulse signal and carry out demonstration.Thereby, the detection efficiency and accuracy of the pulse parameter of multilevel pulse signal can be realized to improve.

Description

Technical Field

[0001] The present invention relates to the field of electronic measurement technology, and in particular to a pulse signal detection method and system. Background Technology

[0002] In modern electronic measurement and control, many devices transmit commands via pulse signals. The timing relationships of these pulse signals represent a wealth of implicit information. Therefore, accurately recording the arrival time, pulse width, voltage level, and duration of these pulse signals is crucial. Furthermore, it is necessary to preserve the original data for monitoring or maintenance personnel to perform subsequent testing and repairs.

[0003] With the increasing demand for signal measurement in existing instruments and equipment, there is an urgent need for pulse signal detection technology that is versatile, highly accurate, and has good synchronization. Therefore, improving the efficiency and accuracy of multi-level pulse signal detection has become a pressing issue. Summary of the Invention

[0004] In view of this, in order to solve the above-mentioned technical problems or some of the technical problems, the present invention provides a pulse signal detection method and system.

[0005] In a first aspect, embodiments of the present invention provide a pulse signal detection method, comprising:

[0006] Receive target pulse signals with a voltage of a preset threshold;

[0007] The target pulse signal is split into multiple single-line pulse signals;

[0008] Rising edge detection is performed on each of the multiple single-line pulse signals to determine the single-line pulse signal with a rising edge as a valid pulse signal;

[0009] The effective pulse signal and the channel number of the effective pulse signal are output to the signal measurement unit so that the signal measurement unit can obtain and display the pulse parameters of the effective pulse signal according to the channel number.

[0010] In one possible implementation, the signal measurement unit obtains and displays the pulse parameters of the valid pulse signal according to the channel number, including:

[0011] After receiving the channel number, the valid pulse signal, and the interrupt pulse, the signal measurement unit captures the valid pulse signal based on the channel number.

[0012] The pulse width and the number of pulses in the effective pulse signal are obtained as the pulse parameters;

[0013] After generating a corresponding data frame from the pulse parameters, the data frame is sent to the main control unit so that the main control unit can parse and save the data frame and display the pulse parameters.

[0014] Secondly, embodiments of the present invention provide a pulse signal detection system, comprising:

[0015] The signal conditioning unit is used to convert multi-level pulse signals into target pulse signals with a voltage of a preset threshold.

[0016] The signal multiplexing unit is used to determine the valid pulse signal from the target pulse signal, and to output the valid pulse signal, the interrupt pulse corresponding to the valid pulse signal, and the channel number.

[0017] The signal measurement unit is used to obtain the pulse parameters of the valid pulse signal after receiving the channel number, the valid pulse signal and the interrupt pulse;

[0018] Signal self-test unit: used to generate a self-test pulse signal and generate self-test pulse parameters based on the self-test pulse signal;

[0019] Main control unit: used to acquire and display the pulse parameters and the effective pulse signal, and to acquire and display the self-test pulse parameters.

[0020] In one possible implementation, the signal conditioning unit is further configured to compare the multi-level pulse signal with a preset reference voltage using a comparator, and then determine the negative pulse signal in the multi-level pulse signal.

[0021] A positive pulse signal is generated by pulling up the negative pulse signal.

[0022] The positive pulse signal is normalized.

[0023] The voltage corresponding to the normalized positive pulse signal is set as the preset threshold to obtain the target pulse signal.

[0024] In one possible implementation, the signal multiplexing unit is further configured to use a multiplexing switch and a comparator to split the target pulse signal into multiple single-wire pulse signals;

[0025] Rising edge detection is performed on each of the multiple single-line pulse signals to determine the single-line pulse signal with a rising edge as the valid pulse signal;

[0026] The interrupt pulse is generated based on the effective pulse signal;

[0027] Obtain the channel number corresponding to the valid pulse signal;

[0028] The interrupt pulse, the valid pulse signal, and the channel number are output to the signal measurement unit.

[0029] In one possible implementation, the signal multiplexing unit is further configured to set the priority of each target pulse signal when there are multiple channels of target pulse signals;

[0030] The target pulse signal is split according to the stated priority.

[0031] In one possible implementation, the signal multiplexing unit is further configured to stop outputting the first valid pulse signal and start outputting the second valid pulse signal if another channel generates a second valid pulse signal while the first valid pulse signal is being output.

[0032] In one possible implementation, the signal measurement unit is further configured to capture the valid pulse signal based on the channel number after detecting the interrupt pulse;

[0033] The pulse width and the number of pulses in the effective pulse signal are obtained as the pulse parameters;

[0034] When the effective pulse signal is held at a certain level for a set threshold time, or when a pulse appears in another channel number, the capture of the effective pulse signal ends.

[0035] After the pulse parameters are packaged into data frames, they are sent to the main control unit.

[0036] In one possible implementation, the signal self-test unit is further configured to generate a preset number of self-test pulse signals with a preset pulse width after receiving a self-test command.

[0037] The self-test pulse signal is sent to the signal measurement unit for measurement via the relay in the self-test unit to obtain the self-test pulse parameters.

[0038] The self-test pulse parameters are packaged into data frames and sent to the main control unit.

[0039] In one possible implementation, the system runs the program for the signal multiplexing unit and the program for the signal measurement unit in the foreground, and the program for the main control unit in the background, as well as the task of detecting the multi-level pulse signal by polling.

[0040] The pulse signal detection scheme provided in this invention receives a target pulse signal with a voltage of a preset threshold; splits the target pulse signal into multiple single-line pulse signals; performs rising edge detection on each of the multiple single-line pulse signals, and determines the single-line pulse signal with a rising edge as a valid pulse signal; outputs the valid pulse signal and its channel number to a signal measurement unit, so that the signal measurement unit can obtain and display the pulse parameters of the valid pulse signal according to the channel number. This improves the detection efficiency and accuracy of pulse parameters for multi-level pulse signals. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a pulse signal detection system provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic flowchart of a pulse signal detection method provided in an embodiment of the present invention;

[0043] Figure 3 A schematic diagram illustrating the principle of converting a multi-level pulse signal into multiple single-line pulse signals, provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic flowchart of a self-test signal processing method provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of a pulse signal detection principle provided in an embodiment of the present invention;

[0046] Figure 6 A flowchart illustrating a method for detecting the rising edge of an interrupt signal according to an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of a data processing thread program flow provided in an embodiment of the present invention;

[0048] Figure 8 A schematic diagram of a serial port communication process provided in an embodiment of the present invention;

[0049] Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] To facilitate understanding of the embodiments of the present invention, further explanations and descriptions will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of the present invention.

[0052] Figure 1 This is a schematic diagram of a pulse signal detection system provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the system specifically includes:

[0053] Signal conditioning unit 1, signal multiplexing unit 2, signal measurement unit 3, main control unit 4, signal self-test unit 5, multiplexing switch 6, comparator 7.

[0054] The signal conditioning unit includes a first comparator and an isolation circuit. The first comparator compares the multi-level pulse signal with a preset reference voltage to determine the negative pulse signal in the multi-level pulse signal. The negative pulse signal is then pulled up to generate a positive pulse signal. The positive pulse signal is then normalized. The voltage corresponding to the normalized positive pulse signal is set to a preset threshold (e.g., 3.3V) to obtain the target pulse signal, which is then output to the signal multiplexing unit.

[0055] The signal multiplexing unit includes a complex programmable logic device (CPLD) for receiving the target pulse signal; it utilizes a multiplexing switch and a second comparator ( Figure 1 The comparator 7) in the middle splits the target pulse signal into multiple single-line pulse signals; it performs rising edge detection on each of the multiple single-line pulse signals, determines the single-line pulse signal with rising edge as the valid pulse signal, generates an interrupt pulse, and outputs the valid pulse signal, the channel number of the valid pulse signal and the interrupt pulse to the signal measurement unit.

[0056] The signal measurement unit includes an ARM processor, which is used to acquire, analyze, and process pulse parameters. The acquired and analyzed data is then packaged and uploaded to the main control unit, which then parses, stores, and displays the pulse parameters. The main control unit includes computer equipment and a host computer.

[0057] Signal self-test unit: By clicking the self-test button in the main control unit, the ARM sends a self-test command to the CPLD, which in turn generates a logic self-test pulse signal. This control relays to send the self-test pulse signal to the signal measurement unit for self-testing and generates self-test pulse parameters. The self-test pulse parameters are then sent to the main control unit for storage and display.

[0058] Figure 2 This is a flowchart illustrating a pulse signal detection method provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the method specifically includes:

[0059] S21. Receive the target pulse signal with a voltage of a preset threshold.

[0060] The pulse signal detection method provided in this embodiment is applied to the signal multiplexing unit of the pulse signal detection system. Specifically, it receives the target pulse signal after being conditioned by the signal conditioning unit, and sends the target pulse to the signal measurement unit for measurement after multiplexing, so as to obtain the pulse parameters.

[0061] In this embodiment, the multi-level pulse signal is first converted into a target pulse signal with a voltage of a preset threshold by a signal conditioning unit. The signal conditioning unit is used to convert the externally input multi-level pulse signal into a target pulse signal with a voltage of a preset threshold, so as to realize the functions of voltage division, comparison and isolation of the output pulse signal of the device. The multi-level pulse signal is a positive and negative pulse signal, and the target pulse signal is a positive pulse signal.

[0062] Specifically, the signal conditioning unit includes a level conversion circuit, which includes a comparator. The multi-level pulse signal is input to the signal conditioning unit. The comparator compares the multi-level pulse signal with a reference voltage with a preset threshold, determines the negative pulse signal in the multi-level pulse signal, pulls up the negative pulse signal to generate a positive pulse signal, and normalizes the positive pulse signal.

[0063] The normalization process includes: using a multiplexer and a comparator, for a single voltage pulse, the pulse is divided and compared with a reference voltage, outputting a normalized level pulse signal with the same characteristics as the original signal; for a multi-level pulse signal, it is compared with different reference voltages and outputs normalized level pulses of different voltage segments. Further, the voltage corresponding to the normalized positive pulse signal is set to a preset threshold (e.g., 3.3V) to obtain the target pulse signal, which is then received by the signal conditioning unit via a signal multiplexing unit.

[0064] In one possible implementation, the signal conditioning unit further includes an isolation circuit for isolating the multi-level pulse signal to remove interference signals from the multi-level pulse signal.

[0065] S22. The target pulse signal is split into multiple single-line pulse signals; rising edge detection is performed on each of the multiple single-line pulse signals to determine that the single-line pulse signal with a rising edge is a valid pulse signal.

[0066] In this embodiment, a signal multiplexing unit determines a valid pulse signal from the target pulse signal and outputs an interrupt pulse corresponding to the valid pulse signal. The signal multiplexing unit can detect and multiplex the current valid pulse signal for output. The target pulse signal is generated in a time-division manner under the control of a multiplexing switch and a comparator. When there are multiple target pulse signals, the signal multiplexing unit detects the valid pulse signal and selects it for output at the output port.

[0067] Specifically, the timing relationship between the original multi-level pulse signal and the target pulse signal is compared one by one by the signal multiplexing unit and the comparator, and the target pulse signal is split into multiple single-line pulse signals; rising edge detection is performed on each of the multiple single-line pulse signals, and the single-line pulse signal with rising edge is determined to be the valid pulse signal; an interrupt pulse is generated based on the valid pulse signal; the channel number corresponding to the valid pulse signal is obtained; and the interrupt pulse, the valid pulse signal, and the channel number are output to the signal measurement unit.

[0068] Since a signal is valid when a rising edge appears, the signal multiplexing unit selects the signal to the output signal terminal and outputs a rising edge interrupt pulse to notify the subsequent signal measurement unit that a valid pulse signal has been generated and to update the channel number of the signal in the signal multiplexing unit. When a multi-level pulse signal is valid, the signal multiplexing unit will select multiple pulse signals related to the signal to the output port.

[0069] As an example Figure 3 This is a schematic diagram illustrating the principle of converting a multi-level pulse signal into multiple single-line pulse signals, as provided in an embodiment of the present invention. Figure 3 As shown, N channels will generate N pulses. Each pulse carries slightly different information, including positive, negative, and both. Taking the complex pulse sequence of the first channel as an example, V1-CH1 represents the original signal of the first channel, including +24V, -24V, -20V, and -30V. After passing through the signal conditioning unit and signal multiplexing unit, a normalized positive pulse signal is obtained. The comparator contains +24V, -20V, -24V, and -30V. Based on the timing relationship between the original multi-level pulse signal and the normalized positive pulse signal, they are compared one by one. The output pulse timing after the +24V comparator is P-CH1, the output pulse timing after the -20V comparator is N-CH1, and so on, resulting in... Figure 3The pulse signal is divided into four single-wire effective pulse signals. These signals are then fed back to the signal multiplexing unit. The signal multiplexing unit generates corresponding interrupt pulses based on the single-wire effective pulse signals and inputs the interrupt pulses, effective pulse signals, and channel numbers to the signal measurement unit. The signal measurement unit captures and analyzes the effective pulse signals. For +24V, only P-CH1 has a high level, indicating that this segment is +24V. Similarly, for -30V, N-CH1, K-CH1, and T-CH1 all have high levels, indicating that this segment is a -30V pulse.

[0070] S23. Output the effective pulse signal and the channel number of the effective pulse signal to the signal measurement unit, so that the signal measurement unit can obtain the pulse parameters of the effective pulse signal according to the channel number.

[0071] In this embodiment, when an interrupt pulse is detected by the signal measurement unit, the pulse parameters of the valid pulse signal are acquired. The signal measurement unit includes an ARM processor, which mainly performs pulse signal measurement, data compression and formatting, and communication with the host computer. The pulse parameters include, but are not limited to, the pulse width and the number of pulses in the valid pulse signal.

[0072] Specifically, after detecting the interrupt pulse issued by the signal multiplexing unit, the signal measurement unit starts the pulse capture function. First, it records the channel number of the current valid pulse signal, captures the valid pulse signal based on the channel number, and then measures the high and low level pulse widths of the valid pulse signal and calculates the number of pulses to obtain the pulse parameters. When the current valid pulse signal is held at a certain level for a longer than a preset threshold, or when a pulse from another channel number appears, the current pulse capture ends, and the captured data is packaged into a data frame according to the protocol format and sent to the main control unit.

[0073] In one possible implementation, when processing multi-channel target pulse signals, the signal multiplexing unit selects the target pulse signal with higher priority for processing according to a certain priority. That is, it processes only one target pulse signal at a time. The smaller the channel number of the target pulse signal is preset, the higher the multiplexing priority.

[0074] For example, the first target pulse signal has the highest priority. When the first valid pulse signal of the first target pulse signal is being output, if the output time exceeds a set threshold, it indicates that the output of the first valid pulse signal may have ended. At this time, the second target pulse signal of other channels generates a second valid pulse signal. The signal multiplexing unit will immediately interrupt the output of the first valid pulse signal and instead multiplex the output of the second valid signal, while simultaneously generating an interrupt pulse for the second valid pulse signal and updating the channel number, and sending it to the signal measurement unit for measurement. Therefore, all parallel target pulse signals appear sequentially on the valid pulse signal, interrupt pulse, and channel number corresponding to the interface of the signal multiplexing unit under the priority mechanism selection, and the signal appearing on each channel is a complete pulse signal.

[0075] The signal measurement unit measures the pulse parameters of the output signal from the preceding signal multiplexing unit to obtain the high-level width, low-level width, and number of pulses of the pulse signal, and then uploads them to the main control computer for judgment and display in a certain frame format.

[0076] S24. Generate a self-test pulse signal through the signal self-test unit, and generate self-test pulse parameters based on the self-test pulse signal.

[0077] In this embodiment, the signal self-test unit mainly includes: a relay, which generates a preset number and preset pulse width of self-test pulse signals through a CPLD after the main control unit generates a self-test command; the self-test pulse signals are output to the signal measurement unit through the relay, and the self-test pulse parameters are obtained through the signal measurement unit.

[0078] Specifically, Figure 4 This is a schematic flowchart of a self-test signal processing method provided in an embodiment of the present invention, as shown below. Figure 4 As shown, after the main control unit issues a self-test command, the ARM parses the command and sets the level of the self-test pulse signal through the CPLD. It then outputs 50 +5V, 50 -5V, 50 +24V, and 50 -29V self-test pulses via relays in a time-division manner. All self-test pulses have a width of 1ms and a duty cycle of 50%. The +5V, -5V, and +24V self-test pulses are compared and isolated before outputting pulses with consistent 3.3V level characteristics. The -29V pulse is compared and isolated before outputting two 3.3V level pulses. Simultaneously with the output of the valid pulse signal corresponding to each self-test pulse signal, the channel number of the signal and the corresponding interrupt pulse are also output. The self-test pulse parameters are obtained through the signal measurement unit, packaged into data frames, and sent to the main control unit.

[0079] S25. The pulse parameters and valid pulse signals are obtained through the main control unit and displayed, as well as the self-test pulse parameters are obtained and displayed.

[0080] In this embodiment, the main control unit can be a computer device, which receives pulse parameters, parses them to obtain the validity or specific time value of the pulse signal, and can display, save or report them, so as to realize the data analysis, storage, fault detection and overall display and monitoring of the system status of the pulse.

[0081] Specifically, Figure 5 This is a schematic diagram of a pulse signal detection principle provided in an embodiment of the present invention, such as... Figure 5 As shown, based on the task processing characteristics, the lower-level computer software generally adopts a front-end and back-end structure. The front-end runs the signal multiplexing unit program and the signal measurement unit program, while the back-end runs the main control unit program, which polls and executes the pulse signal detection task.

[0082] After the lower-level signal measurement unit powers on and resets, it first runs the startup module for configuration; then it calls the initialization program to initialize various functional modules of the system; next, it enters the main loop program, which polls and triggers the serial communication program, signal multiplexing unit program, timer interrupt handling program, and GPIO input / output control program, performs logical judgments according to control rules, and generates control commands based on various task functions. Tasks in the signal multiplexing unit program include pulse signal detection and channel multiplexing. Tasks in the pulse capture program include channel number capture, rising edge capture, and array allocation. Timing measurement tasks include data flags, level duration, interrupt mode, number of pulses, and data length. Tasks in the data processing program include data merging and data compression. Tasks in the serial communication program include data uploading and data receiving.

[0083] In one possible implementation, the lower-level software architecture mainly includes: (1) interrupt pulse detection and data normalization processing; (2) serial communication and data parsing; and (3) interaction with the upper-level computer interface. The lower-level software uses the RT-Thread embedded operating system for task design, and three main tasks are established in the program.

[0084] Task 1: Complete the relevant processing of the signal multiplexing unit communication. First, receive the channel code and valid pulse signal sent by the signal multiplexing unit, start the multi-pulse capture command, and buffer the pulse width and pulse level value of the valid pulse signal. Second, encapsulate the measured pulse parameters and then buffer them in the form of data frames. This is the highest priority task.

[0085] Task 2: Send these data frames to the host computer software via serial port. After the data reception is completed, parse the received data according to the relevant communication protocol. This task has the second priority.

[0086] Task 3: Based on the instructions from the host computer, determine whether there is a self-test pulse signal and control the signal detection multiplexing unit to generate a self-test pulse signal. This task has the lowest priority.

[0087] After the signal measurement unit is powered on and reset, it first calls the initialization program to initialize the various functional modules of the system; then it enters the main loop program to poll and trigger pulse signals for capture start, capture interrupt, timeout interrupt, data merging and encapsulation, etc., performs logical judgments according to control rules, and generates control commands according to various task functions.

[0088] The pulse signal detection method provided in this invention involves receiving a target pulse signal with a voltage of a preset threshold; splitting the target pulse signal into multiple single-line pulse signals; detecting the rising edge of each of the multiple single-line pulse signals to determine the single-line pulse signal with a rising edge as a valid pulse signal; outputting the valid pulse signal and its channel number to a signal measurement unit, so that the signal measurement unit can obtain and display the pulse parameters of the valid pulse signal according to the channel number; generating a self-test pulse signal through a signal self-test unit, and generating self-test pulse parameters based on the self-test pulse signal; and obtaining and displaying the pulse parameters and valid pulse signal through a main control unit, as well as obtaining and displaying the self-test pulse parameters. This method normalizes N positive and negative pulses into N positive pulses and their corresponding level information. Simultaneously, the software layer synchronously captures, acquires, and transmits the N signals, effectively improving the detection accuracy of pulse width and frequency. It can be applied to high-precision multi-channel acquisition scenarios. The signal self-test unit can simulate corresponding signal output functions according to the type of pulse signal to be detected by the device, improving the self-test depth and the overall intelligence of the device.

[0089] The following will describe the process of pulse measurement performed by the signal measurement unit:

[0090] Figure 6 This is a flowchart illustrating a method for detecting the rising edge of an interrupt signal according to an embodiment of the present invention, as shown below. Figure 6 As shown, the method specifically includes:

[0091] Step 1: First, the interrupt signal detects the rising edge of a pulse signal in a certain channel and determines whether the measurement is complete. If the measurement is complete, the time base reading and channel identification are completed, and the capture thread is started to measure the pulse time, pulse width, etc. If the measurement is not complete, the current measurement is ended, the end information is inserted, and the remaining steps are completed.

[0092] In the process of multi-channel pulse signal measurement, all signals are converted into positive pulses after passing through the signal conditioning unit. However, the number, duration, and interrupt type of each pulse signal are different. Therefore, pulse width measurement, pulse counting, timing accumulation, and interrupt classification are required. Interrupt classification includes two types: timeout termination and signal termination forced by interruption from other channels. The pulse signal measurement procedure is as follows: After starting the capture thread, if the current channel is interrupted by another channel, the capture time and pulse width of the current channel are recorded, the data is pushed into the pulse width buffer, the interrupt is updated, and the measurement of the newly arrived channel pulse continues, with timing accumulation. This cycle continues until timeout termination, at which point the data is pushed into the pulse width buffer.

[0093] Step Two: Figure 7 This is a schematic diagram of a data processing thread program flow provided in an embodiment of the present invention, such as... Figure 7 As shown, after the pulse measurement of a certain channel is completed, it needs to be sent to the host computer software via serial port. Therefore, it needs to be sent according to the system protocol format. First, a data frame needs to be created. The amount of data in the pulse width buffer is continuously compared. When there is data in the data frame, the data is extracted. Pulse width calculation, count, and time accumulation are continuously performed. When the measurement ends due to a timeout, a verification is calculated, a frame tail is created, and one pulse measurement is completed. The data is pushed into the data frame buffer and awaits transmission to the host computer. If the data is not finished, it means that the current channel measurement is not complete. The pulses are then merged, and the current data calculation process is repeated.

[0094] Step 3: In real time, determine the amount of data in the data frame buffer. If there is data, upload it to the host computer using a serial communication thread. Figure 8 This is a schematic diagram of a serial port communication process provided in an embodiment of the present invention, as shown below. Figure 8 As shown, when the serial port receives data, the signal measurement unit responds to the interrupt and enters the serial communication function to determine in real time whether the data reception is complete. After the data reception is complete, the received data is parsed according to the relevant communication protocol. After the parsing is completed, the interrupt flag is set, and it is determined whether the system needs to be reset or self-tested, thereby completing the corresponding instruction operation.

[0095] Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Figure 9 The computer device 900 shown includes at least one processor 901, a memory 902, at least one network interface 904, and other user interfaces 903. The various components in the computer device 900 are coupled together via a bus system 905. It is understood that the bus system 905 is used to implement communication between these components. In addition to a data bus, the bus system 905 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 9 The general labeled all buses as Bus System 905.

[0096] The user interface 903 may include a display, keyboard, or clicking device (e.g., mouse, trackball, touchpad, or touchscreen).

[0097] It is understood that the memory 902 in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 902 described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0098] In some implementations, memory 902 stores elements, executable units or data structures, or subsets thereof, or extended sets thereof: operating system 9021 and application program 9022.

[0099] The operating system 9021 includes various system programs, such as the framework layer, core library layer, and driver layer, used to implement various basic business functions and handle hardware-based tasks. The application program 9022 includes various applications, such as a media player and a browser, used to implement various application functions. The program implementing the method of this embodiment can be included in the application program 9022.

[0100] In this embodiment of the invention, by calling the program or instructions stored in the memory 902, specifically the program or instructions stored in the application program 9022, the processor 901 executes the method steps provided in each method embodiment, including, for example:

[0101] The computer device generates corresponding control instructions to control the CPLD and ARM to achieve the following methods:

[0102] Receive target pulse signals with a voltage of a preset threshold;

[0103] The target pulse signal is split into multiple single-line pulse signals;

[0104] Rising edge detection is performed on each of the multiple single-line pulse signals to determine that the single-line pulse signal with a rising edge is a valid pulse signal;

[0105] The effective pulse signal and the channel number of the effective pulse signal are output to the signal measurement unit so that the signal measurement unit can obtain and display the pulse parameters of the effective pulse signal according to the channel number.

[0106] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 901. Processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware or by instructions in the form of software in processor 901. The processor 901 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software units in the decoding processor. The software units may be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 902. Processor 901 reads the information in memory 902 and, in conjunction with its hardware, completes the steps of the above method.

[0107] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0108] For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0109] The computer device provided in this embodiment may be as follows: Figure 9 The computer device shown can perform, for example Figure 2 All steps of the pulse signal detection method are then implemented to achieve... Figure 2 For details on the technical effects of the pulse signal detection method shown, please refer to [link / reference]. Figure 2 The relevant descriptions are presented concisely and will not be elaborated upon here.

[0110] This invention also provides a storage medium (computer-readable storage medium). This storage medium stores one or more programs. The storage medium may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, hard disk, or solid-state drive; the memory may also include combinations of the above types of memory.

[0111] One or more programs in the storage medium can be executed by one or more processors to implement the pulse signal detection method executed on the device side as described above.

[0112] The processor is used to execute a pulse signal detection program stored in the memory to implement the following steps of a pulse signal detection method executed on the device side:

[0113] Receive target pulse signals with a voltage of a preset threshold;

[0114] The target pulse signal is split into multiple single-line pulse signals;

[0115] Rising edge detection is performed on each of the multiple single-line pulse signals to determine that the single-line pulse signal with a rising edge is a valid pulse signal;

[0116] The effective pulse signal and the channel number of the effective pulse signal are output to the signal measurement unit so that the signal measurement unit can obtain and display the pulse parameters of the effective pulse signal according to the channel number.

[0117] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0118] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0119] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A pulse signal detection method, characterized in that, include: Receive target pulse signals with a voltage of a preset threshold; The target pulse signal is split into multiple single-line pulse signals. When there are multiple channels of target pulse signals, a priority is set for each target pulse signal, and the target pulse signal is split according to the priority. Rising edge detection is performed on each of the multiple single-line pulse signals to determine the single-line pulse signal with a rising edge as a valid pulse signal; The effective pulse signal and the channel number of the effective pulse signal are output to the signal measurement unit so that the signal measurement unit can obtain and display the pulse parameters of the effective pulse signal according to the channel number.

2. The method according to claim 1, characterized in that, The signal measurement unit obtains and displays the pulse parameters of the valid pulse signal according to the channel number, including: After receiving the channel number, the valid pulse signal, and the interrupt pulse, the signal measurement unit captures the valid pulse signal based on the channel number. The pulse width and the number of pulses in the effective pulse signal are obtained as the pulse parameters; After generating a corresponding data frame from the pulse parameters, the data frame is sent to the main control unit so that the main control unit can parse and save the data frame and display the pulse parameters.

3. A pulse signal detection system, characterized in that, include: The signal conditioning unit is used to convert multi-level pulse signals into target pulse signals with a voltage of a preset threshold. The signal multiplexing unit is used to determine the valid pulse signal from the target pulse signal, and to output the valid pulse signal, the interrupt pulse corresponding to the valid pulse signal, and the channel number. The signal measurement unit is used to obtain the pulse parameters of the valid pulse signal after receiving the channel number, the valid pulse signal and the interrupt pulse; Signal self-test unit: used to generate a self-test pulse signal and generate self-test pulse parameters based on the self-test pulse signal; Main control unit: used to acquire and display the pulse parameters and the effective pulse signal, and to acquire and display the self-test pulse parameters; The signal multiplexing unit is also used to split the target pulse signal into multiple single-line pulse signals using a multiplexing switch and a comparator; The signal multiplexing unit is also used to set the priority of each target pulse signal when there are multiple channels of target pulse signals; The target pulse signal is split according to the stated priority.

4. The system according to claim 3, characterized in that, The signal conditioning unit is further configured to compare the multi-level pulse signal with a preset reference voltage using a comparator, and then determine the negative pulse signal in the multi-level pulse signal. A positive pulse signal is generated by pulling up the negative pulse signal. The positive pulse signal is normalized. The voltage corresponding to the normalized positive pulse signal is set as the preset threshold to obtain the target pulse signal.

5. The system according to claim 3, characterized in that, The signal multiplexing unit is also used to perform rising edge detection on the multiple single-line pulse signals respectively, and determine the single-line pulse signal with rising edge as the valid pulse signal; The interrupt pulse is generated based on the effective pulse signal; Obtain the channel number corresponding to the valid pulse signal; The interrupt pulse, the valid pulse signal, and the channel number are output to the signal measurement unit.

6. The system according to claim 5, characterized in that, The signal multiplexing unit is also used to stop outputting the first valid pulse signal and start outputting the second valid pulse signal if another channel generates a second valid pulse signal while the first valid pulse signal is being output.

7. The system according to claim 5, characterized in that, The signal measurement unit is further configured to capture the valid pulse signal based on the channel number after detecting the interrupt pulse; The pulse width and the number of pulses in the effective pulse signal are obtained as the pulse parameters; When the effective pulse signal is held at a certain level for a set threshold time, or when a pulse appears in another channel number, the capture of the effective pulse signal ends. After the pulse parameters are packaged into data frames, they are sent to the main control unit.

8. The system according to claim 3, characterized in that, The signal self-test unit is also used to generate a preset number and preset pulse width of self-test pulse signals after receiving a self-test command; The self-test pulse signal is sent to the signal measurement unit for measurement via the relay in the self-test unit to obtain the self-test pulse parameters. The self-test pulse parameters are packaged into data frames and sent to the main control unit.

9. The system according to claim 3, characterized in that, The system runs the program for the signal multiplexing unit and the program for the signal measurement unit in the foreground, and the program for the main control unit in the background, as well as the task of detecting the multi-level pulse signal by polling.

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