Non-volatile memory and method of programming the same
By using a programming method for non-volatile memory and removing the erase state through coarse and fine programming procedures, the problems of increased memory area and decoding delay caused by ECC circuits were solved, thereby improving data reliability and decoding speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MACRONIX INTERNATIONAL CO LTD
- Filing Date
- 2021-11-02
- Publication Date
- 2026-06-02
AI Technical Summary
In the prior art, as the number of bits in the memory increases, a stronger ECC circuit is required to correct errors, which leads to an increase in memory area and decoding delay time, and a decrease in data reliability after long-term operation and multiple programming/erasing.
The non-volatile memory programming method involves executing a coarse programming program to program the memory cell to 2N-1 or 2N programming states, followed by executing a fine programming program to push it to 2N-1 or 2N verification levels, removing the erase state, and reducing bit errors.
This reduces bit errors between the erase and program states, avoids the need for or reduces the area of ECC circuitry, and improves data reliability and decoding speed.
Smart Images
Figure CN115641895B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a memory and its operation programming method, and more particularly to a non-volatile memory and its programming method. Background Technology
[0002] With the development of semiconductor technology, the storage density of memory is constantly increasing. Traditionally, error-correcting code (ECC) circuits are needed to correct errors in the memory to ensure data integrity. After long-term operation and multiple programming / erasing cycles, data reliability usually decreases.
[0003] As the number of bits increases, more robust ECC circuitry is required. However, ECC circuitry occupies memory area and increases decoding latency. To improve area utilization and accelerate decoding speed, researchers are working to develop a memory that requires no ECC circuitry or only a small area of ECC circuitry.
[0004] Public content
[0005] This disclosure relates to a non-volatile memory and its programming method, in which the erase state is removed during the execution of the programming method, thus greatly reducing bit errors between the erase state and the programming state, and therefore the ECC circuit is no longer needed or can be reduced in size.
[0006] According to one aspect of this disclosure, a programming method for non-volatile memory is proposed. The programming method for non-volatile memory includes the following steps: Executing a coarse programming procedure to program all memory cells currently in an erase state to 2... N-1 or 2 N There are two program states. N is a positive integer. Execute a fine programming procedure to push all memory locations to 2. N-1 or 2 N One verification level.
[0007] According to another aspect of this disclosure, a non-volatile memory is proposed. The non-volatile memory includes a memory array and a controller. The memory array includes a plurality of memory cells. The controller is used to execute a coarse programming program to program all the plurality of memory cells currently in an erase state to 2... N-1 or 2 NThe program state is defined as follows: It executes a fine programming procedure to push all memory locations to 2. N-1 or 2 N There are 1 verification level. N is a positive integer.
[0008] According to another aspect of this disclosure, a programming method for non-volatile memory is proposed. The programming method for non-volatile memory includes the following steps: executing a coarse programming procedure to program each of a plurality of memory cells located in an erase state to 2... N-1 or 2 N One of the program states. N is a positive integer. Execute a fine programming procedure to push each of all memory locations to 2. N-1 or 2 N One of the verification levels.
[0009] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description
[0010] Figure 1 This is a block diagram of a non-volatile memory according to one embodiment.
[0011] Figure 2A The example illustrates the threshold voltage distribution of a non-volatile memory after a coarse programming procedure is executed.
[0012] Figure 2B The example illustrates the threshold voltage distribution of a non-volatile memory after performing a fine programming procedure.
[0013] Figure 3 illustrate Figure 2B Threshold voltage distribution of non-volatile memory after heating, prolonged use, or multiple programming / erasing.
[0014] Figure 4 This is a block diagram of a non-volatile memory according to another embodiment.
[0015] Figure 5 According to Figure 4 A flowchart of the programming method for the non-volatile memory in the embodiment.
[0016] Figure 6A Example description based on Figure 5 Implementation 2 N-1 Threshold voltage distribution of a non-volatile memory in a programmed state after executing a coarse programming program (N is, for example, 3).
[0017] Figure 6B Example description based on Figure 5 Implementation 2 N-1 Threshold voltage distribution of a non-volatile memory in a programmed state after executing a fine programming program (N is, for example, 3).
[0018] Figure 7 Example description based on Figure 6B Implementation 2 N-1 Threshold voltage distribution of a non-volatile memory in a programmed state after heating, prolonged use, or multiple programming / erasing (N is, for example, 3).
[0019] Figure 8A Example description based on Figure 5 Implementation 2 N Threshold voltage distribution of a non-volatile memory in a programmed state after executing a coarse programming program (N is, for example, 3).
[0020] Figure 8B Example description based on Figure 5 Implementation 2 N Threshold voltage distribution of a non-volatile memory in a programmed state after executing a fine programming program (N is, for example, 3).
[0021] Figure 9 Example description based on Figure 8B Implementation 2 N Threshold voltage distribution of a non-volatile memory in a programmed state after heating, prolonged use, or multiple programming / erasing (N is, for example, 3).
[0022] Figure 10 This is a flowchart of a programming method for a non-volatile memory according to another embodiment.
[0023] Explanation of reference numerals in the attached figures
[0024] 100, 200: Non-volatile memory
[0025] 110: Memory Array
[0026] 120: Amplifier Circuit
[0027] 130: Peripheral Circuits
[0028] 140: Controller
[0029] 150: Page Buffer
[0030] 160: Voltage regulator
[0031] 170: ECC circuit
[0032] EV: Erasure status
[0033] S110, S120, S210: Steps
[0034] PV1, PV2, PV3, PV4, PV5, PV6, PV7, PV: Programming status
[0035] VR1, VR2, VR3, VR4, VR5, VR6, VR7, VR8: Verification Level Detailed Implementation
[0036] Please refer to Figure 1 This is a block diagram of a non-volatile memory 100 according to an embodiment. The non-volatile memory 100 is, for example, a NAND flash memory, a NOR flash memory, a floating gate memory, or a SONOS memory. The non-volatile memory 100 can be a multi-level cell (MLC) memory, a three-level cell (TLC) memory, a four-level cell (QLC) memory, or a five-level cell (PLC) memory. Furthermore, the non-volatile memory 100 can be a two-dimensional flash memory or a three-dimensional flash memory.
[0037] The non-volatile memory 100 includes, for example, a memory array 110, an amplifier circuit 120, a peripheral circuit 130, a controller 140, a page buffer 150, a voltage regulator 160, and an ECC circuit 170. The memory array 110 includes multiple memory cells. The amplifier circuit 120 senses low-voltage signals in the memory cells and amplifies them to correctly interpret 1 or 0 data. The controller 140 controls the circuitry to execute programming, reading, and erasing methods. The page buffer 150 temporarily stores data. The voltage regulator 160 provides an appropriate voltage.
[0038] Programming methods for non-volatile memory include a coarse programming procedure and a fine programming procedure. Please refer to... Figures 2A-2B , Figure 2A This example illustrates the threshold voltage distribution of a non-volatile memory after executing a coarse programming procedure. Figure 2B The example illustrates the threshold voltage distribution of non-volatile memory after performing a fine programming procedure. Figures 2A-2BIn this context, non-volatile memory is, for example, a three-dimensional NAND flash memory with a three-level cell (TLC) architecture.
[0039] like Figure 2A As shown, during the coarse programming process, some memory cells are programmed to the program state (PV1 to PV7), while others remain in the erase state (EV). Because the coarse programming process only requires roughly dividing the memory cells into multiple clusters, a larger step voltage is used.
[0040] like Figure 2B As shown, in the fine programming process, small step voltages are used to carefully push the memory cells forward to the verification levels VR1 to VR7. Therefore, eight states can be obtained in the end, including the erase state EV and the programming states PV1 to PV7. The memory cells in these eight states are used for data storage.
[0041] Please refer to Figure 3 Its explanation Figure 2B The threshold voltage distribution of a non-volatile memory after heating, prolonged use, or multiple programming / erasing cycles is shown. After heating, prolonged use, or multiple programming / erasing cycles, the erase state EV experiences charge gain and shifts to the right. On the other hand, the programming states PV1 to PV7 shift to the left. Therefore, an ECC circuit 170 is needed to prevent bit errors caused by overlap between the erase state EV and the programming state PV1.
[0042] Please refer to Figure 4 This is a block diagram of a non-volatile memory 200 according to another embodiment. In this embodiment, the controller 140 removes the erase state EV during the execution of the programming method, thus significantly reducing bit errors between the erase state EV and the programming state PV1. Therefore, the ECC circuit 170 is no longer needed or its area can be reduced. The operation of the controller 140 will be explained below by a flowchart.
[0043] Please refer to Figures 5-6B . Figure 5 According to Figure 4 A flowchart of the programming method for the non-volatile memory 200 in this embodiment. Figure 6A Example description based on Figure 5 Implementation 2 N-1 Threshold voltage distribution of a non-volatile memory in a programmed state after executing a coarse programming program (N is, for example, 3). Figure 6B Example description based on Figure 5 Implementation 2 N-1Threshold voltage distribution of a non-volatile memory in a programmed state after executing a fine programming procedure (N is, for example, 3). Controller 140 is used to execute at least this programming method.
[0044] In step S110, the controller 140 executes a coarse programming procedure to program all memory cells in the erased state to 2 N-1 (or 2) N There are 1, 2, 3, 4, and 5 programming states. N is a positive integer, N > 1. In a coarse programming program, since it is only necessary to roughly divide the memory cells into multiple clusters, a larger step voltage is used. If the non-volatile memory is a multi-level cell (MLC) memory, then N is 2; if the non-volatile memory is a three-level cell (TLC) memory, then N is 3; if the non-volatile memory is a four-level cell (QLC) memory, then N is 4; if the non-volatile memory is a five-level cell (PLC) memory, then N is 5.
[0045] like Figure 6A As shown, the non-volatile memory 200 is a three-level cell memory with N being 3. For example, after executing a coarse programming procedure, all memory cells EV in the erase state EV can be programmed to 7 (2 3-1 There are three programming states PV1 to PV7. Each programming state PV1 to PV7 is different from the erase state EV. "Different from" here means that the threshold voltage of any programming state PV1 to PV7 is different from the threshold voltage of the original erase state EV. After executing the coarse programming procedure, no memory cell is in the erase state EV, and the number of memory cells in the erase state EV is 0.
[0046] Then, in step S120, the controller 140 executes a fine programming procedure to push all memory cells to 2. N-1 (or 2) N There are ) verification levels. For example... Figure 6B As shown, in the fine programming process, small step voltages are used to carefully push the memory cells forward to the verification levels VR1 to VR7.
[0047] After executing the programming method, you can obtain 2. N-1 (or 2) N There are 10 programming states, and the storage units located in these programming states are used for data storage. The erase state (EV) has been removed and is not used for data storage. For example... Figure 6B As shown, the storage units located in programming states PV1 to PV7 are used for data storage.
[0048] Please refer to Figure 7 Its example illustration is based on Figure 6BImplementation 2 N-1 The threshold voltage distribution (N is, for example, 3) of a non-volatile memory 200 with programming states after heating, prolonged use, or multiple programming / erasing. After heating, prolonged use, or multiple programming / erasing, programming states PV1 to PV7 shift to the left. Since the erase state EV has been removed during the programming process, bit errors caused by overlap between the erase state EV and programming state PV1 can be significantly reduced, thus eliminating the need for ECC circuitry (e.g., ...). Figure 4 (As shown).
[0049] Figures 6A-7 With 2 N-1 This explanation uses a programming state as an example (N is, for example, 3). Please also refer to... Figures 8A-9 . Figure 8A Example description based on Figure 5 Implementation 2 N Threshold voltage distribution of a non-volatile memory in a programmed state after executing a coarse programming procedure (N is, for example, 3). Figure 8B illustrates the example based on... Figure 5 Implementation 2 N Threshold voltage distribution of a non-volatile memory in a programmed state after a fine programming procedure is performed (N is, for example, 3). Figure 9 Example description based on Figure 8B Implementation 2 N Threshold voltage distribution (N, for example, 3) of a non-volatile memory 200 in a programmed state after heating, prolonged use, or multiple programming / erasing.
[0050] like Figure 8A As shown, after executing the coarse programming procedure, all memory cells EV in the erase state EV are programmed into eight programming states PV1 to PV8. Each programming state PV1 to PV8 is different from the erase state EV. Here, "different from" means that the threshold voltage of any programming state PV1 to PV8 is different from the threshold voltage of the original erase state EV. After executing the coarse programming procedure, no memory cells are in the erase state EV, and the number of memory cells in the erase state EV is 0.
[0051] like Figure 8B As shown, in the fine programming process, small step voltages are used to carefully push the memory cells forward to the verification levels VR1 to VR8.
[0052] like Figure 9 As shown, since the erase state EV has been removed in the programming method, the bit errors caused by overlap between the erase state EV and the programming state PV1 can be significantly reduced, thus eliminating the need for ECC circuitry (such as...). Figure 4 (As shown).
[0053] Please refer to Figure 10 This is a flowchart of a programming method for a non-volatile memory 200 according to another embodiment. In step S210, the controller 140 executes a coarse programming procedure to program each memory cell in the erased state to 2 N -1 (or 2) N One of 2 programming states, where N is a positive integer greater than 1. In this embodiment, each memory cell is programmed into one programming state. After performing a coarse programming procedure, the memory cell may use fewer than 2 programming states. N-1 One (or 2) N The number of non-volatile memory cells is as follows: If the non-volatile memory is a multi-level cell (MLC) memory, N is 2; if it is a three-level cell (TLC) memory, N is 3; if it is a four-level cell (QLC) memory, N is 4; and if it is a five-level cell (PLC) memory, N is 5. For example, when N is 3, the programming states available for the memory cell are programming states PV1 to PV7. In this step, each memory cell in the erase state EV is programmed to one of these seven programming states. It is possible that programming states PV1, PV3 to PV7 are used, but programming state PV2 is not used; therefore, after executing the coarse programming procedure, the memory cell may use fewer than seven programming states.
[0054] Then, in step S220, the controller 140 executes a fine programming procedure to push each memory cell to 2. N-1 (or 2) N One of the ) verify levels. After performing a fine-grained programming procedure, the memory cell may use fewer than 2 programming states. N-1 One (or 2) N Similarly, in this step, each memory cell in the erase state EV is programmed to one of these seven programming states. Therefore, after performing the fine programming procedure, the memory cell may use fewer than seven programming states.
[0055] On the other hand, if the non-volatile memory 200 is a four-level cell (QLC) memory and N is 4. After performing a coarse programming procedure, all memory cells EV in the erase state EV are programmed to 15 (or 16) programming states; or, each memory cell in the erase state is programmed to one of the 15 (or 16) programming states.
[0056] Furthermore, if the non-volatile memory 200 is a five-level cell (PLC) memory and N is 5, after executing the coarse programming program, all memory cells EV in the erase state EV are programmed to 31 (or 32) programming states; or, each memory cell in the erase state is programmed to one of the 31 (or 32) programming states.
[0057] According to the above embodiment, the controller 140 removes the erase state EV during the execution of the programming method, so the bit error between the erase state EV and the programming state PV1 is greatly reduced, and therefore the ECC circuit is no longer needed or can be reduced in size.
[0058] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.
Claims
1. A method for programming non-volatile memory, comprising: performing a coarse program procedure to program all memory cells located in an erased state to N N-1 or 2 N programmed states and remove the erased state, where N is a positive integer; as well as A fine programming procedure is performed to push all these memory cells to 2 N-1 or 2 N verification levels; wherein during the coarse program procedure, larger step voltages are configured to sort the plurality of memory cells into groups, and wherein during the fine program procedure, the plurality of memory cells are programmed with smaller step voltages to push the plurality of memory cells forward into the verify level, wherein removing the erase state comprises: determining an overlap between the erase state and a first program state of the 2 N-1 or 2 N program states; and removing the overlap between the erase state and the first program state.
2. The programming method for non-volatile memory according to claim 1, wherein after the coarse programming procedure is executed, the number of memory cells in the erase state is 0.
3. The programming method for non-volatile memory according to claim 1, wherein the threshold voltage of each programming state is different from the threshold voltage of the erase state.
4. The programming method for non-volatile memory according to claim 1, wherein... If the non-volatile memory is a multi-cell memory and N is 2, after the coarse programming program is executed, all these memory cells in the erase state are programmed to 3 or 4 of these programming states. If the non-volatile memory is a three-level cell memory and N is 3, after executing the coarse programming program, all these memory cells in the erase state are programmed into 7 or 8 of these programming states. If the non-volatile memory is a four-level cell memory with N = 4, after executing the coarse programming procedure, all these memory cells in the erased state are programmed into 15 or 16 of these programming states; and If the non-volatile memory is a five-level cell memory with N being 5, after executing the coarse programming procedure, all these memory cells in the erase state are programmed into 31 or 32 of these programming states.
5. The programming method for non-volatile memory according to claim 1, wherein after the coarse programming procedure is executed, the memory cells in the programming state are used for data storage.
6. A non-volatile memory, comprising: A memory array comprising multiple memory cells; as well as A controller, used to performing a coarse program procedure to program all the memory cells located in an erase state to 2 N-1 or 2 N program states and remove the erase state, where N is a positive integer; and A fine programming procedure is performed to push all these memory cells to 2 N-1 or 2 N verification levels. wherein during the coarse program procedure, larger step voltages are configured to sort the plurality of memory cells into groups, and wherein during the fine program procedure, the plurality of memory cells are programmed with smaller step voltages to push the plurality of memory cells forward into the verify level, wherein removing the erase state comprises: determining an overlap between the erase state and a first program state of the 2 N-1 or 2 N program states; and removing the overlap between the erase state and the first program state.
7. The non-volatile memory according to claim 6, wherein the number of memory cells in the erase state is 0 after the coarse programming procedure is executed.
8. The non-volatile memory of claim 6, wherein the threshold voltage of each programming state is different from the threshold voltage of the erase state.
9. The non-volatile memory according to claim 6, wherein If the non-volatile memory is a multi-cell memory and N is 2, after the coarse programming program is executed, all these memory cells in the erase state are programmed to 3 or 4 of these programming states. If the non-volatile memory is a three-level cell memory and N is 3, after executing the coarse programming program, all these memory cells in the erase state are programmed into 7 or 8 of these programming states. If the non-volatile memory is a four-level cell memory with N = 4, after executing the coarse programming procedure, all these memory cells in the erased state are programmed into 15 or 16 of these programming states; and If the non-volatile memory is a five-level cell memory with N being 5, after executing the coarse programming procedure, all these memory cells in the erase state are programmed into 31 or 32 of these programming states.
10. A method for programming a non-volatile memory, comprising: Perform a coarse programming procedure to program each of a plurality of memory cells in an erased state to 2. N-1 or 2 N One of the programming states, and remove the erase state, where N is a positive integer; as well as Execute a fine-tuning program to push each of these memory units to 2. N-1 or 2 N One of the verification levels; During the coarse programming procedure, a larger step voltage is configured to group the multiple memory cells into several groups. During the fine programming procedure, the multiple memory cells are programmed with a smaller step voltage to push them forward to the verification level. Removing the erase state includes: determining the erase state and the 2 N-1 or 2 N The overlap between the first programming states in a programming state; and the removal of the overlap between the erase state and the first programming state.