A multi-input multi-output ultra-high-definition video processing and display platform

Abstract

The present invention discloses a multi-input, multi-output ultra-high-definition video processing and display platform, which includes a power module, a clock module, a video input module, a video output module, a video decoding module, a video encoding module, a video processing module, a data interconnection module, and a video cache module. The present invention is compatible with the input and output of videos of various resolutions via an HDMI interface, with a single channel supporting video input and output with a maximum resolution of 4K@60Hz. The present invention also has a total of eight video input and output interfaces, allowing the number of video input and output channels to be flexibly set according to user needs. The present invention is equipped with two FPGAs to support multiple video processing functions, has low processing latency, and high configuration flexibility, making it suitable for real-time multi-channel processing and display of ultra-high-definition video.

Description

Technical Field

[0001] The present invention relates to video reception, processing and display in the field of ultra-high-definition video technology, and in particular to a multi-input multi-output ultra-high-definition video processing and display platform. Background Art

[0002] The overall market size of the ultra-high-definition video industry is currently experiencing rapid growth and holds broad prospects. Conventional multi-input, multi-output (MIMO) video platforms, known as video conversion matrices, are widely used in education and security surveillance. However, existing video conversion matrices often offer limited functionality, weak video processing capabilities, and are expensive, failing to meet users' growing demand for replacements. Therefore, designing a MIMO (multi-input, multi-output) ultra-high-definition video processing and display platform is of great practical significance. Summary of the Invention

[0003] The purpose of the present invention is to provide a multi-input multi-output ultra-high-definition video processing and display platform in response to the characteristics of existing video multi-input multi-output platforms on the market, which have single functions, weak video processing capabilities, and high prices.

[0004] The specific technical solution for realizing the present invention is:

[0005] A multi-input multi-output ultra-high-definition video processing and display platform, including a power module, a clock module, a video input module, a video output module, a video decoding module, a video encoding module, a video processing module, a data interconnection module, a video cache module, and a system control module;

[0006] The power supply module is connected to the clock module, video input module, video output module, video decoding module, video encoding module, video processing module, data interconnection module, video cache module, and system control module to provide working power;

[0007] The clock module is connected to the video input module, video output module, video decoding module, video encoding module, video processing module, data interconnection module, video cache module, and system control module to provide a working clock;

[0008] The video input module is connected to the video decoding module and the system control module, and is used to control the decoding operation and receive pixel data of the video source;

[0009] The video buffer module is connected to the video decoding module and the video processing module, and is used to store the received original video data and the processed video data;

[0010] The data interconnection module is connected to the video cache module and is used to transmit and store original video data or processed pixel data;

[0011] The video encoding module is connected to the video output module, the video buffer module and the system control module, and is used to control encoding operations, read out stored video data, and display the encoded video data.

[0012] in:

[0013] The video input module includes an HDMI interface input module and a video source selection module; the HDMI interface input module contains 8 independent video input interfaces and supports 8 independent video inputs; the video source selection module requires the user to select 1920*1080 resolution or 3840*2160 resolution video input according to needs.

[0014] The video decoding module includes a decoding pixel timing adjustment module and a video decoding chip; the decoding pixel timing adjustment module is responsible for aligning the decoded pixel data according to the video's line field synchronization signal to prevent pixel data dislocation; the video decoding chip is responsible for identifying the resolution of the input video source and decoding the video source data according to a preset format.

[0015] The video encoding module includes a coding pixel timing adjustment module and a video encoding chip; the video encoding chip is responsible for encoding the data controlled by the FIFO output buffer according to a preset format; the coding pixel timing adjustment module adjusts the timing of the pixel data sent to the video encoding chip so that the displayed picture is error-free.

[0016] The video cache module includes FIFO input cache control, FIFO output cache control, DDR3 storage control, and DDR4 storage control.

[0017] The data interconnection module includes a video data transceiver protocol, a FIFO input buffer control, and a FIFO output buffer control; wherein the video data transceiver protocol includes determining the data transceiver bit width, selecting the data transmission start flag and the data transmission end flag, and selecting the data transceiver rate;

[0018] The system control module includes a PS-side video codec chip control module and a DDR4 program execution cache module. The PS-side video codec chip control module is connected to the video encoding chip and video decoding chip to control the selection of codec formats and video input and output modes. The DDR4 program execution cache module is connected to the PS-side video codec chip control module to provide a high-speed program execution cache for the PS-side video codec chip control module.

[0019] Compared with the existing technology, the beneficial effects of the present invention are:

[0020] 1) The present invention has a total of 8 HDMI codec chips, which can be independently configured as input or output mode, and a single channel can support video output with a maximum resolution of 4K@60HZ.

[0021] 2) The video processing part of the present invention is equipped with two FPGA chips, which can perform real-time video processing on the input video based on the multi-input and multi-output function, and use the high-speed, concurrent, and pipeline characteristics of FPGA to process large amounts of ultra-high-definition video data for functional development, which can increase the application diversity of the video conversion matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural block diagram of the present invention;

[0023] Figure 2 This is a structural diagram of the video input module of the present invention;

[0024] Figure 3 This is a structural diagram of the video decoding module of the present invention;

[0025] Figure 4 This is a structural diagram of the video encoding module of the present invention;

[0026] Figure 5 This is a structural diagram of the video output module of the present invention;

[0027] Figure 6 This is a structural diagram of the data interconnection module of the present invention;

[0028] Figure 7 This is a structural diagram of the video cache module of the present invention;

[0029] Figure 8 This is a structural diagram of the system control module of the present invention;

[0030] Figure 9 This is a structural diagram of the video processing module of the present invention;

[0031] Figure 10 This is a flowchart of the workflow of an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0033] See Figure 1The present invention includes a power supply module 1, a clock module 2, a video input module 3, a video output module 4, a video decoding module 5, a video encoding module 6, a video processing module 7, a data interconnection module 8, a video cache module 9 and a system control module 10. The power supply module 1 provides working power to the clock module 2, the video input module 3, the video output module 4, the video decoding module 5, the video encoding module 6, the video processing module 7, the data interconnection module 8, the video cache module 9 and the system control module 10; the clock module 2 is connected to the video input module 3, the video output module 4, the video decoding module 5, the video encoding module 6, the video processing module 7, the data interconnection module 8, the video cache module 9 and the system control module 10 to provide a working clock; the video input module 3 is connected to the video decoding module 5, the system control module 10 and the video cache module 9, and under the control of the system control module 10, selects the HDMI port for video input, then receives the externally transmitted video compression code stream, and sends it to the video decoding module 5 performs video decoding, and the decoded data enters the video cache module 9; the video output module 4 is connected to the video encoding module 6, the system control module 10 and the video cache module 9, and under the control of the system control module 10, the HDMI port for video output is selected, and the uncompressed data from the video cache module 9 enters the video encoding module 6, and then the compressed code stream is sent to the video output module 4; the video processing module 7 is connected to the video cache module 9, and reads the original video data from the video cache module 9. The data enters the video processing module 7, and the processed data enters the video cache module 9; the data interconnection module 8 is connected to the video cache module 9, and the data output by the video cache module 9 is transmitted through the data interconnection module 8 and enters the video processing module 7.

[0034] See Figure 2 The video input module 3 of the present invention includes an HDMI interface input module 31 and a video source selection module 32; wherein the HDMI interface input module 31 includes 8 independent video input interfaces and supports 8 independent video inputs; the video source selection module 32 requires the user to select a video input with a resolution of 1920*1080 or a resolution of 3840*2160 according to needs.

[0035] See Figure 3 The video decoding module 5 of the present invention includes a decoding pixel timing adjustment module 51 and a video decoding chip 52; wherein the decoding pixel timing adjustment module 51 is responsible for aligning the decoded pixel data according to the line field synchronization signal of the video to prevent the dislocation of the pixel data; the video decoding chip 52 is responsible for identifying the resolution of the input video source and decoding the video source data according to a preset format.

[0036] See Figure 4The video encoding module 6 includes a coding pixel timing adjustment module 61 and a video encoding chip 62; the video encoding chip 62 is responsible for encoding the data output from the FIFO output buffer control 92 according to a preset format; the coding pixel timing adjustment module 61 adjusts the pixel data timing of the video encoding chip 62 and sends it to the video output module 4, so that the displayed image is error-free.

[0037] See Figure 5 The video output module 4 includes an HDMI interface output module 41 and a video output resolution selection module 42; wherein the HDMI interface output module 41 includes 8 independent HDMI video output interfaces, supporting 8 independent video outputs; the video output resolution selection module 42 requires the user to select 1920*1080 resolution or 3840*2160 resolution video output according to needs.

[0038] See Figure 6 The data interconnection module 8 includes a video data transceiver protocol 81, a data transmission buffer control 82, and a data reception buffer control 83; wherein the video data transceiver protocol 81 includes determining the data transceiver bit width 811, selecting the data transmission start flag and the end flag 812, and selecting the data transceiver rate 813.

[0039] See Figure 7 The video cache module 9 includes a FIFO input cache control 91, a FIFO output cache control 92, a DDR3 storage module 93 and a DDR4 storage module 94; when data is stored, it needs to enter the DDR3 storage module 93 or the DDR4 storage module 94 through the FIFO input cache control 91, and when data is read, it needs to be read from the DDR3 cache module 93 or the DDR4 storage module 94, and then enter the FIFO output cache control 92 for rate matching.

[0040] See Figure 8 The system control module 10 includes a PS-side video codec chip control module 101 and a DDR4 program execution cache module 102. The PS-side video codec chip control module 101 is connected to the video encoding chip 62 and the video decoding chip 52 to control the selection of codec formats and video input and output modes. The DDR4 program execution cache module 102 is connected to the PS-side video codec chip control module 101 to provide a high-speed program execution cache for the PS-side video codec chip control module 101.

[0041] See Figure 9The video processing module 7 includes a KINTEX7 FPGA chip 71 and a ZYNQ_Ultrascale+ FPGA chip 72; wherein the KINTEX7 FPGA chip 71 and the ZYNQ_Ultrascale+ FPGA chip 72 utilize the data interconnection module 8 to collaboratively perform video processing. Example

[0042] See Figure 10 The working process of this embodiment is as follows: after the system is powered on, the power module 1 provides working power to the clock module 2, video input module 3, video output module 4, video decoding module 5, video encoding module 6, video processing module 7, data interconnection module 8, video cache module 9 and system control module 10; the clock module 2 provides working clock to the video input module 3, video output module 4, video decoding module 5, video encoding module 6, video processing module 7, data interconnection module 8, video cache module 9 and system control module 10; the external video source inputs a compressed video stream to the module 3, and the video source selection module 32 selects the resolution of the input video source. After the selection, the video data enters the video decoding chip 52 through the HDMI interface input module 31. The video codec chip 52 requires the PS side video codec chip control module 101 under the system control module 10 to configure the chip to input mode and the decoding pixel format to RGB888. The decoded pixel data needs to be processed by the decoding pixel timing adjustment module 51 and then enter the video cache module 9. After video data enters the video cache module 9, a FIFO input buffer control 91 is required to balance the data flow. The data can then be stored in the DDR3 storage module 93 or the DDR4 storage module 94. When outputting uncompressed video data, a FIFO output buffer control 92 is required to balance the data flow and match the frame rate. Data exiting the FIFO output buffer control 92 can be encoded by the video encoding chip 62 in the video encoding module 6. At this point, the PS-side video codec chip control module 101 in the system control module 10 must configure the chip to output mode and the encoding pixel format to RGB888. The data then passes through the encoding pixel timing adjustment module 61 and enters the video output module 4. Within module 4, the video output resolution selection module 42 selects the output video resolution, which is then output via the HDMI interface output module 41. If more than five channels need to be displayed, the output channels can be expanded using the data interconnect module 8. This module requires the video cache module 9 to transmit and receive data. If special processing is required for the displayed video, image processing can be performed by the video output module 7. This module requires the video cache module 9 to store the data.

Claims

1. A multi-input multi-output ultra-high-definition video processing and display platform, characterized in that: It includes a power supply module (1), a clock module (2), a video input module (3), a video output module (4), a video decoding module (5), a video encoding module (6), a video processing module (7), a data interconnection module (8), a video cache module (9) and a system control module (10); The power supply module (1) is connected to the clock module (2), the video input module (3), the video output module (4), the video decoding module (5), the video encoding module (6), the video processing module (7), the data interconnection module (8), the video cache module (9) and the system control module (10) to provide working power; The clock module (2) is connected to the video input module (3), the video output module (4), the video decoding module (5), the video encoding module (6), the video processing module (7), the data interconnection module (8), the video cache module (9) and the system control module (10) to provide a working clock; The video input module (3) is connected to the video decoding module (5) and the system control module (10) and is used to control the decoding operation and receive pixel data of the video source; The video buffer module (9) is connected to the video decoding module (5) and the video processing module (7), and is used to store received original video data and processed video data; The data interconnection module (8) is connected to the video cache module (9) and is used to transmit and store original video data or processed pixel data; The video encoding module (6) is connected to the video output module (4), the video buffer module (9) and the system control module (10), and is used to control the encoding operation and read out the stored video data and display the encoded video data; wherein: The video decoding module (5) includes a decoding pixel timing adjustment module (51) and a video decoding chip (52); the decoding pixel timing adjustment module (51) aligns the pixel data output by the video decoding chip (52) according to the line field synchronization signal of the video to prevent the dislocation of the pixel data; the video decoding chip (52) identifies the resolution of the input video source and decodes the video source data according to a preset format; The video encoding module (6) includes a coding pixel timing adjustment module (61) and a video encoding chip (62); the video encoding chip (62) encodes the data output by the FIFO output buffer control (92) according to a preset format; the coding pixel timing adjustment module (61) receives the pixel data from the video encoding chip (62), performs timing adjustment, and then sends the data to the video output module (4) so that the displayed image has no errors; The video cache module (9) includes a FIFO input cache control (91), a FIFO output cache control (92), a DDR3 storage module (93) and a DDR4 storage module (94); when data is stored, it enters the DDR3 storage module (93) or the DDR4 storage module (94) through the FIFO input cache control (91); when data is read out, it is read out from the DDR3 cache module (93) or the DDR4 storage module (94), and then passes through the FIFO output cache control (92) for rate matching; The system control module (10) includes a PS side video codec chip control module (101) and a DDR4 program execution cache module (102); wherein the PS side video codec chip control module (101) is connected to the video encoding chip (62) and the video decoding chip (52) to control the selection of the codec format and the selection of the video input and output mode; and the DDR4 program execution cache module (102) is connected to the PS side video codec chip control module (101) to provide a high-speed program execution cache for the PS side video codec chip control module (101).

2. The multi-input multi-output ultra-high-definition video processing and display platform according to claim 1, characterized in that: The video input module (3) includes an HDMI interface input module (31) and a video source selection module (32), and the video after passing through the video source selection module (32) enters the HDMI interface input module (31); The HDMI interface input module (31) includes 8 independent HDMI video input interfaces, supporting 8 independent video inputs; the video source selection module (32) requires the user to select a video input with a resolution of 1920*1080 or a resolution of 3840*2160 according to the user's needs.

3. The multi-input multi-output ultra-high-definition video processing and display platform according to claim 1, characterized in that: The video output module (4) includes an HDMI interface output module (41) and a video output resolution selection module (42); The HDMI interface output module (41) includes 8 independent HDMI video output interfaces, supporting 8 independent video outputs; the video output resolution selection module (42) requires the user to select a video output with a resolution of 1920*1080 or a resolution of 3840*2160 according to the user's needs. After the resolution is selected, the video is output through the HDMI interface output module (41).

4. The multi-input multi-output ultra-high-definition video processing and display platform according to claim 1, characterized in that: The video processing module (7) includes a KINTEX7 FPGA chip (71) and a ZYNQ_Ultrascale+ FPGA chip (72); The KINTEX7 FPGA chip (71) and the ZYNQ_Ultrascale+ FPGA chip (72) utilize the data interconnection module (8) to collaboratively perform video processing.

5. The multi-input multi-output ultra-high-definition video processing and display platform according to claim 1, characterized in that: The data interconnection module (8) includes a video data transceiver protocol (81), a data transmission buffer control (82) and a data reception buffer control (83); The data transmission buffer control (82) performs transmission buffer control according to the video data transmission and reception protocol (81), and the data reception buffer control (83) performs reception buffer control according to the video data transmission and reception protocol (81) to prevent data packets from being accumulated and lost; The video data transmission and reception protocol (81) includes determining the data transmission and reception bit width (811), selecting the data transmission start flag and end flag (812), and selecting the data transmission and reception rate (813); first, the data transmission and reception bit width is determined under the selection of the data transmission and reception rate (813) (811), and then the data transmission start flag and end flag are selected according to the transmission and reception bit width (812).

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