Data communication methods and related devices, systems, media and software products

Abstract

This application provides a data communication method and related apparatus, system, medium, and program product. The data communication method includes: acquiring a scheduling queue; obtaining the identifier of a first virtual network device from the head of the scheduling queue; determining the current state of the first virtual network device as a first state; writing DMA information to a Direct Memory Access (DMA) engine according to the first state; updating the current state of the first virtual network device to a second state; if it is determined that the second state is not the last state of a series of sequentially connected states, the CPU adds the identifier of the first virtual network device to the tail of the scheduling queue and re-acquires the identifier of the virtual network device from the head of the scheduling queue as the identifier of the first virtual network device, until the scheduling queue is empty. Using this application can improve CPU resource utilization.

Description

Technical Field

[0001] This application relates to the field of virtualization technology, and in particular to a data communication method and related apparatus, system, medium and program products. Background Technology

[0002] Virtualization primarily includes processor virtualization, memory virtualization, and input / output (I / O) virtualization. Virtio is a general framework for I / O virtualization within a kernel-based Virtual Machine (KVM) virtual environment. The virtio architecture includes a front-end virtio device driver and a back-end virtio device. A virtio device is essentially a virtualization of various devices (such as network devices and block devices). The virtio device driver manages and controls the virtio device, and the driver and device communicate via a negotiated interface. A virtio device can include a virtio network device (a virtual network device, which can be a virtual network interface card). Each virtio network device contains multiple data queues and a control queue. The data queues are used to send / receive data packets, while the control queue is used to configure and negotiate various network interface card features between the front-end driver and the virtio network device. In heterogeneous computing, both the data queues and the control queue consume queue resources from the back-end hardware. Especially when virtio network devices are used for communication between containers and external systems, a large number of containers create a large number of virtio network devices, consuming significant backend hardware queue resources. To conserve backend hardware queue resources, the ECPU can implement a control queue for the virtio network devices to interact with the frontend driver via control queue messages. This control queue message interaction refers to the DMA transfer of data between the frontend virtio network device driver and the ECPU to execute certain events on the virtio network device. A large number of virtio network devices involve a large number of control queue message interactions; therefore, designing a system for handling these large amounts of control queue message interactions between the ECPU and the frontend virtio network device driver becomes a pressing issue. Summary of the Invention

[0003] This application discloses a data communication method and related devices, systems, media, and program products, which can not only efficiently realize the interaction of a large number of control queue messages between the ECPU side and the front-end driver, but also improve the resource utilization of the CPU.

[0004] In a first aspect, this application provides a data communication method applied to a data communication system. The data communication system includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes a CPU and memory. The memory includes storage space for control queues corresponding to N virtual network devices. The front-end driver includes a first control queue corresponding to each of the N virtual network devices, where N is an integer greater than or equal to 1. The method includes:

[0005] The CPU acquires a scheduling queue, which includes the identifiers of each virtual network device in at least one of the N virtual network devices.

[0006] The CPU obtains the identifier of the first virtual network device from the head of the scheduling queue and determines that the current state of the first virtual network device is the first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed.

[0007] The CPU writes DMA information to the Direct Memory Access (DMA) engine according to the first state and updates the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state after the first state in the sequentially connected multiple states.

[0008] If it is determined that the second state is not the last state of the sequentially connected multiple states, the CPU adds the identifier of the first virtual network device to the tail of the scheduling queue and re-acquires the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device, until the scheduling queue is empty.

[0009] In this embodiment, the event flow executed on each virtual network device is divided into multiple sequentially connected states. Each state involves the transfer of DMA data between the front-end driver and the ECPU. Each time, the CPU retrieves the identifier of the first virtual network device from the head of the scheduling queue, writes the corresponding DMA information to the DMA engine based on the current state of the first virtual network device, updates the current state of the first virtual network device, and adds it to the tail of the scheduling queue. The DMA engine then handles the data transfer itself. This application does not require waiting for the DMA engine to complete the data transfer before retrieving the identifier of the next virtual network device and writing DMA information based on the state of the next virtual network device, thus continuously looping. Since the control queue message interaction process for DMA data transfer is time-consuming, this application allows the CPU to process the DMA information and state updates of other virtual network devices without waiting for the data transfer to complete. The CPU can continuously execute corresponding operations based on the current state of each virtual network device, efficiently handling the interaction of control queue messages for a large number of virtual network devices, i.e., handling the DMA data transfer of a large number of virtual network devices. Furthermore, the CPU can process the information of other virtual network devices without waiting for the data transfer to complete, fully utilizing CPU resources.

[0010] In one possible implementation, the method further includes:

[0011] The CPU receives a notification message sent by the front-end driver, the notification message being used to notify the front-end driver that it is ready to execute the target event on the first virtual network device;

[0012] The CPU adds the identifier of the first virtual network device to the scheduling queue and sets the current state of the first virtual network device to the first state, which is the initial state among the multiple states of sequential connection.

[0013] In one possible implementation, the control queue storage space corresponding to each of the N virtual network devices includes a second control queue and an effective data storage space, wherein the number of descriptors contained in the second control queue is less than the number of descriptors contained in the first control queue.

[0014] In one possible implementation, the sequentially connected multiple states include an initial state S0, a state S1, a state S2, and a state S3.

[0015] The CPU writes DMA information to the Direct Memory Access (DMA) engine according to the first state, and updates the current state of the first virtual network device to the second state, including:

[0016] When the first state is the initial state S0, the CPU writes first DMA information to the DMA engine and updates the current state of the first virtual network device to the state S1. The first DMA information includes first source address information, first destination address information, and a first DMA direction. The first source address information includes the address information of at least one first descriptor in the first control queue corresponding to the first virtual network device. The first destination address information includes the address information of at least one second descriptor contained in the second control queue in the control queue storage space corresponding to the first virtual network device. The first DMA direction indicates from the front-end driver to the ECPU. The at least one first descriptor stores the first address information and the second address information; or...

[0017] When the first state is state S1 and the data transfer indicated by the first DMA information is complete, the CPU writes second DMA information to the DMA engine and updates the current state of the first virtual network device to state S2. The second DMA information includes second source address information, second destination address information, and the first DMA direction. The second source address information includes the first address information stored in at least one second descriptor in the control queue storage space corresponding to the first virtual network device. The second destination address information includes third address information in the effective data storage space in the control queue storage space corresponding to the first virtual network device. The first address information stores first data. Alternatively,

[0018] When the first state is state S2 and the data transfer indicated by the second DMA information is complete, the CPU writes third DMA information to the DMA engine and updates the current state of the first virtual network device to state S3. The third DMA information includes third source address information, third destination address information, and second DMA direction. The third source address information includes fourth address information in the effective data storage space of the control queue storage space corresponding to the first virtual network device. The third destination address information includes the second address information stored in the at least one second descriptor. The second DMA direction indicates from the ECPU to the front-end driver. The fourth address information stores the second data.

[0019] In one possible implementation, when the first state is state S2 and the data transfer indicated by the second DMA information is complete, the CPU writing third DMA information to the DMA engine includes:

[0020] When the first state is state S2 and the data transfer indicated by the second DMA information is completed, the CPU executes the target event on the first virtual network device according to the first data, and after the target event is executed, the CPU writes the third DMA information to the DMA engine.

[0021] In one possible implementation, the second data is used to indicate the execution result of the CPU performing the target event on the first virtual network device.

[0022] Secondly, this application provides a data communication device applied in a data communication system. The data communication system includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes the data communication device and memory. The memory includes control queue storage spaces corresponding to N virtual network devices. The front-end driver includes first control queues corresponding to the N virtual network devices, where N is an integer greater than or equal to 1. The data communication device includes:

[0023] The first acquisition unit is used to acquire a scheduling queue, wherein the scheduling queue includes the identifiers of each virtual network device in at least one of the N virtual network devices;

[0024] The second acquisition unit is used to acquire the identifier of the first virtual network device from the head of the scheduling queue, and determine that the current state of the first virtual network device is a first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed.

[0025] The write unit is used to write DMA information to the direct memory access DMA engine according to the first state, and update the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state of the first state in the sequentially connected multiple states.

[0026] An identifier addition unit is configured to, when it is determined that the second state is not the last state of the sequentially connected plurality of states, add the identifier of the first virtual network device to the tail of the scheduling queue.

[0027] The first acquisition unit reacquires the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device until the scheduling queue is empty.

[0028] Thirdly, this application provides a data communication system, which includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes a central processing unit (CPU) and memory. The memory includes control queue storage space corresponding to N virtual network devices. The front-end driver includes a first control queue corresponding to the N virtual network devices, where N is an integer greater than or equal to 1.

[0029] The front-end driver is used to send at least one notification message to the CPU, the notification message being used to notify the front-end driver that it is ready to perform a target event on the virtual network device;

[0030] The CPU is used to receive the at least one notification message and add the identifier of the at least one virtual network device notified by the at least one notification message to the scheduling queue;

[0031] The CPU is also used to acquire a scheduling queue, the scheduling queue including the identifiers of each virtual network device in at least one of the N virtual network devices;

[0032] The CPU is further configured to obtain the identifier of the first virtual network device from the head of the scheduling queue, and determine that the current state of the first virtual network device is a first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed.

[0033] The CPU is also used to write DMA information to the Direct Memory Access (DMA) engine according to the first state, and update the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state after the first state in the sequentially connected multiple states.

[0034] The CPU is further configured to, when determining that the second state is not the last state of the sequentially connected plurality of states, add the identifier of the first virtual network device to the tail of the scheduling queue, and re-acquire the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device, until the scheduling queue is empty.

[0035] Fourthly, this application provides a data communication device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other; wherein the memory stores program instructions; when the program instructions are executed by the processor, the processor performs the method described in the first aspect and any possible implementation thereof.

[0036] Fifthly, this application provides a data communication device, comprising: a processor, which, when the processor invokes a computer program or instructions in memory, executes the method described in the first aspect and any possible implementation thereof.

[0037] In a sixth aspect, this application provides a computer-readable storage medium storing a computer program; when the computer program is run on one or more processors, it performs the method described in the first aspect and any possible implementation thereof. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below.

[0039] Figure 1 This application provides a schematic diagram of a data communication system architecture.

[0040] Figure 2 This application provides a schematic diagram of a control queue message interaction process.

[0041] Figure 3 A schematic diagram of state division provided for an embodiment of this application;

[0042] Figure 4 A flowchart illustrating a data communication method provided in an embodiment of this application;

[0043] Figure 5 A schematic diagram of a front-end driver and ECPU-side control queue provided in an embodiment of this application;

[0044] Figure 6 A schematic diagram of a scheduling queue processing provided in an embodiment of this application;

[0045] Figure 7 This is a schematic diagram of the structure of a data communication device provided in an embodiment of this application;

[0046] Figure 8 This is a schematic diagram of another data communication device provided in an embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the present invention will be described in further detail below with reference to the accompanying drawings.

[0048] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used only to distinguish different objects and not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0049] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the above phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] In this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0051] The present invention will now be described in detail with reference to the accompanying drawings.

[0052] Please see Figure 1 , Figure 1 This is a schematic diagram of a data communication system architecture provided in an embodiment of this application, such as... Figure 1 As shown, the system architecture may include a front-end driver, a hardware back-end field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), and an embedded central processing unit (ECPU).

[0053] The virtual network device described in this application includes multiple data queues and one control queue. The data queues are used to send / receive data packets, while the control queue is used to configure and negotiate various network interface card (NIC) functionalities between the front-end driver and the virtual network device. Correspondingly, the front-end driver also maintains a control queue for each virtual network device. In heterogeneous computing, both the data queues and the control queue consume queue resources on the back-end hardware. Especially when the virtual network device is used for communication between containers and the outside world, a large number of containers will create a large number of virtual network devices.

[0054] To conserve backend hardware queue resources, this application allows the control queue of the virtual network device to be implemented on the ECPU side for interaction with the frontend driver via control queue messages. The control queue message interaction mentioned in this application can be understood as the interaction between the frontend driver and the ECPU side involved in the entire process of the frontend driver executing a target event on the backend virtual network device. This includes, for example, notification messages sent by the frontend driver to the ECPU side when it has prepared the data for executing the target event, and DMA data transfer interactions between the frontend driver and the ECPU involved in executing the target event. The target event executed on the virtual network device can be the configuration of the virtual network, such as configuring a Virtual Local Area Network (VLAN) on the virtual network device.

[0055] The following is combined with Figure 2 The following example illustrates the control queue message interaction process between the front-end driver and the ECPU. The front-end driver needs to execute a target event on the virtual network device. For example, this target event could be configuring VLAN 10 for the virtual network device. The front-end driver allocates three memory addresses for the data related to configuring VLAN 10, used to store the message type, valid data, and acknowledgment (ACK). The message type indicates that the message is a VLAN configuration message, the valid data is 10, and the ACK is used by the ECPU to write the execution result of the target event.

[0056] The front-end driver fills the message type and valid data into the corresponding memory address, and writes the memory address of the message type and the memory address of the valid data into the first descriptor and the second descriptor of the first control queue corresponding to the virtual network device of the front-end driver, respectively. At the same time, it writes the memory address of the ACK confirmation into the third descriptor.

[0057] Once the front-end driver has prepared the data, it sends a notification message to the ECPU to inform the ECPU that the front-end driver has prepared the relevant data to execute the target event.

[0058] 101, Write the first DMA information: DMA descriptor, front-end driver to ECPU.

[0059] Specifically, optionally, the ECPU writes first DMA information to the DMA engine. This first DMA information includes the source address, destination address, and DMA direction. The source address is the address of the first, second, and third descriptors of the front-end driver; the destination address is the address of the fourth, fifth, and sixth descriptors in the ECPU; and the DMA direction is from the front-end driver to the ECPU. It can be understood that the ECPU and the front-end driver know the addresses of the first, second, and third descriptors during the negotiation process.

[0060] The DMA engine begins to move the memory addresses of the message types stored in the first descriptor, the memory addresses of the valid data stored in the second descriptor, and the memory addresses of the ACKs stored in the third descriptor to the fourth, fifth, and sixth descriptors.

[0061] 102. Determine if DMA is complete.

[0062] 103. If DMA is complete, write the second DMA information: DMA first data, front-end driver to ECPU.

[0063] Optionally, if DMA is completed, the ECPU writes second DMA information to the DMA engine. This second DMA information includes the source address, destination address, and DMA direction. The source address includes the memory address stored in the fourth descriptor and the memory address stored in the fifth descriptor. The destination address includes the memory address allocated in the ECPU for storing the message type and valid data. The DMA direction is from the front-end driver to the ECPU side. In other words, the message type and valid data stored in the front-end driver are moved to the ECPU. For ease of description, the message type and valid data are collectively referred to as the first data.

[0064] 104. Determine if DMA is complete.

[0065] 105. If DMA is complete, process the first data.

[0066] Specifically, if DMA is completed, the ECPU parses the first data and executes the target event, i.e., the event that configures VLAN 10. After executing the target event, the execution result (i.e., the second data) is written to a memory address on the ECPU side.

[0067] 106, Write the third DMA information: DMA second data and preset descriptor, ECPU to front-end driver.

[0068] Specifically, optionally, the ECPU writes third DMA information to the DMA engine. This third DMA information includes a source address, a destination address, and a DMA direction. The source address includes the memory address storing the second data, the destination address includes the address stored in the sixth descriptor, and the DMA direction is from the ECPU side to the front-end driver. That is, the result of executing the target event (i.e., the second data) is written to the memory address of the front-end driver's ACK. In some implementations, to facilitate instructing the front-end driver to release the first, second, and third descriptors, the ECPU also needs to write a flag identifier to a preset descriptor, which can be the first descriptor. Therefore, the ECPU can write the flag identifier to the fourth descriptor. The aforementioned source address can also include the address of the fourth descriptor, and the destination address can also include the address of the first descriptor, i.e., moving the flag identifier from the fourth descriptor to the first descriptor so that the front-end driver can read the flag identifier and then release the first, second, and third descriptors.

[0069] 107. Determine if DMA is complete. If it is complete, end the entire process of executing the target event. This entire process can also be called the control queue message interaction process.

[0070] Combination Figure 2 The process shown in this application aims to improve CPU utilization, allowing the CPU to handle control queue messages from a large number of virtual network devices. Figure 2 The entire process of executing the target event is divided into multiple sequentially connected states, as shown below. Figure 3 The state division shown is for illustrative purposes and is meant to be understood. Figure 3 The state division shown is only an example, and other state division methods are not limited in this application.

[0071] like Figure 3 As shown, the sequentially connected states include state S0, state S1, state S2, state S3, and state S4. It is understood that state S4 may be excluded.

[0072] When the ECPU receives a notification message about the virtual network device from the front-end driver, the virtual network device enters state S0.

[0073] After the ECPU writes the first DMA information to the DMA engine, the virtual network device transitions from state S0 to state S1. In state S1, the DMA engine performs DMA data transfer based on the first DMA information.

[0074] After the ECPU detects that the DMA engine has completed the data transfer based on the first DMA information, it writes the second DMA information to the DMA engine. The virtual network device then transitions from state S1 to state S2. In state S2, the DMA engine performs DMA data transfer based on the second DMA information.

[0075] After the ECPU detects that the DMA engine has completed the data transfer based on the second DMA information, it processes the transferred first data and executes the target event on the virtual network device. After the target event is executed, the ECPU writes the third DMA information to the DMA engine, and the virtual network device transitions from state S2 to state S3. In state S3, the DMA engine performs DMA data transfer based on the third DMA information.

[0076] Once the ECPU detects that the DMA engine has completed the transfer based on the third DMA information, the virtual network device transitions from state S3 to state S4.

[0077] Please see Figure 4 , Figure 4 This is a flowchart illustrating a data communication method provided in an embodiment of this application. The method is applied to a data communication system, which includes a front-end driver and an ECPU. The ECPU includes a central processing unit (CPU) and memory. The memory includes control queue storage spaces corresponding to N virtual network devices. The front-end driver includes first control queues corresponding to the N virtual network devices, where N is an integer greater than or equal to 1. Figure 4 As shown, the above method may include the following steps:

[0078] 201. The front-end driver sends at least one notification message to the CPU, the notification message being used to notify the front-end driver that it is ready to perform a target event on the virtual network device.

[0079] 202. The CPU adds the identifier of at least one virtual network device to the scheduling queue.

[0080] like Figure 5 As shown, for each of the N virtual network devices, the front-end driver has a first control queue and a data space corresponding to each virtual network device. The ECPU-side memory also includes a control queue storage space corresponding to each virtual network device. Each control queue storage space includes a second control queue and an effective data storage space. In this embodiment, the number of descriptors contained in the second control queue is less than the number of descriptors contained in the first control queue, thereby saving memory space on the ECPU side. For example, each first control queue includes 1024 descriptors, while each second control queue includes 4 descriptors.

[0081] The front-end driver can instruct the ECPU side to execute target events on virtual network devices. It is understood that the front-end driver can instruct the ECPU side to execute different target events on different virtual network devices, or it can instruct the ECPU side to execute the same target event on different virtual network devices. This application does not limit this.

[0082] When the front-end driver is ready to execute target event data on the virtual network device, it can send a notification message to the ECPU side. The process of the front-end driver preparing the target time data for execution on the virtual network device can be referred to the description in the foregoing embodiments, and will not be repeated here. Correspondingly, the CPU on the ECPU side adds the identifier of the virtual network device notified by the notification message to the scheduling queue, and sets the current state of the virtual network device to the initial state S0. It is understood that the front-end driver can send at least one notification message, which respectively notifies the front-end driver that data for different virtual network devices is ready. For example, notification message 1 is used to notify the front-end driver that data for virtual network device 1 is ready, notification message 2 is used to notify the front-end driver that data for virtual network device 2 is ready, and so on. It should be noted that the sending time of the at least one message can be the same or different, and this application does not limit this. Whenever the CPU receives a notification message, it adds the identifier of the corresponding virtual network device to the scheduling queue and sets it to the initial state S0. The order in which the identifiers of the at least one virtual network device are arranged in the scheduling queue can be the order in which the notification messages are received; that is, each time a notification message is received, the identifier of the corresponding virtual network device is added to the tail of the scheduling queue.

[0083] 203, The CPU obtains the identifier of the first virtual network device from the head of the scheduling queue.

[0084] 204. The CPU determines that the current state of the first virtual network device is the first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing the target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed.

[0085] The scheduling queue includes the identifier of at least one virtual network device. The CPU retrieves the identifier of one virtual network device from the head of the scheduling queue each time, using it as the identifier of the first virtual network device. The CPU determines the current state of the first virtual network device as a first state. This first state can be one of multiple sequentially connected states. The method for obtaining these multiple states can be referred to the description in the foregoing embodiments, and will not be repeated here. It should be noted that the current state of the first virtual network device can be understood as the current execution stage for executing the target event instructed by the front-end driver on the first virtual network device. For example, if it is currently in state S1, it means that the address information in the descriptor of the front-end driver is being moved into the memory of the ECPU.

[0086] 205. The CPU writes DMA information to the Direct Memory Access (DMA) engine according to the first state and updates the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state after the first state in the sequentially connected multiple states.

[0087] 206. If it is determined that the second state is not the last state of the sequentially connected plurality of states, the CPU adds the identifier of the first virtual network device to the tail of the scheduling queue.

[0088] In some embodiments, the CPU determines the DMA information to be written to the DMA engine based on the current state of the first virtual network device. It is understood that the amount of DMA information to be written to the DMA engine differs depending on the current state of the first virtual network device. For example, the DMA engine may include a DMA queue, which includes at least one descriptor. Each DMA message being written occupies one descriptor. The DMA engine can process each DMA message sequentially; it is understood that the DMA engine can also process multiple DMA messages simultaneously.

[0089] The CPU writes DMA information to the DMA engine and updates the current state of the first virtual network device to the next state, i.e., the second state. It then determines whether this second state is the last of a series of sequentially connected states. If it is not the last state, the identifier of the first virtual network device is added to the tail of the scheduling queue, waiting to be retrieved by the CPU next time. If the second state is the last state, the identifier of the first virtual network device does not need to be added back to the scheduling queue.

[0090] Understandably, the DMA engine can perform data transfer based on the written DMA information. Simultaneously, the CPU does not need to wait for the DMA engine to complete the data transfer and can instead process information from other virtual network devices. Specifically, it retrieves the identifier of the virtual network device from the head of the scheduling queue, using it as the identifier of the first virtual network device, and obtains the current state of that virtual network device as the first state. Based on this first state, it writes DMA information to the DMA engine. In other words, the CPU continuously loops through steps 203-206 until the scheduling queue is empty, without waiting for the data DMA transfer to complete. This improves CPU utilization and allows for efficient processing of control queue messages from multiple virtual network devices.

[0091] It should be noted that, since the DMA information written by the same virtual network device in the next state depends on the data transferred by the DMA information written by the virtual network device in the previous state, before writing DMA information for the next state of the same virtual network device, it is necessary to determine whether the DMA information written by the virtual network device in the previous state has been transferred. If the transfer is completed, new DMA information is written according to the next state. If the transfer is not completed, the identifier of the virtual network device is placed at the tail of the scheduling queue to wait for it to be obtained next time, and no new DMA information is written.

[0092] For example, when the first virtual network device is currently in the initial state S0, the CPU writes first DMA information to the DMA engine and updates the current state of the first virtual network device to the next state, namely state S1. The first DMA information includes first source address information, first destination address information, and a first DMA direction. The first source address information includes the address information of at least one first descriptor in the first control queue corresponding to the first virtual network device. The first destination address information includes the address information of at least one second descriptor contained in the second control queue in the control queue storage space corresponding to the first virtual network device. The first DMA direction indicates from the front-end driver to the ECPU. The at least one first descriptor stores first address information and second address information. The first address information may include the address where first data (including message type and valid data) is stored in the front-end driver. The second address information is the address used to store second data (including the result of the execution target event) written from the ECPU side to the front-end driver. The first DMA information is used to instruct the DMA engine to move the first address information and second address information stored in at least one first descriptor of the front-end driver to at least one second descriptor of the second control queue corresponding to the first virtual network device on the ECPU side. The first address information is used by the ECPU side to subsequently move the first data from the front-end driver to the valid data storage space corresponding to the first virtual network device.

[0093] For example, when the first virtual network device is currently in state S1, and the data transfer indicated by the first DMA information is complete (i.e., the data transfer indicated by the DMA information written in the previous state has been completed), the CPU writes second DMA information to the DMA engine and updates the current state of the first virtual network device to the next state, namely state S2. The second DMA information includes second source address information, second destination address information, and a first DMA direction. The second source address information includes first address information stored in at least one of the second descriptors in the control queue storage space corresponding to the first virtual network device. The second destination address information includes third address information in the effective data storage space of the control queue storage space corresponding to the first virtual network device. The first address information in the front-end driver stores first data, which may include a message type and valid data. The second DMA information is used to instruct the DMA engine to transfer the first data stored in the first address information in the front-end driver to the address indicated by the third address information in the effective data storage space corresponding to the first virtual network device on the ECPU side. This allows the CPU on the ECPU side to execute a target event on the first virtual network device based on the first data.

[0094] It should be noted that if the first virtual network device is currently in state S1 and the data transfer indicated by the first DMA information is not completed, the CPU adds the identifier of the first virtual network device to the tail of the scheduling queue and does not update the current state of the first virtual network device, that is, it remains in state S1.

[0095] For example, if the first virtual network device is currently in state S2 and the data transfer indicated by the second DMA information is complete, the CPU executes a target event on the first virtual network device based on the transferred first data. For instance, if the target event is to set VLAN 10 for the first virtual network device, then the first data includes a message type of VLAN setting type and a valid data value of 10. The CPU then sets VLAN 10 for the first virtual network device based on this first data.

[0096] After executing the target event on the first virtual network device, the CPU can write third DMA information to the DMA engine and update the current state of the first virtual network device to state S3. The third DMA information includes third source address information, third destination address information, and a second DMA direction. The third source address information includes fourth address information in the effective data storage space of the control queue storage space corresponding to the first virtual network device, where second data is stored. This second data can indicate the execution result of executing the target event on the first virtual network device; for example, 1 indicates execution failure, and 0 indicates execution success. The third destination address information includes second address information moved from the front-end driver to the ECPU side in the aforementioned embodiment, and the second DMA direction indicates from the ECPU to the front-end driver. This third DMA information is used to instruct the DMA engine to move the second data stored at the address indicated by the fourth address information in the effective data storage space of the control queue storage space corresponding to the first virtual network device on the ECPU side to the front-end driver. This second data is used to indicate the execution result.

[0097] In some embodiments, such as in a queue storage technique in packed mode, the third DMA information may also instruct the flag identifier to be written into one of the descriptors in at least one first descriptor in the front-end driver, so as to instruct the front-end driver to release the at least one descriptor.

[0098] Optionally, the sequentially connected states may also include state S4, that is, when the data transfer indicated by the third DMA information is completed, the current state of the first virtual network device is updated to state S4. It is understood that state S4 may not be included, that is, state S3 may be the last state, and this application does not limit this.

[0099] It's important to note that state partitioning differs across storage technologies. For example, in split-mode queue storage, besides the descriptor queue, there are also Avail and Used queues. Before the DMA descriptor queue, the descriptor queue index stored in the DMAAvail queue needs to be processed (including two DMA operations: the index of the first DMAAvail queue and the content of the second DMAAvail queue, i.e., the descriptor queue index). After the second data is DMA'd, the descriptor queue index needs to be DMA'd back to the front end (including two DMA operations: the content of the first DMAUsed queue, i.e., the descriptor queue index, and the index of the second DMAUsed queue). Therefore, the sequentially connected states can be: State S0, State S01, State S02, State S1, State S2, State S3, State S30, State S31, and State S4. State S01 refers to the index of the DMAAvail queue, State S02 refers to the content of the DMAAvail queue, State S30 refers to the content of the DMAUsed queue, and State S31 refers to the index of the DMAUsed queue.

[0100] In this embodiment, the event flow executed on each virtual network device is divided into multiple sequentially connected states. Each state involves the transfer of DMA data between the front-end driver and the ECPU. Each time, the CPU retrieves the identifier of the first virtual network device from the head of the scheduling queue, writes the corresponding DMA information to the DMA engine based on the current state of the first virtual network device, updates the current state of the first virtual network device, and adds it to the tail of the scheduling queue. The DMA engine then handles the data transfer itself. This application does not require waiting for the DMA engine to complete the data transfer before retrieving the identifier of the next virtual network device and writing DMA information based on the state of the next virtual network device, thus continuously looping. Since the control queue message interaction process for DMA data transfer is time-consuming, this application allows the CPU to process the DMA information and state updates of other virtual network devices without waiting for the data transfer to complete. The CPU can continuously execute corresponding operations based on the current state of each virtual network device, efficiently handling the interaction of control queue messages for a large number of virtual network devices, i.e., handling the DMA data transfer of a large number of virtual network devices. Furthermore, the CPU can process the information of other virtual network devices without waiting for the data transfer to complete, fully utilizing CPU resources.

[0101] It should be noted that in the specific implementation, not only can the control queue message interactions of existing virtual network devices in the scheduling queue be executed cyclically, but new virtual network device identifiers can also be continuously added to the scheduling queue. For example, if the scheduling queue includes the identifiers of virtual network device 1 and virtual network device 2, and virtual network device 1 is currently in state S2 and virtual network device 2 is currently in state S3, the identifier of virtual network device 3 is added to the scheduling queue and placed at the tail of the queue, and the current state of virtual network device 3 is state S0. It can be understood that the identifiers of virtual network devices in the scheduling queue can also be replaced with the identifiers of the control queue messages corresponding to those virtual network devices.

[0102] The following is in conjunction with the appendix Figure 6 The data communication method of this application is illustrated with an example. The ECPU side includes the ECPUFWD thread and the ECPU control queue thread.

[0103] The ECPUFWD thread receives the ctrQ1 notification message sent by the front-end driver, and the ECPU control queue thread adds the ctrQ1 to the scheduling queue and sets its current state to state S0.

[0104] The ECPUFWD thread receives the ctrQ2 notification message sent by the front-end driver. The ECPU control queue thread adds the ctrQ2 message to the scheduling queue and sets its current state to S0. ctrQ2 follows ctrQ1.

[0105] The ECPU control queue thread retrieves the ctrQ1 at the head of the scheduling queue and the DMA descriptor Desc.

[0106] Optionally, first DMA information is written to the DMA engine. This first DMA information is used by the front-end driver and the ECPU to move the relevant descriptors of ctrQ1. For details, please refer to the description in the previous embodiment, which will not be repeated here. The current state of ctrQ1 is updated to state S1, and it is added to the tail of the scheduling queue.

[0107] The ECPU control queue thread retrieves the ctrQ2 at the head of the scheduling queue and performs DMA Desc.

[0108] Optionally, first DMA information is written to the DMA engine. This first DMA information is used by the front-end driver and the ECPU to move the relevant descriptors of ctrQ2. For details, please refer to the description in the previous embodiments, which will not be repeated here. The current state of ctrQ2 is updated to state S1, and it is added to the tail of the scheduling queue.

[0109] The ECPU control queue thread retrieves ctrQ1 from the head of the scheduling queue and performs DMA on the first data.

[0110] Specifically, optionally, if the data transfer indicated by the first DMA information associated with ctrQ1 is not complete, ctrQ1 is added to the tail of the scheduling queue. If the data transfer indicated by the first DMA information associated with ctrQ1 is complete, second DMA information is written to the DMA engine. This second DMA information is used by the front-end driver and the ECPU side to transfer the first data of ctrQ1. For details, please refer to the description in the foregoing embodiments, which will not be repeated here. The current state of ctrQ1 is updated to state S2, and it is added to the tail of the scheduling queue.

[0111] The ECPU control queue thread retrieves the ctrQ2 at the head of the scheduling queue and performs DMA on the first data.

[0112] Optionally, if the data transfer indicated by the first DMA information associated with ctrQ2 is not complete, ctrQ2 is added to the tail of the scheduling queue. If the data transfer indicated by the first DMA information associated with ctrQ2 is complete, second DMA information is written to the DMA engine. This second DMA information is used by the front-end driver and the ECPU side to transfer the first data of ctrQ2. For details, please refer to the description in the foregoing embodiments, which will not be repeated here. The current state of ctrQ2 is updated to state S2, and it is added to the tail of the scheduling queue.

[0113] The ECPU control queue thread retrieves ctrQ1 from the head of the scheduling queue and performs DMA on the second data and the preset descriptor.

[0114] Specifically, optionally, if the data transfer indicated by the second DMA information associated with ctrQ1 is not complete, ctrQ1 is added to the tail of the scheduling queue. If the data transfer indicated by the second DMA information associated with ctrQ1 is complete, third DMA information is written to the DMA engine. This third DMA information is used by the front-end driver and the ECPU side to transfer the second data and preset descriptor of ctrQ1. For details, please refer to the description in the foregoing embodiments, which will not be repeated here. The current state of ctrQ1 is updated to state S3, and it is added to the tail of the scheduling queue.

[0115] The ECPU control queue thread retrieves the ctrQ2 at the head of the scheduling queue and performs DMA on the second data and the preset descriptor.

[0116] Optionally, if the data transfer indicated by the second DMA information associated with ctrQ2 is not complete, ctrQ2 is added to the tail of the scheduling queue. If the data transfer indicated by the second DMA information associated with ctrQ2 is complete, third DMA information is written to the DMA engine. This third DMA information is used by the front-end driver and the ECPU side to transfer the second data and preset descriptor of ctrQ2. For details, please refer to the description in the foregoing embodiments, which will not be repeated here. The current state of ctrQ2 is updated to state S3, and it is added to the tail of the scheduling queue.

[0117] The ECPU control queue thread retrieves ctrQ1 from the head of the scheduling queue. If the data transfer indicated by the third DMA associated with ctrQ1 is complete, ctrQ1 is removed from the scheduling queue, leaving ctrQ2. If the data transfer indicated by the third DMA associated with ctrQ1 is not complete, ctrQ1 is added to the tail of the scheduling queue.

[0118] The ECPU control queue thread retrieves the CTRQ2 at the head of the scheduling queue. If the data transfer indicated by the third DMA associated with CTRQ2 is complete, the CTRQ2 is removed from the scheduling queue. If the data transfer indicated by the third DMA information associated with CTRQ2 is not complete, CTRQ2 is added to the tail of the scheduling queue.

[0119] The following is combined with Figure 7 and Figure 8 The apparatus provided in the embodiments of this application will be described in detail.

[0120] It is understood that, in order to implement the functions in the above embodiments, the CPU includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the modules and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware, software, or a combination of hardware and software. Whether a function is executed in hardware, software, or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0121] See Figure 7 , Figure 7This is a schematic diagram of a data communication device provided in an embodiment of this application. The data communication device is applied in a data communication system, which includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes the data communication device and memory. The memory includes storage spaces for control queues corresponding to N virtual network devices. The front-end driver includes first control queues corresponding to the N virtual network devices, where N is an integer greater than or equal to 1. Figure 7 As shown, the data communication device 1100 may include:

[0122] The first acquisition unit 1101 is used to acquire a scheduling queue, wherein the scheduling queue includes the identifiers of each virtual network device in at least one of the N virtual network devices;

[0123] The second acquisition unit 1102 is used to acquire the identifier of the first virtual network device from the queue head of the scheduling queue, and determine that the current state of the first virtual network device is a first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed.

[0124] The write unit 1103 is used to write DMA information to the direct memory access DMA engine according to the first state, and update the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state of the first state in the sequentially connected multiple states.

[0125] The identifier addition unit 1104 is used to add the identifier of the first virtual network device to the tail of the scheduling queue when it is determined that the second state is not the last state of the multiple states of sequential connection.

[0126] The first acquisition unit 1101 reacquires the identifier of the virtual network device in the queue head of the scheduling queue as the identifier of the first virtual network device until the scheduling queue is empty.

[0127] Optionally, the data communication device further includes:

[0128] A receiving unit is configured to receive a notification message sent by the front-end driver, the notification message being used to notify the front-end driver that it is ready to execute the target event on the first virtual network device;

[0129] The identifier addition unit 1104 is further configured to add the identifier of the first virtual network device to the scheduling queue, and set the current state of the first virtual network device to the first state, wherein the first state is the initial state among the multiple states of the sequential connection.

[0130] Optionally, the control queue storage space corresponding to each of the N virtual network devices includes a second control queue and an effective data storage space, wherein the number of descriptors contained in the second control queue is less than the number of descriptors contained in the first control queue.

[0131] Optionally, the sequentially connected states include an initial state S0, a state S1, a state S2, and a state S3.

[0132] The writing unit is specifically used to write first DMA information to the DMA engine when the first state is the initial state S0, and update the current state of the first virtual network device to the state S1. The first DMA information includes first source address information, first destination address information, and a first DMA direction. The first source address information includes the address information of at least one first descriptor in the first control queue corresponding to the first virtual network device. The first destination address information includes the address information of at least one second descriptor contained in the second control queue in the control queue storage space corresponding to the first virtual network device. The first DMA direction indicates from the front-end driver to the ECPU. The at least one first descriptor stores the first address information and the second address information; or...

[0133] When the first state is state S1 and the data transfer indicated by the first DMA information is complete, second DMA information is written to the DMA engine, and the current state of the first virtual network device is updated to state S2. The second DMA information includes second source address information, second destination address information, and the first DMA direction. The second source address information includes the first address information stored in at least one second descriptor in the control queue storage space corresponding to the first virtual network device. The second destination address information includes the third address information in the effective data storage space in the control queue storage space corresponding to the first virtual network device. The first address information stores the first data. Alternatively,

[0134] When the first state is state S2 and the data transfer indicated by the second DMA information is complete, third DMA information is written to the DMA engine, and the current state of the first virtual network device is updated to state S3. The third DMA information includes third source address information, third destination address information, and second DMA direction. The third source address information includes fourth address information in the effective data storage space of the control queue storage space corresponding to the first virtual network device. The third destination address information includes the second address information stored in the at least one second descriptor. The second DMA direction indicates from the ECPU to the front-end driver. The fourth address information stores the second data.

[0135] Optionally, the writing unit is specifically configured to execute the target event on the first virtual network device according to the first data when the first state is the state S2 and the data transfer indicated by the second DMA information is completed, and when the target event is executed, the CPU writes the third DMA information to the DMA engine.

[0136] Optionally, the second data is used to indicate the execution result of the CPU performing the target event on the first virtual network device.

[0137] It should be noted that the above-mentioned units are used to execute the relevant content on the CPU side in the above method embodiments.

[0138] In this embodiment, the CPU is presented in the form of units. Here, "unit" can refer to an application-specific integrated circuit (ASIC), a processor and memory executing one or more software or firmware programs, integrated logic circuits, and / or other devices that can provide the aforementioned functions. Furthermore, each of these units can be... Figure 8 It is implemented using the 2101 processor.

[0139] It is understood that the division of the various units of the above-mentioned data communication device is only an example and may not necessarily include all units, may only include some of the units, or may include other functional units, etc. This application does not limit it.

[0140] like Figure 8 The diagram shows another data communication device provided in this application. The data communication device 2100 includes at least one processor 2101, at least one memory 2102, and at least one communication interface 2103. The processor 2101, memory 2102, and communication interface 2103 are connected through a communication bus and communicate with each other.

[0141] Communication interface 2103 is used to communicate with other devices or communication networks, such as Ethernet, RAN, WLAN, etc.

[0142] The memory 2102 may be ROM or other types of static storage devices capable of storing static information and instructions, RAM or other types of dynamic storage devices capable of storing information and instructions, or it may be EEPROM, CD-ROM or other optical disc storage, optical disk storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0143] The memory 2102 stores the application code for executing the above scheme, and its execution is controlled by the processor 2101. The processor 2101 executes the application code stored in the memory 2102.

[0144] The code stored in memory 2102 can execute one of the data communication methods provided above.

[0145] The processor 2101 may also employ one or more integrated circuits to execute related programs in order to implement the data communication method executed on the CPU side in the embodiments of this application.

[0146] The processor 2101 can also be an integrated circuit chip with signal processing capabilities. During implementation, each step of the data communication method of this application can be completed by the integrated logic circuitry in the hardware of the processor 2101 or by instructions in software form. The processor 2101 described above can also be a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and module block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 2102. Processor 2101 reads the information in memory 2102 and, in conjunction with its hardware, completes the data communication method of this application embodiment.

[0147] Communication interface 2103 uses transceiver devices, such as, but not limited to, transceivers, to enable communication between the data communication device and other devices or communication networks. For example, communication interface 2103 can be used to obtain notification messages sent by the front-end driver and to perform data transfer with the front-end driver, etc.

[0148] The bus may include a path for transmitting information between various components of the device (e.g., memory 2102, processor 2101, communication interface 2103).

[0149] This application provides a data communication system, which includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes a central processing unit (CPU) and memory. The memory includes control queue storage space corresponding to N virtual network devices. The front-end driver includes a first control queue corresponding to each of the N virtual network devices, where N is an integer greater than or equal to 1.

[0150] The front-end driver is used to send at least one notification message to the CPU, the notification message being used to notify the front-end driver that it is ready to perform a target event on the virtual network device;

[0151] The CPU is used to receive the at least one notification message and add the identifier of the at least one virtual network device notified by the at least one notification message to the scheduling queue;

[0152] The CPU is also used to acquire a scheduling queue, the scheduling queue including the identifiers of each virtual network device among the at least one virtual network device in the N virtual network devices;

[0153] The CPU is further configured to obtain the identifier of the first virtual network device from the head of the scheduling queue, and determine that the current state of the first virtual network device is a first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed.

[0154] The CPU is also used to write DMA information to the Direct Memory Access (DMA) engine according to the first state, and update the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state after the first state in the sequentially connected multiple states.

[0155] The CPU is further configured to, when determining that the second state is not the last state of the sequentially connected plurality of states, add the identifier of the first virtual network device to the tail of the scheduling queue, and re-acquire the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device, until the scheduling queue is empty.

[0156] This application provides a computer-readable medium that stores program code for execution by a device, the program code including content related to performing the data communication method in the above method embodiments.

[0157] This application provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the relevant content of the data communication method in the above method embodiments.

[0158] This application provides a chip, which includes a processor and a data interface. The processor reads instructions stored in a memory through the data interface and executes the relevant content of the data communication method described in the above method embodiment.

[0159] Optionally, as one implementation, the chip may further include a memory storing instructions, and the processor is used to execute the instructions stored in the memory. When the instructions are executed, the processor is used to perform the relevant content of the data communication method of the above method embodiment.

[0160] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0161] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0163] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0164] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0165] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, ROM, RAM, portable hard drives, magnetic disks, or optical disks.

[0166] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage device, which may include a flash drive, ROM, RAM, disk, or optical disk, etc.

[0167] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A data communication method, characterized in that, The method is applied to a data communication system, which includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes a CPU and memory. The memory includes control queue storage spaces corresponding to N virtual network devices. The front-end driver includes a first control queue corresponding to each of the N virtual network devices, where N is an integer greater than or equal to 1. The method includes: The CPU acquires a scheduling queue, which includes the identifiers of each virtual network device in at least one of the N virtual network devices. The CPU obtains the identifier of the first virtual network device from the head of the scheduling queue and determines that the current state of the first virtual network device is the first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed. The CPU writes DMA information to the Direct Memory Access (DMA) engine according to the first state and updates the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state after the first state in the sequentially connected multiple states. If it is determined that the second state is not the last state of the sequentially connected multiple states, the CPU adds the identifier of the first virtual network device to the tail of the scheduling queue and re-acquires the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device, until the scheduling queue is empty.

2. The method as described in claim 1, characterized in that, The method further includes: The CPU receives a notification message sent by the front-end driver, the notification message being used to notify the front-end driver that it is ready to execute the target event on the first virtual network device; The CPU adds the identifier of the first virtual network device to the scheduling queue and sets the current state of the first virtual network device to the first state, which is the initial state among the multiple states of sequential connection.

3. The method as described in claim 1 or 2, characterized in that, The control queue storage space corresponding to each of the N virtual network devices includes a second control queue and an effective data storage space. The number of descriptors contained in the second control queue is less than the number of descriptors contained in the first control queue.

4. The method as described in claim 3, characterized in that, The sequentially connected states include initial state S0, state S1, state S2, and state S3. The CPU writes DMA information to the Direct Memory Access (DMA) engine according to the first state, and updates the current state of the first virtual network device to the second state, including: When the first state is the initial state S0, the CPU writes first DMA information to the DMA engine and updates the current state of the first virtual network device to the state S1. The first DMA information includes first source address information, first destination address information, and a first DMA direction. The first source address information includes the address information of at least one first descriptor in the first control queue corresponding to the first virtual network device. The first destination address information includes the address information of at least one second descriptor contained in the second control queue in the control queue storage space corresponding to the first virtual network device. The first DMA direction indicates from the front-end driver to the ECPU. The at least one first descriptor stores the first address information and the second address information; or... When the first state is state S1 and the data transfer indicated by the first DMA information is complete, the CPU writes second DMA information to the DMA engine and updates the current state of the first virtual network device to state S2. The second DMA information includes second source address information, second destination address information, and the first DMA direction. The second source address information includes the first address information stored in at least one second descriptor in the control queue storage space corresponding to the first virtual network device. The second destination address information includes third address information in the effective data storage space in the control queue storage space corresponding to the first virtual network device. The first address information stores first data. Alternatively, When the first state is state S2 and the data transfer indicated by the second DMA information is complete, the CPU writes third DMA information to the DMA engine and updates the current state of the first virtual network device to state S3. The third DMA information includes third source address information, third destination address information, and second DMA direction. The third source address information includes fourth address information in the effective data storage space of the control queue storage space corresponding to the first virtual network device. The third destination address information includes the second address information stored in the at least one second descriptor. The second DMA direction indicates from the ECPU to the front-end driver. The fourth address information stores the second data.

5. The method as described in claim 4, characterized in that, When the first state is state S2 and the data transfer indicated by the second DMA information is complete, the CPU writes third DMA information to the DMA engine, including: When the first state is state S2 and the data transfer indicated by the second DMA information is completed, the CPU executes the target event on the first virtual network device according to the first data, and after the target event is executed, the CPU writes the third DMA information to the DMA engine.

6. The method as described in claim 5, characterized in that, The second data is used to indicate the execution result of the CPU executing the target event on the first virtual network device.

7. A data communication device, characterized in that, The data communication device is applied in a data communication system, which includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes the data communication device and memory. The memory includes control queue storage spaces corresponding to N virtual network devices. The front-end driver includes a first control queue corresponding to each of the N virtual network devices, where N is an integer greater than or equal to 1. The data communication device includes: The first acquisition unit is used to acquire a scheduling queue, wherein the scheduling queue includes the identifiers of each virtual network device in at least one of the N virtual network devices; The second acquisition unit is used to acquire the identifier of the first virtual network device from the head of the scheduling queue, and determine that the current state of the first virtual network device is a first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed. The write unit is used to write DMA information to the direct memory access DMA engine according to the first state, and update the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state of the first state in the sequentially connected multiple states. An identifier addition unit is configured to, when it is determined that the second state is not the last state of the sequentially connected plurality of states, add the identifier of the first virtual network device to the tail of the scheduling queue. The first acquisition unit reacquires the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device until the scheduling queue is empty.

8. A data communication system, characterized in that, The data communication system includes a front-end driver and an embedded central processing unit (ECPU). The ECPU includes a central processing unit (CPU) and memory. The memory includes control queue storage space corresponding to N virtual network devices. The front-end driver includes a first control queue corresponding to each of the N virtual network devices. N is an integer greater than or equal to 1. The front-end driver is used to send at least one notification message to the CPU, the notification message being used to notify the front-end driver that it is ready to perform a target event on the virtual network device; The CPU is used to receive the at least one notification message and add the identifier of the at least one virtual network device notified by the at least one notification message to the scheduling queue; The CPU is also used to acquire a scheduling queue, the scheduling queue including the identifiers of each virtual network device among the at least one virtual network device in the N virtual network devices; The CPU is further configured to obtain the identifier of the first virtual network device from the head of the scheduling queue, and determine that the current state of the first virtual network device is a first state. The first state is one of a plurality of states that are sequentially connected. The plurality of states are obtained by dividing the process of executing a target event on the first virtual network device. The connection order of the plurality of states is determined according to the order in which the target event is executed. The CPU is also used to write DMA information to the Direct Memory Access (DMA) engine according to the first state, and update the current state of the first virtual network device to the second state. The DMA information is used for data transfer between the first control queue corresponding to the first virtual network device and the control queue storage space corresponding to the first virtual network device. The second state is the next state after the first state in the sequentially connected multiple states. The CPU is further configured to, when determining that the second state is not the last state of the sequentially connected plurality of states, add the identifier of the first virtual network device to the tail of the scheduling queue, and re-acquire the identifier of the virtual network device in the head of the scheduling queue as the identifier of the first virtual network device, until the scheduling queue is empty.

9. A data communication device, characterized in that, include: The processor executes the method as described in any one of claims 1-6 when the processor invokes a computer program or instructions in memory.

10. A computer-readable storage medium or computer program product, characterized in that, The computer-readable storage medium stores a computer program or instructions; when the computer program or instructions are run on one or more processors, they perform the method as described in any one of claims 1-6, or the computer program product is used to implement the method as described in any one of claims 1-6.

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